opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001
   3    Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 2, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21 02111-1307, USA.  */
  22
  23 #include <stdio.h>
  24 #include "sysdep.h"
  25 #include "opcode/ppc.h"
  26 #include "opintl.h"
  27
  28 /* This file holds the PowerPC opcode table.  The opcode table
  29    includes almost all of the extended instruction mnemonics.  This
  30    permits the disassembler to use them, and simplifies the assembler
  31    logic, at the cost of increasing the table size.  The table is
  32    strictly constant data, so the compiler should be able to put it in
  33    the .text section.
  34
  35    This file also holds the operand table.  All knowledge about
  36    inserting operands into instructions and vice-versa is kept in this
  37    file.  */
  38 \f
  39 /* Local insertion and extraction functions.  */
  40
  41 static unsigned long insert_bat
  42   PARAMS ((unsigned long, long, int, const char **));
  43 static long extract_bat
  44   PARAMS ((unsigned long, int, int *));
  45 static unsigned long insert_bba
  46   PARAMS ((unsigned long, long, int, const char **));
  47 static long extract_bba
  48   PARAMS ((unsigned long, int, int *));
  49 static unsigned long insert_bd
  50   PARAMS ((unsigned long, long, int, const char **));
  51 static long extract_bd
  52   PARAMS ((unsigned long, int, int *));
  53 static unsigned long insert_bdm
  54   PARAMS ((unsigned long, long, int, const char **));
  55 static long extract_bdm
  56   PARAMS ((unsigned long, int, int *));
  57 static unsigned long insert_bdp
  58   PARAMS ((unsigned long, long, int, const char **));
  59 static long extract_bdp
  60   PARAMS ((unsigned long, int, int *));
  61 static int valid_bo
  62   PARAMS ((long, int));
  63 static unsigned long insert_bo
  64   PARAMS ((unsigned long, long, int, const char **));
  65 static long extract_bo
  66   PARAMS ((unsigned long, int, int *));
  67 static unsigned long insert_boe
  68   PARAMS ((unsigned long, long, int, const char **));
  69 static long extract_boe
  70   PARAMS ((unsigned long, int, int *));
  71 static unsigned long insert_ds
  72   PARAMS ((unsigned long, long, int, const char **));
  73 static long extract_ds
  74   PARAMS ((unsigned long, int, int *));
  75 static unsigned long insert_de
  76   PARAMS ((unsigned long, long, int, const char **));
  77 static long extract_de
  78   PARAMS ((unsigned long, int, int *));
  79 static unsigned long insert_des
  80   PARAMS ((unsigned long, long, int, const char **));
  81 static long extract_des
  82   PARAMS ((unsigned long, int, int *));
  83 static unsigned long insert_li
  84   PARAMS ((unsigned long, long, int, const char **));
  85 static long extract_li
  86   PARAMS ((unsigned long, int, int *));
  87 static unsigned long insert_mbe
  88   PARAMS ((unsigned long, long, int, const char **));
  89 static long extract_mbe
  90   PARAMS ((unsigned long, int, int *));
  91 static unsigned long insert_mb6
  92   PARAMS ((unsigned long, long, int, const char **));
  93 static long extract_mb6
  94   PARAMS ((unsigned long, int, int *));
  95 static unsigned long insert_nb
  96   PARAMS ((unsigned long, long, int, const char **));
  97 static long extract_nb
  98   PARAMS ((unsigned long, int, int *));
  99 static unsigned long insert_nsi
 100   PARAMS ((unsigned long, long, int, const char **));
 101 static long extract_nsi
 102   PARAMS ((unsigned long, int, int *));
 103 static unsigned long insert_ral
 104   PARAMS ((unsigned long, long, int, const char **));
 105 static unsigned long insert_ram
 106   PARAMS ((unsigned long, long, int, const char **));
 107 static unsigned long insert_ras
 108   PARAMS ((unsigned long, long, int, const char **));
 109 static unsigned long insert_rbs
 110   PARAMS ((unsigned long, long, int, const char **));
 111 static long extract_rbs
 112   PARAMS ((unsigned long, int, int *));
 113 static unsigned long insert_sh6
 114   PARAMS ((unsigned long, long, int, const char **));
 115 static long extract_sh6
 116   PARAMS ((unsigned long, int, int *));
 117 static unsigned long insert_spr
 118   PARAMS ((unsigned long, long, int, const char **));
 119 static long extract_spr
 120   PARAMS ((unsigned long, int, int *));
 121 static unsigned long insert_tbr
 122   PARAMS ((unsigned long, long, int, const char **));
 123 static long extract_tbr
 124   PARAMS ((unsigned long, int, int *));
 125 \f
 126 /* The operands table.
 127
 128    The fields are bits, shift, insert, extract, flags.
 129
 130    We used to put parens around the various additions, like the one
 131    for BA just below.  However, that caused trouble with feeble
 132    compilers with a limit on depth of a parenthesized expression, like
 133    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
 134    omit the parens, since the macros are never used in a context where
 135    the addition will be ambiguous.  */
 136
 137 const struct powerpc_operand powerpc_operands[] =
 138 {
 139   /* The zero index is used to indicate the end of the list of
 140      operands.  */
 141 #define UNUSED 0
 142   { 0, 0, 0, 0, 0 },
 143
 144   /* The BA field in an XL form instruction.  */
 145 #define BA UNUSED + 1
 146 #define BA_MASK (0x1f << 16)
 147   { 5, 16, 0, 0, PPC_OPERAND_CR },
 148
 149   /* The BA field in an XL form instruction when it must be the same
 150      as the BT field in the same instruction.  */
 151 #define BAT BA + 1
 152   { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 153
 154   /* The BB field in an XL form instruction.  */
 155 #define BB BAT + 1
 156 #define BB_MASK (0x1f << 11)
 157   { 5, 11, 0, 0, PPC_OPERAND_CR },
 158
 159   /* The BB field in an XL form instruction when it must be the same
 160      as the BA field in the same instruction.  */
 161 #define BBA BB + 1
 162   { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 163
 164   /* The BD field in a B form instruction.  The lower two bits are
 165      forced to zero.  */
 166 #define BD BBA + 1
 167   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 168
 169   /* The BD field in a B form instruction when absolute addressing is
 170      used.  */
 171 #define BDA BD + 1
 172   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 173
 174   /* The BD field in a B form instruction when the - modifier is used.
 175      This sets the y bit of the BO field appropriately.  */
 176 #define BDM BDA + 1
 177   { 16, 0, insert_bdm, extract_bdm,
 178       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 179
 180   /* The BD field in a B form instruction when the - modifier is used
 181      and absolute address is used.  */
 182 #define BDMA BDM + 1
 183   { 16, 0, insert_bdm, extract_bdm,
 184       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 185
 186   /* The BD field in a B form instruction when the + modifier is used.
 187      This sets the y bit of the BO field appropriately.  */
 188 #define BDP BDMA + 1
 189   { 16, 0, insert_bdp, extract_bdp,
 190       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 191
 192   /* The BD field in a B form instruction when the + modifier is used
 193      and absolute addressing is used.  */
 194 #define BDPA BDP + 1
 195   { 16, 0, insert_bdp, extract_bdp,
 196       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 197
 198   /* The BF field in an X or XL form instruction.  */
 199 #define BF BDPA + 1
 200   { 3, 23, 0, 0, PPC_OPERAND_CR },
 201
 202   /* An optional BF field.  This is used for comparison instructions,
 203      in which an omitted BF field is taken as zero.  */
 204 #define OBF BF + 1
 205   { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 206
 207   /* The BFA field in an X or XL form instruction.  */
 208 #define BFA OBF + 1
 209   { 3, 18, 0, 0, PPC_OPERAND_CR },
 210
 211   /* The BI field in a B form or XL form instruction.  */
 212 #define BI BFA + 1
 213 #define BI_MASK (0x1f << 16)
 214   { 5, 16, 0, 0, PPC_OPERAND_CR },
 215
 216   /* The BO field in a B form instruction.  Certain values are
 217      illegal.  */
 218 #define BO BI + 1
 219 #define BO_MASK (0x1f << 21)
 220   { 5, 21, insert_bo, extract_bo, 0 },
 221
 222   /* The BO field in a B form instruction when the + or - modifier is
 223      used.  This is like the BO field, but it must be even.  */
 224 #define BOE BO + 1
 225   { 5, 21, insert_boe, extract_boe, 0 },
 226
 227   /* The BT field in an X or XL form instruction.  */
 228 #define BT BOE + 1
 229   { 5, 21, 0, 0, PPC_OPERAND_CR },
 230
 231   /* The condition register number portion of the BI field in a B form
 232      or XL form instruction.  This is used for the extended
 233      conditional branch mnemonics, which set the lower two bits of the
 234      BI field.  This field is optional.  */
 235 #define CR BT + 1
 236   { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 237
 238   /* The CT field in an X form instruction.  */
 239 #define CT CR + 1
 240   { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 241
 242   /* The D field in a D form instruction.  This is a displacement off
 243      a register, and implies that the next operand is a register in
 244      parentheses.  */
 245 #define D CT + 1
 246   { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 247
 248   /* The DE field in a DE form instruction.  This is like D, but is 12
 249      bits only.  */
 250 #define DE D + 1
 251   { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
 252
 253   /* The DES field in a DES form instruction.  This is like DS, but is 14
 254      bits only (12 stored.)  */
 255 #define DES DE + 1
 256   { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 257
 258   /* The DS field in a DS form instruction.  This is like D, but the
 259      lower two bits are forced to zero.  */
 260 #define DS DES + 1
 261   { 16, 0, insert_ds, extract_ds,
 262       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 263
 264   /* The E field in a wrteei instruction.  */
 265 #define E DS + 1
 266   { 1, 15, 0, 0, 0 },
 267
 268   /* The FL1 field in a POWER SC form instruction.  */
 269 #define FL1 E + 1
 270   { 4, 12, 0, 0, 0 },
 271
 272   /* The FL2 field in a POWER SC form instruction.  */
 273 #define FL2 FL1 + 1
 274   { 3, 2, 0, 0, 0 },
 275
 276   /* The FLM field in an XFL form instruction.  */
 277 #define FLM FL2 + 1
 278   { 8, 17, 0, 0, 0 },
 279
 280   /* The FRA field in an X or A form instruction.  */
 281 #define FRA FLM + 1
 282 #define FRA_MASK (0x1f << 16)
 283   { 5, 16, 0, 0, PPC_OPERAND_FPR },
 284
 285   /* The FRB field in an X or A form instruction.  */
 286 #define FRB FRA + 1
 287 #define FRB_MASK (0x1f << 11)
 288   { 5, 11, 0, 0, PPC_OPERAND_FPR },
 289
 290   /* The FRC field in an A form instruction.  */
 291 #define FRC FRB + 1
 292 #define FRC_MASK (0x1f << 6)
 293   { 5, 6, 0, 0, PPC_OPERAND_FPR },
 294
 295   /* The FRS field in an X form instruction or the FRT field in a D, X
 296      or A form instruction.  */
 297 #define FRS FRC + 1
 298 #define FRT FRS
 299   { 5, 21, 0, 0, PPC_OPERAND_FPR },
 300
 301   /* The FXM field in an XFX instruction.  */
 302 #define FXM FRS + 1
 303 #define FXM_MASK (0xff << 12)
 304   { 8, 12, 0, 0, 0 },
 305
 306   /* The L field in a D or X form instruction.  */
 307 #define L FXM + 1
 308   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 309
 310   /* The LEV field in a POWER SC form instruction.  */
 311 #define LEV L + 1
 312   { 7, 5, 0, 0, 0 },
 313
 314   /* The LI field in an I form instruction.  The lower two bits are
 315      forced to zero.  */
 316 #define LI LEV + 1
 317   { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 318
 319   /* The LI field in an I form instruction when used as an absolute
 320      address.  */
 321 #define LIA LI + 1
 322   { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 323
 324   /* The LS field in an X (sync) form instruction.  */
 325 #define LS LIA + 1
 326   { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 327
 328   /* The MB field in an M form instruction.  */
 329 #define MB LS + 1
 330 #define MB_MASK (0x1f << 6)
 331   { 5, 6, 0, 0, 0 },
 332
 333   /* The ME field in an M form instruction.  */
 334 #define ME MB + 1
 335 #define ME_MASK (0x1f << 1)
 336   { 5, 1, 0, 0, 0 },
 337
 338   /* The MB and ME fields in an M form instruction expressed a single
 339      operand which is a bitmask indicating which bits to select.  This
 340      is a two operand form using PPC_OPERAND_NEXT.  See the
 341      description in opcode/ppc.h for what this means.  */
 342 #define MBE ME + 1
 343   { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 344   { 32, 0, insert_mbe, extract_mbe, 0 },
 345
 346   /* The MB or ME field in an MD or MDS form instruction.  The high
 347      bit is wrapped to the low end.  */
 348 #define MB6 MBE + 2
 349 #define ME6 MB6
 350 #define MB6_MASK (0x3f << 5)
 351   { 6, 5, insert_mb6, extract_mb6, 0 },
 352
 353   /* The MO field in an mbar instruction.  */
 354 #define MO MB6 + 1
 355   { 5, 21, 0, 0, 0 },
 356
 357   /* The NB field in an X form instruction.  The value 32 is stored as
 358      0.  */
 359 #define NB MO + 1
 360   { 6, 11, insert_nb, extract_nb, 0 },
 361
 362   /* The NSI field in a D form instruction.  This is the same as the
 363      SI field, only negated.  */
 364 #define NSI NB + 1
 365   { 16, 0, insert_nsi, extract_nsi,
 366       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 367
 368   /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */
 369 #define RA NSI + 1
 370 #define RA_MASK (0x1f << 16)
 371   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 372
 373   /* The RA field in a D or X form instruction which is an updating
 374      load, which means that the RA field may not be zero and may not
 375      equal the RT field.  */
 376 #define RAL RA + 1
 377   { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
 378
 379   /* The RA field in an lmw instruction, which has special value
 380      restrictions.  */
 381 #define RAM RAL + 1
 382   { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
 383
 384   /* The RA field in a D or X form instruction which is an updating
 385      store or an updating floating point load, which means that the RA
 386      field may not be zero.  */
 387 #define RAS RAM + 1
 388   { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
 389
 390   /* The RB field in an X, XO, M, or MDS form instruction.  */
 391 #define RB RAS + 1
 392 #define RB_MASK (0x1f << 11)
 393   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 394
 395   /* The RB field in an X form instruction when it must be the same as
 396      the RS field in the instruction.  This is used for extended
 397      mnemonics like mr.  */
 398 #define RBS RB + 1
 399   { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 400
 401   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 402      instruction or the RT field in a D, DS, X, XFX or XO form
 403      instruction.  */
 404 #define RS RBS + 1
 405 #define RT RS
 406 #define RT_MASK (0x1f << 21)
 407   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 408
 409   /* The SH field in an X or M form instruction.  */
 410 #define SH RS + 1
 411 #define SH_MASK (0x1f << 11)
 412   { 5, 11, 0, 0, 0 },
 413
 414   /* The SH field in an MD form instruction.  This is split.  */
 415 #define SH6 SH + 1
 416 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 417   { 6, 1, insert_sh6, extract_sh6, 0 },
 418
 419   /* The SI field in a D form instruction.  */
 420 #define SI SH6 + 1
 421   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 422
 423   /* The SI field in a D form instruction when we accept a wide range
 424      of positive values.  */
 425 #define SISIGNOPT SI + 1
 426   { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 427
 428   /* The SPR field in an XFX form instruction.  This is flipped--the
 429      lower 5 bits are stored in the upper 5 and vice- versa.  */
 430 #define SPR SISIGNOPT + 1
 431 #define SPR_MASK (0x3ff << 11)
 432   { 10, 11, insert_spr, extract_spr, 0 },
 433
 434   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 435 #define SPRBAT SPR + 1
 436 #define SPRBAT_MASK (0x3 << 17)
 437   { 2, 17, 0, 0, 0 },
 438
 439   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 440 #define SPRG SPRBAT + 1
 441 #define SPRG_MASK (0x3 << 16)
 442   { 2, 16, 0, 0, 0 },
 443
 444   /* The SR field in an X form instruction.  */
 445 #define SR SPRG + 1
 446   { 4, 16, 0, 0, 0 },
 447
 448   /* The STRM field in an X AltiVec form instruction.  */
 449 #define STRM SR + 1
 450 #define STRM_MASK (0x3 << 21)
 451   { 2, 21, 0, 0, 0 },
 452
 453   /* The SV field in a POWER SC form instruction.  */
 454 #define SV STRM + 1
 455   { 14, 2, 0, 0, 0 },
 456
 457   /* The TBR field in an XFX form instruction.  This is like the SPR
 458      field, but it is optional.  */
 459 #define TBR SV + 1
 460   { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 461
 462   /* The TO field in a D or X form instruction.  */
 463 #define TO TBR + 1
 464 #define TO_MASK (0x1f << 21)
 465   { 5, 21, 0, 0, 0 },
 466
 467   /* The U field in an X form instruction.  */
 468 #define U TO + 1
 469   { 4, 12, 0, 0, 0 },
 470
 471   /* The UI field in a D form instruction.  */
 472 #define UI U + 1
 473   { 16, 0, 0, 0, 0 },
 474
 475   /* The VA field in a VA, VX or VXR form instruction. */
 476 #define VA UI + 1
 477 #define VA_MASK (0x1f << 16)
 478   { 5, 16, 0, 0, PPC_OPERAND_VR },
 479
 480   /* The VB field in a VA, VX or VXR form instruction. */
 481 #define VB VA + 1
 482 #define VB_MASK (0x1f << 11)
 483   { 5, 11, 0, 0, PPC_OPERAND_VR },
 484
 485   /* The VC field in a VA form instruction. */
 486 #define VC VB + 1
 487 #define VC_MASK (0x1f << 6)
 488   { 5, 6, 0, 0, PPC_OPERAND_VR },
 489
 490   /* The VD or VS field in a VA, VX, VXR or X form instruction. */
 491 #define VD VC + 1
 492 #define VS VD
 493 #define VD_MASK (0x1f << 21)
 494   { 5, 21, 0, 0, PPC_OPERAND_VR },
 495
 496   /* The SIMM field in a VX form instruction. */
 497 #define SIMM VD + 1
 498   { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
 499
 500   /* The UIMM field in a VX form instruction. */
 501 #define UIMM SIMM + 1
 502   { 5, 16, 0, 0, 0 },
 503
 504   /* The SHB field in a VA form instruction. */
 505 #define SHB UIMM + 1
 506   { 4, 6, 0, 0, 0 },
 507
 508   /* The WS field.  */
 509 #define WS SHB + 1
 510 #define WS_MASK (0x7 << 11)
 511   { 3, 11, 0, 0, 0 },
 512
 513 };
 514
 515 /* The functions used to insert and extract complicated operands.  */
 516
 517 /* The BA field in an XL form instruction when it must be the same as
 518    the BT field in the same instruction.  This operand is marked FAKE.
 519    The insertion function just copies the BT field into the BA field,
 520    and the extraction function just checks that the fields are the
 521    same.  */
 522
 523 /*ARGSUSED*/
 524 static unsigned long
 525 insert_bat (insn, value, dialect, errmsg)
 526      unsigned long insn;
 527      long value ATTRIBUTE_UNUSED;
 528      int dialect ATTRIBUTE_UNUSED;
 529      const char **errmsg ATTRIBUTE_UNUSED;
 530 {
 531   return insn | (((insn >> 21) & 0x1f) << 16);
 532 }
 533
 534 static long
 535 extract_bat (insn, dialect, invalid)
 536      unsigned long insn;
 537      int dialect ATTRIBUTE_UNUSED;
 538      int *invalid;
 539 {
 540   if (invalid != (int *) NULL
 541       && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 542     *invalid = 1;
 543   return 0;
 544 }
 545
 546 /* The BB field in an XL form instruction when it must be the same as
 547    the BA field in the same instruction.  This operand is marked FAKE.
 548    The insertion function just copies the BA field into the BB field,
 549    and the extraction function just checks that the fields are the
 550    same.  */
 551
 552 /*ARGSUSED*/
 553 static unsigned long
 554 insert_bba (insn, value, dialect, errmsg)
 555      unsigned long insn;
 556      long value ATTRIBUTE_UNUSED;
 557      int dialect ATTRIBUTE_UNUSED;
 558      const char **errmsg ATTRIBUTE_UNUSED;
 559 {
 560   return insn | (((insn >> 16) & 0x1f) << 11);
 561 }
 562
 563 static long
 564 extract_bba (insn, dialect, invalid)
 565      unsigned long insn;
 566      int dialect ATTRIBUTE_UNUSED;
 567      int *invalid;
 568 {
 569   if (invalid != (int *) NULL
 570       && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 571     *invalid = 1;
 572   return 0;
 573 }
 574
 575 /* The BD field in a B form instruction.  The lower two bits are
 576    forced to zero.  */
 577
 578 /*ARGSUSED*/
 579 static unsigned long
 580 insert_bd (insn, value, dialect, errmsg)
 581      unsigned long insn;
 582      long value;
 583      int dialect ATTRIBUTE_UNUSED;
 584      const char **errmsg ATTRIBUTE_UNUSED;
 585 {
 586   return insn | (value & 0xfffc);
 587 }
 588
 589 /*ARGSUSED*/
 590 static long
 591 extract_bd (insn, dialect, invalid)
 592      unsigned long insn;
 593      int dialect ATTRIBUTE_UNUSED;
 594      int *invalid ATTRIBUTE_UNUSED;
 595 {
 596   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 597 }
 598
 599 /* The BD field in a B form instruction when the - modifier is used.
 600    This modifier means that the branch is not expected to be taken.
 601    For 32 bit targets we set the y bit of the BO field to 1 if the
 602    offset is negative.  When extracting, we require that the y bit be
 603    1 and that the offset be positive, since if the y bit is 0 we just
 604    want to print the normal form of the instruction.
 605    64 bit targets use two bits, "a", and "t", instead of the "y" bit.
 606    at == 10 => not taken, at == 11 => taken.  The t bit is 00001 in
 607    BO field, the a bit is 00010 for branch on CR(BI) and 01000 for
 608    branch on CTR.  */
 609
 610 /*ARGSUSED*/
 611 static unsigned long
 612 insert_bdm (insn, value, dialect, errmsg)
 613      unsigned long insn;
 614      long value;
 615      int dialect;
 616      const char **errmsg ATTRIBUTE_UNUSED;
 617 {
 618   if ((dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_64)) != PPC_OPCODE_64)
 619     {
 620       if ((value & 0x8000) != 0)
 621         insn |= 1 << 21;
 622     }
 623   else
 624     {
 625       if ((insn & (0x14 << 21)) == (0x04 << 21))
 626         insn |= 0x02 << 21;
 627       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 628         insn |= 0x08 << 21;
 629     }
 630   return insn | (value & 0xfffc);
 631 }
 632
 633 static long
 634 extract_bdm (insn, dialect, invalid)
 635      unsigned long insn;
 636      int dialect;
 637      int *invalid;
 638 {
 639   if (invalid != (int *) NULL)
 640     {
 641       if ((dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_64)) != PPC_OPCODE_64)
 642         {
 643           if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
 644             *invalid = 1;
 645         }
 646       else
 647         {
 648           if ((insn & (0x17 << 21)) != (0x06 << 21)
 649               && (insn & (0x1d << 21)) != (0x18 << 21))
 650             *invalid = 1;
 651         }
 652     }
 653   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 654 }
 655
 656 /* The BD field in a B form instruction when the + modifier is used.
 657    This is like BDM, above, except that the branch is expected to be
 658    taken.  */
 659
 660 /*ARGSUSED*/
 661 static unsigned long
 662 insert_bdp (insn, value, dialect, errmsg)
 663      unsigned long insn;
 664      long value;
 665      int dialect;
 666      const char **errmsg ATTRIBUTE_UNUSED;
 667 {
 668   if ((dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_64)) != PPC_OPCODE_64)
 669     {
 670       if ((value & 0x8000) == 0)
 671         insn |= 1 << 21;
 672     }
 673   else
 674     {
 675       if ((insn & (0x14 << 21)) == (0x04 << 21))
 676         insn |= 0x03 << 21;
 677       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 678         insn |= 0x09 << 21;
 679     }
 680   return insn | (value & 0xfffc);
 681 }
 682
 683 static long
 684 extract_bdp (insn, dialect, invalid)
 685      unsigned long insn;
 686      int dialect;
 687      int *invalid;
 688 {
 689   if (invalid != (int *) NULL)
 690     {
 691       if ((dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_64)) != PPC_OPCODE_64)
 692         {
 693           if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
 694             *invalid = 1;
 695         }
 696       else
 697         {
 698           if ((insn & (0x17 << 21)) != (0x07 << 21)
 699               && (insn & (0x1d << 21)) != (0x19 << 21))
 700             *invalid = 1;
 701         }
 702     }
 703   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 704 }
 705
 706 /* Check for legal values of a BO field.  */
 707
 708 static int
 709 valid_bo (value, dialect)
 710      long value;
 711      int dialect;
 712 {
 713   if ((dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_64)) != PPC_OPCODE_64)
 714     {
 715       /* Certain encodings have bits that are required to be zero.
 716          These are (z must be zero, y may be anything):
 717              001zy
 718              011zy
 719              1z00y
 720              1z01y
 721              1z1zz
 722       */
 723       switch (value & 0x14)
 724         {
 725         default:
 726         case 0:
 727           return 1;
 728         case 0x4:
 729           return (value & 0x2) == 0;
 730         case 0x10:
 731           return (value & 0x8) == 0;
 732         case 0x14:
 733           return value == 0x14;
 734         }
 735     }
 736   else
 737     {
 738       /* Certain encodings have bits that are required to be zero.
 739          These are (z must be zero, a & t may be anything):
 740              0000z
 741              0001z
 742              0100z
 743              0101z
 744              001at
 745              011at
 746              1a00t
 747              1a01t
 748              1z1zz
 749       */
 750       if ((value & 0x14) == 0)
 751         return (value & 0x1) == 0;
 752       else if ((value & 0x14) == 0x14)
 753         return value == 0x14;
 754       else
 755         return 1;
 756     }
 757 }
 758
 759 /* The BO field in a B form instruction.  Warn about attempts to set
 760    the field to an illegal value.  */
 761
 762 static unsigned long
 763 insert_bo (insn, value, dialect, errmsg)
 764      unsigned long insn;
 765      long value;
 766      int dialect;
 767      const char **errmsg;
 768 {
 769   if (errmsg != (const char **) NULL
 770       && ! valid_bo (value, dialect))
 771     *errmsg = _("invalid conditional option");
 772   return insn | ((value & 0x1f) << 21);
 773 }
 774
 775 static long
 776 extract_bo (insn, dialect, invalid)
 777      unsigned long insn;
 778      int dialect;
 779      int *invalid;
 780 {
 781   long value;
 782
 783   value = (insn >> 21) & 0x1f;
 784   if (invalid != (int *) NULL
 785       && ! valid_bo (value, dialect))
 786     *invalid = 1;
 787   return value;
 788 }
 789
 790 /* The BO field in a B form instruction when the + or - modifier is
 791    used.  This is like the BO field, but it must be even.  When
 792    extracting it, we force it to be even.  */
 793
 794 static unsigned long
 795 insert_boe (insn, value, dialect, errmsg)
 796      unsigned long insn;
 797      long value;
 798      int dialect;
 799      const char **errmsg;
 800 {
 801   if (errmsg != (const char **) NULL)
 802     {
 803       if (! valid_bo (value, dialect))
 804         *errmsg = _("invalid conditional option");
 805       else if ((value & 1) != 0)
 806         *errmsg = _("attempt to set y bit when using + or - modifier");
 807     }
 808   return insn | ((value & 0x1f) << 21);
 809 }
 810
 811 static long
 812 extract_boe (insn, dialect, invalid)
 813      unsigned long insn;
 814      int dialect;
 815      int *invalid;
 816 {
 817   long value;
 818
 819   value = (insn >> 21) & 0x1f;
 820   if (invalid != (int *) NULL
 821       && ! valid_bo (value, dialect))
 822     *invalid = 1;
 823   return value & 0x1e;
 824 }
 825
 826 /* The DS field in a DS form instruction.  This is like D, but the
 827    lower two bits are forced to zero.  */
 828
 829 /*ARGSUSED*/
 830 static unsigned long
 831 insert_ds (insn, value, dialect, errmsg)
 832      unsigned long insn;
 833      long value;
 834      int dialect ATTRIBUTE_UNUSED;
 835      const char **errmsg;
 836 {
 837   if ((value & 3) != 0 && errmsg != NULL)
 838     *errmsg = _("offset not a multiple of 4");
 839   return insn | (value & 0xfffc);
 840 }
 841
 842 /*ARGSUSED*/
 843 static long
 844 extract_ds (insn, dialect, invalid)
 845      unsigned long insn;
 846      int dialect ATTRIBUTE_UNUSED;
 847      int *invalid ATTRIBUTE_UNUSED;
 848 {
 849   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 850 }
 851
 852 /* The DE field in a DE form instruction.  */
 853
 854 /*ARGSUSED*/
 855 static unsigned long
 856 insert_de (insn, value, dialect, errmsg)
 857      unsigned long insn;
 858      long value;
 859      int dialect ATTRIBUTE_UNUSED;
 860      const char **errmsg;
 861 {
 862   if ((value > 2047 || value < -2048) && errmsg != NULL)
 863     *errmsg = _("offset not between -2048 and 2047");
 864   return insn | ((value << 4) & 0xfff0);
 865 }
 866
 867 /*ARGSUSED*/
 868 static long
 869 extract_de (insn, dialect, invalid)
 870      unsigned long insn;
 871      int dialect ATTRIBUTE_UNUSED;
 872      int *invalid ATTRIBUTE_UNUSED;
 873 {
 874   return (insn & 0xfff0) >> 4;
 875 }
 876
 877 /* The DES field in a DES form instruction.  */
 878
 879 /*ARGSUSED*/
 880 static unsigned long
 881 insert_des (insn, value, dialect, errmsg)
 882      unsigned long insn;
 883      long value;
 884      int dialect ATTRIBUTE_UNUSED;
 885      const char **errmsg;
 886 {
 887   if ((value > 8191 || value < -8192) && errmsg != NULL)
 888     *errmsg = _("offset not between -8192 and 8191");
 889   else if ((value & 3) != 0 && errmsg != NULL)
 890     *errmsg = _("offset not a multiple of 4");
 891   return insn | ((value << 2) & 0xfff0);
 892 }
 893
 894 /*ARGSUSED*/
 895 static long
 896 extract_des (insn, dialect, invalid)
 897      unsigned long insn;
 898      int dialect ATTRIBUTE_UNUSED;
 899      int *invalid ATTRIBUTE_UNUSED;
 900 {
 901   return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
 902 }
 903
 904 /* The LI field in an I form instruction.  The lower two bits are
 905    forced to zero.  */
 906
 907 /*ARGSUSED*/
 908 static unsigned long
 909 insert_li (insn, value, dialect, errmsg)
 910      unsigned long insn;
 911      long value;
 912      int dialect ATTRIBUTE_UNUSED;
 913      const char **errmsg;
 914 {
 915   if ((value & 3) != 0 && errmsg != (const char **) NULL)
 916     *errmsg = _("ignoring least significant bits in branch offset");
 917   return insn | (value & 0x3fffffc);
 918 }
 919
 920 /*ARGSUSED*/
 921 static long
 922 extract_li (insn, dialect, invalid)
 923      unsigned long insn;
 924      int dialect ATTRIBUTE_UNUSED;
 925      int *invalid ATTRIBUTE_UNUSED;
 926 {
 927   return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
 928 }
 929
 930 /* The MB and ME fields in an M form instruction expressed as a single
 931    operand which is itself a bitmask.  The extraction function always
 932    marks it as invalid, since we never want to recognize an
 933    instruction which uses a field of this type.  */
 934
 935 static unsigned long
 936 insert_mbe (insn, value, dialect, errmsg)
 937      unsigned long insn;
 938      long value;
 939      int dialect ATTRIBUTE_UNUSED;
 940      const char **errmsg;
 941 {
 942   unsigned long uval, mask;
 943   int mb, me, mx, count, last;
 944
 945   uval = value;
 946
 947   if (uval == 0)
 948     {
 949       if (errmsg != (const char **) NULL)
 950         *errmsg = _("illegal bitmask");
 951       return insn;
 952     }
 953
 954   mb = 0;
 955   me = 32;
 956   if ((uval & 1) != 0)
 957     last = 1;
 958   else
 959     last = 0;
 960   count = 0;
 961
 962   /* mb: location of last 0->1 transition */
 963   /* me: location of last 1->0 transition */
 964   /* count: # transitions */
 965
 966   for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
 967     {
 968       if ((uval & mask) && !last)
 969         {
 970           ++count;
 971           mb = mx;
 972           last = 1;
 973         }
 974       else if (!(uval & mask) && last)
 975         {
 976           ++count;
 977           me = mx;
 978           last = 0;
 979         }
 980     }
 981   if (me == 0)
 982     me = 32;
 983
 984   if (count != 2 && (count != 0 || ! last))
 985     {
 986       if (errmsg != (const char **) NULL)
 987         *errmsg = _("illegal bitmask");
 988     }
 989
 990   return insn | (mb << 6) | ((me - 1) << 1);
 991 }
 992
 993 static long
 994 extract_mbe (insn, dialect, invalid)
 995      unsigned long insn;
 996      int dialect ATTRIBUTE_UNUSED;
 997      int *invalid;
 998 {
 999   long ret;
1000   int mb, me;
1001   int i;
1002
1003   if (invalid != (int *) NULL)
1004     *invalid = 1;
1005
1006   mb = (insn >> 6) & 0x1f;
1007   me = (insn >> 1) & 0x1f;
1008   if (mb < me + 1)
1009     {
1010       ret = 0;
1011       for (i = mb; i <= me; i++)
1012         ret |= (long) 1 << (31 - i);
1013     }
1014   else if (mb == me + 1)
1015     ret = ~0;
1016   else /* (mb > me + 1) */
1017     {
1018       ret = ~ (long) 0;
1019       for (i = me + 1; i < mb; i++)
1020         ret &= ~ ((long) 1 << (31 - i));
1021     }
1022   return ret;
1023 }
1024
1025 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1026    is wrapped to the low end.  */
1027
1028 /*ARGSUSED*/
1029 static unsigned long
1030 insert_mb6 (insn, value, dialect, errmsg)
1031      unsigned long insn;
1032      long value;
1033      int dialect ATTRIBUTE_UNUSED;
1034      const char **errmsg ATTRIBUTE_UNUSED;
1035 {
1036   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1037 }
1038
1039 /*ARGSUSED*/
1040 static long
1041 extract_mb6 (insn, dialect, invalid)
1042      unsigned long insn;
1043      int dialect ATTRIBUTE_UNUSED;
1044      int *invalid ATTRIBUTE_UNUSED;
1045 {
1046   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1047 }
1048
1049 /* The NB field in an X form instruction.  The value 32 is stored as
1050    0.  */
1051
1052 static unsigned long
1053 insert_nb (insn, value, dialect, errmsg)
1054      unsigned long insn;
1055      long value;
1056      int dialect ATTRIBUTE_UNUSED;
1057      const char **errmsg;
1058 {
1059   if (value < 0 || value > 32)
1060     *errmsg = _("value out of range");
1061   if (value == 32)
1062     value = 0;
1063   return insn | ((value & 0x1f) << 11);
1064 }
1065
1066 /*ARGSUSED*/
1067 static long
1068 extract_nb (insn, dialect, invalid)
1069      unsigned long insn;
1070      int dialect ATTRIBUTE_UNUSED;
1071      int *invalid ATTRIBUTE_UNUSED;
1072 {
1073   long ret;
1074
1075   ret = (insn >> 11) & 0x1f;
1076   if (ret == 0)
1077     ret = 32;
1078   return ret;
1079 }
1080
1081 /* The NSI field in a D form instruction.  This is the same as the SI
1082    field, only negated.  The extraction function always marks it as
1083    invalid, since we never want to recognize an instruction which uses
1084    a field of this type.  */
1085
1086 /*ARGSUSED*/
1087 static unsigned long
1088 insert_nsi (insn, value, dialect, errmsg)
1089      unsigned long insn;
1090      long value;
1091      int dialect ATTRIBUTE_UNUSED;
1092      const char **errmsg ATTRIBUTE_UNUSED;
1093 {
1094   return insn | ((- value) & 0xffff);
1095 }
1096
1097 static long
1098 extract_nsi (insn, dialect, invalid)
1099      unsigned long insn;
1100      int dialect ATTRIBUTE_UNUSED;
1101      int *invalid;
1102 {
1103   if (invalid != (int *) NULL)
1104     *invalid = 1;
1105   return - (((insn & 0xffff) ^ 0x8000) - 0x8000);
1106 }
1107
1108 /* The RA field in a D or X form instruction which is an updating
1109    load, which means that the RA field may not be zero and may not
1110    equal the RT field.  */
1111
1112 static unsigned long
1113 insert_ral (insn, value, dialect, errmsg)
1114      unsigned long insn;
1115      long value;
1116      int dialect ATTRIBUTE_UNUSED;
1117      const char **errmsg;
1118 {
1119   if (value == 0
1120       || (unsigned long) value == ((insn >> 21) & 0x1f))
1121     *errmsg = "invalid register operand when updating";
1122   return insn | ((value & 0x1f) << 16);
1123 }
1124
1125 /* The RA field in an lmw instruction, which has special value
1126    restrictions.  */
1127
1128 static unsigned long
1129 insert_ram (insn, value, dialect, errmsg)
1130      unsigned long insn;
1131      long value;
1132      int dialect ATTRIBUTE_UNUSED;
1133      const char **errmsg;
1134 {
1135   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1136     *errmsg = _("index register in load range");
1137   return insn | ((value & 0x1f) << 16);
1138 }
1139
1140 /* The RA field in a D or X form instruction which is an updating
1141    store or an updating floating point load, which means that the RA
1142    field may not be zero.  */
1143
1144 static unsigned long
1145 insert_ras (insn, value, dialect, errmsg)
1146      unsigned long insn;
1147      long value;
1148      int dialect ATTRIBUTE_UNUSED;
1149      const char **errmsg;
1150 {
1151   if (value == 0)
1152     *errmsg = _("invalid register operand when updating");
1153   return insn | ((value & 0x1f) << 16);
1154 }
1155
1156 /* The RB field in an X form instruction when it must be the same as
1157    the RS field in the instruction.  This is used for extended
1158    mnemonics like mr.  This operand is marked FAKE.  The insertion
1159    function just copies the BT field into the BA field, and the
1160    extraction function just checks that the fields are the same.  */
1161
1162 /*ARGSUSED*/
1163 static unsigned long
1164 insert_rbs (insn, value, dialect, errmsg)
1165      unsigned long insn;
1166      long value ATTRIBUTE_UNUSED;
1167      int dialect ATTRIBUTE_UNUSED;
1168      const char **errmsg ATTRIBUTE_UNUSED;
1169 {
1170   return insn | (((insn >> 21) & 0x1f) << 11);
1171 }
1172
1173 static long
1174 extract_rbs (insn, dialect, invalid)
1175      unsigned long insn;
1176      int dialect ATTRIBUTE_UNUSED;
1177      int *invalid;
1178 {
1179   if (invalid != (int *) NULL
1180       && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1181     *invalid = 1;
1182   return 0;
1183 }
1184
1185 /* The SH field in an MD form instruction.  This is split.  */
1186
1187 /*ARGSUSED*/
1188 static unsigned long
1189 insert_sh6 (insn, value, dialect, errmsg)
1190      unsigned long insn;
1191      long value;
1192      int dialect ATTRIBUTE_UNUSED;
1193      const char **errmsg ATTRIBUTE_UNUSED;
1194 {
1195   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1196 }
1197
1198 /*ARGSUSED*/
1199 static long
1200 extract_sh6 (insn, dialect, invalid)
1201      unsigned long insn;
1202      int dialect ATTRIBUTE_UNUSED;
1203      int *invalid ATTRIBUTE_UNUSED;
1204 {
1205   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1206 }
1207
1208 /* The SPR field in an XFX form instruction.  This is flipped--the
1209    lower 5 bits are stored in the upper 5 and vice- versa.  */
1210
1211 static unsigned long
1212 insert_spr (insn, value, dialect, errmsg)
1213      unsigned long insn;
1214      long value;
1215      int dialect ATTRIBUTE_UNUSED;
1216      const char **errmsg ATTRIBUTE_UNUSED;
1217 {
1218   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1219 }
1220
1221 static long
1222 extract_spr (insn, dialect, invalid)
1223      unsigned long insn;
1224      int dialect ATTRIBUTE_UNUSED;
1225      int *invalid ATTRIBUTE_UNUSED;
1226 {
1227   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1228 }
1229
1230 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1231    is optional.  When TBR is omitted, it must be inserted as 268 (the
1232    magic number of the TB register).  These functions treat 0
1233    (indicating an omitted optional operand) as 268.  This means that
1234    ``mftb 4,0'' is not handled correctly.  This does not matter very
1235    much, since the architecture manual does not define mftb as
1236    accepting any values other than 268 or 269.  */
1237
1238 #define TB (268)
1239
1240 static unsigned long
1241 insert_tbr (insn, value, dialect, errmsg)
1242      unsigned long insn;
1243      long value;
1244      int dialect ATTRIBUTE_UNUSED;
1245      const char **errmsg ATTRIBUTE_UNUSED;
1246 {
1247   if (value == 0)
1248     value = TB;
1249   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1250 }
1251
1252 static long
1253 extract_tbr (insn, dialect, invalid)
1254      unsigned long insn;
1255      int dialect ATTRIBUTE_UNUSED;
1256      int *invalid ATTRIBUTE_UNUSED;
1257 {
1258   long ret;
1259
1260   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1261   if (ret == TB)
1262     ret = 0;
1263   return ret;
1264 }
1265 \f
1266 /* Macros used to form opcodes.  */
1267
1268 /* The main opcode.  */
1269 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1270 #define OP_MASK OP (0x3f)
1271
1272 /* The main opcode combined with a trap code in the TO field of a D
1273    form instruction.  Used for extended mnemonics for the trap
1274    instructions.  */
1275 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1276 #define OPTO_MASK (OP_MASK | TO_MASK)
1277
1278 /* The main opcode combined with a comparison size bit in the L field
1279    of a D form or X form instruction.  Used for extended mnemonics for
1280    the comparison instructions.  */
1281 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1282 #define OPL_MASK OPL (0x3f,1)
1283
1284 /* An A form instruction.  */
1285 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1286 #define A_MASK A (0x3f, 0x1f, 1)
1287
1288 /* An A_MASK with the FRB field fixed.  */
1289 #define AFRB_MASK (A_MASK | FRB_MASK)
1290
1291 /* An A_MASK with the FRC field fixed.  */
1292 #define AFRC_MASK (A_MASK | FRC_MASK)
1293
1294 /* An A_MASK with the FRA and FRC fields fixed.  */
1295 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1296
1297 /* A B form instruction.  */
1298 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1299 #define B_MASK B (0x3f, 1, 1)
1300
1301 /* A B form instruction setting the BO field.  */
1302 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1303 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1304
1305 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1306    matching a conditional branch regardless of the setting of the y
1307    bit.  Similarly for the 'at' bits used for 64 bit branch hints.  */
1308 #define Y_MASK   (((unsigned long) 1) << 21)
1309 #define AT1_MASK (((unsigned long) 3) << 21)
1310 #define AT2_MASK (((unsigned long) 9) << 21)
1311 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1312 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1313
1314 /* A B form instruction setting the BO field and the condition bits of
1315    the BI field.  */
1316 #define BBOCB(op, bo, cb, aa, lk) \
1317   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1318 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1319
1320 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1321 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1322 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1323 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1324
1325 /* A BBOYCB_MASK in which the BI field is fixed.  */
1326 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1327 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1328
1329 /* The main opcode mask with the RA field clear.  */
1330 #define DRA_MASK (OP_MASK | RA_MASK)
1331
1332 /* A DS form instruction.  */
1333 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1334 #define DS_MASK DSO (0x3f, 3)
1335
1336 /* A DE form instruction.  */
1337 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1338 #define DE_MASK DEO (0x3e, 0xf)
1339
1340 /* An M form instruction.  */
1341 #define M(op, rc) (OP (op) | ((rc) & 1))
1342 #define M_MASK M (0x3f, 1)
1343
1344 /* An M form instruction with the ME field specified.  */
1345 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1346
1347 /* An M_MASK with the MB and ME fields fixed.  */
1348 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1349
1350 /* An M_MASK with the SH and ME fields fixed.  */
1351 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1352
1353 /* An MD form instruction.  */
1354 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1355 #define MD_MASK MD (0x3f, 0x7, 1)
1356
1357 /* An MD_MASK with the MB field fixed.  */
1358 #define MDMB_MASK (MD_MASK | MB6_MASK)
1359
1360 /* An MD_MASK with the SH field fixed.  */
1361 #define MDSH_MASK (MD_MASK | SH6_MASK)
1362
1363 /* An MDS form instruction.  */
1364 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1365 #define MDS_MASK MDS (0x3f, 0xf, 1)
1366
1367 /* An MDS_MASK with the MB field fixed.  */
1368 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1369
1370 /* An SC form instruction.  */
1371 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1372 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1373
1374 /* An VX form instruction. */
1375 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1376
1377 /* The mask for an VX form instruction. */
1378 #define VX_MASK VX(0x3f, 0x7ff)
1379
1380 /* An VA form instruction. */
1381 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1382
1383 /* The mask for an VA form instruction. */
1384 #define VXA_MASK VXA(0x3f, 0x3f)
1385
1386 /* An VXR form instruction. */
1387 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1388
1389 /* The mask for a VXR form instruction. */
1390 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1391
1392 /* An X form instruction.  */
1393 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1394
1395 /* An X form instruction with the RC bit specified.  */
1396 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1397
1398 /* The mask for an X form instruction.  */
1399 #define X_MASK XRC (0x3f, 0x3ff, 1)
1400
1401 /* An X_MASK with the RA field fixed.  */
1402 #define XRA_MASK (X_MASK | RA_MASK)
1403
1404 /* An X_MASK with the RB field fixed.  */
1405 #define XRB_MASK (X_MASK | RB_MASK)
1406
1407 /* An X_MASK with the RT field fixed.  */
1408 #define XRT_MASK (X_MASK | RT_MASK)
1409
1410 /* An X_MASK with the RA and RB fields fixed.  */
1411 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1412
1413 /* An X_MASK with the RT and RA fields fixed.  */
1414 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1415
1416 /* An X form comparison instruction.  */
1417 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1418
1419 /* The mask for an X form comparison instruction.  */
1420 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1421
1422 /* The mask for an X form comparison instruction with the L field
1423    fixed.  */
1424 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1425
1426 /* An X form trap instruction with the TO field specified.  */
1427 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1428 #define XTO_MASK (X_MASK | TO_MASK)
1429
1430 /* An X form tlb instruction with the SH field specified.  */
1431 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1432 #define XTLB_MASK (X_MASK | SH_MASK)
1433
1434 /* An X form sync instruction.  */
1435 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1436
1437 /* An X form sync instruction with everything filled in except the LS field.  */
1438 #define XSYNC_MASK (0xff9fffff)
1439
1440 /* An X form AltiVec dss instruction.  */
1441 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1442 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1443
1444 /* An XFL form instruction.  */
1445 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1446 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1447
1448 /* An XL form instruction with the LK field set to 0.  */
1449 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1450
1451 /* An XL form instruction which uses the LK field.  */
1452 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1453
1454 /* The mask for an XL form instruction.  */
1455 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1456
1457 /* An XL form instruction which explicitly sets the BO field.  */
1458 #define XLO(op, bo, xop, lk) \
1459   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1460 #define XLO_MASK (XL_MASK | BO_MASK)
1461
1462 /* An XL form instruction which explicitly sets the y bit of the BO
1463    field.  */
1464 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1465 #define XLYLK_MASK (XL_MASK | Y_MASK)
1466
1467 /* An XL form instruction which sets the BO field and the condition
1468    bits of the BI field.  */
1469 #define XLOCB(op, bo, cb, xop, lk) \
1470   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1471 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1472
1473 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1474 #define XLBB_MASK (XL_MASK | BB_MASK)
1475 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1476 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1477
1478 /* An XL_MASK with the BO and BB fields fixed.  */
1479 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1480
1481 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1482 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1483
1484 /* An XO form instruction.  */
1485 #define XO(op, xop, oe, rc) \
1486   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1487 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1488
1489 /* An XO_MASK with the RB field fixed.  */
1490 #define XORB_MASK (XO_MASK | RB_MASK)
1491
1492 /* An XS form instruction.  */
1493 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1494 #define XS_MASK XS (0x3f, 0x1ff, 1)
1495
1496 /* A mask for the FXM version of an XFX form instruction.  */
1497 #define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1498
1499 /* An XFX form instruction with the FXM field filled in.  */
1500 #define XFXM(op, xop, fxm) \
1501   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1502
1503 /* An XFX form instruction with the SPR field filled in.  */
1504 #define XSPR(op, xop, spr) \
1505   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1506 #define XSPR_MASK (X_MASK | SPR_MASK)
1507
1508 /* An XFX form instruction with the SPR field filled in except for the
1509    SPRBAT field.  */
1510 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1511
1512 /* An XFX form instruction with the SPR field filled in except for the
1513    SPRG field.  */
1514 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1515
1516 /* An X form instruction with everything filled in except the E field.  */
1517 #define XE_MASK (0xffff7fff)
1518
1519 /* The BO encodings used in extended conditional branch mnemonics.  */
1520 #define BODNZF  (0x0)
1521 #define BODNZFP (0x1)
1522 #define BODZF   (0x2)
1523 #define BODZFP  (0x3)
1524 #define BODNZT  (0x8)
1525 #define BODNZTP (0x9)
1526 #define BODZT   (0xa)
1527 #define BODZTP  (0xb)
1528
1529 #define BOF     (0x4)
1530 #define BOFP    (0x5)
1531 #define BOFM64  (0x6)
1532 #define BOFP64  (0x7)
1533 #define BOT     (0xc)
1534 #define BOTP    (0xd)
1535 #define BOTM64  (0xe)
1536 #define BOTP64  (0xf)
1537
1538 #define BODNZ   (0x10)
1539 #define BODNZP  (0x11)
1540 #define BODZ    (0x12)
1541 #define BODZP   (0x13)
1542 #define BODNZM64 (0x18)
1543 #define BODNZP64 (0x19)
1544 #define BODZM64 (0x1a)
1545 #define BODZP64 (0x1b)
1546
1547 #define BOU     (0x14)
1548
1549 /* The BI condition bit encodings used in extended conditional branch
1550    mnemonics.  */
1551 #define CBLT    (0)
1552 #define CBGT    (1)
1553 #define CBEQ    (2)
1554 #define CBSO    (3)
1555
1556 /* The TO encodings used in extended trap mnemonics.  */
1557 #define TOLGT   (0x1)
1558 #define TOLLT   (0x2)
1559 #define TOEQ    (0x4)
1560 #define TOLGE   (0x5)
1561 #define TOLNL   (0x5)
1562 #define TOLLE   (0x6)
1563 #define TOLNG   (0x6)
1564 #define TOGT    (0x8)
1565 #define TOGE    (0xc)
1566 #define TONL    (0xc)
1567 #define TOLT    (0x10)
1568 #define TOLE    (0x14)
1569 #define TONG    (0x14)
1570 #define TONE    (0x18)
1571 #define TOU     (0x1f)
1572 \f
1573 /* Smaller names for the flags so each entry in the opcodes table will
1574    fit on a single line.  */
1575 #undef  PPC
1576 #define PPC     PPC_OPCODE_PPC | PPC_OPCODE_ANY
1577 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1578 #define PPCCOM32 PPC_OPCODE_32 | PPCCOM
1579 #define PPCCOM64 PPC_OPCODE_64 | PPCCOM
1580 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1581 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1582 #define PPCONLY PPC_OPCODE_PPC
1583 #define PPC403  PPC_OPCODE_403
1584 #define PPC405  PPC403
1585 #define PPC750  PPC
1586 #define PPC860  PPC
1587 #define PPCVEC  PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
1588 #define POWER   PPC_OPCODE_POWER | PPC_OPCODE_ANY
1589 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1590 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1591 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1592 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1593 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1594 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1595 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1596 #define MFDEC1  PPC_OPCODE_POWER
1597 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601
1598 #define BOOKE   PPC_OPCODE_BOOKE
1599 #define BOOKE64 PPC_OPCODE_BOOKE64
1600 \f
1601 /* The opcode table.
1602
1603    The format of the opcode table is:
1604
1605    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
1606
1607    NAME is the name of the instruction.
1608    OPCODE is the instruction opcode.
1609    MASK is the opcode mask; this is used to tell the disassembler
1610      which bits in the actual opcode must match OPCODE.
1611    FLAGS are flags indicated what processors support the instruction.
1612    OPERANDS is the list of operands.
1613
1614    The disassembler reads the table in order and prints the first
1615    instruction which matches, so this table is sorted to put more
1616    specific instructions before more general instructions.  It is also
1617    sorted by major opcode.  */
1618
1619 const struct powerpc_opcode powerpc_opcodes[] = {
1620 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
1621 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
1622 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
1623 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
1624 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
1625 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
1626 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
1627 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
1628 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
1629 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
1630 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
1631 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
1632 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
1633 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
1634 { "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },
1635
1636 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1637 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1638 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1639 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1640 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
1641 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
1642 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1643 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1644 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
1645 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
1646 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1647 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1648 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
1649 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
1650 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1651 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1652 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1653 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1654 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
1655 { "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
1656 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1657 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1658 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1659 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1660 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
1661 { "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
1662 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1663 { "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1664 { "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
1665 { "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },
1666
1667 { "macchw",     XO(4,172,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1668 { "macchw.",    XO(4,172,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1669 { "macchwo",    XO(4,172,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1670 { "macchwo.",   XO(4,172,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1671 { "macchws",    XO(4,236,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1672 { "macchws.",   XO(4,236,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1673 { "macchwso",   XO(4,236,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1674 { "macchwso.",  XO(4,236,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1675 { "macchwsu",   XO(4,204,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1676 { "macchwsu.",  XO(4,204,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1677 { "macchwsuo",  XO(4,204,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1678 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1679 { "macchwu",    XO(4,140,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1680 { "macchwu.",   XO(4,140,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1681 { "macchwuo",   XO(4,140,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1682 { "macchwuo.",  XO(4,140,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1683 { "machhw",     XO(4,44,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1684 { "machhw.",    XO(4,44,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1685 { "machhwo",    XO(4,44,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1686 { "machhwo.",   XO(4,44,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1687 { "machhws",    XO(4,108,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1688 { "machhws.",   XO(4,108,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1689 { "machhwso",   XO(4,108,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1690 { "machhwso.",  XO(4,108,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1691 { "machhwsu",   XO(4,76,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1692 { "machhwsu.",  XO(4,76,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1693 { "machhwsuo",  XO(4,76,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1694 { "machhwsuo.", XO(4,76,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1695 { "machhwu",    XO(4,12,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1696 { "machhwu.",   XO(4,12,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1697 { "machhwuo",   XO(4,12,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1698 { "machhwuo.",  XO(4,12,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1699 { "maclhw",     XO(4,428,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1700 { "maclhw.",    XO(4,428,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1701 { "maclhwo",    XO(4,428,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1702 { "maclhwo.",   XO(4,428,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1703 { "maclhws",    XO(4,492,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1704 { "maclhws.",   XO(4,492,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1705 { "maclhwso",   XO(4,492,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1706 { "maclhwso.",  XO(4,492,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1707 { "maclhwsu",   XO(4,460,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1708 { "maclhwsu.",  XO(4,460,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1709 { "maclhwsuo",  XO(4,460,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1710 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1711 { "maclhwu",    XO(4,396,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1712 { "maclhwu.",   XO(4,396,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1713 { "maclhwuo",   XO(4,396,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1714 { "maclhwuo.",  XO(4,396,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1715 { "mulchw",     XRC(4,168,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1716 { "mulchw.",    XRC(4,168,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1717 { "mulchwu",    XRC(4,136,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1718 { "mulchwu.",   XRC(4,136,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1719 { "mulhhw",     XRC(4,40,0),   X_MASK,  PPC405,         { RT, RA, RB } },
1720 { "mulhhw.",    XRC(4,40,1),   X_MASK,  PPC405,         { RT, RA, RB } },
1721 { "mulhhwu",    XRC(4,8,0),    X_MASK,  PPC405,         { RT, RA, RB } },
1722 { "mulhhwu.",   XRC(4,8,1),    X_MASK,  PPC405,         { RT, RA, RB } },
1723 { "mullhw",     XRC(4,424,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1724 { "mullhw.",    XRC(4,424,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1725 { "mullhwu",    XRC(4,392,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1726 { "mullhwu.",   XRC(4,392,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1727 { "nmacchw",    XO(4,174,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1728 { "nmacchw.",   XO(4,174,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1729 { "nmacchwo",   XO(4,174,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1730 { "nmacchwo.",  XO(4,174,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1731 { "nmacchws",   XO(4,238,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1732 { "nmacchws.",  XO(4,238,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1733 { "nmacchwso",  XO(4,238,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1734 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1735 { "nmachhw",    XO(4,46,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1736 { "nmachhw.",   XO(4,46,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1737 { "nmachhwo",   XO(4,46,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1738 { "nmachhwo.",  XO(4,46,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1739 { "nmachhws",   XO(4,110,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1740 { "nmachhws.",  XO(4,110,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1741 { "nmachhwso",  XO(4,110,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1742 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1743 { "nmaclhw",    XO(4,430,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1744 { "nmaclhw.",   XO(4,430,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1745 { "nmaclhwo",   XO(4,430,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1746 { "nmaclhwo.",  XO(4,430,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1747 { "nmaclhws",   XO(4,494,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1748 { "nmaclhws.",  XO(4,494,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1749 { "nmaclhwso",  XO(4,494,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1750 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1751 { "mfvscr",  VX(4, 1540), VX_MASK,      PPCVEC,         { VD } },
1752 { "mtvscr",  VX(4, 1604), VX_MASK,      PPCVEC,         { VB } },
1753 { "vaddcuw", VX(4,  384), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1754 { "vaddfp",  VX(4,   10), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1755 { "vaddsbs", VX(4,  768), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1756 { "vaddshs", VX(4,  832), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1757 { "vaddsws", VX(4,  896), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1758 { "vaddubm", VX(4,    0), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1759 { "vaddubs", VX(4,  512), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1760 { "vadduhm", VX(4,   64), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1761 { "vadduhs", VX(4,  576), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1762 { "vadduwm", VX(4,  128), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1763 { "vadduws", VX(4,  640), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1764 { "vand",    VX(4, 1028), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1765 { "vandc",   VX(4, 1092), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1766 { "vavgsb",  VX(4, 1282), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1767 { "vavgsh",  VX(4, 1346), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1768 { "vavgsw",  VX(4, 1410), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1769 { "vavgub",  VX(4, 1026), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1770 { "vavguh",  VX(4, 1090), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1771 { "vavguw",  VX(4, 1154), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1772 { "vcfsx",   VX(4,  842), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1773 { "vcfux",   VX(4,  778), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1774 { "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1775 { "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1776 { "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1777 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1778 { "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1779 { "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1780 { "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1781 { "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1782 { "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1783 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1784 { "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1785 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1786 { "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1787 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1788 { "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1789 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1790 { "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1791 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1792 { "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1793 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1794 { "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1795 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1796 { "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1797 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1798 { "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1799 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1800 { "vctsxs",    VX(4,  970), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1801 { "vctuxs",    VX(4,  906), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1802 { "vexptefp",  VX(4,  394), VX_MASK,    PPCVEC,         { VD, VB } },
1803 { "vlogefp",   VX(4,  458), VX_MASK,    PPCVEC,         { VD, VB } },
1804 { "vmaddfp",   VXA(4,  46), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1805 { "vmaxfp",    VX(4, 1034), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1806 { "vmaxsb",    VX(4,  258), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1807 { "vmaxsh",    VX(4,  322), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1808 { "vmaxsw",    VX(4,  386), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1809 { "vmaxub",    VX(4,    2), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1810 { "vmaxuh",    VX(4,   66), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1811 { "vmaxuw",    VX(4,  130), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1812 { "vmhaddshs", VXA(4,  32), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1813 { "vmhraddshs", VXA(4, 33), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1814 { "vminfp",    VX(4, 1098), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1815 { "vminsb",    VX(4,  770), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1816 { "vminsh",    VX(4,  834), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1817 { "vminsw",    VX(4,  898), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1818 { "vminub",    VX(4,  514), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1819 { "vminuh",    VX(4,  578), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1820 { "vminuw",    VX(4,  642), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1821 { "vmladduhm", VXA(4,  34), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1822 { "vmrghb",    VX(4,   12), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1823 { "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1824 { "vmrghw",    VX(4,  140), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1825 { "vmrglb",    VX(4,  268), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1826 { "vmrglh",    VX(4,  332), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1827 { "vmrglw",    VX(4,  396), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1828 { "vmsummbm",  VXA(4,  37), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1829 { "vmsumshm",  VXA(4,  40), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1830 { "vmsumshs",  VXA(4,  41), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1831 { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1832 { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1833 { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1834 { "vmulesb",   VX(4,  776), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1835 { "vmulesh",   VX(4,  840), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1836 { "vmuleub",   VX(4,  520), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1837 { "vmuleuh",   VX(4,  584), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1838 { "vmulosb",   VX(4,  264), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1839 { "vmulosh",   VX(4,  328), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1840 { "vmuloub",   VX(4,    8), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1841 { "vmulouh",   VX(4,   72), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1842 { "vnmsubfp",  VXA(4,  47), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
1843 { "vnor",      VX(4, 1284), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1844 { "vor",       VX(4, 1156), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1845 { "vperm",     VXA(4,  43), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1846 { "vpkpx",     VX(4,  782), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1847 { "vpkshss",   VX(4,  398), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1848 { "vpkshus",   VX(4,  270), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1849 { "vpkswss",   VX(4,  462), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1850 { "vpkswus",   VX(4,  334), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1851 { "vpkuhum",   VX(4,   14), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1852 { "vpkuhus",   VX(4,  142), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1853 { "vpkuwum",   VX(4,   78), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1854 { "vpkuwus",   VX(4,  206), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1855 { "vrefp",     VX(4,  266), VX_MASK,    PPCVEC,         { VD, VB } },
1856 { "vrfim",     VX(4,  714), VX_MASK,    PPCVEC,         { VD, VB } },
1857 { "vrfin",     VX(4,  522), VX_MASK,    PPCVEC,         { VD, VB } },
1858 { "vrfip",     VX(4,  650), VX_MASK,    PPCVEC,         { VD, VB } },
1859 { "vrfiz",     VX(4,  586), VX_MASK,    PPCVEC,         { VD, VB } },
1860 { "vrlb",      VX(4,    4), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1861 { "vrlh",      VX(4,   68), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1862 { "vrlw",      VX(4,  132), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1863 { "vrsqrtefp", VX(4,  330), VX_MASK,    PPCVEC,         { VD, VB } },
1864 { "vsel",      VXA(4,  42), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1865 { "vsl",       VX(4,  452), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1866 { "vslb",      VX(4,  260), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1867 { "vsldoi",    VXA(4,  44), VXA_MASK,   PPCVEC,         { VD, VA, VB, SHB } },
1868 { "vslh",      VX(4,  324), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1869 { "vslo",      VX(4, 1036), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1870 { "vslw",      VX(4,  388), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1871 { "vspltb",    VX(4,  524), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1872 { "vsplth",    VX(4,  588), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1873 { "vspltisb",  VX(4,  780), VX_MASK,    PPCVEC,         { VD, SIMM } },
1874 { "vspltish",  VX(4,  844), VX_MASK,    PPCVEC,         { VD, SIMM } },
1875 { "vspltisw",  VX(4,  908), VX_MASK,    PPCVEC,         { VD, SIMM } },
1876 { "vspltw",    VX(4,  652), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1877 { "vsr",       VX(4,  708), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1878 { "vsrab",     VX(4,  772), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1879 { "vsrah",     VX(4,  836), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1880 { "vsraw",     VX(4,  900), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1881 { "vsrb",      VX(4,  516), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1882 { "vsrh",      VX(4,  580), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1883 { "vsro",      VX(4, 1100), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1884 { "vsrw",      VX(4,  644), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1885 { "vsubcuw",   VX(4, 1408), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1886 { "vsubfp",    VX(4,   74), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1887 { "vsubsbs",   VX(4, 1792), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1888 { "vsubshs",   VX(4, 1856), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1889 { "vsubsws",   VX(4, 1920), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1890 { "vsububm",   VX(4, 1024), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1891 { "vsububs",   VX(4, 1536), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1892 { "vsubuhm",   VX(4, 1088), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1893 { "vsubuhs",   VX(4, 1600), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1894 { "vsubuwm",   VX(4, 1152), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1895 { "vsubuws",   VX(4, 1664), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1896 { "vsumsws",   VX(4, 1928), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1897 { "vsum2sws",  VX(4, 1672), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1898 { "vsum4sbs",  VX(4, 1800), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1899 { "vsum4shs",  VX(4, 1608), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1900 { "vsum4ubs",  VX(4, 1544), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1901 { "vupkhpx",   VX(4,  846), VX_MASK,    PPCVEC,         { VD, VB } },
1902 { "vupkhsb",   VX(4,  526), VX_MASK,    PPCVEC,         { VD, VB } },
1903 { "vupkhsh",   VX(4,  590), VX_MASK,    PPCVEC,         { VD, VB } },
1904 { "vupklpx",   VX(4,  974), VX_MASK,    PPCVEC,         { VD, VB } },
1905 { "vupklsb",   VX(4,  654), VX_MASK,    PPCVEC,         { VD, VB } },
1906 { "vupklsh",   VX(4,  718), VX_MASK,    PPCVEC,         { VD, VB } },
1907 { "vxor",      VX(4, 1220), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1908
1909 { "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
1910 { "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
1911
1912 { "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
1913 { "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
1914
1915 { "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },
1916
1917 { "bce",     B(9,0,0),  B_MASK,         BOOKE64,        { BO, BI, BD } },
1918 { "bcel",    B(9,0,1),  B_MASK,         BOOKE64,        { BO, BI, BD } },
1919 { "bcea",    B(9,1,0),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
1920 { "bcela",   B(9,1,1),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
1921
1922 { "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
1923 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
1924 { "cmpli",   OP(10),    OP_MASK,        PPCONLY,        { BF, L, RA, UI } },
1925 { "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },
1926
1927 { "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
1928 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
1929 { "cmpi",    OP(11),    OP_MASK,        PPCONLY,        { BF, L, RA, SI } },
1930 { "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },
1931
1932 { "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1933 { "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
1934 { "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1935
1936 { "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1937 { "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
1938 { "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1939
1940 { "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
1941 { "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
1942 { "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1943 { "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA } },
1944 { "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1945 { "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA } },
1946
1947 { "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
1948 { "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
1949 { "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA,SISIGNOPT } },
1950 { "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA,SISIGNOPT } },
1951 { "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1952
1953 { "bdnz-",   BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM,   { BDM } },
1954 { "bdnz+",   BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM,   { BDP } },
1955 { "bdnz",    BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM,   { BD } },
1956 { "bdn",     BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM,   { BD } },
1957 { "bdnzl-",  BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM,   { BDM } },
1958 { "bdnzl+",  BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM,   { BDP } },
1959 { "bdnzl",   BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM,   { BD } },
1960 { "bdnl",    BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM,   { BD } },
1961 { "bdnza-",  BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM,   { BDMA } },
1962 { "bdnza+",  BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM,   { BDPA } },
1963 { "bdnza",   BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM,   { BDA } },
1964 { "bdna",    BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM,   { BDA } },
1965 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM,   { BDMA } },
1966 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM,   { BDPA } },
1967 { "bdnzla",  BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM,   { BDA } },
1968 { "bdnla",   BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM,   { BDA } },
1969 { "bdz-",    BBO(16,BODZ,0,0),  BBOATBI_MASK, PPCCOM,   { BDM } },
1970 { "bdz+",    BBO(16,BODZ,0,0),  BBOATBI_MASK, PPCCOM,   { BDP } },
1971 { "bdz",     BBO(16,BODZ,0,0),  BBOATBI_MASK, COM,      { BD } },
1972 { "bdzl-",   BBO(16,BODZ,0,1),  BBOATBI_MASK, PPCCOM,   { BDM } },
1973 { "bdzl+",   BBO(16,BODZ,0,1),  BBOATBI_MASK, PPCCOM,   { BDP } },
1974 { "bdzl",    BBO(16,BODZ,0,1),  BBOATBI_MASK, COM,      { BD } },
1975 { "bdza-",   BBO(16,BODZ,1,0),  BBOATBI_MASK, PPCCOM,   { BDMA } },
1976 { "bdza+",   BBO(16,BODZ,1,0),  BBOATBI_MASK, PPCCOM,   { BDPA } },
1977 { "bdza",    BBO(16,BODZ,1,0),  BBOATBI_MASK, COM,      { BDA } },
1978 { "bdzla-",  BBO(16,BODZ,1,1),  BBOATBI_MASK, PPCCOM,   { BDMA } },
1979 { "bdzla+",  BBO(16,BODZ,1,1),  BBOATBI_MASK, PPCCOM,   { BDPA } },
1980 { "bdzla",   BBO(16,BODZ,1,1),  BBOATBI_MASK, COM,      { BDA } },
1981 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
1982 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
1983 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
1984 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
1985 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
1986 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
1987 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
1988 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
1989 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
1990 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
1991 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
1992 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
1993 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
1994 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
1995 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
1996 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
1997 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
1998 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
1999 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2000 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2001 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2002 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2003 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2004 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2005 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2006 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2007 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2008 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2009 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2010 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2011 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2012 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2013 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2014 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2015 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2016 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2017 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2018 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2019 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2020 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2021 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2022 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2023 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2024 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2025 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2026 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2027 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2028 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2029 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2030 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2031 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2032 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2033 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2034 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2035 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2036 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2037 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2038 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2039 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2040 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2041 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2042 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2043 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2044 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2045 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2046 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2047 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2048 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2049 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2050 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2051 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2052 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2053 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2054 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2055 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2056 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2057 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2058 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2059 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2060 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2061 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2062 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2063 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2064 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2065 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2066 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2067 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2068 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2069 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2070 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2071 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2072 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2073 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2074 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2075 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2076 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2077 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2078 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2079 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2080 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2081 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2082 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2083 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2084 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2085 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2086 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2087 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2088 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2089 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2090 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2091 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2092 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2093 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2094 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2095 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2096 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2097 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2098 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2099 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2100 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2101 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2102 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2103 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2104 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2105 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2106 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2107 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2108 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2109 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2110 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2111 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2112 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2113 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2114 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2115 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2116 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2117 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2118 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2119 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2120 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2121 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2122 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2123 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2124 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2125 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM32,   { BI, BDM } },
2126 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM32,   { BI, BDP } },
2127 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2128 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM32,   { BI, BDM } },
2129 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM32,   { BI, BDP } },
2130 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2131 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM32,   { BI, BDMA } },
2132 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM32,   { BI, BDPA } },
2133 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2134 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM32,   { BI, BDMA } },
2135 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM32,   { BI, BDPA } },
2136 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2137 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM32,   { BI, BDM } },
2138 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM32,   { BI, BDP } },
2139 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2140 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM32,   { BI, BDM } },
2141 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM32,   { BI, BDP } },
2142 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2143 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM32,   { BI, BDMA } },
2144 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM32,   { BI, BDPA } },
2145 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2146 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM32,   { BI, BDMA } },
2147 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM32,   { BI, BDPA } },
2148 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2149 { "bt-",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2150 { "bt+",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2151 { "bt",      BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2152 { "bbt",     BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2153 { "btl-",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2154 { "btl+",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2155 { "btl",     BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2156 { "bbtl",    BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2157 { "bta-",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2158 { "bta+",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2159 { "bta",     BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2160 { "bbta",    BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2161 { "btla-",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2162 { "btla+",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2163 { "btla",    BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2164 { "bbtla",   BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2165 { "bf-",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2166 { "bf+",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2167 { "bf",      BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2168 { "bbf",     BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2169 { "bfl-",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2170 { "bfl+",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2171 { "bfl",     BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2172 { "bbfl",    BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2173 { "bfa-",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2174 { "bfa+",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2175 { "bfa",     BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2176 { "bbfa",    BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2177 { "bfla-",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2178 { "bfla+",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2179 { "bfla",    BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2180 { "bbfla",   BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2181 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM32,    { BI, BDM } },
2182 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM32,    { BI, BDP } },
2183 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2184 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM32,    { BI, BDM } },
2185 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM32,    { BI, BDP } },
2186 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2187 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM32,    { BI, BDMA } },
2188 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM32,    { BI, BDPA } },
2189 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2190 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM32,    { BI, BDMA } },
2191 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM32,    { BI, BDPA } },
2192 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2193 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM32,    { BI, BDM } },
2194 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM32,    { BI, BDP } },
2195 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2196 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM32,    { BI, BDM } },
2197 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM32,    { BI, BDP } },
2198 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2199 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM32,    { BI, BDMA } },
2200 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM32,    { BI, BDPA } },
2201 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2202 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM32,    { BI, BDMA } },
2203 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM32,    { BI, BDPA } },
2204 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2205 { "bc-",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2206 { "bc+",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2207 { "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
2208 { "bcl-",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2209 { "bcl+",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2210 { "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
2211 { "bca-",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2212 { "bca+",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2213 { "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
2214 { "bcla-",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2215 { "bcla+",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2216 { "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },
2217
2218 { "sc",      SC(17,1,0), 0xffffffff,    PPC,            { 0 } },
2219 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2220 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2221 { "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
2222 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
2223
2224 { "b",       B(18,0,0), B_MASK,         COM,            { LI } },
2225 { "bl",      B(18,0,1), B_MASK,         COM,            { LI } },
2226 { "ba",      B(18,1,0), B_MASK,         COM,            { LIA } },
2227 { "bla",     B(18,1,1), B_MASK,         COM,            { LIA } },
2228
2229 { "mcrf",    XL(19,0),  XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
2230
2231 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2232 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2233 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2234 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2235 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2236 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM32,       { 0 } },
2237 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM32,      { 0 } },
2238 { "bdnzlr-", XLO(19,BODNZM64,16,0), XLBOBIBB_MASK, PPCCOM64,    { 0 } },
2239 { "bdnzlr+", XLO(19,BODNZP64,16,0), XLBOBIBB_MASK, PPCCOM64,    { 0 } },
2240 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2241 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM32,       { 0 } },
2242 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM32,      { 0 } },
2243 { "bdnzlrl-",XLO(19,BODNZM64,16,1), XLBOBIBB_MASK, PPCCOM64,    { 0 } },
2244 { "bdnzlrl+",XLO(19,BODNZP64,16,1), XLBOBIBB_MASK, PPCCOM64,    { 0 } },
2245 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2246 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM32,        { 0 } },
2247 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM32,       { 0 } },
2248 { "bdzlr-",  XLO(19,BODZM64,16,0), XLBOBIBB_MASK, PPCCOM64,     { 0 } },
2249 { "bdzlr+",  XLO(19,BODZP64,16,0), XLBOBIBB_MASK, PPCCOM64,     { 0 } },
2250 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2251 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM32,        { 0 } },
2252 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM32,       { 0 } },
2253 { "bdzlrl-", XLO(19,BODZM64,16,1), XLBOBIBB_MASK, PPCCOM64,     { 0 } },
2254 { "bdzlrl+", XLO(19,BODZP64,16,1), XLBOBIBB_MASK, PPCCOM64,     { 0 } },
2255 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2256 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2257 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2258 { "bltlr-",  XLOCB(19,BOTM64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2259 { "bltlr+",  XLOCB(19,BOTP64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2260 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2261 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2262 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2263 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2264 { "bltlrl-", XLOCB(19,BOTM64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2265 { "bltlrl+", XLOCB(19,BOTP64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2266 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2267 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2268 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2269 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2270 { "bgtlr-",  XLOCB(19,BOTM64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2271 { "bgtlr+",  XLOCB(19,BOTP64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2272 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2273 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2274 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2275 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2276 { "bgtlrl-", XLOCB(19,BOTM64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2277 { "bgtlrl+", XLOCB(19,BOTP64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2278 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2279 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2280 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2281 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2282 { "beqlr-",  XLOCB(19,BOTM64,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2283 { "beqlr+",  XLOCB(19,BOTP64,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2284 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2285 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2286 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2287 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2288 { "beqlrl-", XLOCB(19,BOTM64,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2289 { "beqlrl+", XLOCB(19,BOTP64,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2290 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2291 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2292 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2293 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2294 { "bsolr-",  XLOCB(19,BOTM64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2295 { "bsolr+",  XLOCB(19,BOTP64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2296 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2297 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2298 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2299 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2300 { "bsolrl-", XLOCB(19,BOTM64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2301 { "bsolrl+", XLOCB(19,BOTP64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2302 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2303 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2304 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2305 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2306 { "bunlr-",  XLOCB(19,BOTM64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2307 { "bunlr+",  XLOCB(19,BOTP64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2308 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2309 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2310 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2311 { "bunlrl-", XLOCB(19,BOTM64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2312 { "bunlrl+", XLOCB(19,BOTP64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2313 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2314 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2315 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2316 { "bgelr-",  XLOCB(19,BOFM64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2317 { "bgelr+",  XLOCB(19,BOFP64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2318 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2319 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2320 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2321 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2322 { "bgelrl-", XLOCB(19,BOFM64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2323 { "bgelrl+", XLOCB(19,BOFP64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2324 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2325 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2326 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2327 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2328 { "bnllr-",  XLOCB(19,BOFM64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2329 { "bnllr+",  XLOCB(19,BOFP64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2330 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2331 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2332 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2333 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2334 { "bnllrl-", XLOCB(19,BOFM64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2335 { "bnllrl+", XLOCB(19,BOFP64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2336 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2337 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2338 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2339 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2340 { "blelr-",  XLOCB(19,BOFM64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2341 { "blelr+",  XLOCB(19,BOFP64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2342 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2343 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2344 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2345 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2346 { "blelrl-", XLOCB(19,BOFM64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2347 { "blelrl+", XLOCB(19,BOFP64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2348 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2349 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2350 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2351 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2352 { "bnglr-",  XLOCB(19,BOFM64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2353 { "bnglr+",  XLOCB(19,BOFP64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2354 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2355 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2356 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2357 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2358 { "bnglrl-", XLOCB(19,BOFM64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2359 { "bnglrl+", XLOCB(19,BOFP64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2360 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2361 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2362 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2363 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2364 { "bnelr-",  XLOCB(19,BOFM64,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2365 { "bnelr+",  XLOCB(19,BOFP64,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2366 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2367 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2368 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2369 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2370 { "bnelrl-", XLOCB(19,BOFM64,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2371 { "bnelrl+", XLOCB(19,BOFP64,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2372 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2373 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2374 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2375 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2376 { "bnslr-",  XLOCB(19,BOFM64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2377 { "bnslr+",  XLOCB(19,BOFP64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2378 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2379 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2380 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2381 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2382 { "bnslrl-", XLOCB(19,BOFM64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2383 { "bnslrl+", XLOCB(19,BOFP64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2384 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2385 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2386 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2387 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2388 { "bnulr-",  XLOCB(19,BOFM64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2389 { "bnulr+",  XLOCB(19,BOFP64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2390 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2391 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2392 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2393 { "bnulrl-", XLOCB(19,BOFM64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2394 { "bnulrl+", XLOCB(19,BOFP64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2395 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2396 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM32,   { BI } },
2397 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM32,  { BI } },
2398 { "btlr-",   XLO(19,BOTM64,16,0), XLBOBB_MASK, PPCCOM64,        { BI } },
2399 { "btlr+",   XLO(19,BOTP64,16,0), XLBOBB_MASK, PPCCOM64,        { BI } },
2400 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2401 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2402 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM32,   { BI } },
2403 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM32,  { BI } },
2404 { "btlrl-",  XLO(19,BOTM64,16,1), XLBOBB_MASK, PPCCOM64,        { BI } },
2405 { "btlrl+",  XLO(19,BOTP64,16,1), XLBOBB_MASK, PPCCOM64,        { BI } },
2406 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2407 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2408 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM32,   { BI } },
2409 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM32,  { BI } },
2410 { "bflr-",   XLO(19,BOFM64,16,0), XLBOBB_MASK, PPCCOM64,        { BI } },
2411 { "bflr+",   XLO(19,BOFP64,16,0), XLBOBB_MASK, PPCCOM64,        { BI } },
2412 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2413 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2414 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM32,   { BI } },
2415 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM32,  { BI } },
2416 { "bflrl-",  XLO(19,BOFM64,16,1), XLBOBB_MASK, PPCCOM64,        { BI } },
2417 { "bflrl+",  XLO(19,BOFP64,16,1), XLBOBB_MASK, PPCCOM64,        { BI } },
2418 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2419 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2420 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2421 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2422 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2423 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2424 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2425 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2426 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2427 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2428 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2429 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2430 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2431 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2432 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2433 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2434 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2435 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2436 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2437 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2438 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2439 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2440 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2441 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2442 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2443 { "bclr",    XLLK(19,16,0), XLYBB_MASK, PPCCOM,         { BO, BI } },
2444 { "bclrl",   XLLK(19,16,1), XLYBB_MASK, PPCCOM,         { BO, BI } },
2445 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2446 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2447 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2448 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2449 { "bcr",     XLLK(19,16,0), XLBB_MASK,  PWRCOM,         { BO, BI } },
2450 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  PWRCOM,         { BO, BI } },
2451 { "bclre",   XLLK(19,17,0), XLBB_MASK,  BOOKE64,        { BO, BI } },
2452 { "bclrel",  XLLK(19,17,1), XLBB_MASK,  BOOKE64,        { BO, BI } },
2453
2454 { "rfid",    XL(19,18), 0xffffffff,     PPC64,          { 0 } },
2455
2456 { "crnot",   XL(19,33), XL_MASK,        PPCCOM,         { BT, BA, BBA } },
2457 { "crnor",   XL(19,33), XL_MASK,        COM,            { BT, BA, BB } },
2458
2459 { "rfi",     XL(19,50), 0xffffffff,     COM,            { 0 } },
2460 { "rfci",    XL(19,51), 0xffffffff,     PPC403,         { 0 } },
2461 { "rfci",    XL(19,51), 0xffffffff,     BOOKE,          { 0 } },
2462
2463 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
2464
2465 { "crandc",  XL(19,129), XL_MASK,       COM,            { BT, BA, BB } },
2466
2467 { "isync",   XL(19,150), 0xffffffff,    PPCCOM,         { 0 } },
2468 { "ics",     XL(19,150), 0xffffffff,    PWRCOM,         { 0 } },
2469
2470 { "crclr",   XL(19,193), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2471 { "crxor",   XL(19,193), XL_MASK,       COM,            { BT, BA, BB } },
2472
2473 { "crnand",  XL(19,225), XL_MASK,       COM,            { BT, BA, BB } },
2474
2475 { "crand",   XL(19,257), XL_MASK,       COM,            { BT, BA, BB } },
2476
2477 { "crset",   XL(19,289), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2478 { "creqv",   XL(19,289), XL_MASK,       COM,            { BT, BA, BB } },
2479
2480 { "crorc",   XL(19,417), XL_MASK,       COM,            { BT, BA, BB } },
2481
2482 { "crmove",  XL(19,449), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
2483 { "cror",    XL(19,449), XL_MASK,       COM,            { BT, BA, BB } },
2484
2485 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
2486 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
2487 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2488 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2489 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2490 { "bltctr-", XLOCB(19,BOTM64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2491 { "bltctr+", XLOCB(19,BOTP64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2492 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2493 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2494 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2495 { "bltctrl-",XLOCB(19,BOTM64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2496 { "bltctrl+",XLOCB(19,BOTP64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2497 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2498 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2499 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2500 { "bgtctr-", XLOCB(19,BOTM64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2501 { "bgtctr+", XLOCB(19,BOTP64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2502 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2503 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2504 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2505 { "bgtctrl-",XLOCB(19,BOTM64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2506 { "bgtctrl+",XLOCB(19,BOTP64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2507 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2508 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2509 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2510 { "beqctr-", XLOCB(19,BOTM64,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2511 { "beqctr+", XLOCB(19,BOTP64,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2512 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2513 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2514 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2515 { "beqctrl-",XLOCB(19,BOTM64,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2516 { "beqctrl+",XLOCB(19,BOTP64,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2517 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2518 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2519 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2520 { "bsoctr-", XLOCB(19,BOTM64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2521 { "bsoctr+", XLOCB(19,BOTP64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2522 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2523 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2524 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2525 { "bsoctrl-",XLOCB(19,BOTM64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2526 { "bsoctrl+",XLOCB(19,BOTP64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2527 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2528 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2529 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2530 { "bunctr-", XLOCB(19,BOTM64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2531 { "bunctr+", XLOCB(19,BOTP64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2532 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2533 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2534 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2535 { "bunctrl-",XLOCB(19,BOTM64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2536 { "bunctrl+",XLOCB(19,BOTP64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2537 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2538 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2539 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2540 { "bgectr-", XLOCB(19,BOFM64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2541 { "bgectr+", XLOCB(19,BOFP64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2542 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2543 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2544 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2545 { "bgectrl-",XLOCB(19,BOFM64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2546 { "bgectrl+",XLOCB(19,BOFP64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2547 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2548 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2549 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2550 { "bnlctr-", XLOCB(19,BOFM64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2551 { "bnlctr+", XLOCB(19,BOFP64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2552 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2553 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2554 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2555 { "bnlctrl-",XLOCB(19,BOFM64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2556 { "bnlctrl+",XLOCB(19,BOFP64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2557 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2558 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2559 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2560 { "blectr-", XLOCB(19,BOFM64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2561 { "blectr+", XLOCB(19,BOFP64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2562 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2563 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2564 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2565 { "blectrl-",XLOCB(19,BOFM64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2566 { "blectrl+",XLOCB(19,BOFP64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2567 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2568 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2569 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2570 { "bngctr-", XLOCB(19,BOFM64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2571 { "bngctr+", XLOCB(19,BOFP64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2572 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2573 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2574 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2575 { "bngctrl-",XLOCB(19,BOFM64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2576 { "bngctrl+",XLOCB(19,BOFP64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2577 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2578 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2579 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2580 { "bnectr-", XLOCB(19,BOFM64,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2581 { "bnectr+", XLOCB(19,BOFP64,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2582 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2583 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2584 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2585 { "bnectrl-",XLOCB(19,BOFM64,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2586 { "bnectrl+",XLOCB(19,BOFP64,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2587 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2588 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2589 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2590 { "bnsctr-", XLOCB(19,BOFM64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2591 { "bnsctr+", XLOCB(19,BOFP64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2592 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2593 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2594 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2595 { "bnsctrl-",XLOCB(19,BOFM64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2596 { "bnsctrl+",XLOCB(19,BOFP64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2597 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2598 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2599 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2600 { "bnuctr-", XLOCB(19,BOFM64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2601 { "bnuctr+", XLOCB(19,BOFP64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2602 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2603 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM32, { CR } },
2604 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2605 { "bnuctrl-",XLOCB(19,BOFM64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2606 { "bnuctrl+",XLOCB(19,BOFP64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2607 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2608 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM32, { BI } },
2609 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM32, { BI } },
2610 { "btctr-",  XLO(19,BOTM64,528,0), XLBOBB_MASK, PPCCOM64, { BI } },
2611 { "btctr+",  XLO(19,BOTP64,528,0), XLBOBB_MASK, PPCCOM64, { BI } },
2612 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2613 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM32, { BI } },
2614 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM32, { BI } },
2615 { "btctrl-", XLO(19,BOTM64,528,1), XLBOBB_MASK, PPCCOM64, { BI } },
2616 { "btctrl+", XLO(19,BOTP64,528,1), XLBOBB_MASK, PPCCOM64, { BI } },
2617 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2618 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM32, { BI } },
2619 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM32, { BI } },
2620 { "bfctr-",  XLO(19,BOFM64,528,0), XLBOBB_MASK, PPCCOM64, { BI } },
2621 { "bfctr+",  XLO(19,BOFP64,528,0), XLBOBB_MASK, PPCCOM64, { BI } },
2622 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2623 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM32, { BI } },
2624 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM32, { BI } },
2625 { "bfctrl-", XLO(19,BOFM64,528,1), XLBOBB_MASK, PPCCOM64, { BI } },
2626 { "bfctrl+", XLO(19,BOFP64,528,1), XLBOBB_MASK, PPCCOM64, { BI } },
2627 { "bcctr",   XLLK(19,528,0),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
2628 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2629 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2630 { "bcctrl",  XLLK(19,528,1),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
2631 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2632 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2633 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
2634 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
2635 { "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
2636 { "bcctrel", XLLK(19,529,1),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
2637
2638 { "rlwimi",  M(20,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2639 { "rlimi",   M(20,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2640
2641 { "rlwimi.", M(20,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2642 { "rlimi.",  M(20,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2643
2644 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, SH } },
2645 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
2646 { "rlwinm",  M(21,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2647 { "rlinm",   M(21,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2648 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPCCOM,         { RA,RS,SH } },
2649 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
2650 { "rlwinm.", M(21,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2651 { "rlinm.",  M(21,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2652
2653 { "rlmi",    M(22,0),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
2654 { "rlmi.",   M(22,1),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
2655
2656 { "be",      B(22,0,0), B_MASK,         BOOKE64,        { LI } },
2657 { "bel",     B(22,0,1), B_MASK,         BOOKE64,        { LI } },
2658 { "bea",     B(22,1,0), B_MASK,         BOOKE64,        { LIA } },
2659 { "bela",    B(22,1,1), B_MASK,         BOOKE64,        { LIA } },
2660
2661 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
2662 { "rlwnm",   M(23,0),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
2663 { "rlnm",    M(23,0),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
2664 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
2665 { "rlwnm.",  M(23,1),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
2666 { "rlnm.",   M(23,1),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
2667
2668 { "nop",     OP(24),    0xffffffff,     PPCCOM,         { 0 } },
2669 { "ori",     OP(24),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2670 { "oril",    OP(24),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2671
2672 { "oris",    OP(25),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2673 { "oriu",    OP(25),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2674
2675 { "xori",    OP(26),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2676 { "xoril",   OP(26),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2677
2678 { "xoris",   OP(27),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2679 { "xoriu",   OP(27),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2680
2681 { "andi.",   OP(28),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2682 { "andil.",  OP(28),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2683
2684 { "andis.",  OP(29),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2685 { "andiu.",  OP(29),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2686
2687 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
2688 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
2689 { "rldicl",  MD(30,0,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2690 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
2691 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
2692 { "rldicl.", MD(30,0,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2693
2694 { "rldicr",  MD(30,1,0), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
2695 { "rldicr.", MD(30,1,1), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
2696
2697 { "rldic",   MD(30,2,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2698 { "rldic.",  MD(30,2,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2699
2700 { "rldimi",  MD(30,3,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2701 { "rldimi.", MD(30,3,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2702
2703 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
2704 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
2705 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
2706 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
2707
2708 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
2709 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
2710
2711 { "cmpw",    XCMPL(31,0,0), XCMPL_MASK, PPCCOM,         { OBF, RA, RB } },
2712 { "cmpd",    XCMPL(31,0,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
2713 { "cmp",     X(31,0),   XCMP_MASK,      PPCONLY,        { BF, L, RA, RB } },
2714 { "cmp",     X(31,0),   XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
2715
2716 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,         { RA, RB } },
2717 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,         { RA, RB } },
2718 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,         { RA, RB } },
2719 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,         { RA, RB } },
2720 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPCCOM,         { RA, RB } },
2721 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  PWRCOM,         { RA, RB } },
2722 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,         { RA, RB } },
2723 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,         { RA, RB } },
2724 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,         { RA, RB } },
2725 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,         { RA, RB } },
2726 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,         { RA, RB } },
2727 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,         { RA, RB } },
2728 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,         { RA, RB } },
2729 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,         { RA, RB } },
2730 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPCCOM,         { RA, RB } },
2731 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  PWRCOM,         { RA, RB } },
2732 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPCCOM,         { RA, RB } },
2733 { "tge",     XTO(31,4,TOGE), XTO_MASK,  PWRCOM,         { RA, RB } },
2734 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPCCOM,         { RA, RB } },
2735 { "tnl",     XTO(31,4,TONL), XTO_MASK,  PWRCOM,         { RA, RB } },
2736 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPCCOM,         { RA, RB } },
2737 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  PWRCOM,         { RA, RB } },
2738 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPCCOM,         { RA, RB } },
2739 { "tle",     XTO(31,4,TOLE), XTO_MASK,  PWRCOM,         { RA, RB } },
2740 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPCCOM,         { RA, RB } },
2741 { "tng",     XTO(31,4,TONG), XTO_MASK,  PWRCOM,         { RA, RB } },
2742 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPCCOM,         { RA, RB } },
2743 { "tne",     XTO(31,4,TONE), XTO_MASK,  PWRCOM,         { RA, RB } },
2744 { "trap",    XTO(31,4,TOU), 0xffffffff, PPCCOM,         { 0 } },
2745 { "tw",      X(31,4),   X_MASK,         PPCCOM,         { TO, RA, RB } },
2746 { "t",       X(31,4),   X_MASK,         PWRCOM,         { TO, RA, RB } },
2747
2748 { "subfc",   XO(31,8,0,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2749 { "sf",      XO(31,8,0,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2750 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
2751 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2752 { "sf.",     XO(31,8,0,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2753 { "subc.",   XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RB, RA } },
2754 { "subfco",  XO(31,8,1,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2755 { "sfo",     XO(31,8,1,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2756 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
2757 { "subfco.", XO(31,8,1,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2758 { "sfo.",    XO(31,8,1,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2759 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
2760
2761 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC64,          { RT, RA, RB } },
2762 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC64,          { RT, RA, RB } },
2763
2764 { "addc",    XO(31,10,0,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2765 { "a",       XO(31,10,0,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2766 { "addc.",   XO(31,10,0,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2767 { "a.",      XO(31,10,0,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2768 { "addco",   XO(31,10,1,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2769 { "ao",      XO(31,10,1,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2770 { "addco.",  XO(31,10,1,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2771 { "ao.",     XO(31,10,1,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2772
2773 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2774 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2775
2776 { "mfcr",    X(31,19),  XRARB_MASK,     COM,            { RT } },
2777
2778 { "lwarx",   X(31,20),  X_MASK,         PPC,            { RT, RA, RB } },
2779
2780 { "ldx",     X(31,21),  X_MASK,         PPC64,          { RT, RA, RB } },
2781
2782 { "icbt",    X(31,22),  X_MASK,         BOOKE,          { CT, RA, RB } },
2783
2784 { "lwzx",    X(31,23),  X_MASK,         PPCCOM,         { RT, RA, RB } },
2785 { "lx",      X(31,23),  X_MASK,         PWRCOM,         { RT, RA, RB } },
2786
2787 { "slw",     XRC(31,24,0), X_MASK,      PPCCOM,         { RA, RS, RB } },
2788 { "sl",      XRC(31,24,0), X_MASK,      PWRCOM,         { RA, RS, RB } },
2789 { "slw.",    XRC(31,24,1), X_MASK,      PPCCOM,         { RA, RS, RB } },
2790 { "sl.",     XRC(31,24,1), X_MASK,      PWRCOM,         { RA, RS, RB } },
2791
2792 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPCCOM,         { RA, RS } },
2793 { "cntlz",   XRC(31,26,0), XRB_MASK,    PWRCOM,         { RA, RS } },
2794 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPCCOM,         { RA, RS } },
2795 { "cntlz.",  XRC(31,26,1), XRB_MASK,    PWRCOM,         { RA, RS } },
2796
2797 { "sld",     XRC(31,27,0), X_MASK,      PPC64,          { RA, RS, RB } },
2798 { "sld.",    XRC(31,27,1), X_MASK,      PPC64,          { RA, RS, RB } },
2799
2800 { "and",     XRC(31,28,0), X_MASK,      COM,            { RA, RS, RB } },
2801 { "and.",    XRC(31,28,1), X_MASK,      COM,            { RA, RS, RB } },
2802
2803 { "maskg",   XRC(31,29,0), X_MASK,      M601,           { RA, RS, RB } },
2804 { "maskg.",  XRC(31,29,1), X_MASK,      M601,           { RA, RS, RB } },
2805
2806 { "icbte",   X(31,30),  X_MASK,         BOOKE64,        { CT, RA, RB } },
2807
2808 { "lwzxe",   X(31,31),  X_MASK,         BOOKE64,        { RT, RA, RB } },
2809
2810 { "cmplw",   XCMPL(31,32,0), XCMPL_MASK, PPCCOM,        { OBF, RA, RB } },
2811 { "cmpld",   XCMPL(31,32,1), XCMPL_MASK, PPC64,         { OBF, RA, RB } },
2812 { "cmpl",    X(31,32),  XCMP_MASK,       PPCONLY,       { BF, L, RA, RB } },
2813 { "cmpl",    X(31,32),  XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
2814
2815 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2816 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
2817 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2818 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
2819 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
2820 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
2821 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
2822 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
2823
2824 { "ldux",    X(31,53),  X_MASK,         PPC64,          { RT, RAL, RB } },
2825
2826 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
2827
2828 { "lwzux",   X(31,55),  X_MASK,         PPCCOM,         { RT, RAL, RB } },
2829 { "lux",     X(31,55),  X_MASK,         PWRCOM,         { RT, RA, RB } },
2830
2831 { "dcbste",  X(31,62),  XRT_MASK,       BOOKE64,        { RA, RB } },
2832
2833 { "lwzuxe",  X(31,63),  X_MASK,         BOOKE64,        { RT, RAL, RB } },
2834
2835 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC64,          { RA, RS } },
2836 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC64,          { RA, RS } },
2837
2838 { "andc",    XRC(31,60,0), X_MASK,      COM,            { RA, RS, RB } },
2839 { "andc.",   XRC(31,60,1), X_MASK,      COM,            { RA, RS, RB } },
2840
2841 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,         { RA, RB } },
2842 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,         { RA, RB } },
2843 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,         { RA, RB } },
2844 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,         { RA, RB } },
2845 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,         { RA, RB } },
2846 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,         { RA, RB } },
2847 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,         { RA, RB } },
2848 { "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,         { RA, RB } },
2849 { "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,         { RA, RB } },
2850 { "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,         { RA, RB } },
2851 { "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,         { RA, RB } },
2852 { "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,         { RA, RB } },
2853 { "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,         { RA, RB } },
2854 { "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,         { RA, RB } },
2855 { "td",      X(31,68),  X_MASK,          PPC64,         { TO, RA, RB } },
2856
2857 { "mulhd",   XO(31,73,0,0), XO_MASK,     PPC64,         { RT, RA, RB } },
2858 { "mulhd.",  XO(31,73,0,1), XO_MASK,     PPC64,         { RT, RA, RB } },
2859
2860 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2861 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2862
2863 { "mtsrd",   X(31,82),  XRB_MASK|(1<<20), PPC64,        { SR, RS } },
2864
2865 { "mfmsr",   X(31,83),  XRARB_MASK,     COM,            { RT } },
2866
2867 { "ldarx",   X(31,84),  X_MASK,         PPC64,          { RT, RA, RB } },
2868
2869 { "dcbf",    X(31,86),  XRT_MASK,       PPC,            { RA, RB } },
2870
2871 { "lbzx",    X(31,87),  X_MASK,         COM,            { RT, RA, RB } },
2872
2873 { "dcbfe",   X(31,94),  XRT_MASK,       BOOKE64,        { RA, RB } },
2874
2875 { "lbzxe",   X(31,95),  X_MASK,         BOOKE64,        { RT, RA, RB } },
2876
2877 { "neg",     XO(31,104,0,0), XORB_MASK, COM,            { RT, RA } },
2878 { "neg.",    XO(31,104,0,1), XORB_MASK, COM,            { RT, RA } },
2879 { "nego",    XO(31,104,1,0), XORB_MASK, COM,            { RT, RA } },
2880 { "nego.",   XO(31,104,1,1), XORB_MASK, COM,            { RT, RA } },
2881
2882 { "mul",     XO(31,107,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2883 { "mul.",    XO(31,107,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2884 { "mulo",    XO(31,107,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2885 { "mulo.",   XO(31,107,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2886
2887 { "mtsrdin", X(31,114), XRA_MASK,       PPC64,          { RS, RB } },
2888
2889 { "clf",     X(31,118), XTO_MASK,       POWER,          { RA, RB } },
2890
2891 { "lbzux",   X(31,119), X_MASK,         COM,            { RT, RAL, RB } },
2892
2893 { "not",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RBS } },
2894 { "nor",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RB } },
2895 { "not.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RBS } },
2896 { "nor.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RB } },
2897
2898 { "lwarxe",  X(31,126), X_MASK,         BOOKE64,        { RT, RA, RB } },
2899
2900 { "lbzuxe",  X(31,127), X_MASK,         BOOKE64,        { RT, RAL, RB } },
2901
2902 { "wrtee",   X(31,131), XRARB_MASK,     PPC403,         { RS } },
2903 { "wrtee",   X(31,131), XRARB_MASK,     BOOKE,          { RS } },
2904
2905 { "subfe",   XO(31,136,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2906 { "sfe",     XO(31,136,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2907 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2908 { "sfe.",    XO(31,136,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2909 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2910 { "sfeo",    XO(31,136,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2911 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2912 { "sfeo.",   XO(31,136,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2913
2914 { "adde",    XO(31,138,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2915 { "ae",      XO(31,138,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2916 { "adde.",   XO(31,138,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2917 { "ae.",     XO(31,138,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2918 { "addeo",   XO(31,138,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2919 { "aeo",     XO(31,138,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2920 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2921 { "aeo.",    XO(31,138,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2922
2923 { "mtcr",    XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM,      { RS }},
2924 { "mtcrf",   X(31,144), XFXFXM_MASK,    COM,            { FXM, RS } },
2925
2926 { "mtmsr",   X(31,146), XRARB_MASK,     COM,            { RS } },
2927
2928 { "stdx",    X(31,149), X_MASK,         PPC64,          { RS, RA, RB } },
2929
2930 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA, RB } },
2931
2932 { "stwx",    X(31,151), X_MASK,         PPCCOM,         { RS, RA, RB } },
2933 { "stx",     X(31,151), X_MASK,         PWRCOM,         { RS, RA, RB } },
2934
2935 { "stwcxe.", XRC(31,158,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
2936
2937 { "stwxe",   X(31,159), X_MASK,         BOOKE64,        { RS, RA, RB } },
2938
2939 { "slq",     XRC(31,152,0), X_MASK,     M601,           { RA, RS, RB } },
2940 { "slq.",    XRC(31,152,1), X_MASK,     M601,           { RA, RS, RB } },
2941
2942 { "sle",     XRC(31,153,0), X_MASK,     M601,           { RA, RS, RB } },
2943 { "sle.",    XRC(31,153,1), X_MASK,     M601,           { RA, RS, RB } },
2944
2945 { "wrteei",  X(31,163), XE_MASK,        PPC403,         { E } },
2946 { "wrteei",  X(31,163), XE_MASK,        BOOKE,          { E } },
2947
2948 { "mtmsrd",  X(31,178), XRARB_MASK,     PPC64,          { RS } },
2949
2950 { "stdux",   X(31,181), X_MASK,         PPC64,          { RS, RAS, RB } },
2951
2952 { "stwux",   X(31,183), X_MASK,         PPCCOM,         { RS, RAS, RB } },
2953 { "stux",    X(31,183), X_MASK,         PWRCOM,         { RS, RA, RB } },
2954
2955 { "sliq",    XRC(31,184,0), X_MASK,     M601,           { RA, RS, SH } },
2956 { "sliq.",   XRC(31,184,1), X_MASK,     M601,           { RA, RS, SH } },
2957
2958 { "stwuxe",  X(31,191), X_MASK,         BOOKE64,        { RS, RAS, RB } },
2959
2960 { "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2961 { "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2962 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2963 { "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2964 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2965 { "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2966 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2967 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2968
2969 { "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2970 { "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2971 { "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2972 { "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2973 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2974 { "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2975 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2976 { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2977
2978 { "mtsr",    X(31,210), XRB_MASK|(1<<20), COM32,        { SR, RS } },
2979
2980 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC64,          { RS, RA, RB } },
2981
2982 { "stbx",    X(31,215), X_MASK,         COM,            { RS, RA, RB } },
2983
2984 { "sllq",    XRC(31,216,0), X_MASK,     M601,           { RA, RS, RB } },
2985 { "sllq.",   XRC(31,216,1), X_MASK,     M601,           { RA, RS, RB } },
2986
2987 { "sleq",    XRC(31,217,0), X_MASK,     M601,           { RA, RS, RB } },
2988 { "sleq.",   XRC(31,217,1), X_MASK,     M601,           { RA, RS, RB } },
2989
2990 { "stbxe",   X(31,223), X_MASK,         BOOKE64,        { RS, RA, RB } },
2991
2992 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2993 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2994 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2995 { "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2996 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2997 { "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2998 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2999 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3000
3001 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3002 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3003 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3004 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3005
3006 { "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3007 { "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3008 { "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3009 { "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3010 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3011 { "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3012 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3013 { "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3014
3015 { "mullw",   XO(31,235,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3016 { "muls",    XO(31,235,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3017 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3018 { "muls.",   XO(31,235,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3019 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3020 { "mulso",   XO(31,235,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3021 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3022 { "mulso.",  XO(31,235,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3023
3024 { "mtsrin",  X(31,242), XRA_MASK,       PPC32,          { RS, RB } },
3025 { "mtsri",   X(31,242), XRA_MASK,       POWER32,        { RS, RB } },
3026
3027 { "dcbtst",  X(31,246), XRT_MASK,       PPC,            { CT, RA, RB } },
3028
3029 { "stbux",   X(31,247), X_MASK,         COM,            { RS, RAS, RB } },
3030
3031 { "slliq",   XRC(31,248,0), X_MASK,     M601,           { RA, RS, SH } },
3032 { "slliq.",  XRC(31,248,1), X_MASK,     M601,           { RA, RS, SH } },
3033
3034 { "dcbtste", X(31,253), X_MASK,         BOOKE64,        { CT, RA, RB } },
3035
3036 { "stbuxe",  X(31,255), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3037
3038 { "mfdcrx",  X(31,259), X_MASK,         BOOKE,          { RS, RA } },
3039
3040 { "icbt",    X(31,262), XRT_MASK,       PPC403,         { RA, RB } },
3041
3042 { "doz",     XO(31,264,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3043 { "doz.",    XO(31,264,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3044 { "dozo",    XO(31,264,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3045 { "dozo.",   XO(31,264,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3046
3047 { "add",     XO(31,266,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3048 { "cax",     XO(31,266,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3049 { "add.",    XO(31,266,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3050 { "cax.",    XO(31,266,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3051 { "addo",    XO(31,266,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3052 { "caxo",    XO(31,266,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3053 { "addo.",   XO(31,266,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3054 { "caxo.",   XO(31,266,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3055
3056 { "mfapidi", X(31,275), X_MASK,         BOOKE,          { RT, RA } },
3057
3058 { "lscbx",   XRC(31,277,0), X_MASK,     M601,           { RT, RA, RB } },
3059 { "lscbx.",  XRC(31,277,1), X_MASK,     M601,           { RT, RA, RB } },
3060
3061 { "dcbt",    X(31,278), XRT_MASK,       PPC,            { CT, RA, RB } },
3062
3063 { "lhzx",    X(31,279), X_MASK,         COM,            { RT, RA, RB } },
3064
3065 { "eqv",     XRC(31,284,0), X_MASK,     COM,            { RA, RS, RB } },
3066 { "eqv.",    XRC(31,284,1), X_MASK,     COM,            { RA, RS, RB } },
3067
3068 { "dcbte",   X(31,286), X_MASK,         BOOKE64,        { CT, RA, RB } },
3069
3070 { "lhzxe",   X(31,287), X_MASK,         BOOKE64,        { RT, RA, RB } },
3071
3072 { "tlbie",   X(31,306), XRTRA_MASK,     PPC,            { RB } },
3073 { "tlbi",    X(31,306), XRT_MASK,       POWER,          { RA, RB } },
3074
3075 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
3076
3077 { "lhzux",   X(31,311), X_MASK,         COM,            { RT, RAL, RB } },
3078
3079 { "xor",     XRC(31,316,0), X_MASK,     COM,            { RA, RS, RB } },
3080 { "xor.",    XRC(31,316,1), X_MASK,     COM,            { RA, RS, RB } },
3081
3082 { "lhzuxe",  X(31,319), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3083
3084 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403,        { RT } },
3085 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403,        { RT } },
3086 { "mfbr0",   XSPR(31,323,128), XSPR_MASK, PPC403,       { RT } },
3087 { "mfbr1",   XSPR(31,323,129), XSPR_MASK, PPC403,       { RT } },
3088 { "mfbr2",   XSPR(31,323,130), XSPR_MASK, PPC403,       { RT } },
3089 { "mfbr3",   XSPR(31,323,131), XSPR_MASK, PPC403,       { RT } },
3090 { "mfbr4",   XSPR(31,323,132), XSPR_MASK, PPC403,       { RT } },
3091 { "mfbr5",   XSPR(31,323,133), XSPR_MASK, PPC403,       { RT } },
3092 { "mfbr6",   XSPR(31,323,134), XSPR_MASK, PPC403,       { RT } },
3093 { "mfbr7",   XSPR(31,323,135), XSPR_MASK, PPC403,       { RT } },
3094 { "mfbear",  XSPR(31,323,144), XSPR_MASK, PPC403,       { RT } },
3095 { "mfbesr",  XSPR(31,323,145), XSPR_MASK, PPC403,       { RT } },
3096 { "mfiocr",  XSPR(31,323,160), XSPR_MASK, PPC403,       { RT } },
3097 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,      { RT } },
3098 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,      { RT } },
3099 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,      { RT } },
3100 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,      { RT } },
3101 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,      { RT } },
3102 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,      { RT } },
3103 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,      { RT } },
3104 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,      { RT } },
3105 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,      { RT } },
3106 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,      { RT } },
3107 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,      { RT } },
3108 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,      { RT } },
3109 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,      { RT } },
3110 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,      { RT } },
3111 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,      { RT } },
3112 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,      { RT } },
3113 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,      { RT } },
3114 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,      { RT } },
3115 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,      { RT } },
3116 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,      { RT } },
3117 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403,       { RT } },
3118 { "mfdcr",   X(31,323), X_MASK,         PPC403,         { RT, SPR } },
3119 { "mfdcr",   X(31,323), X_MASK,         BOOKE,          { RT, SPR } },
3120
3121 { "div",     XO(31,331,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3122 { "div.",    XO(31,331,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3123 { "divo",    XO(31,331,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3124 { "divo.",   XO(31,331,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3125
3126 { "mfmq",     XSPR(31,339,0),   XSPR_MASK, M601,        { RT } },
3127 { "mfxer",    XSPR(31,339,1),   XSPR_MASK, COM,         { RT } },
3128 { "mfrtcu",   XSPR(31,339,4),   XSPR_MASK, COM,         { RT } },
3129 { "mfrtcl",   XSPR(31,339,5),   XSPR_MASK, COM,         { RT } },
3130 { "mfdec",    XSPR(31,339,6),   XSPR_MASK, MFDEC1,      { RT } },
3131 { "mflr",     XSPR(31,339,8),   XSPR_MASK, COM,         { RT } },
3132 { "mfctr",    XSPR(31,339,9),   XSPR_MASK, COM,         { RT } },
3133 { "mftid",    XSPR(31,339,17),  XSPR_MASK, POWER,       { RT } },
3134 { "mfdsisr",  XSPR(31,339,18),  XSPR_MASK, COM,         { RT } },
3135 { "mfdar",    XSPR(31,339,19),  XSPR_MASK, COM,         { RT } },
3136 { "mfdec",    XSPR(31,339,22),  XSPR_MASK, MFDEC2,      { RT } },
3137 { "mfsdr0",   XSPR(31,339,24),  XSPR_MASK, POWER,       { RT } },
3138 { "mfsdr1",   XSPR(31,339,25),  XSPR_MASK, COM,         { RT } },
3139 { "mfsrr0",   XSPR(31,339,26),  XSPR_MASK, COM,         { RT } },
3140 { "mfsrr1",   XSPR(31,339,27),  XSPR_MASK, COM,         { RT } },
3141 { "mfcmpa",   XSPR(31,339,144), XSPR_MASK, PPC860,      { RT } },
3142 { "mfcmpb",   XSPR(31,339,145), XSPR_MASK, PPC860,      { RT } },
3143 { "mfcmpc",   XSPR(31,339,146), XSPR_MASK, PPC860,      { RT } },
3144 { "mfcmpd",   XSPR(31,339,147), XSPR_MASK, PPC860,      { RT } },
3145 { "mficr",    XSPR(31,339,148), XSPR_MASK, PPC860,      { RT } },
3146 { "mfder",    XSPR(31,339,149), XSPR_MASK, PPC860,      { RT } },
3147 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860,      { RT } },
3148 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860,      { RT } },
3149 { "mfcmpe",   XSPR(31,339,152), XSPR_MASK, PPC860,      { RT } },
3150 { "mfcmpf",   XSPR(31,339,153), XSPR_MASK, PPC860,      { RT } },
3151 { "mfcmpg",   XSPR(31,339,154), XSPR_MASK, PPC860,      { RT } },
3152 { "mfcmph",   XSPR(31,339,155), XSPR_MASK, PPC860,      { RT } },
3153 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860,      { RT } },
3154 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860,      { RT } },
3155 { "mfictrl",  XSPR(31,339,158), XSPR_MASK, PPC860,      { RT } },
3156 { "mfbar",    XSPR(31,339,159), XSPR_MASK, PPC860,      { RT } },
3157 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC,      { RT } },
3158 { "mfsprg4",  XSPR(31,339,260), XSPR_MASK, PPC405,      { RT } },
3159 { "mfsprg5",  XSPR(31,339,261), XSPR_MASK, PPC405,      { RT } },
3160 { "mfsprg6",  XSPR(31,339,262), XSPR_MASK, PPC405,      { RT } },
3161 { "mfsprg7",  XSPR(31,339,263), XSPR_MASK, PPC405,      { RT } },
3162 { "mfsprg",   XSPR(31,339,272), XSPRG_MASK, PPC,        { RT, SPRG } },
3163 { "mfsprg0",  XSPR(31,339,272), XSPR_MASK, PPC,         { RT } },
3164 { "mfsprg1",  XSPR(31,339,273), XSPR_MASK, PPC,         { RT } },
3165 { "mfsprg2",  XSPR(31,339,274), XSPR_MASK, PPC,         { RT } },
3166 { "mfsprg3",  XSPR(31,339,275), XSPR_MASK, PPC,         { RT } },
3167 { "mfasr",    XSPR(31,339,280), XSPR_MASK, PPC64,       { RT } },
3168 { "mfear",    XSPR(31,339,282), XSPR_MASK, PPC,         { RT } },
3169 { "mfpvr",    XSPR(31,339,287), XSPR_MASK, PPC,         { RT } },
3170 { "mfibatu",  XSPR(31,339,528), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
3171 { "mfibatl",  XSPR(31,339,529), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
3172 { "mfdbatu",  XSPR(31,339,536), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
3173 { "mfdbatl",  XSPR(31,339,537), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
3174 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860,      { RT } },
3175 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860,      { RT } },
3176 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860,      { RT } },
3177 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860,      { RT } },
3178 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860,      { RT } },
3179 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860,      { RT } },
3180 { "mfdpdr",   XSPR(31,339,630), XSPR_MASK, PPC860,      { RT } },
3181 { "mfdpir",   XSPR(31,339,631), XSPR_MASK, PPC860,      { RT } },
3182 { "mfimmr",   XSPR(31,339,638), XSPR_MASK, PPC860,      { RT } },
3183 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860,      { RT } },
3184 { "mfmi_ap",  XSPR(31,339,786), XSPR_MASK, PPC860,      { RT } },
3185 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860,      { RT } },
3186 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860,      { RT } },
3187 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860,      { RT } },
3188 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860,      { RT } },
3189 { "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860,      { RT } },
3190 { "mfmd_ap",  XSPR(31,339,794), XSPR_MASK, PPC860,      { RT } },
3191 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860,      { RT } },
3192 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860,      { RT } },
3193 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860,      { RT } },
3194 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860,      { RT } },
3195 { "mfm_tw",   XSPR(31,339,799), XSPR_MASK, PPC860,      { RT } },
3196 { "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860,     { RT } },
3197 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860,    { RT } },
3198 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860,    { RT } },
3199 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860,    { RT } },
3200 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860,    { RT } },
3201 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860,    { RT } },
3202 { "mfzpr",      XSPR(31,339,944), XSPR_MASK, PPC403,    { RT } },
3203 { "mfpid",      XSPR(31,339,945), XSPR_MASK, PPC403,    { RT } },
3204 { "mfccr0",     XSPR(31,339,947), XSPR_MASK, PPC405,    { RT } },
3205 { "mficdbdr",   XSPR(31,339,979), XSPR_MASK, PPC403,    { RT } },
3206 { "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
3207 { "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
3208 { "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
3209 { "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
3210 { "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
3211 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
3212 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
3213 { "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,   { RT } },
3214 { "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,   { RT } },
3215 { "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,   { RT } },
3216 { "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,   { RT } },
3217 { "mfmmcr0",    XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
3218 { "mfpmc1",     XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
3219 { "mfsgr",      XSPR(31,339,953),  XSPR_MASK, PPC403,   { RT } },
3220 { "mfpmc2",     XSPR(31,339,954),  XSPR_MASK, PPC750,   { RT } },
3221 { "mfdcwr",     XSPR(31,339,954),  XSPR_MASK, PPC403,   { RT } },
3222 { "mfsia",      XSPR(31,339,955),  XSPR_MASK, PPC750,   { RT } },
3223 { "mfsler",     XSPR(31,339,955),  XSPR_MASK, PPC405,   { RT } },
3224 { "mfmmcr1",    XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
3225 { "mfsu0r",     XSPR(31,339,956),  XSPR_MASK, PPC405,   { RT } },
3226 { "mfpmc3",     XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
3227 { "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
3228 { "mfpmc4",     XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
3229 { "mfesr",   XSPR(31,339,980), XSPR_MASK, PPC403,       { RT } },
3230 { "mfdear",  XSPR(31,339,981), XSPR_MASK, PPC403,       { RT } },
3231 { "mfevpr",  XSPR(31,339,982), XSPR_MASK, PPC403,       { RT } },
3232 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403,       { RT } },
3233 { "mftsr",   XSPR(31,339,984), XSPR_MASK, PPC403,       { RT } },
3234 { "mftcr",   XSPR(31,339,986), XSPR_MASK, PPC403,       { RT } },
3235 { "mfpit",   XSPR(31,339,987), XSPR_MASK, PPC403,       { RT } },
3236 { "mftbhi",  XSPR(31,339,988), XSPR_MASK, PPC403,       { RT } },
3237 { "mftblo",  XSPR(31,339,989), XSPR_MASK, PPC403,       { RT } },
3238 { "mfsrr2",  XSPR(31,339,990), XSPR_MASK, PPC403,       { RT } },
3239 { "mfsrr3",  XSPR(31,339,991), XSPR_MASK, PPC403,       { RT } },
3240 { "mfdbsr",  XSPR(31,339,1008), XSPR_MASK, PPC403,      { RT } },
3241 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405,      { RT } },
3242 { "mfiac1",  XSPR(31,339,1012), XSPR_MASK, PPC403,      { RT } },
3243 { "mfiac2",  XSPR(31,339,1013), XSPR_MASK, PPC403,      { RT } },
3244 { "mfdac1",  XSPR(31,339,1014), XSPR_MASK, PPC403,      { RT } },
3245 { "mfdac2",  XSPR(31,339,1015), XSPR_MASK, PPC403,      { RT } },
3246 { "mfdccr",  XSPR(31,339,1018), XSPR_MASK, PPC403,      { RT } },
3247 { "mficcr",  XSPR(31,339,1019), XSPR_MASK, PPC403,      { RT } },
3248 { "mfpbl1",  XSPR(31,339,1020), XSPR_MASK, PPC403,      { RT } },
3249 { "mfpbu1",  XSPR(31,339,1021), XSPR_MASK, PPC403,      { RT } },
3250 { "mfpbl2",  XSPR(31,339,1022), XSPR_MASK, PPC403,      { RT } },
3251 { "mfpbu2",  XSPR(31,339,1023), XSPR_MASK, PPC403,      { RT } },
3252 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
3253 { "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
3254 { "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
3255 { "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
3256 { "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
3257 { "mfspr",   X(31,339), X_MASK,         COM,            { RT, SPR } },
3258
3259 { "lwax",    X(31,341), X_MASK,         PPC64,          { RT, RA, RB } },
3260
3261 { "dst",     XDSS(31,342,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3262 { "dstt",    XDSS(31,342,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3263
3264 { "lhax",    X(31,343), X_MASK,         COM,            { RT, RA, RB } },
3265
3266 { "lhaxe",   X(31,351), X_MASK,         BOOKE64,        { RT, RA, RB } },
3267
3268 { "dstst",   XDSS(31,374,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3269 { "dststt",  XDSS(31,374,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3270
3271 { "dccci",   X(31,454), XRT_MASK,       PPC403,         { RA, RB } },
3272
3273 { "abs",     XO(31,360,0,0), XORB_MASK, M601,           { RT, RA } },
3274 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,           { RT, RA } },
3275 { "abso",    XO(31,360,1,0), XORB_MASK, M601,           { RT, RA } },
3276 { "abso.",   XO(31,360,1,1), XORB_MASK, M601,           { RT, RA } },
3277
3278 { "divs",    XO(31,363,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3279 { "divs.",   XO(31,363,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3280 { "divso",   XO(31,363,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3281 { "divso.",  XO(31,363,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3282
3283 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
3284
3285 { "mftbl",   XSPR(31,371,268), XSPR_MASK, PPC,          { RT } },
3286 { "mftbu",   XSPR(31,371,269), XSPR_MASK, PPC,          { RT } },
3287 { "mftb",    X(31,371), X_MASK,         PPC,            { RT, TBR } },
3288
3289 { "lwaux",   X(31,373), X_MASK,         PPC64,          { RT, RAL, RB } },
3290
3291 { "lhaux",   X(31,375), X_MASK,         COM,            { RT, RAL, RB } },
3292
3293 { "lhauxe",  X(31,383), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3294
3295 { "mtdcrx",  X(31,387), X_MASK,         BOOKE,          { RA, RS } },
3296
3297 { "subfe64", XO(31,392,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3298 { "subfe64o",XO(31,392,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3299
3300 { "adde64",  XO(31,394,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3301 { "adde64o", XO(31,394,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3302
3303 { "slbmte",  X(31,402), XRA_MASK,       PPC64,          { RS, RB } },
3304
3305 { "sthx",    X(31,407), X_MASK,         COM,            { RS, RA, RB } },
3306
3307 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
3308
3309 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
3310
3311 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
3312
3313 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
3314
3315 { "orc",     XRC(31,412,0), X_MASK,     COM,            { RA, RS, RB } },
3316 { "orc.",    XRC(31,412,1), X_MASK,     COM,            { RA, RS, RB } },
3317
3318 { "sradi",   XS(31,413,0), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3319 { "sradi.",  XS(31,413,1), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3320
3321 { "sthxe",   X(31,415), X_MASK,         BOOKE64,        { RS, RA, RB } },
3322
3323 { "slbie",   X(31,434), XRTRA_MASK,     PPC64,          { RB } },
3324
3325 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
3326
3327 { "sthux",   X(31,439), X_MASK,         COM,            { RS, RAS, RB } },
3328
3329 { "sthuxe",  X(31,447), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3330
3331 { "mr",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RBS } },
3332 { "or",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RB } },
3333 { "mr.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RBS } },
3334 { "or.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RB } },
3335
3336 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403,        { RT } },
3337 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403,        { RT } },
3338 { "mtbr0",   XSPR(31,451,128), XSPR_MASK, PPC403,       { RT } },
3339 { "mtbr1",   XSPR(31,451,129), XSPR_MASK, PPC403,       { RT } },
3340 { "mtbr2",   XSPR(31,451,130), XSPR_MASK, PPC403,       { RT } },
3341 { "mtbr3",   XSPR(31,451,131), XSPR_MASK, PPC403,       { RT } },
3342 { "mtbr4",   XSPR(31,451,132), XSPR_MASK, PPC403,       { RT } },
3343 { "mtbr5",   XSPR(31,451,133), XSPR_MASK, PPC403,       { RT } },
3344 { "mtbr6",   XSPR(31,451,134), XSPR_MASK, PPC403,       { RT } },
3345 { "mtbr7",   XSPR(31,451,135), XSPR_MASK, PPC403,       { RT } },
3346 { "mtbear",  XSPR(31,451,144), XSPR_MASK, PPC403,       { RT } },
3347 { "mtbesr",  XSPR(31,451,145), XSPR_MASK, PPC403,       { RT } },
3348 { "mtiocr",  XSPR(31,451,160), XSPR_MASK, PPC403,       { RT } },
3349 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,      { RT } },
3350 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,      { RT } },
3351 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,      { RT } },
3352 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,      { RT } },
3353 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,      { RT } },
3354 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,      { RT } },
3355 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,      { RT } },
3356 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,      { RT } },
3357 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,      { RT } },
3358 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,      { RT } },
3359 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,      { RT } },
3360 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,      { RT } },
3361 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,      { RT } },
3362 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,      { RT } },
3363 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,      { RT } },
3364 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,      { RT } },
3365 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,      { RT } },
3366 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,      { RT } },
3367 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,      { RT } },
3368 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,      { RT } },
3369 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403,       { RT } },
3370 { "mtdcr",   X(31,451), X_MASK,         PPC403,         { SPR, RS } },
3371 { "mtdcr",   X(31,451), X_MASK,         BOOKE,          { SPR, RS } },
3372
3373 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3374 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
3375
3376 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3377 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3378 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3379 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3380
3381 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3382 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
3383
3384 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3385 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3386 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3387 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
3388
3389 { "mtmq",    XSPR(31,467,0),   XSPR_MASK,    M601,      { RS } },
3390 { "mtxer",   XSPR(31,467,1),   XSPR_MASK,    COM,       { RS } },
3391 { "mtlr",    XSPR(31,467,8),   XSPR_MASK,    COM,       { RS } },
3392 { "mtctr",   XSPR(31,467,9),   XSPR_MASK,    COM,       { RS } },
3393 { "mttid",   XSPR(31,467,17),  XSPR_MASK,    POWER,     { RS } },
3394 { "mtdsisr", XSPR(31,467,18),  XSPR_MASK,    COM,       { RS } },
3395 { "mtdar",   XSPR(31,467,19),  XSPR_MASK,    COM,       { RS } },
3396 { "mtrtcu",  XSPR(31,467,20),  XSPR_MASK,    COM,       { RS } },
3397 { "mtrtcl",  XSPR(31,467,21),  XSPR_MASK,    COM,       { RS } },
3398 { "mtdec",   XSPR(31,467,22),  XSPR_MASK,    COM,       { RS } },
3399 { "mtsdr0",  XSPR(31,467,24),  XSPR_MASK,    POWER,     { RS } },
3400 { "mtsdr1",  XSPR(31,467,25),  XSPR_MASK,    COM,       { RS } },
3401 { "mtsrr0",  XSPR(31,467,26),  XSPR_MASK,    COM,       { RS } },
3402 { "mtsrr1",  XSPR(31,467,27),  XSPR_MASK,    COM,       { RS } },
3403 { "mtcmpa",   XSPR(31,467,144), XSPR_MASK, PPC860,      { RT } },
3404 { "mtcmpb",   XSPR(31,467,145), XSPR_MASK, PPC860,      { RT } },
3405 { "mtcmpc",   XSPR(31,467,146), XSPR_MASK, PPC860,      { RT } },
3406 { "mtcmpd",   XSPR(31,467,147), XSPR_MASK, PPC860,      { RT } },
3407 { "mticr",    XSPR(31,467,148), XSPR_MASK, PPC860,      { RT } },
3408 { "mtder",    XSPR(31,467,149), XSPR_MASK, PPC860,      { RT } },
3409 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860,      { RT } },
3410 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860,      { RT } },
3411 { "mtcmpe",   XSPR(31,467,152), XSPR_MASK, PPC860,      { RT } },
3412 { "mtcmpf",   XSPR(31,467,153), XSPR_MASK, PPC860,      { RT } },
3413 { "mtcmpg",   XSPR(31,467,154), XSPR_MASK, PPC860,      { RT } },
3414 { "mtcmph",   XSPR(31,467,155), XSPR_MASK, PPC860,      { RT } },
3415 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860,      { RT } },
3416 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860,      { RT } },
3417 { "mtictrl",  XSPR(31,467,158), XSPR_MASK, PPC860,      { RT } },
3418 { "mtbar",    XSPR(31,467,159), XSPR_MASK, PPC860,      { RT } },
3419 { "mtvrsave",XSPR(31,467,256), XSPR_MASK,    PPCVEC,    { RT } },
3420 { "mtsprg",  XSPR(31,467,272), XSPRG_MASK,   PPC,       { SPRG, RS } },
3421 { "mtsprg0", XSPR(31,467,272), XSPR_MASK,    PPC,       { RT } },
3422 { "mtsprg1", XSPR(31,467,273), XSPR_MASK,    PPC,       { RT } },
3423 { "mtsprg2", XSPR(31,467,274), XSPR_MASK,    PPC,       { RT } },
3424 { "mtsprg3", XSPR(31,467,275), XSPR_MASK,    PPC,       { RT } },
3425 { "mtsprg4", XSPR(31,467,276), XSPR_MASK,    PPC405,    { RT } },
3426 { "mtsprg5", XSPR(31,467,277), XSPR_MASK,    PPC405,    { RT } },
3427 { "mtsprg6", XSPR(31,467,278), XSPR_MASK,    PPC405,    { RT } },
3428 { "mtsprg7", XSPR(31,467,279), XSPR_MASK,    PPC405,    { RT } },
3429 { "mtasr",   XSPR(31,467,280), XSPR_MASK,    PPC64,     { RS } },
3430 { "mtear",   XSPR(31,467,282), XSPR_MASK,    PPC,       { RS } },
3431 { "mttbl",   XSPR(31,467,284), XSPR_MASK,    PPC,       { RS } },
3432 { "mttbu",   XSPR(31,467,285), XSPR_MASK,    PPC,       { RS } },
3433 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
3434 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
3435 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
3436 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
3437 { "mtzpr",   XSPR(31,467,944), XSPR_MASK, PPC403,       { RT } },
3438 { "mtpid",   XSPR(31,467,945), XSPR_MASK, PPC403,       { RT } },
3439 { "mtccr0",  XSPR(31,467,947), XSPR_MASK, PPC405,       { RT } },
3440 { "mtiac3",  XSPR(31,467,948), XSPR_MASK, PPC405,       { RT } },
3441 { "mtiac4",  XSPR(31,467,949), XSPR_MASK, PPC405,       { RT } },
3442 { "mtdvc1",  XSPR(31,467,950), XSPR_MASK, PPC405,       { RT } },
3443 { "mtdvc2",  XSPR(31,467,951), XSPR_MASK, PPC405,       { RT } },
3444 { "mtsgr",   XSPR(31,467,953), XSPR_MASK, PPC403,       { RT } },
3445 { "mtdcwr",  XSPR(31,467,954), XSPR_MASK, PPC403,       { RT } },
3446 { "mtsler",  XSPR(31,467,955), XSPR_MASK, PPC405,       { RT } },
3447 { "mtsu0r",  XSPR(31,467,956), XSPR_MASK, PPC405,       { RT } },
3448 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405,       { RT } },
3449 { "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403,       { RT } },
3450 { "mtesr",   XSPR(31,467,980), XSPR_MASK, PPC403,       { RT } },
3451 { "mtdear",  XSPR(31,467,981), XSPR_MASK, PPC403,       { RT } },
3452 { "mtevpr",  XSPR(31,467,982), XSPR_MASK, PPC403,       { RT } },
3453 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403,       { RT } },
3454 { "mttsr",   XSPR(31,467,984), XSPR_MASK, PPC403,       { RT } },
3455 { "mttcr",   XSPR(31,467,986), XSPR_MASK, PPC403,       { RT } },
3456 { "mtpit",   XSPR(31,467,987), XSPR_MASK, PPC403,       { RT } },
3457 { "mttbhi",  XSPR(31,467,988), XSPR_MASK, PPC403,       { RT } },
3458 { "mttblo",  XSPR(31,467,989), XSPR_MASK, PPC403,       { RT } },
3459 { "mtsrr2",  XSPR(31,467,990), XSPR_MASK, PPC403,       { RT } },
3460 { "mtsrr3",  XSPR(31,467,991), XSPR_MASK, PPC403,       { RT } },
3461 { "mtdbsr",  XSPR(31,467,1008), XSPR_MASK, PPC403,      { RT } },
3462 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405,      { RT } },
3463 { "mtiac1",  XSPR(31,467,1012), XSPR_MASK, PPC403,      { RT } },
3464 { "mtiac2",  XSPR(31,467,1013), XSPR_MASK, PPC403,      { RT } },
3465 { "mtdac1",  XSPR(31,467,1014), XSPR_MASK, PPC403,      { RT } },
3466 { "mtdac2",  XSPR(31,467,1015), XSPR_MASK, PPC403,      { RT } },
3467 { "mtdccr",  XSPR(31,467,1018), XSPR_MASK, PPC403,      { RT } },
3468 { "mticcr",  XSPR(31,467,1019), XSPR_MASK, PPC403,      { RT } },
3469 { "mtpbl1",  XSPR(31,467,1020), XSPR_MASK, PPC403,      { RT } },
3470 { "mtpbu1",  XSPR(31,467,1021), XSPR_MASK, PPC403,      { RT } },
3471 { "mtpbl2",  XSPR(31,467,1022), XSPR_MASK, PPC403,      { RT } },
3472 { "mtpbu2",  XSPR(31,467,1023), XSPR_MASK, PPC403,      { RT } },
3473 { "mtummcr0",   XSPR(31,467,936),  XSPR_MASK, PPC750,   { RT } },
3474 { "mtupmc1",    XSPR(31,467,937),  XSPR_MASK, PPC750,   { RT } },
3475 { "mtupmc2",    XSPR(31,467,938),  XSPR_MASK, PPC750,   { RT } },
3476 { "mtusia",     XSPR(31,467,939),  XSPR_MASK, PPC750,   { RT } },
3477 { "mtummcr1",   XSPR(31,467,940),  XSPR_MASK, PPC750,   { RT } },
3478 { "mtupmc3",    XSPR(31,467,941),  XSPR_MASK, PPC750,   { RT } },
3479 { "mtupmc4",    XSPR(31,467,942),  XSPR_MASK, PPC750,   { RT } },
3480 { "mtmmcr0",    XSPR(31,467,952),  XSPR_MASK, PPC750,   { RT } },
3481 { "mtpmc1",     XSPR(31,467,953),  XSPR_MASK, PPC750,   { RT } },
3482 { "mtpmc2",     XSPR(31,467,954),  XSPR_MASK, PPC750,   { RT } },
3483 { "mtsia",      XSPR(31,467,955),  XSPR_MASK, PPC750,   { RT } },
3484 { "mtmmcr1",    XSPR(31,467,956),  XSPR_MASK, PPC750,   { RT } },
3485 { "mtpmc3",     XSPR(31,467,957),  XSPR_MASK, PPC750,   { RT } },
3486 { "mtpmc4",     XSPR(31,467,958),  XSPR_MASK, PPC750,   { RT } },
3487 { "mtl2cr",     XSPR(31,467,1017), XSPR_MASK, PPC750,   { RT } },
3488 { "mtictc",     XSPR(31,467,1019), XSPR_MASK, PPC750,   { RT } },
3489 { "mtthrm1",    XSPR(31,467,1020), XSPR_MASK, PPC750,   { RT } },
3490 { "mtthrm2",    XSPR(31,467,1021), XSPR_MASK, PPC750,   { RT } },
3491 { "mtthrm3",    XSPR(31,467,1022), XSPR_MASK, PPC750,   { RT } },
3492 { "mtspr",   X(31,467),        X_MASK,       COM,       { SPR, RS } },
3493
3494 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
3495
3496 { "nand",    XRC(31,476,0), X_MASK,     COM,            { RA, RS, RB } },
3497 { "nand.",   XRC(31,476,1), X_MASK,     COM,            { RA, RS, RB } },
3498
3499 { "dcbie",   X(31,478), XRT_MASK,       BOOKE64,        { RA, RB } },
3500
3501 { "dcread",  X(31,486), X_MASK,         PPC403,         { RT, RA, RB }},
3502
3503 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,           { RT, RA } },
3504 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3505 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,           { RT, RA } },
3506 { "nabso",   XO(31,488,1,0), XORB_MASK, M601,           { RT, RA } },
3507 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
3508 { "nabso.",  XO(31,488,1,1), XORB_MASK, M601,           { RT, RA } },
3509
3510 { "divd",    XO(31,489,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3511 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3512 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3513 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3514
3515 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3516 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
3517
3518 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3519 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3520 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3521 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
3522
3523 { "slbia",   X(31,498), 0xffffffff,     PPC64,          { 0 } },
3524
3525 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
3526
3527 { "stdcxe.", XRC(31,511,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
3528
3529 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), COM,        { BF } },
3530
3531 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE,      { BF } },
3532
3533 { "clcs",    X(31,531), XRB_MASK,       M601,           { RT, RA } },
3534
3535 { "lswx",    X(31,533), X_MASK,         PPCCOM,         { RT, RA, RB } },
3536 { "lsx",     X(31,533), X_MASK,         PWRCOM,         { RT, RA, RB } },
3537
3538 { "lwbrx",   X(31,534), X_MASK,         PPCCOM,         { RT, RA, RB } },
3539 { "lbrx",    X(31,534), X_MASK,         PWRCOM,         { RT, RA, RB } },
3540
3541 { "lfsx",    X(31,535), X_MASK,         COM,            { FRT, RA, RB } },
3542
3543 { "srw",     XRC(31,536,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
3544 { "sr",      XRC(31,536,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
3545 { "srw.",    XRC(31,536,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
3546 { "sr.",     XRC(31,536,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
3547
3548 { "rrib",    XRC(31,537,0), X_MASK,     M601,           { RA, RS, RB } },
3549 { "rrib.",   XRC(31,537,1), X_MASK,     M601,           { RA, RS, RB } },
3550
3551 { "srd",     XRC(31,539,0), X_MASK,     PPC64,          { RA, RS, RB } },
3552 { "srd.",    XRC(31,539,1), X_MASK,     PPC64,          { RA, RS, RB } },
3553
3554 { "maskir",  XRC(31,541,0), X_MASK,     M601,           { RA, RS, RB } },
3555 { "maskir.", XRC(31,541,1), X_MASK,     M601,           { RA, RS, RB } },
3556
3557 { "lwbrxe",  X(31,542), X_MASK,         BOOKE64,        { RT, RA, RB } },
3558
3559 { "lfsxe",   X(31,543), X_MASK,         BOOKE64,        { FRT, RA, RB } },
3560
3561 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
3562
3563 { "lfsux",   X(31,567), X_MASK,         COM,            { FRT, RAS, RB } },
3564
3565 { "lfsuxe",  X(31,575), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
3566
3567 { "mfsr",    X(31,595), XRB_MASK|(1<<20), COM32,        { RT, SR } },
3568
3569 { "lswi",    X(31,597), X_MASK,         PPCCOM,         { RT, RA, NB } },
3570 { "lsi",     X(31,597), X_MASK,         PWRCOM,         { RT, RA, NB } },
3571
3572 { "lwsync",  XSYNC(31,598,1), 0xffffffff, PPCONLY,      { 0 } },
3573 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,        { 0 } },
3574 { "sync",    X(31,598), XSYNC_MASK,     PPCCOM,         { LS } },
3575 { "dcs",     X(31,598), 0xffffffff,     PWRCOM,         { 0 } },
3576 { "msync",   X(31,598), 0xf80007fe,     BOOKE,          { 0 } },
3577
3578 { "lfdx",    X(31,599), X_MASK,         COM,            { FRT, RA, RB } },
3579
3580 { "lfdxe",   X(31,607), X_MASK,         BOOKE64,        { FRT, RA, RB } },
3581
3582 { "mfsri",   X(31,627), X_MASK,         PWRCOM,         { RT, RA, RB } },
3583
3584 { "dclst",   X(31,630), XRB_MASK,       PWRCOM,         { RS, RA } },
3585
3586 { "lfdux",   X(31,631), X_MASK,         COM,            { FRT, RAS, RB } },
3587
3588 { "lfduxe",  X(31,639), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
3589
3590 { "mfsrin",  X(31,659), XRA_MASK,       PPC32,          { RT, RB } },
3591
3592 { "stswx",   X(31,661), X_MASK,         PPCCOM,         { RS, RA, RB } },
3593 { "stsx",    X(31,661), X_MASK,         PWRCOM,         { RS, RA, RB } },
3594
3595 { "stwbrx",  X(31,662), X_MASK,         PPCCOM,         { RS, RA, RB } },
3596 { "stbrx",   X(31,662), X_MASK,         PWRCOM,         { RS, RA, RB } },
3597
3598 { "stfsx",   X(31,663), X_MASK,         COM,            { FRS, RA, RB } },
3599
3600 { "srq",     XRC(31,664,0), X_MASK,     M601,           { RA, RS, RB } },
3601 { "srq.",    XRC(31,664,1), X_MASK,     M601,           { RA, RS, RB } },
3602
3603 { "sre",     XRC(31,665,0), X_MASK,     M601,           { RA, RS, RB } },
3604 { "sre.",    XRC(31,665,1), X_MASK,     M601,           { RA, RS, RB } },
3605
3606 { "stwbrxe", X(31,670), X_MASK,         BOOKE64,        { RS, RA, RB } },
3607
3608 { "stfsxe",  X(31,671), X_MASK,         BOOKE64,        { FRS, RA, RB } },
3609
3610 { "stfsux",  X(31,695), X_MASK,         COM,            { FRS, RAS, RB } },
3611
3612 { "sriq",    XRC(31,696,0), X_MASK,     M601,           { RA, RS, SH } },
3613 { "sriq.",   XRC(31,696,1), X_MASK,     M601,           { RA, RS, SH } },
3614
3615 { "stfsuxe", X(31,703), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
3616
3617 { "stswi",   X(31,725), X_MASK,         PPCCOM,         { RS, RA, NB } },
3618 { "stsi",    X(31,725), X_MASK,         PWRCOM,         { RS, RA, NB } },
3619
3620 { "stfdx",   X(31,727), X_MASK,         COM,            { FRS, RA, RB } },
3621
3622 { "srlq",    XRC(31,728,0), X_MASK,     M601,           { RA, RS, RB } },
3623 { "srlq.",   XRC(31,728,1), X_MASK,     M601,           { RA, RS, RB } },
3624
3625 { "sreq",    XRC(31,729,0), X_MASK,     M601,           { RA, RS, RB } },
3626 { "sreq.",   XRC(31,729,1), X_MASK,     M601,           { RA, RS, RB } },
3627
3628 { "stfdxe",  X(31,735), X_MASK,         BOOKE64,        { FRS, RA, RB } },
3629
3630 { "dcba",    X(31,758), XRT_MASK,       PPC405,         { RA, RB } },
3631 { "dcba",    X(31,758), XRT_MASK,       BOOKE,          { RA, RB } },
3632
3633 { "stfdux",  X(31,759), X_MASK,         COM,            { FRS, RAS, RB } },
3634
3635 { "srliq",   XRC(31,760,0), X_MASK,     M601,           { RA, RS, SH } },
3636 { "srliq.",  XRC(31,760,1), X_MASK,     M601,           { RA, RS, SH } },
3637
3638 { "dcbae",   X(31,766), XRT_MASK,       BOOKE64,        { RA, RB } },
3639
3640 { "stfduxe", X(31,767), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
3641
3642 { "tlbivax", X(31,786), XRT_MASK,       BOOKE,          { RA, RB } },
3643 { "tlbivaxe",X(31,787), XRT_MASK,       BOOKE,          { RA, RB } },
3644
3645 { "lhbrx",   X(31,790), X_MASK,         COM,            { RT, RA, RB } },
3646
3647 { "sraw",    XRC(31,792,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
3648 { "sra",     XRC(31,792,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
3649 { "sraw.",   XRC(31,792,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
3650 { "sra.",    XRC(31,792,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
3651
3652 { "srad",    XRC(31,794,0), X_MASK,     PPC64,          { RA, RS, RB } },
3653 { "srad.",   XRC(31,794,1), X_MASK,     PPC64,          { RA, RS, RB } },
3654
3655 { "lhbrxe",  X(31,798), X_MASK,         BOOKE64,        { RT, RA, RB } },
3656
3657 { "ldxe",    X(31,799), X_MASK,         BOOKE64,        { RT, RA, RB } },
3658 { "lduxe",   X(31,831), X_MASK,         BOOKE64,        { RT, RA, RB } },
3659
3660 { "rac",     X(31,818), X_MASK,         PWRCOM,         { RT, RA, RB } },
3661
3662 { "dss",     XDSS(31,822,0), XDSS_MASK, PPCVEC,         { STRM } },
3663 { "dssall",  XDSS(31,822,1), XDSS_MASK, PPCVEC,         { STRM } },
3664
3665 { "srawi",   XRC(31,824,0), X_MASK,     PPCCOM,         { RA, RS, SH } },
3666 { "srai",    XRC(31,824,0), X_MASK,     PWRCOM,         { RA, RS, SH } },
3667 { "srawi.",  XRC(31,824,1), X_MASK,     PPCCOM,         { RA, RS, SH } },
3668 { "srai.",   XRC(31,824,1), X_MASK,     PWRCOM,         { RA, RS, SH } },
3669
3670 { "slbmfev", X(31,851), XRA_MASK,       PPC64,          { RT, RB } },
3671
3672 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
3673 { "mbar",    X(31,854), 0xffffffff,     BOOKE,          { MO } },
3674
3675 { "tlbsx",   XRC(31,914,0), X_MASK,     PPC403,         { RT, RA, RB } },
3676 { "tlbsx.",  XRC(31,914,1), X_MASK,     PPC403,         { RT, RA, RB } },
3677
3678 { "tlbsx",   XRC(31,914,0), X_MASK,     BOOKE,          { RA, RB } },
3679 { "tlbsxe",  XRC(31,915,0), X_MASK,     BOOKE,          { RA, RB } },
3680
3681 { "slbmfee", X(31,915), XRA_MASK,       PPC64,          { RT, RB } },
3682
3683 { "sthbrx",  X(31,918), X_MASK,         COM,            { RS, RA, RB } },
3684
3685 { "sraq",    XRC(31,920,0), X_MASK,     M601,           { RA, RS, RB } },
3686 { "sraq.",   XRC(31,920,1), X_MASK,     M601,           { RA, RS, RB } },
3687
3688 { "srea",    XRC(31,921,0), X_MASK,     M601,           { RA, RS, RB } },
3689 { "srea.",   XRC(31,921,1), X_MASK,     M601,           { RA, RS, RB } },
3690
3691 { "extsh",   XRC(31,922,0), XRB_MASK,   PPCCOM,         { RA, RS } },
3692 { "exts",    XRC(31,922,0), XRB_MASK,   PWRCOM,         { RA, RS } },
3693 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPCCOM,         { RA, RS } },
3694 { "exts.",   XRC(31,922,1), XRB_MASK,   PWRCOM,         { RA, RS } },
3695
3696 { "sthbrxe", X(31,926), X_MASK,         BOOKE64,        { RS, RA, RB } },
3697
3698 { "stdxe",   X(31,927), X_MASK,         BOOKE64,        { RS, RA, RB } },
3699
3700 { "tlbre",   X(31,946), X_MASK,         BOOKE,          { RT, RA, WS } },
3701
3702 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403,         { RT, RA } },
3703 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403,         { RT, RA } },
3704
3705 { "sraiq",   XRC(31,952,0), X_MASK,     M601,           { RA, RS, SH } },
3706 { "sraiq.",  XRC(31,952,1), X_MASK,     M601,           { RA, RS, SH } },
3707
3708 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
3709 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
3710
3711 { "stduxe",  X(31,959), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3712
3713 { "iccci",   X(31,966), XRT_MASK,       PPC403,         { RA, RB } },
3714
3715 { "tlbld",   X(31,978), XRTRA_MASK,     PPC,            { RB } },
3716
3717 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403,         { RT, RA } },
3718 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403,         { RT, RA } },
3719 { "tlbwe",   X(31,978), X_MASK,         PPC403,         { RS, RA, SH } },
3720
3721 { "tlbwe",   X(31,978), X_MASK,         BOOKE,          { RT, RA, WS } },
3722
3723 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
3724
3725 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA, RB } },
3726
3727 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC,            { RA, RS } },
3728 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC,            { RA, RS } },
3729
3730 { "icread",  X(31,998), XRT_MASK,       PPC403,         { RA, RB } },
3731
3732 { "icbie",   X(31,990), XRT_MASK,       BOOKE64,        { RA, RB } },
3733 { "stfiwxe", X(31,991), X_MASK,         BOOKE64,        { FRS, RA, RB } },
3734
3735 { "tlbli",   X(31,1010), XRTRA_MASK,    PPC,            { RB } },
3736
3737 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
3738 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
3739
3740 { "dcbze",   X(31,1022), XRT_MASK,      BOOKE64,        { RA, RB } },
3741
3742 { "lvebx",   X(31,   7), X_MASK,        PPCVEC,         { VD, RA, RB } },
3743 { "lvehx",   X(31,  39), X_MASK,        PPCVEC,         { VD, RA, RB } },
3744 { "lvewx",   X(31,  71), X_MASK,        PPCVEC,         { VD, RA, RB } },
3745 { "lvsl",    X(31,   6), X_MASK,        PPCVEC,         { VD, RA, RB } },
3746 { "lvsr",    X(31,  38), X_MASK,        PPCVEC,         { VD, RA, RB } },
3747 { "lvx",     X(31, 103), X_MASK,        PPCVEC,         { VD, RA, RB } },
3748 { "lvxl",    X(31, 359), X_MASK,        PPCVEC,         { VD, RA, RB } },
3749 { "stvebx",  X(31, 135), X_MASK,        PPCVEC,         { VS, RA, RB } },
3750 { "stvehx",  X(31, 167), X_MASK,        PPCVEC,         { VS, RA, RB } },
3751 { "stvewx",  X(31, 199), X_MASK,        PPCVEC,         { VS, RA, RB } },
3752 { "stvx",    X(31, 231), X_MASK,        PPCVEC,         { VS, RA, RB } },
3753 { "stvxl",   X(31, 487), X_MASK,        PPCVEC,         { VS, RA, RB } },
3754
3755 { "lwz",     OP(32),    OP_MASK,        PPCCOM,         { RT, D, RA } },
3756 { "l",       OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA } },
3757
3758 { "lwzu",    OP(33),    OP_MASK,        PPCCOM,         { RT, D, RAL } },
3759 { "lu",      OP(33),    OP_MASK,        PWRCOM,         { RT, D, RA } },
3760
3761 { "lbz",     OP(34),    OP_MASK,        COM,            { RT, D, RA } },
3762
3763 { "lbzu",    OP(35),    OP_MASK,        COM,            { RT, D, RAL } },
3764
3765 { "stw",     OP(36),    OP_MASK,        PPCCOM,         { RS, D, RA } },
3766 { "st",      OP(36),    OP_MASK,        PWRCOM,         { RS, D, RA } },
3767
3768 { "stwu",    OP(37),    OP_MASK,        PPCCOM,         { RS, D, RAS } },
3769 { "stu",     OP(37),    OP_MASK,        PWRCOM,         { RS, D, RA } },
3770
3771 { "stb",     OP(38),    OP_MASK,        COM,            { RS, D, RA } },
3772
3773 { "stbu",    OP(39),    OP_MASK,        COM,            { RS, D, RAS } },
3774
3775 { "lhz",     OP(40),    OP_MASK,        COM,            { RT, D, RA } },
3776
3777 { "lhzu",    OP(41),    OP_MASK,        COM,            { RT, D, RAL } },
3778
3779 { "lha",     OP(42),    OP_MASK,        COM,            { RT, D, RA } },
3780
3781 { "lhau",    OP(43),    OP_MASK,        COM,            { RT, D, RAL } },
3782
3783 { "sth",     OP(44),    OP_MASK,        COM,            { RS, D, RA } },
3784
3785 { "sthu",    OP(45),    OP_MASK,        COM,            { RS, D, RAS } },
3786
3787 { "lmw",     OP(46),    OP_MASK,        PPCCOM,         { RT, D, RAM } },
3788 { "lm",      OP(46),    OP_MASK,        PWRCOM,         { RT, D, RA } },
3789
3790 { "stmw",    OP(47),    OP_MASK,        PPCCOM,         { RS, D, RA } },
3791 { "stm",     OP(47),    OP_MASK,        PWRCOM,         { RS, D, RA } },
3792
3793 { "lfs",     OP(48),    OP_MASK,        COM,            { FRT, D, RA } },
3794
3795 { "lfsu",    OP(49),    OP_MASK,        COM,            { FRT, D, RAS } },
3796
3797 { "lfd",     OP(50),    OP_MASK,        COM,            { FRT, D, RA } },
3798
3799 { "lfdu",    OP(51),    OP_MASK,        COM,            { FRT, D, RAS } },
3800
3801 { "stfs",    OP(52),    OP_MASK,        COM,            { FRS, D, RA } },
3802
3803 { "stfsu",   OP(53),    OP_MASK,        COM,            { FRS, D, RAS } },
3804
3805 { "stfd",    OP(54),    OP_MASK,        COM,            { FRS, D, RA } },
3806
3807 { "stfdu",   OP(55),    OP_MASK,        COM,            { FRS, D, RAS } },
3808
3809 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA } },
3810
3811 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA } },
3812
3813 { "lbze",    DEO(58,0), DE_MASK,        BOOKE64,        { RT, DE, RA } },
3814 { "lbzue",   DEO(58,1), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
3815 { "lhze",    DEO(58,2), DE_MASK,        BOOKE64,        { RT, DE, RA } },
3816 { "lhzue",   DEO(58,3), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
3817 { "lhae",    DEO(58,4), DE_MASK,        BOOKE64,        { RT, DE, RA } },
3818 { "lhaue",   DEO(58,5), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
3819 { "lwze",    DEO(58,6), DE_MASK,        BOOKE64,        { RT, DE, RA } },
3820 { "lwzue",   DEO(58,7), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
3821 { "stbe",    DEO(58,8), DE_MASK,        BOOKE64,        { RS, DE, RA } },
3822 { "stbue",   DEO(58,9), DE_MASK,        BOOKE64,        { RS, DE, RAS } },
3823 { "sthe",    DEO(58,10), DE_MASK,       BOOKE64,        { RS, DE, RA } },
3824 { "sthue",   DEO(58,11), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
3825 { "stwe",    DEO(58,14), DE_MASK,       BOOKE64,        { RS, DE, RA } },
3826 { "stwue",   DEO(58,15), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
3827
3828 { "ld",      DSO(58,0), DS_MASK,        PPC64,          { RT, DS, RA } },
3829
3830 { "ldu",     DSO(58,1), DS_MASK,        PPC64,          { RT, DS, RAL } },
3831
3832 { "lwa",     DSO(58,2), DS_MASK,        PPC64,          { RT, DS, RA } },
3833
3834 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3835 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3836
3837 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3838 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3839
3840 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3841 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3842
3843 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3844 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3845
3846 { "fres",    A(59,24,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3847 { "fres.",   A(59,24,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3848
3849 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
3850 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
3851
3852 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3853 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3854
3855 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3856 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3857
3858 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3859 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3860
3861 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3862 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3863
3864 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
3865
3866 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
3867
3868 { "lde",     DEO(62,0), DE_MASK,        BOOKE64,        { RT, DES, RA } },
3869 { "ldue",    DEO(62,1), DE_MASK,        BOOKE64,        { RT, DES, RA } },
3870 { "lfse",    DEO(62,4), DE_MASK,        BOOKE64,        { FRT, DES, RA } },
3871 { "lfsue",   DEO(62,5), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
3872 { "lfde",    DEO(62,6), DE_MASK,        BOOKE64,        { FRT, DES, RA } },
3873 { "lfdue",   DEO(62,7), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
3874 { "stde",    DEO(62,8), DE_MASK,        BOOKE64,        { RS, DES, RA } },
3875 { "stdue",   DEO(62,9), DE_MASK,        BOOKE64,        { RS, DES, RAS } },
3876 { "stfse",   DEO(62,12), DE_MASK,       BOOKE64,        { FRS, DES, RA } },
3877 { "stfsue",  DEO(62,13), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
3878 { "stfde",   DEO(62,14), DE_MASK,       BOOKE64,        { FRS, DES, RA } },
3879 { "stfdue",  DEO(62,15), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
3880
3881 { "std",     DSO(62,0), DS_MASK,        PPC64,          { RS, DS, RA } },
3882
3883 { "stdu",    DSO(62,1), DS_MASK,        PPC64,          { RS, DS, RAS } },
3884
3885 { "fcmpu",   X(63,0),   X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
3886
3887 { "frsp",    XRC(63,12,0), XRA_MASK,    COM,            { FRT, FRB } },
3888 { "frsp.",   XRC(63,12,1), XRA_MASK,    COM,            { FRT, FRB } },
3889
3890 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3891 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
3892 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3893 { "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
3894
3895 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3896 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
3897 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3898 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
3899
3900 { "fdiv",    A(63,18,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3901 { "fd",      A(63,18,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3902 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3903 { "fd.",     A(63,18,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3904
3905 { "fsub",    A(63,20,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3906 { "fs",      A(63,20,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3907 { "fsub.",   A(63,20,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3908 { "fs.",     A(63,20,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3909
3910 { "fadd",    A(63,21,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3911 { "fa",      A(63,21,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3912 { "fadd.",   A(63,21,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3913 { "fa.",     A(63,21,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3914
3915 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
3916 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
3917
3918 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3919 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3920
3921 { "fmul",    A(63,25,0), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
3922 { "fm",      A(63,25,0), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
3923 { "fmul.",   A(63,25,1), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
3924 { "fm.",     A(63,25,1), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
3925
3926 { "frsqrte", A(63,26,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3927 { "frsqrte.",A(63,26,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3928
3929 { "fmsub",   A(63,28,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3930 { "fms",     A(63,28,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3931 { "fmsub.",  A(63,28,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3932 { "fms.",    A(63,28,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3933
3934 { "fmadd",   A(63,29,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3935 { "fma",     A(63,29,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3936 { "fmadd.",  A(63,29,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3937 { "fma.",    A(63,29,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3938
3939 { "fnmsub",  A(63,30,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3940 { "fnms",    A(63,30,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3941 { "fnmsub.", A(63,30,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3942 { "fnms.",   A(63,30,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3943
3944 { "fnmadd",  A(63,31,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3945 { "fnma",    A(63,31,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3946 { "fnmadd.", A(63,31,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3947 { "fnma.",   A(63,31,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3948
3949 { "fcmpo",   X(63,32),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
3950
3951 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  COM,            { BT } },
3952 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  COM,            { BT } },
3953
3954 { "fneg",    XRC(63,40,0), XRA_MASK,    COM,            { FRT, FRB } },
3955 { "fneg.",   XRC(63,40,1), XRA_MASK,    COM,            { FRT, FRB } },
3956
3957 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), COM,  { BF, BFA } },
3958
3959 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  COM,            { BT } },
3960 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  COM,            { BT } },
3961
3962 { "fmr",     XRC(63,72,0), XRA_MASK,    COM,            { FRT, FRB } },
3963 { "fmr.",    XRC(63,72,1), XRA_MASK,    COM,            { FRT, FRB } },
3964
3965 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3966 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3967
3968 { "fnabs",   XRC(63,136,0), XRA_MASK,   COM,            { FRT, FRB } },
3969 { "fnabs.",  XRC(63,136,1), XRA_MASK,   COM,            { FRT, FRB } },
3970
3971 { "fabs",    XRC(63,264,0), XRA_MASK,   COM,            { FRT, FRB } },
3972 { "fabs.",   XRC(63,264,1), XRA_MASK,   COM,            { FRT, FRB } },
3973
3974 { "mffs",    XRC(63,583,0), XRARB_MASK, COM,            { FRT } },
3975 { "mffs.",   XRC(63,583,1), XRARB_MASK, COM,            { FRT } },
3976
3977 { "mtfsf",   XFL(63,711,0), XFL_MASK,   COM,            { FLM, FRB } },
3978 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   COM,            { FLM, FRB } },
3979
3980 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3981 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3982
3983 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3984 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3985
3986 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3987 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3988
3989 };
3990
3991 const int powerpc_num_opcodes =
3992   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
3993 \f
3994 /* The macro table.  This is only used by the assembler.  */
3995
3996 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
3997    when x=0; 32-x when x is between 1 and 31; are negative if x is
3998    negative; and are 32 or more otherwise.  This is what you want
3999    when, for instance, you are emulating a right shift by a
4000    rotate-left-and-mask, because the underlying instructions support
4001    shifts of size 0 but not shifts of size 32.  By comparison, when
4002    extracting x bits from some word you want to use just 32-x, because
4003    the underlying instructions don't support extracting 0 bits but do
4004    support extracting the whole word (32 bits in this case).  */
4005
4006 const struct powerpc_macro powerpc_macros[] = {
4007 { "extldi",  4,   PPC64,        "rldicr %0,%1,%3,(%2)-1" },
4008 { "extldi.", 4,   PPC64,        "rldicr. %0,%1,%3,(%2)-1" },
4009 { "extrdi",  4,   PPC64,        "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4010 { "extrdi.", 4,   PPC64,        "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4011 { "insrdi",  4,   PPC64,        "rldimi %0,%1,64-((%2)+(%3)),%3" },
4012 { "insrdi.", 4,   PPC64,        "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4013 { "rotrdi",  3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4014 { "rotrdi.", 3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4015 { "sldi",    3,   PPC64,        "rldicr %0,%1,%2,63-(%2)" },
4016 { "sldi.",   3,   PPC64,        "rldicr. %0,%1,%2,63-(%2)" },
4017 { "srdi",    3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4018 { "srdi.",   3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4019 { "clrrdi",  3,   PPC64,        "rldicr %0,%1,0,63-(%2)" },
4020 { "clrrdi.", 3,   PPC64,        "rldicr. %0,%1,0,63-(%2)" },
4021 { "clrlsldi",4,   PPC64,        "rldic %0,%1,%3,(%2)-(%3)" },
4022 { "clrlsldi.",4,  PPC64,        "rldic. %0,%1,%3,(%2)-(%3)" },
4023
4024 { "extlwi",  4,   PPCCOM,       "rlwinm %0,%1,%3,0,(%2)-1" },
4025 { "extlwi.", 4,   PPCCOM,       "rlwinm. %0,%1,%3,0,(%2)-1" },
4026 { "extrwi",  4,   PPCCOM,       "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
4027 { "extrwi.", 4,   PPCCOM,       "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
4028 { "inslwi",  4,   PPCCOM,       "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4029 { "inslwi.", 4,   PPCCOM,       "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4030 { "insrwi",  4,   PPCCOM,       "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4031 { "insrwi.", 4,   PPCCOM,       "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4032 { "rotrwi",  3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4033 { "rotrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4034 { "slwi",    3,   PPCCOM,       "rlwinm %0,%1,%2,0,31-(%2)" },
4035 { "sli",     3,   PWRCOM,       "rlinm %0,%1,%2,0,31-(%2)" },
4036 { "slwi.",   3,   PPCCOM,       "rlwinm. %0,%1,%2,0,31-(%2)" },
4037 { "sli.",    3,   PWRCOM,       "rlinm. %0,%1,%2,0,31-(%2)" },
4038 { "srwi",    3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4039 { "sri",     3,   PWRCOM,       "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4040 { "srwi.",   3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4041 { "sri.",    3,   PWRCOM,       "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4042 { "clrrwi",  3,   PPCCOM,       "rlwinm %0,%1,0,0,31-(%2)" },
4043 { "clrrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,0,0,31-(%2)" },
4044 { "clrlslwi",4,   PPCCOM,       "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4045 { "clrlslwi.",4,  PPCCOM,       "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4046
4047 };
4048
4049 const int powerpc_num_macros =
4050   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);