opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5 This file is part of GDB, GAS, and the GNU binutils.
   6
   7 GDB, GAS, and the GNU binutils are free software; you can redistribute
   8 them and/or modify them under the terms of the GNU General Public
   9 License as published by the Free Software Foundation; either version
  10 2, or (at your option) any later version.
  11
  12 GDB, GAS, and the GNU binutils are distributed in the hope that they
  13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15 the GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this file; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
  20
  21 #include <stdio.h>
  22 #include "ansidecl.h"
  23 #include "opcode/ppc.h"
  24
  25 /* This file holds the PowerPC opcode table.  The opcode table
  26    includes almost all of the extended instruction mnemonics.  This
  27    permits the disassembler to use them, and simplifies the assembler
  28    logic, at the cost of increasing the table size.  The table is
  29    strictly constant data, so the compiler should be able to put it in
  30    the .text section.
  31
  32    This file also holds the operand table.  All knowledge about
  33    inserting operands into instructions and vice-versa is kept in this
  34    file.  */
  35 \f
  36 /* Local insertion and extraction functions.  */
  37
  38 static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));
  39 static long extract_bat PARAMS ((unsigned long, int *));
  40 static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));
  41 static long extract_bba PARAMS ((unsigned long, int *));
  42 static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
  43 static long extract_bd PARAMS ((unsigned long, int *));
  44 static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));
  45 static long extract_bdm PARAMS ((unsigned long, int *));
  46 static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));
  47 static long extract_bdp PARAMS ((unsigned long, int *));
  48 static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
  49 static long extract_bo PARAMS ((unsigned long, int *));
  50 static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));
  51 static long extract_boe PARAMS ((unsigned long, int *));
  52 static unsigned long insert_cr PARAMS ((unsigned long, long, const char **));
  53 static long extract_cr PARAMS ((unsigned long, int *));
  54 static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
  55 static long extract_ds PARAMS ((unsigned long, int *));
  56 static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
  57 static long extract_li PARAMS ((unsigned long, int *));
  58 static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));
  59 static long extract_mbe PARAMS ((unsigned long, int *));
  60 static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));
  61 static long extract_mb6 PARAMS ((unsigned long, int *));
  62 static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
  63 static long extract_nb PARAMS ((unsigned long, int *));
  64 static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
  65 static long extract_nsi PARAMS ((unsigned long, int *));
  66 static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
  67 static long extract_rbs PARAMS ((unsigned long, int *));
  68 static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
  69 static long extract_sh6 PARAMS ((unsigned long, int *));
  70 static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
  71 static long extract_spr PARAMS ((unsigned long, int *));
  72 \f
  73 /* The operands table.
  74
  75    The fields are bits, shift, signed, insert, extract, flags.  */
  76
  77 const struct powerpc_operand powerpc_operands[] =
  78 {
  79   /* The zero index is used to indicate the end of the list of
  80      operands.  */
  81 #define UNUSED (0)
  82   { 0, 0, 0, 0, 0 },
  83
  84   /* The BA field in an XL form instruction.  */
  85 #define BA (UNUSED + 1)
  86 #define BA_MASK (0x1f << 16)
  87   { 5, 16, 0, 0, PPC_OPERAND_CR },
  88
  89   /* The BA field in an XL form instruction when it must be the same
  90      as the BT field in the same instruction.  */
  91 #define BAT (BA + 1)
  92   { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
  93
  94   /* The BB field in an XL form instruction.  */
  95 #define BB (BAT + 1)
  96 #define BB_MASK (0x1f << 11)
  97   { 5, 11, 0, 0, PPC_OPERAND_CR },
  98
  99   /* The BB field in an XL form instruction when it must be the same
 100      as the BA field in the same instruction.  */
 101 #define BBA (BB + 1)
 102   { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 103
 104   /* The BD field in a B form instruction.  The lower two bits are
 105      forced to zero.  */
 106 #define BD (BBA + 1)
 107   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 108
 109   /* The BD field in a B form instruction when absolute addressing is
 110      used.  */
 111 #define BDA (BD + 1)
 112   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 113
 114   /* The BD field in a B form instruction when the - modifier is used.
 115      This sets the y bit of the BO field appropriately.  */
 116 #define BDM (BDA + 1)
 117   { 16, 0, insert_bdm, extract_bdm,
 118       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 119
 120   /* The BD field in a B form instruction when the - modifier is used
 121      and absolute address is used.  */
 122 #define BDMA (BDM + 1)
 123   { 16, 0, insert_bdm, extract_bdm,
 124       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 125
 126   /* The BD field in a B form instruction when the + modifier is used.
 127      This sets the y bit of the BO field appropriately.  */
 128 #define BDP (BDMA + 1)
 129   { 16, 0, insert_bdp, extract_bdp,
 130       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 131
 132   /* The BD field in a B form instruction when the + modifier is used
 133      and absolute addressing is used.  */
 134 #define BDPA (BDP + 1)
 135   { 16, 0, insert_bdp, extract_bdp,
 136       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 137
 138   /* The BF field in an X or XL form instruction.  */
 139 #define BF (BDPA + 1)
 140   { 3, 23, 0, 0, PPC_OPERAND_CR },
 141
 142   /* An optional BF field.  This is used for comparison instructions,
 143      in which an omitted BF field is taken as zero.  */
 144 #define OBF (BF + 1)
 145   { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 146
 147   /* The BFA field in an X or XL form instruction.  */
 148 #define BFA (OBF + 1)
 149   { 3, 18, 0, 0, PPC_OPERAND_CR },
 150
 151   /* The BI field in a B form or XL form instruction.  */
 152 #define BI (BFA + 1)
 153 #define BI_MASK (0x1f << 16)
 154   { 5, 16, 0, 0, PPC_OPERAND_CR },
 155
 156   /* The BO field in a B form instruction.  Certain values are
 157      illegal.  */
 158 #define BO (BI + 1)
 159 #define BO_MASK (0x1f << 21)
 160   { 5, 21, insert_bo, extract_bo, 0 },
 161
 162   /* The BO field in a B form instruction when the + or - modifier is
 163      used.  This is like the BO field, but it must be even.  */
 164 #define BOE (BO + 1)
 165   { 5, 21, insert_boe, extract_boe, 0 },
 166
 167   /* The BT field in an X or XL form instruction.  */
 168 #define BT (BOE + 1)
 169   { 5, 21, 0, 0, PPC_OPERAND_CR },
 170
 171   /* The condition register number portion of the BI field in a B form
 172      or XL form instruction.  This is used for the extended
 173      conditional branch mnemonics, which set the lower two bits of the
 174      BI field.  This field is optional.  */
 175 #define CR (BT + 1)
 176   { 5, 16, insert_cr, extract_cr, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 177
 178   /* The D field in a D form instruction.  This is a displacement off
 179      a register, and implies that the next operand is a register in
 180      parentheses.  */
 181 #define D (CR + 1)
 182   { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 183
 184   /* The DS field in a DS form instruction.  This is like D, but the
 185      lower two bits are forced to zero.  */
 186 #define DS (D + 1)
 187   { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 188
 189   /* The FL1 field in a POWER SC form instruction.  */
 190 #define FL1 (DS + 1)
 191   { 4, 12, 0, 0, 0 },
 192
 193   /* The FL2 field in a POWER SC form instruction.  */
 194 #define FL2 (FL1 + 1)
 195   { 3, 2, 0, 0, 0 },
 196
 197   /* The FLM field in an XFL form instruction.  */
 198 #define FLM (FL2 + 1)
 199   { 8, 17, 0, 0, 0 },
 200
 201   /* The FRA field in an X or A form instruction.  */
 202 #define FRA (FLM + 1)
 203 #define FRA_MASK (0x1f << 16)
 204   { 5, 16, 0, 0, PPC_OPERAND_FPR },
 205
 206   /* The FRB field in an X or A form instruction.  */
 207 #define FRB (FRA + 1)
 208 #define FRB_MASK (0x1f << 11)
 209   { 5, 11, 0, 0, PPC_OPERAND_FPR },
 210
 211   /* The FRC field in an A form instruction.  */
 212 #define FRC (FRB + 1)
 213 #define FRC_MASK (0x1f << 6)
 214   { 5, 6, 0, 0, PPC_OPERAND_FPR },
 215
 216   /* The FRS field in an X form instruction or the FRT field in a D, X
 217      or A form instruction.  */
 218 #define FRS (FRC + 1)
 219 #define FRT (FRS)
 220   { 5, 21, 0, 0, PPC_OPERAND_FPR },
 221
 222   /* The FXM field in an XFX instruction.  */
 223 #define FXM (FRS + 1)
 224   { 8, 12, 0, 0, 0 },
 225
 226   /* The L field in a D or X form instruction.  */
 227 #define L (FXM + 1)
 228   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 229
 230   /* The LEV field in a POWER SC form instruction.  */
 231 #define LEV (L + 1)
 232   { 7, 5, 0, 0, 0 },
 233
 234   /* The LI field in an I form instruction.  The lower two bits are
 235      forced to zero.  */
 236 #define LI (LEV + 1)
 237   { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 238
 239   /* The LI field in an I form instruction when used as an absolute
 240      address.  */
 241 #define LIA (LI + 1)
 242   { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 243
 244   /* The MB field in an M form instruction.  */
 245 #define MB (LIA + 1)
 246 #define MB_MASK (0x1f << 6)
 247   { 5, 6, 0, 0, 0 },
 248
 249   /* The ME field in an M form instruction.  */
 250 #define ME (MB + 1)
 251 #define ME_MASK (0x1f << 1)
 252   { 5, 1, 0, 0, 0 },
 253
 254   /* The MB and ME fields in an M form instruction expressed a single
 255      operand which is a bitmask indicating which bits to select.  This
 256      is a two operand form using PPC_OPERAND_NEXT.  See the
 257      description in opcode/ppc.h for what this means.  */
 258 #define MBE (ME + 1)
 259   { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 260   { 32, 0, insert_mbe, extract_mbe, 0 },
 261
 262   /* The MB or ME field in an MD or MDS form instruction.  The high
 263      bit is wrapped to the low end.  */
 264 #define MB6 (MBE + 2)
 265 #define ME6 (MB6)
 266 #define MB6_MASK (0x3f << 5)
 267   { 6, 5, insert_mb6, extract_mb6, 0 },
 268
 269   /* The NB field in an X form instruction.  The value 32 is stored as
 270      0.  */
 271 #define NB (MB6 + 1)
 272   { 6, 11, insert_nb, extract_nb, 0 },
 273
 274   /* The NSI field in a D form instruction.  This is the same as the
 275      SI field, only negated.  */
 276 #define NSI (NB + 1)
 277   { 16, 0, insert_nsi, extract_nsi,
 278       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 279
 280   /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */
 281 #define RA (NSI + 1)
 282 #define RA_MASK (0x1f << 16)
 283   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 284
 285   /* The RB field in an X, XO, M, or MDS form instruction.  */
 286 #define RB (RA + 1)
 287 #define RB_MASK (0x1f << 11)
 288   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 289
 290   /* The RB field in an X form instruction when it must be the same as
 291      the RS field in the instruction.  This is used for extended
 292      mnemonics like mr.  */
 293 #define RBS (RB + 1)
 294   { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 295
 296   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 297      instruction or the RT field in a D, DS, X, XFX or XO form
 298      instruction.  */
 299 #define RS (RBS + 1)
 300 #define RT (RS)
 301 #define RT_MASK (0x1f << 21)
 302   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 303
 304   /* The SH field in an X or M form instruction.  */
 305 #define SH (RS + 1)
 306 #define SH_MASK (0x1f << 11)
 307   { 5, 11, 0, 0, 0 },
 308
 309   /* The SH field in an MD form instruction.  This is split.  */
 310 #define SH6 (SH + 1)
 311 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 312   { 6, 1, insert_sh6, extract_sh6, 0 },
 313
 314   /* The SI field in a D form instruction.  */
 315 #define SI (SH6 + 1)
 316   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 317
 318   /* The SI field in a D form instruction when we accept a wide range
 319      of positive values.  */
 320 #define SISIGNOPT (SI + 1)
 321   { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 322
 323   /* The SPR or TBR field in an XFX form instruction.  This is
 324      flipped--the lower 5 bits are stored in the upper 5 and vice-
 325      versa.  */
 326 #define SPR (SISIGNOPT + 1)
 327 #define TBR (SPR)
 328 #define SPR_MASK (0x3ff << 11)
 329   { 10, 11, insert_spr, extract_spr, 0 },
 330
 331   /* The SR field in an X form instruction.  */
 332 #define SR (SPR + 1)
 333   { 4, 16, 0, 0, 0 },
 334
 335   /* The SV field in a POWER SC form instruction.  */
 336 #define SV (SR + 1)
 337   { 14, 2, 0, 0, 0 },
 338
 339   /* The TO field in a D or X form instruction.  */
 340 #define TO (SV + 1)
 341 #define TO_MASK (0x1f << 21)
 342   { 5, 21, 0, 0, 0 },
 343
 344   /* The U field in an X form instruction.  */
 345 #define U (TO + 1)
 346   { 4, 12, 0, 0, 0 },
 347
 348   /* The UI field in a D form instruction.  */
 349 #define UI (U + 1)
 350   { 16, 0, 0, 0, 0 },
 351 };
 352
 353 /* The functions used to insert and extract complicated operands.  */
 354
 355 /* The BA field in an XL form instruction when it must be the same as
 356    the BT field in the same instruction.  This operand is marked FAKE.
 357    The insertion function just copies the BT field into the BA field,
 358    and the extraction function just checks that the fields are the
 359    same.  */
 360
 361 /*ARGSUSED*/
 362 static unsigned long
 363 insert_bat (insn, value, errmsg)
 364      unsigned long insn;
 365      long value;
 366      const char **errmsg;
 367 {
 368   return insn | (((insn >> 21) & 0x1f) << 16);
 369 }
 370
 371 static long
 372 extract_bat (insn, invalid)
 373      unsigned long insn;
 374      int *invalid;
 375 {
 376   if (invalid != (int *) NULL
 377       && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 378     *invalid = 1;
 379   return 0;
 380 }
 381
 382 /* The BB field in an XL form instruction when it must be the same as
 383    the BA field in the same instruction.  This operand is marked FAKE.
 384    The insertion function just copies the BA field into the BB field,
 385    and the extraction function just checks that the fields are the
 386    same.  */
 387
 388 /*ARGSUSED*/
 389 static unsigned long
 390 insert_bba (insn, value, errmsg)
 391      unsigned long insn;
 392      long value;
 393      const char **errmsg;
 394 {
 395   return insn | (((insn >> 16) & 0x1f) << 11);
 396 }
 397
 398 static long
 399 extract_bba (insn, invalid)
 400      unsigned long insn;
 401      int *invalid;
 402 {
 403   if (invalid != (int *) NULL
 404       && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 405     *invalid = 1;
 406   return 0;
 407 }
 408
 409 /* The BD field in a B form instruction.  The lower two bits are
 410    forced to zero.  */
 411
 412 /*ARGSUSED*/
 413 static unsigned long
 414 insert_bd (insn, value, errmsg)
 415      unsigned long insn;
 416      long value;
 417      const char **errmsg;
 418 {
 419   return insn | (value & 0xfffc);
 420 }
 421
 422 /*ARGSUSED*/
 423 static long
 424 extract_bd (insn, invalid)
 425      unsigned long insn;
 426      int *invalid;
 427 {
 428   if ((insn & 0x8000) != 0)
 429     return (insn & 0xfffc) - 0x10000;
 430   else
 431     return insn & 0xfffc;
 432 }
 433
 434 /* The BD field in a B form instruction when the - modifier is used.
 435    This modifier means that the branch is not expected to be taken.
 436    We must set the y bit of the BO field to 1 if the offset is
 437    negative.  When extracting, we require that the y bit be 1 and that
 438    the offset be positive, since if the y bit is 0 we just want to
 439    print the normal form of the instruction.  */
 440
 441 /*ARGSUSED*/
 442 static unsigned long
 443 insert_bdm (insn, value, errmsg)
 444      unsigned long insn;
 445      long value;
 446      const char **errmsg;
 447 {
 448   if ((value & 0x8000) != 0)
 449     insn |= 1 << 21;
 450   return insn | (value & 0xfffc);
 451 }
 452
 453 static long
 454 extract_bdm (insn, invalid)
 455      unsigned long insn;
 456      int *invalid;
 457 {
 458   if (invalid != (int *) NULL
 459       && ((insn & (1 << 21)) == 0
 460           || (insn & (1 << 15) == 0)))
 461     *invalid = 1;
 462   if ((insn & 0x8000) != 0)
 463     return (insn & 0xfffc) - 0x10000;
 464   else
 465     return insn & 0xfffc;
 466 }
 467
 468 /* The BD field in a B form instruction when the + modifier is used.
 469    This is like BDM, above, except that the branch is expected to be
 470    taken.  */
 471
 472 /*ARGSUSED*/
 473 static unsigned long
 474 insert_bdp (insn, value, errmsg)
 475      unsigned long insn;
 476      long value;
 477      const char **errmsg;
 478 {
 479   if ((value & 0x8000) == 0)
 480     insn |= 1 << 21;
 481   return insn | (value & 0xfffc);
 482 }
 483
 484 static long
 485 extract_bdp (insn, invalid)
 486      unsigned long insn;
 487      int *invalid;
 488 {
 489   if (invalid != (int *) NULL
 490       && ((insn & (1 << 21)) == 0
 491           || (insn & (1 << 15)) != 0))
 492     *invalid = 1;
 493   if ((insn & 0x8000) != 0)
 494     return (insn & 0xfffc) - 0x10000;
 495   else
 496     return insn & 0xfffc;
 497 }
 498
 499 /* Check for legal values of a BO field.  */
 500
 501 static int
 502 valid_bo (value)
 503      long value;
 504 {
 505   /* Certain encodings have bits that are required to be zero.  These
 506      are (z must be zero, y may be anything):
 507          001zy
 508          011zy
 509          1z00y
 510          1z01y
 511          1z1zz
 512      */
 513   switch (value & 0x14)
 514     {
 515     default:
 516     case 0:
 517       return 1;
 518     case 0x4:
 519       return (value & 0x2) == 0;
 520     case 0x10:
 521       return (value & 0x8) == 0;
 522     case 0x14:
 523       return value == 0x14;
 524     }
 525 }
 526
 527 /* The BO field in a B form instruction.  Warn about attempts to set
 528    the field to an illegal value.  */
 529
 530 static unsigned long
 531 insert_bo (insn, value, errmsg)
 532      unsigned long insn;
 533      long value;
 534      const char **errmsg;
 535 {
 536   if (errmsg != (const char **) NULL
 537       && ! valid_bo (value))
 538     *errmsg = "invalid conditional option";
 539   return insn | ((value & 0x1f) << 21);
 540 }
 541
 542 static long
 543 extract_bo (insn, invalid)
 544      unsigned long insn;
 545      int *invalid;
 546 {
 547   long value;
 548
 549   value = (insn >> 21) & 0x1f;
 550   if (invalid != (int *) NULL
 551       && ! valid_bo (value))
 552     *invalid = 1;
 553   return value;
 554 }
 555
 556 /* The BO field in a B form instruction when the + or - modifier is
 557    used.  This is like the BO field, but it must be even.  When
 558    extracting it, we force it to be even.  */
 559
 560 static unsigned long
 561 insert_boe (insn, value, errmsg)
 562      unsigned long insn;
 563      long value;
 564      const char **errmsg;
 565 {
 566   if (errmsg != (const char **) NULL)
 567     {
 568       if (! valid_bo (value))
 569         *errmsg = "invalid conditional option";
 570       else if ((value & 1) != 0)
 571         *errmsg = "attempt to set y bit when using + or - modifier";
 572     }
 573   return insn | ((value & 0x1f) << 21);
 574 }
 575
 576 static long
 577 extract_boe (insn, invalid)
 578      unsigned long insn;
 579      int *invalid;
 580 {
 581   long value;
 582
 583   value = (insn >> 21) & 0x1f;
 584   if (invalid != (int *) NULL
 585       && ! valid_bo (value))
 586     *invalid = 1;
 587   return value & 0x1e;
 588 }
 589
 590 /* The condition register number portion of the BI field in a B form
 591    or XL form instruction.  This is used for the extended conditional
 592    branch mnemonics, which set the lower two bits of the BI field.  It
 593    is the BI field with the lower two bits ignored.  */
 594
 595 /*ARGSUSED*/
 596 static unsigned long
 597 insert_cr (insn, value, errmsg)
 598      unsigned long insn;
 599      long value;
 600      const char **errmsg;
 601 {
 602   return insn | ((value & 0x1c) << 16);
 603 }
 604
 605 /*ARGSUSED*/
 606 static long
 607 extract_cr (insn, invalid)
 608      unsigned long insn;
 609      int *invalid;
 610 {
 611   return (insn >> 16) & 0x1c;
 612 }
 613
 614 /* The DS field in a DS form instruction.  This is like D, but the
 615    lower two bits are forced to zero.  */
 616
 617 /*ARGSUSED*/
 618 static unsigned long
 619 insert_ds (insn, value, errmsg)
 620      unsigned long insn;
 621      long value;
 622      const char **errmsg;
 623 {
 624   return insn | (value & 0xfffc);
 625 }
 626
 627 /*ARGSUSED*/
 628 static long
 629 extract_ds (insn, invalid)
 630      unsigned long insn;
 631      int *invalid;
 632 {
 633   if ((insn & 0x8000) != 0)
 634     return (insn & 0xfffc) - 0x10000;
 635   else
 636     return insn & 0xfffc;
 637 }
 638
 639 /* The LI field in an I form instruction.  The lower two bits are
 640    forced to zero.  */
 641
 642 /*ARGSUSED*/
 643 static unsigned long
 644 insert_li (insn, value, errmsg)
 645      unsigned long insn;
 646      long value;
 647      const char **errmsg;
 648 {
 649   return insn | (value & 0x3fffffc);
 650 }
 651
 652 /*ARGSUSED*/
 653 static long
 654 extract_li (insn, invalid)
 655      unsigned long insn;
 656      int *invalid;
 657 {
 658   if ((insn & 0x2000000) != 0)
 659     return (insn & 0x3fffffc) - 0x4000000;
 660   else
 661     return insn & 0x3fffffc;
 662 }
 663
 664 /* The MB and ME fields in an M form instruction expressed as a single
 665    operand which is itself a bitmask.  The extraction function always
 666    marks it as invalid, since we never want to recognize an
 667    instruction which uses a field of this type.  */
 668
 669 static unsigned long
 670 insert_mbe (insn, value, errmsg)
 671      unsigned long insn;
 672      long value;
 673      const char **errmsg;
 674 {
 675   unsigned long uval;
 676   int mb, me;
 677
 678   uval = value;
 679
 680   if (uval == 0)
 681     {
 682       if (errmsg != (const char **) NULL)
 683         *errmsg = "illegal bitmask";
 684       return insn;
 685     }
 686
 687   me = 31;
 688   while ((uval & 1) == 0)
 689     {
 690       uval >>= 1;
 691       --me;
 692     }
 693
 694   mb = me;
 695   uval >>= 1;
 696   while ((uval & 1) != 0)
 697     {
 698       uval >>= 1;
 699       --mb;
 700     }
 701
 702   if (uval != 0)
 703     {
 704       if (errmsg != (const char **) NULL)
 705         *errmsg = "illegal bitmask";
 706     }
 707
 708   return insn | (mb << 6) | (me << 1);
 709 }
 710
 711 static long
 712 extract_mbe (insn, invalid)
 713      unsigned long insn;
 714      int *invalid;
 715 {
 716   long ret;
 717   int mb, me;
 718   int i;
 719
 720   if (invalid != (int *) NULL)
 721     *invalid = 1;
 722
 723   ret = 0;
 724   mb = (insn >> 6) & 0x1f;
 725   me = (insn >> 1) & 0x1f;
 726   for (i = mb; i < me; i++)
 727     ret |= 1 << (31 - i);
 728   return ret;
 729 }
 730
 731 /* The MB or ME field in an MD or MDS form instruction.  The high bit
 732    is wrapped to the low end.  */
 733
 734 /*ARGSUSED*/
 735 static unsigned long
 736 insert_mb6 (insn, value, errmsg)
 737      unsigned long insn;
 738      long value;
 739      const char **errmsg;
 740 {
 741   return insn | ((value & 0x1f) << 6) | (value & 0x20);
 742 }
 743
 744 /*ARGSUSED*/
 745 static long
 746 extract_mb6 (insn, invalid)
 747      unsigned long insn;
 748      int *invalid;
 749 {
 750   return ((insn >> 6) & 0x1f) | (insn & 0x20);
 751 }
 752
 753 /* The NB field in an X form instruction.  The value 32 is stored as
 754    0.  */
 755
 756 static unsigned long
 757 insert_nb (insn, value, errmsg)
 758      unsigned long insn;
 759      long value;
 760      const char **errmsg;
 761 {
 762   if (value < 0 || value > 32)
 763     *errmsg = "value out of range";
 764   if (value == 32)
 765     value = 0;
 766   return insn | ((value & 0x1f) << 11);
 767 }
 768
 769 /*ARGSUSED*/
 770 static long
 771 extract_nb (insn, invalid)
 772      unsigned long insn;
 773      int *invalid;
 774 {
 775   long ret;
 776
 777   ret = (insn >> 11) & 0x1f;
 778   if (ret == 0)
 779     ret = 32;
 780   return ret;
 781 }
 782
 783 /* The NSI field in a D form instruction.  This is the same as the SI
 784    field, only negated.  The extraction function always marks it as
 785    invalid, since we never want to recognize an instruction which uses
 786    a field of this type.  */
 787
 788 /*ARGSUSED*/
 789 static unsigned long
 790 insert_nsi (insn, value, errmsg)
 791      unsigned long insn;
 792      long value;
 793      const char **errmsg;
 794 {
 795   return insn | ((- value) & 0xffff);
 796 }
 797
 798 static long
 799 extract_nsi (insn, invalid)
 800      unsigned long insn;
 801      int *invalid;
 802 {
 803   if (invalid != (int *) NULL)
 804     *invalid = 1;
 805   if ((insn & 0x8000) != 0)
 806     return - ((insn & 0xffff) - 0x10000);
 807   else
 808     return - (insn & 0xffff);
 809 }
 810
 811 /* The RB field in an X form instruction when it must be the same as
 812    the RS field in the instruction.  This is used for extended
 813    mnemonics like mr.  This operand is marked FAKE.  The insertion
 814    function just copies the BT field into the BA field, and the
 815    extraction function just checks that the fields are the same.  */
 816
 817 /*ARGSUSED*/
 818 static unsigned long
 819 insert_rbs (insn, value, errmsg)
 820      unsigned long insn;
 821      long value;
 822      const char **errmsg;
 823 {
 824   return insn | (((insn >> 21) & 0x1f) << 11);
 825 }
 826
 827 static long
 828 extract_rbs (insn, invalid)
 829      unsigned long insn;
 830      int *invalid;
 831 {
 832   if (invalid != (int *) NULL
 833       && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
 834     *invalid = 1;
 835   return 0;
 836 }
 837
 838 /* The SH field in an MD form instruction.  This is split.  */
 839
 840 /*ARGSUSED*/
 841 static unsigned long
 842 insert_sh6 (insn, value, errmsg)
 843      unsigned long insn;
 844      long value;
 845      const char **errmsg;
 846 {
 847   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
 848 }
 849
 850 /*ARGSUSED*/
 851 static long
 852 extract_sh6 (insn, invalid)
 853      unsigned long insn;
 854      int *invalid;
 855 {
 856   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
 857 }
 858
 859 /* The SPR or TBR field in an XFX form instruction.  This is
 860    flipped--the lower 5 bits are stored in the upper 5 and vice-
 861    versa.  */
 862
 863 static unsigned long
 864 insert_spr (insn, value, errmsg)
 865      unsigned long insn;
 866      long value;
 867      const char **errmsg;
 868 {
 869   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
 870 }
 871
 872 static long
 873 extract_spr (insn, invalid)
 874      unsigned long insn;
 875      int *invalid;
 876 {
 877   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
 878 }
 879 \f
 880 /* Macros used to form opcodes.  */
 881
 882 /* The main opcode.  */
 883 #define OP(x) (((x) & 0x3f) << 26)
 884 #define OP_MASK OP (0x3f)
 885
 886 /* The main opcode combined with a trap code in the TO field of a D
 887    form instruction.  Used for extended mnemonics for the trap
 888    instructions.  */
 889 #define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21))
 890 #define OPTO_MASK (OP_MASK | TO_MASK)
 891
 892 /* The main opcode combined with a comparison size bit in the L field
 893    of a D form or X form instruction.  Used for extended mnemonics for
 894    the comparison instructions.  */
 895 #define OPL(x,l) (OP (x) | (((l) & 1) << 21))
 896 #define OPL_MASK OPL (0x3f,1)
 897
 898 /* An A form instruction.  */
 899 #define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1))
 900 #define A_MASK A (0x3f, 0x1f, 1)
 901
 902 /* An A_MASK with the FRB field fixed.  */
 903 #define AFRB_MASK (A_MASK | FRB_MASK)
 904
 905 /* An A_MASK with the FRC field fixed.  */
 906 #define AFRC_MASK (A_MASK | FRC_MASK)
 907
 908 /* An A_MASK with the FRA and FRC fields fixed.  */
 909 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
 910
 911 /* A B form instruction.  */
 912 #define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1))
 913 #define B_MASK B (0x3f, 1, 1)
 914
 915 /* A B form instruction setting the BO field.  */
 916 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21))
 917 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
 918
 919 /* A BBO_MASK with the y bit of the BO field removed.  This permits
 920    matching a conditional branch regardless of the setting of the y
 921    bit.  */
 922 #define Y_MASK (1 << 21)
 923 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
 924
 925 /* A B form instruction setting the BO field and the condition bits of
 926    the BI field.  */
 927 #define BBOCB(op, bo, cb, aa, lk) \
 928   (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16))
 929 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
 930
 931 /* A BBOCB_MASK with the y bit of the BO field removed.  */
 932 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
 933
 934 /* A BBOYCB_MASK in which the BI field is fixed.  */
 935 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
 936
 937 /* The main opcode mask with the RA field clear.  */
 938 #define DRA_MASK (OP_MASK | RA_MASK)
 939
 940 /* A DS form instruction.  */
 941 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
 942 #define DS_MASK DSO (0x3f, 3)
 943
 944 /* An M form instruction.  */
 945 #define M(op, rc) (OP (op) | ((rc) & 1))
 946 #define M_MASK M (0x3f, 1)
 947
 948 /* An M form instruction with the ME field specified.  */
 949 #define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1))
 950
 951 /* An M_MASK with the MB and ME fields fixed.  */
 952 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
 953
 954 /* An M_MASK with the SH and ME fields fixed.  */
 955 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
 956
 957 /* An MD form instruction.  */
 958 #define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1))
 959 #define MD_MASK MD (0x3f, 0x7, 1)
 960
 961 /* An MD_MASK with the MB field fixed.  */
 962 #define MDMB_MASK (MD_MASK | MB6_MASK)
 963
 964 /* An MD_MASK with the SH field fixed.  */
 965 #define MDSH_MASK (MD_MASK | SH6_MASK)
 966
 967 /* An MDS form instruction.  */
 968 #define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1))
 969 #define MDS_MASK MDS (0x3f, 0xf, 1)
 970
 971 /* An MDS_MASK with the MB field fixed.  */
 972 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
 973
 974 /* An SC form instruction.  */
 975 #define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1))
 976 #define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1)
 977
 978 /* An X form instruction.  */
 979 #define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
 980
 981 /* An X form instruction with the RC bit specified.  */
 982 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
 983
 984 /* The mask for an X form instruction.  */
 985 #define X_MASK XRC (0x3f, 0x3ff, 1)
 986
 987 /* An X_MASK with the RA field fixed.  */
 988 #define XRA_MASK (X_MASK | RA_MASK)
 989
 990 /* An X_MASK with the RB field fixed.  */
 991 #define XRB_MASK (X_MASK | RB_MASK)
 992
 993 /* An X_MASK with the RT field fixed.  */
 994 #define XRT_MASK (X_MASK | RT_MASK)
 995
 996 /* An X_MASK with the RA and RB fields fixed.  */
 997 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
 998
 999 /* An X_MASK with the RT and RA fields fixed.  */
1000 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1001
1002 /* An X form comparison instruction.  */
1003 #define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21))
1004
1005 /* The mask for an X form comparison instruction.  */
1006 #define XCMP_MASK (X_MASK | (1 << 22))
1007
1008 /* The mask for an X form comparison instruction with the L field
1009    fixed.  */
1010 #define XCMPL_MASK (XCMP_MASK | (1 << 21))
1011
1012 /* An X form trap instruction with the TO field specified.  */
1013 #define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21))
1014 #define XTO_MASK (X_MASK | TO_MASK)
1015
1016 /* An XFL form instruction.  */
1017 #define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1))
1018 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16))
1019
1020 /* An XL form instruction with the LK field set to 0.  */
1021 #define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1022
1023 /* An XL form instruction which uses the LK field.  */
1024 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1025
1026 /* The mask for an XL form instruction.  */
1027 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1028
1029 /* An XL form instruction which explicitly sets the BO field.  */
1030 #define XLO(op, bo, xop, lk) \
1031   (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21))
1032 #define XLO_MASK (XL_MASK | BO_MASK)
1033
1034 /* An XL form instruction which explicitly sets the y bit of the BO
1035    field.  */
1036 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21))
1037 #define XLYLK_MASK (XL_MASK | Y_MASK)
1038
1039 /* An XL form instruction which sets the BO field and the condition
1040    bits of the BI field.  */
1041 #define XLOCB(op, bo, cb, xop, lk) \
1042   (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16))
1043 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1044
1045 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1046 #define XLBB_MASK (XL_MASK | BB_MASK)
1047 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1048 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1049
1050 /* An XL_MASK with the BO and BB fields fixed.  */
1051 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1052
1053 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1054 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1055
1056 /* An XO form instruction.  */
1057 #define XO(op, xop, oe, rc) \
1058   (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1))
1059 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1060
1061 /* An XO_MASK with the RB field fixed.  */
1062 #define XORB_MASK (XO_MASK | RB_MASK)
1063
1064 /* An XS form instruction.  */
1065 #define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
1066 #define XS_MASK XS (0x3f, 0x1ff, 1)
1067
1068 /* An XFX form instruction with the SPR field filled in.  */
1069 #define XSPR(op, xop, spr) \
1070   (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
1071 #define XSPR_MASK (X_MASK | SPR_MASK)
1072
1073 /* The BO encodings used in extended conditional branch mnemonics.  */
1074 #define BODNZF  (0x0)
1075 #define BODNZFP (0x1)
1076 #define BODZF   (0x2)
1077 #define BODZFP  (0x3)
1078 #define BOF     (0x4)
1079 #define BOFP    (0x5)
1080 #define BODNZT  (0x8)
1081 #define BODNZTP (0x9)
1082 #define BODZT   (0xa)
1083 #define BODZTP  (0xb)
1084 #define BOT     (0xc)
1085 #define BOTP    (0xd)
1086 #define BODNZ   (0x10)
1087 #define BODNZP  (0x11)
1088 #define BODZ    (0x12)
1089 #define BODZP   (0x13)
1090 #define BOU     (0x14)
1091
1092 /* The BI condition bit encodings used in extended conditional branch
1093    mnemonics.  */
1094 #define CBLT    (0)
1095 #define CBGT    (1)
1096 #define CBEQ    (2)
1097 #define CBSO    (3)
1098
1099 /* The TO encodings used in extended trap mnemonics.  */
1100 #define TOLGT   (0x1)
1101 #define TOLLT   (0x2)
1102 #define TOEQ    (0x4)
1103 #define TOLGE   (0x5)
1104 #define TOLNL   (0x5)
1105 #define TOLLE   (0x6)
1106 #define TOLNG   (0x6)
1107 #define TOGT    (0x8)
1108 #define TOGE    (0xc)
1109 #define TONL    (0xc)
1110 #define TOLT    (0x10)
1111 #define TOLE    (0x14)
1112 #define TONG    (0x14)
1113 #define TONE    (0x18)
1114 #define TOU     (0x1f)
1115 \f
1116 /* Smaller names for the flags so each entry in the opcodes table will
1117    fit on a single line.  */
1118 #define PPC PPC_OPCODE_PPC
1119 #define POWER PPC_OPCODE_POWER
1120 #define POWER2 PPC_OPCODE_POWER2
1121 #define B32 PPC_OPCODE_32
1122 #define B64 PPC_OPCODE_64
1123 #define M601 PPC_OPCODE_601
1124 \f
1125 /* The opcode table.
1126
1127    The format of the opcode table is:
1128
1129    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
1130
1131    NAME is the name of the instruction.
1132    OPCODE is the instruction opcode.
1133    MASK is the opcode mask; this is used to tell the disassembler
1134      which bits in the actual opcode must match OPCODE.
1135    FLAGS are flags indicated what processors support the instruction.
1136    OPERANDS is the list of operands.
1137
1138    The disassembler reads the table in order and prints the first
1139    instruction which matches, so this table is sorted to put more
1140    specific instructions before more general instructions.  It is also
1141    sorted by major opcode.  */
1142
1143 const struct powerpc_opcode powerpc_opcodes[] = {
1144 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC|B64,        { RA, SI } },
1145 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC|B64,        { RA, SI } },
1146 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC|B64,        { RA, SI } },
1147 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC|B64,        { RA, SI } },
1148 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC|B64,        { RA, SI } },
1149 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC|B64,        { RA, SI } },
1150 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC|B64,        { RA, SI } },
1151 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC|B64,        { RA, SI } },
1152 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC|B64,        { RA, SI } },
1153 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC|B64,        { RA, SI } },
1154 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC|B64,        { RA, SI } },
1155 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC|B64,        { RA, SI } },
1156 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC|B64,        { RA, SI } },
1157 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC|B64,        { RA, SI } },
1158 { "tdi",     OP(2),     OP_MASK,        PPC|B64,        { TO, RA, SI } },
1159
1160 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPC,            { RA, SI } },
1161 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  POWER,          { RA, SI } },
1162 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPC,            { RA, SI } },
1163 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  POWER,          { RA, SI } },
1164 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPC,            { RA, SI } },
1165 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   POWER,          { RA, SI } },
1166 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPC,            { RA, SI } },
1167 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  POWER,          { RA, SI } },
1168 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPC,            { RA, SI } },
1169 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  POWER,          { RA, SI } },
1170 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPC,            { RA, SI } },
1171 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  POWER,          { RA, SI } },
1172 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPC,            { RA, SI } },
1173 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  POWER,          { RA, SI } },
1174 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPC,            { RA, SI } },
1175 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   POWER,          { RA, SI } },
1176 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPC,            { RA, SI } },
1177 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   POWER,          { RA, SI } },
1178 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPC,            { RA, SI } },
1179 { "tnli",    OPTO(3,TONL), OPTO_MASK,   POWER,          { RA, SI } },
1180 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPC,            { RA, SI } },
1181 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   POWER,          { RA, SI } },
1182 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPC,            { RA, SI } },
1183 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   POWER,          { RA, SI } },
1184 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPC,            { RA, SI } },
1185 { "tngi",    OPTO(3,TONG), OPTO_MASK,   POWER,          { RA, SI } },
1186 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPC,            { RA, SI } },
1187 { "tnei",    OPTO(3,TONE), OPTO_MASK,   POWER,          { RA, SI } },
1188 { "twi",     OP(3),     OP_MASK,        PPC,            { TO, RA, SI } },
1189 { "ti",      OP(3),     OP_MASK,        POWER,          { TO, RA, SI } },
1190
1191 { "mulli",   OP(7),     OP_MASK,        PPC,            { RT, RA, SI } },
1192 { "muli",    OP(7),     OP_MASK,        POWER,          { RT, RA, SI } },
1193
1194 { "subfic",  OP(8),     OP_MASK,        PPC,            { RT, RA, SI } },
1195 { "sfi",     OP(8),     OP_MASK,        POWER,          { RT, RA, SI } },
1196
1197 { "dozi",    OP(9),     OP_MASK,        POWER|M601,     { RT, RA, SI } },
1198
1199 { "cmplwi",  OPL(10,0), OPL_MASK,       PPC,            { OBF, RA, UI } },
1200 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC|B64,        { OBF, RA, UI } },
1201 { "cmpli",   OP(10),    OP_MASK,        PPC,            { BF, L, RA, UI } },
1202 { "cmpli",   OP(10),    OP_MASK,        POWER,          { BF, RA, UI } },
1203
1204 { "cmpwi",   OPL(11,0), OPL_MASK,       PPC,            { OBF, RA, SI } },
1205 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC|B64,        { OBF, RA, SI } },
1206 { "cmpi",    OP(11),    OP_MASK,        PPC,            { BF, L, RA, SI } },
1207 { "cmpi",    OP(11),    OP_MASK,        POWER,          { BF, RA, SI } },
1208
1209 { "addic",   OP(12),    OP_MASK,        PPC,            { RT, RA, SI } },
1210 { "ai",      OP(12),    OP_MASK,        POWER,          { RT, RA, SI } },
1211 { "subic",   OP(12),    OP_MASK,        PPC,            { RT, RA, NSI } },
1212
1213 { "addic.",  OP(13),    OP_MASK,        PPC,            { RT, RA, SI } },
1214 { "ai.",     OP(13),    OP_MASK,        POWER,          { RT, RA, SI } },
1215 { "subic.",  OP(13),    OP_MASK,        PPC,            { RT, RA, NSI } },
1216
1217 { "li",      OP(14),    DRA_MASK,       PPC,            { RT, SI } },
1218 { "lil",     OP(14),    DRA_MASK,       POWER,          { RT, SI } },
1219 { "addi",    OP(14),    OP_MASK,        PPC,            { RT, RA, SI } },
1220 { "cal",     OP(14),    OP_MASK,        POWER,          { RT, D, RA } },
1221 { "subi",    OP(14),    OP_MASK,        PPC,            { RT, RA, NSI } },
1222 { "la",      OP(14),    OP_MASK,        PPC,            { RT, D, RA } },
1223
1224 { "lis",     OP(15),    DRA_MASK,       PPC,            { RT, SISIGNOPT } },
1225 { "liu",     OP(15),    DRA_MASK,       POWER,          { RT, SISIGNOPT } },
1226 { "addis",   OP(15),    OP_MASK,        PPC,            { RT,RA,SISIGNOPT } },
1227 { "cau",     OP(15),    OP_MASK,        POWER,          { RT,RA,SISIGNOPT } },
1228 { "subis",   OP(15),    OP_MASK,        PPC,            { RT, RA, NSI } },
1229
1230 { "bdnz-",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC,       { BDM } },
1231 { "bdnz+",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC,       { BDP } },
1232 { "bdnz",    BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC,       { BD } },
1233 { "bdn",     BBO(16,BODNZ,0,0), BBOYBI_MASK, POWER,     { BD } },
1234 { "bdnzl-",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC,       { BDM } },
1235 { "bdnzl+",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC,       { BDP } },
1236 { "bdnzl",   BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC,       { BD } },
1237 { "bdnl",    BBO(16,BODNZ,0,1), BBOYBI_MASK, POWER,     { BD } },
1238 { "bdnza-",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC,       { BDMA } },
1239 { "bdnza+",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC,       { BDPA } },
1240 { "bdnza",   BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC,       { BDA } },
1241 { "bdna",    BBO(16,BODNZ,1,0), BBOYBI_MASK, POWER,     { BDA } },
1242 { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC,       { BDMA } },
1243 { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC,       { BDPA } },
1244 { "bdnzla",  BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC,       { BDA } },
1245 { "bdnla",   BBO(16,BODNZ,1,1), BBOYBI_MASK, POWER,     { BDA } },
1246 { "bdz-",    BBO(16,BODZ,0,0), BBOYBI_MASK, PPC,        { BDM } },
1247 { "bdz+",    BBO(16,BODZ,0,0), BBOYBI_MASK, PPC,        { BDP } },
1248 { "bdz",     BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER,  { BD } },
1249 { "bdzl-",   BBO(16,BODZ,0,1), BBOYBI_MASK, PPC,        { BDM } },
1250 { "bdzl+",   BBO(16,BODZ,0,1), BBOYBI_MASK, PPC,        { BDP } },
1251 { "bdzl",    BBO(16,BODZ,0,1), BBOYBI_MASK, PPC|POWER,  { BD } },
1252 { "bdza-",   BBO(16,BODZ,1,0), BBOYBI_MASK, PPC,        { BDMA } },
1253 { "bdza+",   BBO(16,BODZ,1,0), BBOYBI_MASK, PPC,        { BDPA } },
1254 { "bdza",    BBO(16,BODZ,1,0), BBOYBI_MASK, PPC|POWER,  { BDA } },
1255 { "bdzla-",  BBO(16,BODZ,1,1), BBOYBI_MASK, PPC,        { BDMA } },
1256 { "bdzla+",  BBO(16,BODZ,1,1), BBOYBI_MASK, PPC,        { BDPA } },
1257 { "bdzla",   BBO(16,BODZ,1,1), BBOYBI_MASK, PPC|POWER,  { BDA } },
1258 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1259 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1260 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1261 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1262 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1263 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1264 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1265 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1266 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1267 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1268 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1269 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1270 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1271 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1272 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1273 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1274 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1275 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1276 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1277 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1278 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1279 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1280 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1281 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1282 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1283 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1284 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1285 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1286 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1287 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1288 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1289 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1290 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1291 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1292 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1293 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1294 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1295 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1296 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1297 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1298 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1299 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1300 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1301 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1302 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1303 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1304 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1305 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1306 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1307 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1308 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BD } },
1309 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1310 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1311 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BD } },
1312 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1313 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1314 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDA } },
1315 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1316 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1317 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDA } },
1318 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1319 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1320 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1321 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1322 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1323 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1324 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1325 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1326 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1327 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1328 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1329 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1330 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1331 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1332 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1333 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1334 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1335 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1336 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1337 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1338 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1339 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1340 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1341 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1342 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1343 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1344 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1345 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1346 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1347 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1348 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1349 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1350 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1351 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1352 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1353 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1354 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1355 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1356 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1357 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1358 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1359 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1360 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1361 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1362 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1363 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1364 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1365 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1366 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1367 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1368 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1369 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1370 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1371 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1372 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1373 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1374 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1375 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1376 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1377 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1378 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1379 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1380 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1381 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1382 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1383 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1384 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1385 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1386 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1387 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1388 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1389 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1390 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1391 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1392 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BD } },
1393 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1394 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1395 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BD } },
1396 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1397 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1398 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDA } },
1399 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1400 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1401 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDA } },
1402 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, PPC,        { BI, BDM } },
1403 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, PPC,        { BI, BDP } },
1404 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPC,        { BI, BD } },
1405 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC,        { BI, BDM } },
1406 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC,        { BI, BDP } },
1407 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPC,        { BI, BD } },
1408 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC,        { BI, BDMA } },
1409 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC,        { BI, BDPA } },
1410 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPC,        { BI, BDA } },
1411 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC,        { BI, BDMA } },
1412 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC,        { BI, BDPA } },
1413 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPC,        { BI, BDA } },
1414 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, PPC,        { BI, BDM } },
1415 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, PPC,        { BI, BDP } },
1416 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPC,        { BI, BD } },
1417 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC,        { BI, BDM } },
1418 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC,        { BI, BDP } },
1419 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPC,        { BI, BD } },
1420 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC,        { BI, BDMA } },
1421 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC,        { BI, BDPA } },
1422 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPC,        { BI, BDA } },
1423 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC,        { BI, BDMA } },
1424 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC,        { BI, BDPA } },
1425 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPC,        { BI, BDA } },
1426 { "bt-",     BBO(16,BOT,0,0), BBOY_MASK, PPC,           { BI, BDM } },
1427 { "bt+",     BBO(16,BOT,0,0), BBOY_MASK, PPC,           { BI, BDP } },
1428 { "bt",      BBO(16,BOT,0,0), BBOY_MASK, PPC,           { BI, BD } },
1429 { "bbt",     BBO(16,BOT,0,0), BBOY_MASK, POWER,         { BI, BD } },
1430 { "btl-",    BBO(16,BOT,0,1), BBOY_MASK, PPC,           { BI, BDM } },
1431 { "btl+",    BBO(16,BOT,0,1), BBOY_MASK, PPC,           { BI, BDP } },
1432 { "btl",     BBO(16,BOT,0,1), BBOY_MASK, PPC,           { BI, BD } },
1433 { "bbtl",    BBO(16,BOT,0,1), BBOY_MASK, POWER,         { BI, BD } },
1434 { "bta-",    BBO(16,BOT,1,0), BBOY_MASK, PPC,           { BI, BDMA } },
1435 { "bta+",    BBO(16,BOT,1,0), BBOY_MASK, PPC,           { BI, BDPA } },
1436 { "bta",     BBO(16,BOT,1,0), BBOY_MASK, PPC,           { BI, BDA } },
1437 { "bbta",    BBO(16,BOT,1,0), BBOY_MASK, POWER,         { BI, BDA } },
1438 { "btla-",   BBO(16,BOT,1,1), BBOY_MASK, PPC,           { BI, BDMA } },
1439 { "btla+",   BBO(16,BOT,1,1), BBOY_MASK, PPC,           { BI, BDPA } },
1440 { "btla",    BBO(16,BOT,1,1), BBOY_MASK, PPC,           { BI, BDA } },
1441 { "bbtla",   BBO(16,BOT,1,1), BBOY_MASK, POWER,         { BI, BDA } },
1442 { "bf-",     BBO(16,BOF,0,0), BBOY_MASK, PPC,           { BI, BDM } },
1443 { "bf+",     BBO(16,BOF,0,0), BBOY_MASK, PPC,           { BI, BDP } },
1444 { "bf",      BBO(16,BOF,0,0), BBOY_MASK, PPC,           { BI, BD } },
1445 { "bbf",     BBO(16,BOF,0,0), BBOY_MASK, POWER,         { BI, BD } },
1446 { "bfl-",    BBO(16,BOF,0,1), BBOY_MASK, PPC,           { BI, BDM } },
1447 { "bfl+",    BBO(16,BOF,0,1), BBOY_MASK, PPC,           { BI, BDP } },
1448 { "bfl",     BBO(16,BOF,0,1), BBOY_MASK, PPC,           { BI, BD } },
1449 { "bbfl",    BBO(16,BOF,0,1), BBOY_MASK, POWER,         { BI, BD } },
1450 { "bfa-",    BBO(16,BOF,1,0), BBOY_MASK, PPC,           { BI, BDMA } },
1451 { "bfa+",    BBO(16,BOF,1,0), BBOY_MASK, PPC,           { BI, BDPA } },
1452 { "bfa",     BBO(16,BOF,1,0), BBOY_MASK, PPC,           { BI, BDA } },
1453 { "bbfa",    BBO(16,BOF,1,0), BBOY_MASK, POWER,         { BI, BDA } },
1454 { "bfla-",   BBO(16,BOF,1,1), BBOY_MASK, PPC,           { BI, BDMA } },
1455 { "bfla+",   BBO(16,BOF,1,1), BBOY_MASK, PPC,           { BI, BDPA } },
1456 { "bfla",    BBO(16,BOF,1,1), BBOY_MASK, PPC,           { BI, BDA } },
1457 { "bbfla",   BBO(16,BOF,1,1), BBOY_MASK, POWER,         { BI, BDA } },
1458 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, PPC,         { BI, BDM } },
1459 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, PPC,         { BI, BDP } },
1460 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPC,         { BI, BD } },
1461 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, PPC,         { BI, BDM } },
1462 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, PPC,         { BI, BDP } },
1463 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPC,         { BI, BD } },
1464 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, PPC,         { BI, BDMA } },
1465 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, PPC,         { BI, BDPA } },
1466 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPC,         { BI, BDA } },
1467 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC,         { BI, BDMA } },
1468 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC,         { BI, BDPA } },
1469 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPC,         { BI, BDA } },
1470 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, PPC,         { BI, BDM } },
1471 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, PPC,         { BI, BDP } },
1472 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPC,         { BI, BD } },
1473 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, PPC,         { BI, BDM } },
1474 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, PPC,         { BI, BDP } },
1475 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPC,         { BI, BD } },
1476 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, PPC,         { BI, BDMA } },
1477 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, PPC,         { BI, BDPA } },
1478 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPC,         { BI, BDA } },
1479 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC,         { BI, BDMA } },
1480 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC,         { BI, BDPA } },
1481 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPC,         { BI, BDA } },
1482 { "bc-",     B(16,0,0), B_MASK,         PPC,            { BOE, BI, BDM } },
1483 { "bc+",     B(16,0,0), B_MASK,         PPC,            { BOE, BI, BDP } },
1484 { "bc",      B(16,0,0), B_MASK,         PPC|POWER,      { BO, BI, BD } },
1485 { "bcl-",    B(16,0,1), B_MASK,         PPC,            { BOE, BI, BDM } },
1486 { "bcl+",    B(16,0,1), B_MASK,         PPC,            { BOE, BI, BDP } },
1487 { "bcl",     B(16,0,1), B_MASK,         PPC|POWER,      { BO, BI, BD } },
1488 { "bca-",    B(16,1,0), B_MASK,         PPC,            { BOE, BI, BDMA } },
1489 { "bca+",    B(16,1,0), B_MASK,         PPC,            { BOE, BI, BDPA } },
1490 { "bca",     B(16,1,0), B_MASK,         PPC|POWER,      { BO, BI, BDA } },
1491 { "bcla-",   B(16,1,1), B_MASK,         PPC,            { BOE, BI, BDMA } },
1492 { "bcla+",   B(16,1,1), B_MASK,         PPC,            { BOE, BI, BDPA } },
1493 { "bcla",    B(16,1,1), B_MASK,         PPC|POWER,      { BO, BI, BDA } },
1494
1495 { "sc",      SC(17,1,0), 0xffffffff,    PPC,            { 0 } },
1496 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
1497 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
1498 { "svca",    SC(17,1,0), SC_MASK,       POWER,          { SV } },
1499 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
1500
1501 { "b",       B(18,0,0), B_MASK,         PPC|POWER,      { LI } },
1502 { "bl",      B(18,0,1), B_MASK,         PPC|POWER,      { LI } },
1503 { "ba",      B(18,1,0), B_MASK,         PPC|POWER,      { LIA } },
1504 { "bla",     B(18,1,1), B_MASK,         PPC|POWER,      { LIA } },
1505
1506 { "mcrf",    XL(19,0),  XLBB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
1507
1508 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPC,      { 0 } },
1509 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, POWER,    { 0 } },
1510 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPC,      { 0 } },
1511 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, POWER,    { 0 } },
1512 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC,    { 0 } },
1513 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC,    { 0 } },
1514 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC,   { 0 } },
1515 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC,    { 0 } },
1516 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC,    { 0 } },
1517 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC,   { 0 } },
1518 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC,     { 0 } },
1519 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC,     { 0 } },
1520 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC,    { 0 } },
1521 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC,     { 0 } },
1522 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC,     { 0 } },
1523 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC,    { 0 } },
1524 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1525 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1526 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1527 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1528 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1529 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1530 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1531 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1532 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1533 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1534 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1535 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1536 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1537 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1538 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1539 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1540 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1541 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1542 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1543 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1544 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1545 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1546 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1547 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1548 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1549 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1550 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1551 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1552 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1553 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1554 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1555 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1556 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1557 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1558 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1559 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1560 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1561 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1562 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1563 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1564 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1565 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1566 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1567 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1568 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1569 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1570 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1571 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1572 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1573 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1574 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1575 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1576 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1577 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1578 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1579 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1580 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1581 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1582 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1583 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1584 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1585 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1586 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1587 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1588 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1589 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1590 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1591 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1592 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1593 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1594 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1595 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1596 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1597 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1598 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1599 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1600 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1601 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1602 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1603 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1604 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1605 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1606 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1607 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1608 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1609 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1610 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1611 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1612 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1613 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1614 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1615 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1616 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPC,        { BI } },
1617 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, PPC,        { BI } },
1618 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, PPC,       { BI } },
1619 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, POWER,      { BI } },
1620 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPC,        { BI } },
1621 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, PPC,        { BI } },
1622 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, PPC,       { BI } },
1623 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, POWER,      { BI } },
1624 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPC,        { BI } },
1625 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, PPC,        { BI } },
1626 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, PPC,       { BI } },
1627 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, POWER,      { BI } },
1628 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPC,        { BI } },
1629 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, PPC,        { BI } },
1630 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, PPC,       { BI } },
1631 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, POWER,      { BI } },
1632 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC,     { BI } },
1633 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC,     { BI } },
1634 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC,    { BI } },
1635 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC,     { BI } },
1636 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC,    { BI } },
1637 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC,   { BI } },
1638 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC,     { BI } },
1639 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC,     { BI } },
1640 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC,    { BI } },
1641 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC,     { BI } },
1642 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC,    { BI } },
1643 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC,   { BI } },
1644 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPC,      { BI } },
1645 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC,      { BI } },
1646 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC,     { BI } },
1647 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPC,      { BI } },
1648 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC,      { BI } },
1649 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC,     { BI } },
1650 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPC,      { BI } },
1651 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC,      { BI } },
1652 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC,     { BI } },
1653 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPC,      { BI } },
1654 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC,      { BI } },
1655 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC,     { BI } },
1656 { "bclr",    XLLK(19,16,0), XLYBB_MASK, PPC,            { BO, BI } },
1657 { "bclrl",   XLLK(19,16,1), XLYBB_MASK, PPC,            { BO, BI } },
1658 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPC,         { BOE, BI } },
1659 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPC,         { BOE, BI } },
1660 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPC,         { BOE, BI } },
1661 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPC,         { BOE, BI } },
1662 { "bcr",     XLLK(19,16,0), XLBB_MASK,  POWER,          { BO, BI } },
1663 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  POWER,          { BO, BI } },
1664
1665 { "crnot",   XL(19,33), XL_MASK,        PPC,            { BT, BA, BBA } },
1666 { "crnor",   XL(19,33), XL_MASK,        PPC|POWER,      { BT, BA, BB } },
1667
1668 { "rfi",     XL(19,50), 0xffffffff,     PPC|POWER,      { 0 } },
1669
1670 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
1671
1672 { "crandc",  XL(19,129), XL_MASK,       PPC|POWER,      { BT, BA, BB } },
1673
1674 { "isync",   XL(19,150), 0xffffffff,    PPC,            { 0 } },
1675 { "ics",     XL(19,150), 0xffffffff,    POWER,          { 0 } },
1676
1677 { "crclr",   XL(19,193), XL_MASK,       PPC,            { BT, BAT, BBA } },
1678 { "crxor",   XL(19,193), XL_MASK,       PPC|POWER,      { BT, BA, BB } },
1679
1680 { "crnand",  XL(19,225), XL_MASK,       PPC|POWER,      { BT, BA, BB } },
1681
1682 { "crand",   XL(19,257), XL_MASK,       PPC|POWER,      { BT, BA, BB } },
1683
1684 { "crset",   XL(19,289), XL_MASK,       PPC,            { BT, BAT, BBA } },
1685 { "creqv",   XL(19,289), XL_MASK,       PPC|POWER,      { BT, BA, BB } },
1686
1687 { "crorc",   XL(19,417), XL_MASK,       PPC|POWER,      { BT, BA, BB } },
1688
1689 { "crmove",  XL(19,449), XL_MASK,       PPC,            { BT, BA, BBA } },
1690 { "cror",    XL(19,449), XL_MASK,       PPC|POWER,      { BT, BA, BB } },
1691
1692 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, PPC|POWER, { 0 } },
1693 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, PPC|POWER, { 0 } },
1694 { "bltctr",  XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1695 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1696 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1697 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1698 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1699 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1700 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1701 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1702 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1703 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1704 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1705 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1706 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1707 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1708 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1709 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1710 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1711 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1712 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1713 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1714 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1715 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1716 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1717 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1718 { "bunctr",  XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1719 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1720 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1721 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1722 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1723 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1724 { "bgectr",  XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1725 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1726 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1727 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1728 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1729 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1730 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1731 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1732 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1733 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1734 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1735 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1736 { "blectr",  XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1737 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1738 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1739 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1740 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1741 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1742 { "bngctr",  XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1743 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1744 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1745 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1746 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1747 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1748 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1749 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1750 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1751 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1752 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1753 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1754 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1755 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1756 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1757 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1758 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1759 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1760 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1761 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1762 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1763 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1764 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1765 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1766 { "btctr",   XLO(19,BOT,528,0), XLBOBB_MASK, PPC,       { BI } },
1767 { "btctr-",  XLO(19,BOT,528,0), XLBOBB_MASK, PPC,       { BI } },
1768 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, PPC,      { BI } },
1769 { "btctrl",  XLO(19,BOT,528,1), XLBOBB_MASK, PPC,       { BI } },
1770 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC,       { BI } },
1771 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC,      { BI } },
1772 { "bfctr",   XLO(19,BOF,528,0), XLBOBB_MASK, PPC,       { BI } },
1773 { "bfctr-",  XLO(19,BOF,528,0), XLBOBB_MASK, PPC,       { BI } },
1774 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, PPC,      { BI } },
1775 { "bfctrl",  XLO(19,BOF,528,1), XLBOBB_MASK, PPC,       { BI } },
1776 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC,       { BI } },
1777 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC,      { BI } },
1778 { "bcctr",   XLLK(19,528,0), XLYBB_MASK, PPC,           { BO, BI } },
1779 { "bcctr-",  XLYLK(19,528,0,0), XLYBB_MASK, PPC,        { BOE, BI } },
1780 { "bcctr+",  XLYLK(19,528,1,0), XLYBB_MASK, PPC,        { BOE, BI } },
1781 { "bcctrl",  XLLK(19,528,1), XLYBB_MASK, PPC,           { BO, BI } },
1782 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC,        { BOE, BI } },
1783 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC,        { BOE, BI } },
1784 { "bcc",     XLLK(19,528,0), XLBB_MASK, POWER,          { BO, BI } },
1785 { "bccl",    XLLK(19,528,1), XLBB_MASK, POWER,          { BO, BI } },
1786
1787 { "rlwimi",  M(20,0),   M_MASK,         PPC,            { RA,RS,SH,MBE,ME } },
1788 { "rlimi",   M(20,0),   M_MASK,         POWER,          { RA,RS,SH,MBE,ME } },
1789
1790 { "rlwimi.", M(20,1),   M_MASK,         PPC,            { RA,RS,SH,MBE,ME } },
1791 { "rlimi.",  M(20,1),   M_MASK,         POWER,          { RA,RS,SH,MBE,ME } },
1792
1793 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPC,            { RA, RS, SH } },
1794 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPC,            { RA, RS, MB } },
1795 { "rlwinm",  M(21,0),   M_MASK,         PPC,            { RA,RS,SH,MBE,ME } },
1796 { "rlinm",   M(21,0),   M_MASK,         POWER,          { RA,RS,SH,MBE,ME } },
1797 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPC,            { RA,RS,SH } },
1798 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPC,            { RA, RS, MB } },
1799 { "rlwinm.", M(21,1),   M_MASK,         PPC,            { RA,RS,SH,MBE,ME } },
1800 { "rlinm.",  M(21,1),   M_MASK,         POWER,          { RA,RS,SH,MBE,ME } },
1801
1802 { "rlmi",    M(22,0),   M_MASK,         POWER|M601,     { RA,RS,RB,MBE,ME } },
1803 { "rlmi.",   M(22,1),   M_MASK,         POWER|M601,     { RA,RS,RB,MBE,ME } },
1804
1805 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPC,            { RA, RS, RB } },
1806 { "rlwnm",   M(23,0),   M_MASK,         PPC,            { RA,RS,RB,MBE,ME } },
1807 { "rlnm",    M(23,0),   M_MASK,         POWER,          { RA,RS,RB,MBE,ME } },
1808 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPC,            { RA, RS, RB } },
1809 { "rlwnm.",  M(23,1),   M_MASK,         PPC,            { RA,RS,RB,MBE,ME } },
1810 { "rlnm.",   M(23,1),   M_MASK,         POWER,          { RA,RS,RB,MBE,ME } },
1811
1812 { "nop",     OP(24),    0xffffffff,     PPC,            { 0 } },
1813 { "ori",     OP(24),    OP_MASK,        PPC,            { RA, RS, UI } },
1814 { "oril",    OP(24),    OP_MASK,        POWER,          { RA, RS, UI } },
1815
1816 { "oris",    OP(25),    OP_MASK,        PPC,            { RA, RS, UI } },
1817 { "oriu",    OP(25),    OP_MASK,        POWER,          { RA, RS, UI } },
1818
1819 { "xori",    OP(26),    OP_MASK,        PPC,            { RA, RS, UI } },
1820 { "xoril",   OP(26),    OP_MASK,        POWER,          { RA, RS, UI } },
1821
1822 { "xoris",   OP(27),    OP_MASK,        PPC,            { RA, RS, UI } },
1823 { "xoriu",   OP(27),    OP_MASK,        POWER,          { RA, RS, UI } },
1824
1825 { "andi.",   OP(28),    OP_MASK,        PPC,            { RA, RS, UI } },
1826 { "andil.",  OP(28),    OP_MASK,        POWER,          { RA, RS, UI } },
1827
1828 { "andis.",  OP(29),    OP_MASK,        PPC,            { RA, RS, UI } },
1829 { "andiu.",  OP(29),    OP_MASK,        POWER,          { RA, RS, UI } },
1830
1831 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC|B64,        { RA, RS, SH6 } },
1832 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC|B64,        { RA, RS, MB6 } },
1833 { "rldicl",  MD(30,0,0), MD_MASK,       PPC|B64,        { RA, RS, SH6, MB6 } },
1834 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC|B64,        { RA, RS, SH6 } },
1835 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC|B64,        { RA, RS, MB6 } },
1836 { "rldicl.", MD(30,0,1), MD_MASK,       PPC|B64,        { RA, RS, SH6, MB6 } },
1837
1838 { "rldicr",  MD(30,1,0), MD_MASK,       PPC|B64,        { RA, RS, SH6, ME6 } },
1839 { "rldicr.", MD(30,1,1), MD_MASK,       PPC|B64,        { RA, RS, SH6, ME6 } },
1840
1841 { "rldic",   MD(30,2,0), MD_MASK,       PPC|B64,        { RA, RS, SH6, MB6 } },
1842 { "rldic.",  MD(30,2,1), MD_MASK,       PPC|B64,        { RA, RS, SH6, MB6 } },
1843
1844 { "rldimi",  MD(30,3,0), MD_MASK,       PPC|B64,        { RA, RS, SH6, MB6 } },
1845 { "rldimi.", MD(30,3,1), MD_MASK,       PPC|B64,        { RA, RS, SH6, MB6 } },
1846
1847 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC|B64,        { RA, RS, RB } },
1848 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC|B64,        { RA, RS, RB, MB6 } },
1849 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC|B64,        { RA, RS, RB } },
1850 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC|B64,        { RA, RS, RB, MB6 } },
1851
1852 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC|B64,        { RA, RS, RB, ME6 } },
1853 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC|B64,        { RA, RS, RB, ME6 } },
1854
1855 { "cmpw",    XCMPL(31,0,0), XCMPL_MASK, PPC,            { OBF, RA, RB } },
1856 { "cmpd",    XCMPL(31,0,1), XCMPL_MASK, PPC|B64,        { OBF, RA, RB } },
1857 { "cmp",     X(31,0),   XCMPL_MASK,     POWER,          { BF, RA, RB } },
1858 { "cmp",     X(31,0),   XCMP_MASK,      PPC,            { BF, L, RA, RB } },
1859
1860 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPC,            { RA, RB } },
1861 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, POWER,          { RA, RB } },
1862 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPC,            { RA, RB } },
1863 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, POWER,          { RA, RB } },
1864 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPC,            { RA, RB } },
1865 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  POWER,          { RA, RB } },
1866 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPC,            { RA, RB } },
1867 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, POWER,          { RA, RB } },
1868 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPC,            { RA, RB } },
1869 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, POWER,          { RA, RB } },
1870 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPC,            { RA, RB } },
1871 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, POWER,          { RA, RB } },
1872 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPC,            { RA, RB } },
1873 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, POWER,          { RA, RB } },
1874 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPC,            { RA, RB } },
1875 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  POWER,          { RA, RB } },
1876 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPC,            { RA, RB } },
1877 { "tge",     XTO(31,4,TOGE), XTO_MASK,  POWER,          { RA, RB } },
1878 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPC,            { RA, RB } },
1879 { "tnl",     XTO(31,4,TONL), XTO_MASK,  POWER,          { RA, RB } },
1880 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPC,            { RA, RB } },
1881 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  POWER,          { RA, RB } },
1882 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPC,            { RA, RB } },
1883 { "tle",     XTO(31,4,TOLE), XTO_MASK,  POWER,          { RA, RB } },
1884 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPC,            { RA, RB } },
1885 { "tng",     XTO(31,4,TONG), XTO_MASK,  POWER,          { RA, RB } },
1886 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPC,            { RA, RB } },
1887 { "tne",     XTO(31,4,TONE), XTO_MASK,  POWER,          { RA, RB } },
1888 { "trap",    XTO(31,4,TOU), 0xffffffff, PPC,            { 0 } },
1889 { "tw",      X(31,4),   X_MASK,         PPC,            { TO, RA, RB } },
1890 { "t",       X(31,4),   X_MASK,         POWER,          { TO, RA, RB } },
1891
1892 { "subfc",   XO(31,8,0,0), XO_MASK,     PPC,            { RT, RA, RB } },
1893 { "sf",      XO(31,8,0,0), XO_MASK,     POWER,          { RT, RA, RB } },
1894 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
1895 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPC,            { RT, RA, RB } },
1896 { "sf.",     XO(31,8,0,1), XO_MASK,     POWER,          { RT, RA, RB } },
1897 { "subc.",   XO(31,8,0,1), XO_MASK,     PPC,            { RT, RB, RA } },
1898 { "subfco",  XO(31,8,1,0), XO_MASK,     PPC,            { RT, RA, RB } },
1899 { "sfo",     XO(31,8,1,0), XO_MASK,     POWER,          { RT, RA, RB } },
1900 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
1901 { "subfco.", XO(31,8,1,1), XO_MASK,     PPC,            { RT, RA, RB } },
1902 { "sfo.",    XO(31,8,1,1), XO_MASK,     POWER,          { RT, RA, RB } },
1903 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
1904
1905 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC|B64,        { RT, RA, RB } },
1906 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC|B64,        { RT, RA, RB } },
1907
1908 { "addc",    XO(31,10,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
1909 { "a",       XO(31,10,0,0), XO_MASK,    POWER,          { RT, RA, RB } },
1910 { "addc.",   XO(31,10,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
1911 { "a.",      XO(31,10,0,1), XO_MASK,    POWER,          { RT, RA, RB } },
1912 { "addco",   XO(31,10,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
1913 { "ao",      XO(31,10,1,0), XO_MASK,    POWER,          { RT, RA, RB } },
1914 { "addco.",  XO(31,10,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
1915 { "ao.",     XO(31,10,1,1), XO_MASK,    POWER,          { RT, RA, RB } },
1916
1917 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
1918 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
1919
1920 { "mfcr",    X(31,19),  XRARB_MASK,     POWER|PPC,      { RT } },
1921
1922 { "lwarx",   X(31,20),  X_MASK,         PPC,            { RT, RA, RB } },
1923
1924 { "ldx",     X(31,21),  X_MASK,         PPC|B64,        { RT, RA, RB } },
1925
1926 { "lwzx",    X(31,23),  X_MASK,         PPC,            { RT, RA, RB } },
1927 { "lx",      X(31,23),  X_MASK,         POWER,          { RT, RA, RB } },
1928
1929 { "slw",     XRC(31,24,0), X_MASK,      PPC,            { RA, RS, RB } },
1930 { "sl",      XRC(31,24,0), X_MASK,      POWER,          { RA, RS, RB } },
1931 { "slw.",    XRC(31,24,1), X_MASK,      PPC,            { RA, RS, RB } },
1932 { "sl.",     XRC(31,24,1), X_MASK,      POWER,          { RA, RS, RB } },
1933
1934 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPC,            { RA, RS } },
1935 { "cntlz",   XRC(31,26,0), XRB_MASK,    POWER,          { RA, RS } },
1936 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPC,            { RA, RS } },
1937 { "cntlz.",  XRC(31,26,1), XRB_MASK,    POWER,          { RA, RS } },
1938
1939 { "sld",     XRC(31,27,0), X_MASK,      PPC|B64,        { RA, RS, RB } },
1940 { "sld.",    XRC(31,27,1), X_MASK,      PPC|B64,        { RA, RS, RB } },
1941
1942 { "and",     XRC(31,28,0), X_MASK,      PPC|POWER,      { RA, RS, RB } },
1943 { "and.",    XRC(31,28,1), X_MASK,      PPC|POWER,      { RA, RS, RB } },
1944
1945 { "maskg",   XRC(31,29,0), X_MASK,      POWER|M601,     { RA, RS, RB } },
1946 { "maskg.",  XRC(31,29,1), X_MASK,      POWER|M601,     { RA, RS, RB } },
1947
1948 { "cmplw",   XCMPL(31,32,0), XCMPL_MASK, PPC,           { OBF, RA, RB } },
1949 { "cmpld",   XCMPL(31,32,1), XCMPL_MASK, PPC|B64,       { OBF, RA, RB } },
1950 { "cmpl",    X(31,32),  XCMPL_MASK,     POWER,          { BF, RA, RB } },
1951 { "cmpl",    X(31,32),  XCMP_MASK,      PPC,            { BF, L, RA, RB } },
1952
1953 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
1954 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
1955 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
1956 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
1957 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
1958 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
1959 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
1960 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
1961
1962 { "ldux",    X(31,53),  X_MASK,         PPC|B64,        { RT, RA, RB } },
1963
1964 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
1965
1966 { "lwzux",   X(31,55),  X_MASK,         PPC,            { RT, RA, RB } },
1967 { "lux",     X(31,55),  X_MASK,         POWER,          { RT, RA, RB } },
1968
1969 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC|B64,        { RA, RS } },
1970 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC|B64,        { RA, RS } },
1971
1972 { "andc",    XRC(31,60,0), X_MASK,      PPC|POWER,      { RA, RS, RB } },
1973 { "andc.",   XRC(31,60,1), X_MASK,      PPC|POWER,      { RA, RS, RB } },
1974
1975 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC|B64,       { RA, RB } },
1976 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC|B64,       { RA, RB } },
1977 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK, PPC|B64,        { RA, RB } },
1978 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC|B64,       { RA, RB } },
1979 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC|B64,       { RA, RB } },
1980 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC|B64,       { RA, RB } },
1981 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC|B64,       { RA, RB } },
1982 { "tdgt",    XTO(31,68,TOGT), XTO_MASK, PPC|B64,        { RA, RB } },
1983 { "tdge",    XTO(31,68,TOGE), XTO_MASK, PPC|B64,        { RA, RB } },
1984 { "tdnl",    XTO(31,68,TONL), XTO_MASK, PPC|B64,        { RA, RB } },
1985 { "tdlt",    XTO(31,68,TOLT), XTO_MASK, PPC|B64,        { RA, RB } },
1986 { "tdle",    XTO(31,68,TOLE), XTO_MASK, PPC|B64,        { RA, RB } },
1987 { "tdng",    XTO(31,68,TONG), XTO_MASK, PPC|B64,        { RA, RB } },
1988 { "tdne",    XTO(31,68,TONE), XTO_MASK, PPC|B64,        { RA, RB } },
1989 { "td",      X(31,68),  X_MASK,         PPC|B64,        { TO, RA, RB } },
1990
1991 { "mulhd",   XO(31,73,0,0), XO_MASK,    PPC|B64,        { RT, RA, RB } },
1992 { "mulhd.",  XO(31,73,0,1), XO_MASK,    PPC|B64,        { RT, RA, RB } },
1993
1994 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
1995 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
1996
1997 { "mfmsr",   X(31,83),  XRARB_MASK,     PPC|POWER,      { RT } },
1998
1999 { "ldarx",   X(31,84),  X_MASK,         PPC|B64,        { RT, RA, RB } },
2000
2001 { "dcbf",    X(31,86),  XRT_MASK,       PPC,            { RA, RB } },
2002
2003 { "lbzx",    X(31,87),  X_MASK,         PPC|POWER,      { RT, RA, RB } },
2004
2005 { "neg",     XO(31,104,0,0), XORB_MASK, PPC|POWER,      { RT, RA } },
2006 { "neg.",    XO(31,104,0,1), XORB_MASK, PPC|POWER,      { RT, RA } },
2007 { "nego",    XO(31,104,1,0), XORB_MASK, PPC|POWER,      { RT, RA } },
2008 { "nego.",   XO(31,104,1,1), XORB_MASK, PPC|POWER,      { RT, RA } },
2009
2010 { "mul",     XO(31,107,0,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2011 { "mul.",    XO(31,107,0,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2012 { "mulo",    XO(31,107,1,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2013 { "mulo.",   XO(31,107,1,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2014
2015 { "clf",     X(31,118), XRB_MASK,       POWER,          { RT, RA } },
2016
2017 { "lbzux",   X(31,119), X_MASK,         PPC|POWER,      { RT, RA, RB } },
2018
2019 { "not",     XRC(31,124,0), X_MASK,     PPC|POWER,      { RA, RS, RBS } },
2020 { "nor",     XRC(31,124,0), X_MASK,     PPC|POWER,      { RA, RS, RB } },
2021 { "not.",    XRC(31,124,1), X_MASK,     PPC|POWER,      { RA, RS, RBS } },
2022 { "nor.",    XRC(31,124,1), X_MASK,     PPC|POWER,      { RA, RS, RB } },
2023
2024 { "subfe",   XO(31,136,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
2025 { "sfe",     XO(31,136,0,0), XO_MASK,   POWER,          { RT, RA, RB } },
2026 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
2027 { "sfe.",    XO(31,136,0,1), XO_MASK,   POWER,          { RT, RA, RB } },
2028 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
2029 { "sfeo",    XO(31,136,1,0), XO_MASK,   POWER,          { RT, RA, RB } },
2030 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
2031 { "sfeo.",   XO(31,136,1,1), XO_MASK,   POWER,          { RT, RA, RB } },
2032
2033 { "adde",    XO(31,138,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
2034 { "ae",      XO(31,138,0,0), XO_MASK,   POWER,          { RT, RA, RB } },
2035 { "adde.",   XO(31,138,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
2036 { "ae.",     XO(31,138,0,1), XO_MASK,   POWER,          { RT, RA, RB } },
2037 { "addeo",   XO(31,138,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
2038 { "aeo",     XO(31,138,1,0), XO_MASK,   POWER,          { RT, RA, RB } },
2039 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
2040 { "aeo.",    XO(31,138,1,1), XO_MASK,   POWER,          { RT, RA, RB } },
2041
2042 { "mtcrf",   X(31,144), X_MASK|(1<<20)|(1<<11), PPC|POWER, { FXM, RS } },
2043
2044 { "mtmsr",   X(31,146), XRARB_MASK,     PPC|POWER,      { RS } },
2045
2046 { "stdx",    X(31,149), X_MASK,         PPC|B64,        { RS, RA, RB } },
2047
2048 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA, RB } },
2049
2050 { "stwx",    X(31,151), X_MASK,         PPC,            { RS, RA, RB } },
2051 { "stx",     X(31,151), X_MASK,         POWER,          { RS, RA, RB } },
2052
2053 { "slq",     XRC(31,152,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
2054 { "slq.",    XRC(31,152,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
2055
2056 { "sle",     XRC(31,153,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
2057 { "sle.",    XRC(31,153,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
2058
2059 { "stdux",   X(31,181), X_MASK,         PPC|B64,        { RS, RA, RB } },
2060
2061 { "stwux",   X(31,183), X_MASK,         PPC,            { RS, RA, RB } },
2062 { "stux",    X(31,183), X_MASK,         POWER,          { RS, RA, RB } },
2063
2064 { "sliq",    XRC(31,184,0), X_MASK,     POWER|M601,     { RA, RS, SH } },
2065 { "sliq.",   XRC(31,184,1), X_MASK,     POWER|M601,     { RA, RS, SH } },
2066
2067 { "subfze",  XO(31,200,0,0), XORB_MASK, PPC,            { RT, RA } },
2068 { "sfze",    XO(31,200,0,0), XORB_MASK, POWER,          { RT, RA } },
2069 { "subfze.", XO(31,200,0,1), XORB_MASK, PPC,            { RT, RA } },
2070 { "sfze.",   XO(31,200,0,1), XORB_MASK, POWER,          { RT, RA } },
2071 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPC,            { RT, RA } },
2072 { "sfzeo",   XO(31,200,1,0), XORB_MASK, POWER,          { RT, RA } },
2073 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPC,            { RT, RA } },
2074 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, POWER,          { RT, RA } },
2075
2076 { "addze",   XO(31,202,0,0), XORB_MASK, PPC,            { RT, RA } },
2077 { "aze",     XO(31,202,0,0), XORB_MASK, POWER,          { RT, RA } },
2078 { "addze.",  XO(31,202,0,1), XORB_MASK, PPC,            { RT, RA } },
2079 { "aze.",    XO(31,202,0,1), XORB_MASK, POWER,          { RT, RA } },
2080 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPC,            { RT, RA } },
2081 { "azeo",    XO(31,202,1,0), XORB_MASK, POWER,          { RT, RA } },
2082 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPC,            { RT, RA } },
2083 { "azeo.",   XO(31,202,1,1), XORB_MASK, POWER,          { RT, RA } },
2084
2085 { "mtsr",    X(31,210), XRB_MASK|(1<<20), PPC|POWER|B32, { SR, RS } },
2086
2087 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC|B64,        { RS, RA, RB } },
2088
2089 { "stbx",    X(31,215), X_MASK,         PPC|POWER,      { RS, RA, RB } },
2090
2091 { "sllq",    XRC(31,216,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
2092 { "sllq.",   XRC(31,216,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
2093
2094 { "sleq",    XRC(31,217,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
2095 { "sleq.",   XRC(31,217,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
2096
2097 { "subfme",  XO(31,232,0,0), XORB_MASK, PPC,            { RT, RA } },
2098 { "sfme",    XO(31,232,0,0), XORB_MASK, POWER,          { RT, RA } },
2099 { "subfme.", XO(31,232,0,1), XORB_MASK, PPC,            { RT, RA } },
2100 { "sfme.",   XO(31,232,0,1), XORB_MASK, POWER,          { RT, RA } },
2101 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPC,            { RT, RA } },
2102 { "sfmeo",   XO(31,232,1,0), XORB_MASK, POWER,          { RT, RA } },
2103 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPC,            { RT, RA } },
2104 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, POWER,          { RT, RA } },
2105
2106 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC|B64,        { RT, RA, RB } },
2107 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC|B64,        { RT, RA, RB } },
2108 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC|B64,        { RT, RA, RB } },
2109 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC|B64,        { RT, RA, RB } },
2110
2111 { "addme",   XO(31,234,0,0), XORB_MASK, PPC,            { RT, RA } },
2112 { "ame",     XO(31,234,0,0), XORB_MASK, POWER,          { RT, RA } },
2113 { "addme.",  XO(31,234,0,1), XORB_MASK, PPC,            { RT, RA } },
2114 { "ame.",    XO(31,234,0,1), XORB_MASK, POWER,          { RT, RA } },
2115 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPC,            { RT, RA } },
2116 { "ameo",    XO(31,234,1,0), XORB_MASK, POWER,          { RT, RA } },
2117 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPC,            { RT, RA } },
2118 { "ameo.",   XO(31,234,1,1), XORB_MASK, POWER,          { RT, RA } },
2119
2120 { "mullw",   XO(31,235,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
2121 { "muls",    XO(31,235,0,0), XO_MASK,   POWER,          { RT, RA, RB } },
2122 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
2123 { "muls.",   XO(31,235,0,1), XO_MASK,   POWER,          { RT, RA, RB } },
2124 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
2125 { "mulso",   XO(31,235,1,0), XO_MASK,   POWER,          { RT, RA, RB } },
2126 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
2127 { "mulso.",  XO(31,235,1,1), XO_MASK,   POWER,          { RT, RA, RB } },
2128
2129 { "mtsrin",  X(31,242), XRA_MASK,       PPC|B32,        { RS, RB } },
2130 { "mtsri",   X(31,242), XRA_MASK,       POWER|B32,      { RS, RB } },
2131
2132 { "dcbtst",  X(31,246), XRT_MASK,       PPC,            { RA, RB } },
2133
2134 { "stbux",   X(31,247), X_MASK,         PPC|POWER,      { RS, RA, RB } },
2135
2136 { "slliq",   XRC(31,248,0), X_MASK,     POWER|M601,     { RA, RS, SH } },
2137 { "slliq.",  XRC(31,248,1), X_MASK,     POWER|M601,     { RA, RS, SH } },
2138
2139 { "doz",     XO(31,264,0,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2140 { "doz.",    XO(31,264,0,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2141 { "dozo",    XO(31,264,1,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2142 { "dozo.",   XO(31,264,1,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2143
2144 { "add",     XO(31,266,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
2145 { "cax",     XO(31,266,0,0), XO_MASK,   POWER,          { RT, RA, RB } },
2146 { "add.",    XO(31,266,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
2147 { "cax.",    XO(31,266,0,1), XO_MASK,   POWER,          { RT, RA, RB } },
2148 { "addo",    XO(31,266,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
2149 { "caxo",    XO(31,266,1,0), XO_MASK,   POWER,          { RT, RA, RB } },
2150 { "addo.",   XO(31,266,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
2151 { "caxo.",   XO(31,266,1,1), XO_MASK,   POWER,          { RT, RA, RB } },
2152
2153 { "lscbx",   XRC(31,277,0), X_MASK,     POWER|M601,     { RT, RA, RB } },
2154 { "lscbx.",  XRC(31,277,1), X_MASK,     POWER|M601,     { RT, RA, RB } },
2155
2156 { "dcbt",    X(31,278), XRT_MASK,       PPC,            { RA, RB } },
2157
2158 { "lhzx",    X(31,279), X_MASK,         PPC|POWER,      { RT, RA, RB } },
2159
2160 { "eqv",     XRC(31,284,0), X_MASK,     PPC|POWER,      { RA, RS, RB } },
2161 { "eqv.",    XRC(31,284,1), X_MASK,     PPC|POWER,      { RA, RS, RB } },
2162
2163 { "tlbie",   X(31,306), XRTRA_MASK,     PPC,            { RB } },
2164 { "tlbi",    X(31,306), XRTRA_MASK,     POWER,          { RB } },
2165
2166 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
2167
2168 { "lhzux",   X(31,311), X_MASK,         PPC|POWER,      { RT, RA, RB } },
2169
2170 { "xor",     XRC(31,316,0), X_MASK,     PPC|POWER,      { RA, RS, RB } },
2171 { "xor.",    XRC(31,316,1), X_MASK,     PPC|POWER,      { RA, RS, RB } },
2172
2173 { "div",     XO(31,331,0,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2174 { "div.",    XO(31,331,0,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2175 { "divo",    XO(31,331,1,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2176 { "divo.",   XO(31,331,1,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2177
2178 { "mfmq",    XSPR(31,339,0), XSPR_MASK, POWER|M601,     { RT } },
2179 { "mfxer",   XSPR(31,339,1), XSPR_MASK, PPC|POWER,      { RT } },
2180 { "mflr",    XSPR(31,339,8), XSPR_MASK, PPC|POWER,      { RT } },
2181 { "mfctr",   XSPR(31,339,9), XSPR_MASK, PPC|POWER,      { RT } },
2182 { "mfspr",   X(31,339), X_MASK,         PPC|POWER,      { RT, SPR } },
2183
2184 { "lwax",    X(31,341), X_MASK,         PPC|B64,        { RT, RA, RB } },
2185
2186 { "lhax",    X(31,343), X_MASK,         PPC|POWER,      { RT, RA, RB } },
2187
2188 { "abs",     XO(31,360,0,0), XORB_MASK, POWER|M601,     { RT, RA } },
2189 { "abs.",    XO(31,360,0,1), XORB_MASK, POWER|M601,     { RT, RA } },
2190 { "abso",    XO(31,360,1,0), XORB_MASK, POWER|M601,     { RT, RA } },
2191 { "abso.",   XO(31,360,1,1), XORB_MASK, POWER|M601,     { RT, RA } },
2192
2193 { "divs",    XO(31,363,0,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2194 { "divs.",   XO(31,363,0,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2195 { "divso",   XO(31,363,1,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2196 { "divso.",  XO(31,363,1,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
2197
2198 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
2199
2200 { "mftb",    X(31,371), X_MASK,         PPC,            { RT, TBR } },
2201
2202 { "lwaux",   X(31,373), X_MASK,         PPC|B64,        { RT, RA, RB } },
2203
2204 { "lhaux",   X(31,375), X_MASK,         PPC|POWER,      { RT, RA, RB } },
2205
2206 { "sthx",    X(31,407), X_MASK,         PPC|POWER,      { RS, RA, RB } },
2207
2208 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
2209
2210 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
2211
2212 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
2213
2214 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
2215
2216 { "orc",     XRC(31,412,0), X_MASK,     PPC|POWER,      { RA, RS, RB } },
2217 { "orc.",    XRC(31,412,1), X_MASK,     PPC|POWER,      { RA, RS, RB } },
2218
2219 { "sradi",   XS(31,413,0), XS_MASK,     PPC|B64,        { RA, RS, SH6 } },
2220 { "sradi.",  XS(31,413,1), XS_MASK,     PPC|B64,        { RA, RS, SH6 } },
2221
2222 { "slbie",   X(31,434), XRTRA_MASK,     PPC|B64,        { RB } },
2223
2224 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
2225
2226 { "sthux",   X(31,439), X_MASK,         PPC|POWER,      { RS, RA, RB } },
2227
2228 { "mr",      XRC(31,444,0), X_MASK,     PPC|POWER,      { RA, RS, RBS } },
2229 { "or",      XRC(31,444,0), X_MASK,     PPC|POWER,      { RA, RS, RB } },
2230 { "mr.",     XRC(31,444,1), X_MASK,     PPC|POWER,      { RA, RS, RBS } },
2231 { "or.",     XRC(31,444,1), X_MASK,     PPC|POWER,      { RA, RS, RB } },
2232
2233 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC|B64,        { RT, RA, RB } },
2234 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC|B64,        { RT, RA, RB } },
2235 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC|B64,        { RT, RA, RB } },
2236 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC|B64,        { RT, RA, RB } },
2237
2238 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
2239 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
2240 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
2241 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
2242
2243 { "mtmq",    XSPR(31,467,0), XSPR_MASK, POWER|M601,     { RS } },
2244 { "mtxer",   XSPR(31,467,1), XSPR_MASK, PPC|POWER,      { RS } },
2245 { "mtlr",    XSPR(31,467,8), XSPR_MASK, PPC|POWER,      { RS } },
2246 { "mtctr",   XSPR(31,467,9), XSPR_MASK, PPC|POWER,      { RS } },
2247 { "mtspr",   X(31,467), X_MASK,         PPC|POWER,      { SPR, RS } },
2248
2249 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
2250
2251 { "nand",    XRC(31,476,0), X_MASK,     PPC|POWER,      { RA, RS, RB } },
2252 { "nand.",   XRC(31,476,1), X_MASK,     PPC|POWER,      { RA, RS, RB } },
2253
2254 { "nabs",    XO(31,488,0,0), XORB_MASK, POWER|M601,     { RT, RA } },
2255 { "nabs.",   XO(31,488,0,1), XORB_MASK, POWER|M601,     { RT, RA } },
2256 { "nabso",   XO(31,488,1,0), XORB_MASK, POWER|M601,     { RT, RA } },
2257 { "nabso.",  XO(31,488,1,1), XORB_MASK, POWER|M601,     { RT, RA } },
2258
2259 { "divd",    XO(31,489,0,0), XO_MASK,   PPC|B64,        { RT, RA, RB } },
2260 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC|B64,        { RT, RA, RB } },
2261 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC|B64,        { RT, RA, RB } },
2262 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC|B64,        { RT, RA, RB } },
2263
2264 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
2265 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
2266 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
2267 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
2268
2269 { "slbia",   X(31,498), 0xffffffff,     PPC|B64,        { 0 } },
2270
2271 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
2272
2273 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), PPC|POWER,  { BF } },
2274
2275 { "clcs",    X(31,531), XRB_MASK,       POWER|M601,     { RT, RA } },
2276
2277 { "lswx",    X(31,533), X_MASK,         PPC,            { RT, RA, RB } },
2278 { "lsx",     X(31,533), X_MASK,         POWER,          { RT, RA, RB } },
2279
2280 { "lwbrx",   X(31,534), X_MASK,         PPC,            { RT, RA, RB } },
2281 { "lbrx",    X(31,534), X_MASK,         POWER,          { RT, RA, RB } },
2282
2283 { "lfsx",    X(31,535), X_MASK,         PPC|POWER,      { FRT, RA, RB } },
2284
2285 { "srw",     XRC(31,536,0), X_MASK,     PPC,            { RA, RS, RB } },
2286 { "sr",      XRC(31,536,0), X_MASK,     POWER,          { RA, RS, RB } },
2287 { "srw.",    XRC(31,536,1), X_MASK,     PPC,            { RA, RS, RB } },
2288 { "sr.",     XRC(31,536,1), X_MASK,     POWER,          { RA, RS, RB } },
2289
2290 { "rrib",    XRC(31,537,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
2291 { "rrib.",   XRC(31,537,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
2292
2293 { "srd",     XRC(31,539,0), X_MASK,     PPC|B64,        { RA, RS, RB } },
2294 { "srd.",    XRC(31,539,1), X_MASK,     PPC|B64,        { RA, RS, RB } },
2295
2296 { "maskir",  XRC(31,541,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
2297 { "maskir.", XRC(31,541,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
2298
2299 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
2300
2301 { "lfsux",   X(31,567), X_MASK,         PPC|POWER,      { FRT, RA, RB } },
2302
2303 { "mfsr",    X(31,595), XRB_MASK|(1<<20), PPC|POWER|B32, { RT, SR } },
2304
2305 { "lswi",    X(31,597), X_MASK,         PPC,            { RT, RA, NB } },
2306 { "lsi",     X(31,597), X_MASK,         POWER,          { RT, RA, NB } },
2307
2308 { "sync",    X(31,598), 0xffffffff,     PPC,            { 0 } },
2309 { "dcs",     X(31,598), 0xffffffff,     POWER,          { 0 } },
2310
2311 { "lfdx",    X(31,599), X_MASK,         PPC|POWER,      { FRT, RA, RB } },
2312
2313 { "mfsri",   X(31,627), X_MASK,         POWER,          { RT, RA, RB } },
2314
2315 { "dclst",   X(31,630), XRB_MASK,       POWER,          { RS, RA } },
2316
2317 { "lfdux",   X(31,631), X_MASK,         PPC|POWER,      { FRT, RA, RB } },
2318
2319 { "mfsrin",  X(31,659), XRA_MASK,       PPC|B32,        { RT, RB } },
2320
2321 { "stswx",   X(31,661), X_MASK,         PPC,            { RS, RA, RB } },
2322 { "stsx",    X(31,661), X_MASK,         POWER,          { RS, RA, RB } },
2323
2324 { "stwbrx",  X(31,662), X_MASK,         PPC,            { RS, RA, RB } },
2325 { "stbrx",   X(31,662), X_MASK,         POWER,          { RS, RA, RB } },
2326
2327 { "stfsx",   X(31,663), X_MASK,         PPC|POWER,      { FRS, RA, RB } },
2328
2329 { "srq",     XRC(31,664,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
2330 { "srq.",    XRC(31,664,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
2331
2332 { "sre",     XRC(31,665,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
2333 { "sre.",    XRC(31,665,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
2334
2335 { "stfsux",  X(31,695), X_MASK,         PPC|POWER,      { FRS, RA, RB } },
2336
2337 { "sriq",    XRC(31,696,0), X_MASK,     POWER|M601,     { RA, RS, SH } },
2338 { "sriq.",   XRC(31,696,1), X_MASK,     POWER|M601,     { RA, RS, SH } },
2339
2340 { "stswi",   X(31,725), X_MASK,         PPC,            { RS, RA, NB } },
2341 { "stsi",    X(31,725), X_MASK,         POWER,          { RS, RA, NB } },
2342
2343 { "stfdx",   X(31,727), X_MASK,         PPC|POWER,      { FRS, RA, RB } },
2344
2345 { "srlq",    XRC(31,728,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
2346 { "srlq.",   XRC(31,728,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
2347
2348 { "sreq",    XRC(31,729,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
2349 { "sreq.",   XRC(31,729,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
2350
2351 { "stfdux",  X(31,759), X_MASK,         PPC|POWER,      { FRS, RA, RB } },
2352
2353 { "srliq",   XRC(31,760,0), X_MASK,     POWER|M601,     { RA, RS, SH } },
2354 { "srliq.",  XRC(31,760,1), X_MASK,     POWER|M601,     { RA, RS, SH } },
2355
2356 { "lhbrx",   X(31,790), X_MASK,         PPC|POWER,      { RT, RA, RB } },
2357
2358 { "sraw",    XRC(31,792,0), X_MASK,     PPC,            { RA, RS, RB } },
2359 { "sra",     XRC(31,792,0), X_MASK,     POWER,          { RA, RS, RB } },
2360 { "sraw.",   XRC(31,792,1), X_MASK,     PPC,            { RA, RS, RB } },
2361 { "sra.",    XRC(31,792,1), X_MASK,     POWER,          { RA, RS, RB } },
2362
2363 { "srad",    XRC(31,794,0), X_MASK,     PPC|B64,        { RA, RS, RB } },
2364 { "srad.",   XRC(31,794,1), X_MASK,     PPC|B64,        { RA, RS, RB } },
2365
2366 { "rac",     X(31,818), X_MASK,         POWER,          { RT, RA, RB } },
2367
2368 { "srawi",   XRC(31,824,0), X_MASK,     PPC,            { RA, RS, SH } },
2369 { "srai",    XRC(31,824,0), X_MASK,     POWER,          { RA, RS, SH } },
2370 { "srawi.",  XRC(31,824,1), X_MASK,     PPC,            { RA, RS, SH } },
2371 { "srai.",   XRC(31,824,1), X_MASK,     POWER,          { RA, RS, SH } },
2372
2373 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
2374
2375 { "sthbrx",  X(31,918), X_MASK,         PPC|POWER,      { RS, RA, RB } },
2376
2377 { "sraq",    XRC(31,920,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
2378 { "sraq.",   XRC(31,920,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
2379
2380 { "srea",    XRC(31,921,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
2381 { "srea.",   XRC(31,921,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
2382
2383 { "extsh",   XRC(31,922,0), XRB_MASK,   PPC,            { RA, RS } },
2384 { "exts",    XRC(31,922,0), XRB_MASK,   POWER,          { RA, RS } },
2385 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPC,            { RA, RS } },
2386 { "exts.",   XRC(31,922,1), XRB_MASK,   POWER,          { RA, RS } },
2387
2388 { "sraiq",   XRC(31,952,0), X_MASK,     POWER|M601,     { RA, RS, SH } },
2389 { "sraiq.",  XRC(31,952,1), X_MASK,     POWER|M601,     { RA, RS, SH } },
2390
2391 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
2392 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
2393
2394 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
2395
2396 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA, RB } },
2397
2398 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC,            { RA, RS } },
2399 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC,            { RA, RS } },
2400
2401 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
2402 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
2403
2404 { "lwz",     OP(32),    OP_MASK,        PPC,            { RT, D, RA } },
2405 { "l",       OP(32),    OP_MASK,        POWER,          { RT, D, RA } },
2406
2407 { "lwzu",    OP(33),    OP_MASK,        PPC,            { RT, D, RA } },
2408 { "lu",      OP(33),    OP_MASK,        POWER,          { RT, D, RA } },
2409
2410 { "lbz",     OP(34),    OP_MASK,        PPC|POWER,      { RT, D, RA } },
2411
2412 { "lbzu",    OP(35),    OP_MASK,        PPC|POWER,      { RT, D, RA } },
2413
2414 { "stw",     OP(36),    OP_MASK,        PPC,            { RS, D, RA } },
2415 { "st",      OP(36),    OP_MASK,        POWER,          { RS, D, RA } },
2416
2417 { "stwu",    OP(37),    OP_MASK,        PPC,            { RS, D, RA } },
2418 { "stu",     OP(37),    OP_MASK,        POWER,          { RS, D, RA } },
2419
2420 { "stb",     OP(38),    OP_MASK,        PPC|POWER,      { RS, D, RA } },
2421
2422 { "stbu",    OP(39),    OP_MASK,        PPC|POWER,      { RS, D, RA } },
2423
2424 { "lhz",     OP(40),    OP_MASK,        PPC|POWER,      { RT, D, RA } },
2425
2426 { "lhzu",    OP(41),    OP_MASK,        PPC|POWER,      { RT, D, RA } },
2427
2428 { "lha",     OP(42),    OP_MASK,        PPC|POWER,      { RT, D, RA } },
2429
2430 { "lhau",    OP(43),    OP_MASK,        PPC|POWER,      { RT, D, RA } },
2431
2432 { "sth",     OP(44),    OP_MASK,        PPC|POWER,      { RS, D, RA } },
2433
2434 { "sthu",    OP(45),    OP_MASK,        PPC|POWER,      { RS, D, RA } },
2435
2436 { "lmw",     OP(46),    OP_MASK,        PPC,            { RT, D, RA } },
2437 { "lm",      OP(46),    OP_MASK,        POWER,          { RT, D, RA } },
2438
2439 { "stmw",    OP(47),    OP_MASK,        PPC,            { RS, D, RA } },
2440 { "stm",     OP(47),    OP_MASK,        POWER,          { RS, D, RA } },
2441
2442 { "lfs",     OP(48),    OP_MASK,        PPC|POWER,      { FRT, D, RA } },
2443
2444 { "lfsu",    OP(49),    OP_MASK,        PPC|POWER,      { FRT, D, RA } },
2445
2446 { "lfd",     OP(50),    OP_MASK,        PPC|POWER,      { FRT, D, RA } },
2447
2448 { "lfdu",    OP(51),    OP_MASK,        PPC|POWER,      { FRT, D, RA } },
2449
2450 { "stfs",    OP(52),    OP_MASK,        PPC|POWER,      { FRS, D, RA } },
2451
2452 { "stfsu",   OP(53),    OP_MASK,        PPC|POWER,      { FRS, D, RA } },
2453
2454 { "stfd",    OP(54),    OP_MASK,        PPC|POWER,      { FRS, D, RA } },
2455
2456 { "stfdu",   OP(55),    OP_MASK,        PPC|POWER,      { FRS, D, RA } },
2457
2458 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA } },
2459
2460 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA } },
2461
2462 { "ld",      DSO(58,0), DS_MASK,        PPC|B64,        { RT, DS, RA } },
2463
2464 { "ldu",     DSO(58,1), DS_MASK,        PPC|B64,        { RT, DS, RA } },
2465
2466 { "lwa",     DSO(58,2), DS_MASK,        PPC|B64,        { RT, DS, RA } },
2467
2468 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2469 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2470
2471 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2472 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2473
2474 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2475 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2476
2477 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
2478 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
2479
2480 { "fres",    A(59,24,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
2481 { "fres.",   A(59,24,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
2482
2483 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
2484 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
2485
2486 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2487 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2488
2489 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2490 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2491
2492 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2493 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2494
2495 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2496 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2497
2498 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
2499
2500 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
2501
2502 { "std",     DSO(62,0), DS_MASK,        PPC|B64,        { RS, DS, RA } },
2503
2504 { "stdu",    DSO(62,1), DS_MASK,        PPC|B64,        { RS, DS, RA } },
2505
2506 { "fcmpu",   X(63,0),   X_MASK|(3<<21), PPC|POWER,      { BF, FRA, FRB } },
2507
2508 { "frsp",    XRC(63,12,0), XRA_MASK,    PPC|POWER,      { FRT, FRB } },
2509 { "frsp.",   XRC(63,12,1), XRA_MASK,    PPC|POWER,      { FRT, FRB } },
2510
2511 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPC,            { FRT, FRB } },
2512 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
2513 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPC,            { FRT, FRB } },
2514 { "fcir.",   XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
2515
2516 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPC,            { FRT, FRB } },
2517 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
2518 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPC,            { FRT, FRB } },
2519 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
2520
2521 { "fdiv",    A(63,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2522 { "fd",      A(63,18,0), AFRC_MASK,     POWER,          { FRT, FRA, FRB } },
2523 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2524 { "fd.",     A(63,18,1), AFRC_MASK,     POWER,          { FRT, FRA, FRB } },
2525
2526 { "fsub",    A(63,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2527 { "fs",      A(63,20,0), AFRC_MASK,     POWER,          { FRT, FRA, FRB } },
2528 { "fsub.",   A(63,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2529 { "fs.",     A(63,20,1), AFRC_MASK,     POWER,          { FRT, FRA, FRB } },
2530
2531 { "fadd",    A(63,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2532 { "fa",      A(63,21,0), AFRC_MASK,     POWER,          { FRT, FRA, FRB } },
2533 { "fadd.",   A(63,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2534 { "fa.",     A(63,21,1), AFRC_MASK,     POWER,          { FRT, FRA, FRB } },
2535
2536 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPC|POWER2,     { FRT, FRB } },
2537 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPC|POWER2,     { FRT, FRB } },
2538
2539 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2540 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2541
2542 { "fmul",    A(63,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
2543 { "fm",      A(63,25,0), AFRB_MASK,     POWER,          { FRT, FRA, FRC } },
2544 { "fmul.",   A(63,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
2545 { "fm.",     A(63,25,1), AFRB_MASK,     POWER,          { FRT, FRA, FRC } },
2546
2547 { "frsqrte", A(63,26,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
2548 { "frsqrte.",A(63,26,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
2549
2550 { "fmsub",   A(63,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2551 { "fms",     A(63,28,0), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
2552 { "fmsub.",  A(63,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2553 { "fms.",    A(63,28,1), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
2554
2555 { "fmadd",   A(63,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2556 { "fma",     A(63,29,0), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
2557 { "fmadd.",  A(63,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2558 { "fma.",    A(63,29,1), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
2559
2560 { "fnmsub",  A(63,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2561 { "fnms",    A(63,30,0), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
2562 { "fnmsub.", A(63,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2563 { "fnms.",   A(63,30,1), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
2564
2565 { "fnmadd",  A(63,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2566 { "fnma",    A(63,31,0), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
2567 { "fnmadd.", A(63,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2568 { "fnma.",   A(63,31,1), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
2569
2570 { "fcmpo",   X(63,30),  X_MASK|(3<<21), PPC|POWER,      { BF, FRA, FRB } },
2571
2572 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  PPC|POWER,      { BT } },
2573 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  PPC|POWER,      { BT } },
2574
2575 { "fneg",    XRC(63,40,0), XRA_MASK,    PPC|POWER,      { FRT, FRB } },
2576 { "fneg.",   XRC(63,40,1), XRA_MASK,    PPC|POWER,      { FRT, FRB } },
2577
2578 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
2579
2580 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  PPC|POWER,      { BT } },
2581 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  PPC|POWER,      { BT } },
2582
2583 { "fmr",     XRC(63,72,0), XRA_MASK,    PPC|POWER,      { FRT, FRB } },
2584 { "fmr.",    XRC(63,72,1), XRA_MASK,    PPC|POWER,      { FRT, FRB } },
2585
2586 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2587 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2588
2589 { "fnabs",   XRC(63,136,0), XRA_MASK,   PPC|POWER,      { FRT, FRB } },
2590 { "fnabs.",  XRC(63,136,1), XRA_MASK,   PPC|POWER,      { FRT, FRB } },
2591
2592 { "fabs",    XRC(63,264,0), XRA_MASK,   PPC|POWER,      { FRT, FRB } },
2593 { "fabs.",   XRC(63,264,1), XRA_MASK,   PPC|POWER,      { FRT, FRB } },
2594
2595 { "mffs",    XRC(63,583,0), XRARB_MASK, PPC|POWER,      { FRT } },
2596 { "mffs.",   XRC(63,583,1), XRARB_MASK, PPC|POWER,      { FRT } },
2597
2598 { "mtfsf",   XFL(63,711,0), XFL_MASK,   PPC|POWER,      { FLM, FRB } },
2599 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   PPC|POWER,      { FLM, FRB } },
2600
2601 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC|B64,        { FRT, FRB } },
2602 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC|B64,        { FRT, FRB } },
2603
2604 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC|B64,        { FRT, FRB } },
2605 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC|B64,        { FRT, FRB } },
2606
2607 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC|B64,        { FRT, FRB } },
2608 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC|B64,        { FRT, FRB } },
2609
2610 };
2611
2612 const int powerpc_num_opcodes =
2613   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
2614 \f
2615 /* The macro table.  This is only used by the assembler.  */
2616
2617 const struct powerpc_macro powerpc_macros[] = {
2618 { "extldi",  4,   PPC|B64,      "rldicr %0,%1,%3,(%2)-1" },
2619 { "extldi.", 4,   PPC|B64,      "rldicr. %0,%1,%3,(%2)-1" },
2620 { "extrdi",  4,   PPC|B64,      "rldicl %0,%1,(%2)+(%3),64-(%2)" },
2621 { "extrdi.", 4,   PPC|B64,      "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
2622 { "insrdi",  4,   PPC|B64,      "rldimi %0,%1,64-((%2)+(%3)),%3" },
2623 { "insrdi.", 4,   PPC|B64,      "rldimi. %0,%1,64-((%2)+(%3)),%3" },
2624 { "rotrdi",  3,   PPC|B64,      "rldicl %0,%1,64-(%2),0" },
2625 { "rotrdi.", 3,   PPC|B64,      "rldicl. %0,%1,64-(%2),0" },
2626 { "sldi",    3,   PPC|B64,      "rldicr %0,%1,%2,63-(%2)" },
2627 { "sldi.",   3,   PPC|B64,      "rldicr. %0,%1,%2,63-(%2)" },
2628 { "srdi",    3,   PPC|B64,      "rldicl %0,%1,64-(%2),%2" },
2629 { "srdi.",   3,   PPC|B64,      "rldicl. %0,%1,64-(%2),%2" },
2630 { "clrrdi",  3,   PPC|B64,      "rldicr %0,%1,0,63-(%2)" },
2631 { "clrrdi.", 3,   PPC|B64,      "rldicr. %0,%1,0,63-(%2)" },
2632 { "clrlsldi",4,   PPC|B64,      "rldic %0,%1,%3,(%2)-(%3)" },
2633 { "clrlsldi.",4,  PPC|B64,      "rldic. %0,%1,%3,(%2)-(%3)" },
2634
2635 { "extlwi",  4,   PPC,          "rlwinm %0,%1,%3,0,(%2)-1" },
2636 { "extlwi.", 4,   PPC,          "rlwinm. %0,%1,%3,0,(%2)-1" },
2637 { "extrwi",  4,   PPC,          "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
2638 { "extrwi.", 4,   PPC,          "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
2639 { "inslwi",  4,   PPC,          "rlwimi %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2640 { "inslwi.", 4,   PPC,          "rlwimi. %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2641 { "insrwi",  4,   PPC,          "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
2642 { "insrwi.", 4,   PPC,          "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
2643 { "rotrwi",  3,   PPC,          "rlwinm %0,%1,32-(%2),0,31" },
2644 { "rotrwi.", 3,   PPC,          "rlwinm. %0,%1,32-(%2),0,31" },
2645 { "slwi",    3,   PPC,          "rlwinm %0,%1,%2,0,31-(%2)" },
2646 { "sli",     3,   POWER,        "rlinm %0,%1,%2,0,31-(%2)" },
2647 { "slwi.",   3,   PPC,          "rlwinm. %0,%1,%2,0,31-(%2)" },
2648 { "sli.",    3,   POWER,        "rlinm. %0,%1,%2,0,31-(%2)" },
2649 { "srwi",    3,   PPC,          "rlwinm %0,%1,32-(%2),%2,31" },
2650 { "sri",     3,   POWER,        "rlinm %0,%1,32-(%2),%2,31" },
2651 { "srwi.",   3,   PPC,          "rlwinm. %0,%1,32-(%2),%2,31" },
2652 { "sri.",    3,   POWER,        "rlinm. %0,%1,32-(%2),%2,31" },
2653 { "clrrwi",  3,   PPC,          "rlwinm %0,%1,0,0,31-(%2)" },
2654 { "clrrwi.", 3,   PPC,          "rlwinm. %0,%1,0,0,31-(%2)" },
2655 { "clrlslwi",4,   PPC,          "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
2656 { "clrlslwi.",4,  PPC,          "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
2657
2658 };
2659
2660 const int powerpc_num_macros =
2661   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);