1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Written by Ian Lance Taylor, Cygnus Support
7 This file is part of the GNU opcodes library.
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this file; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "opcode/ppc.h"
29 /* This file holds the PowerPC opcode table. The opcode table
30 includes almost all of the extended instruction mnemonics. This
31 permits the disassembler to use them, and simplifies the assembler
32 logic, at the cost of increasing the table size. The table is
33 strictly constant data, so the compiler should be able to put it in
36 This file also holds the operand table. All knowledge about
37 inserting operands into instructions and vice-versa is kept in this
40 /* Local insertion and extraction functions. */
42 static unsigned long insert_arx (unsigned long, long, ppc_cpu_t
, const char **);
43 static long extract_arx (unsigned long, ppc_cpu_t
, int *);
44 static unsigned long insert_ary (unsigned long, long, ppc_cpu_t
, const char **);
45 static long extract_ary (unsigned long, ppc_cpu_t
, int *);
46 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t
, const char **);
47 static long extract_bat (unsigned long, ppc_cpu_t
, int *);
48 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t
, const char **);
49 static long extract_bba (unsigned long, ppc_cpu_t
, int *);
50 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t
, const char **);
51 static long extract_bdm (unsigned long, ppc_cpu_t
, int *);
52 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t
, const char **);
53 static long extract_bdp (unsigned long, ppc_cpu_t
, int *);
54 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t
, const char **);
55 static long extract_bo (unsigned long, ppc_cpu_t
, int *);
56 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t
, const char **);
57 static long extract_boe (unsigned long, ppc_cpu_t
, int *);
58 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t
, const char **);
59 static long extract_fxm (unsigned long, ppc_cpu_t
, int *);
60 static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t
, const char **);
61 static long extract_li20 (unsigned long, ppc_cpu_t
, int *);
62 static unsigned long insert_ls (unsigned long, long, ppc_cpu_t
, const char **);
63 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t
, const char **);
64 static long extract_mbe (unsigned long, ppc_cpu_t
, int *);
65 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t
, const char **);
66 static long extract_mb6 (unsigned long, ppc_cpu_t
, int *);
67 static long extract_nb (unsigned long, ppc_cpu_t
, int *);
68 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t
, const char **);
69 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t
, const char **);
70 static long extract_nsi (unsigned long, ppc_cpu_t
, int *);
71 static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t
, const char **);
72 static long extract_oimm (unsigned long, ppc_cpu_t
, int *);
73 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t
, const char **);
74 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t
, const char **);
75 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t
, const char **);
76 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t
, const char **);
77 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t
, const char **);
78 static long extract_rbs (unsigned long, ppc_cpu_t
, int *);
79 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t
, const char **);
80 static unsigned long insert_rx (unsigned long, long, ppc_cpu_t
, const char **);
81 static long extract_rx (unsigned long, ppc_cpu_t
, int *);
82 static unsigned long insert_ry (unsigned long, long, ppc_cpu_t
, const char **);
83 static long extract_ry (unsigned long, ppc_cpu_t
, int *);
84 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t
, const char **);
85 static long extract_sh6 (unsigned long, ppc_cpu_t
, int *);
86 static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t
, const char **);
87 static long extract_sci8 (unsigned long, ppc_cpu_t
, int *);
88 static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t
, const char **);
89 static long extract_sci8n (unsigned long, ppc_cpu_t
, int *);
90 static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t
, const char **);
91 static long extract_sd4h (unsigned long, ppc_cpu_t
, int *);
92 static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t
, const char **);
93 static long extract_sd4w (unsigned long, ppc_cpu_t
, int *);
94 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t
, const char **);
95 static long extract_spr (unsigned long, ppc_cpu_t
, int *);
96 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t
, const char **);
97 static long extract_sprg (unsigned long, ppc_cpu_t
, int *);
98 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t
, const char **);
99 static long extract_tbr (unsigned long, ppc_cpu_t
, int *);
100 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t
, const char **);
101 static long extract_xt6 (unsigned long, ppc_cpu_t
, int *);
102 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t
, const char **);
103 static long extract_xa6 (unsigned long, ppc_cpu_t
, int *);
104 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t
, const char **);
105 static long extract_xb6 (unsigned long, ppc_cpu_t
, int *);
106 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t
, const char **);
107 static long extract_xb6s (unsigned long, ppc_cpu_t
, int *);
108 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t
, const char **);
109 static long extract_xc6 (unsigned long, ppc_cpu_t
, int *);
110 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t
, const char **);
111 static long extract_dm (unsigned long, ppc_cpu_t
, int *);
112 static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t
, const char **);
113 static long extract_vlesi (unsigned long, ppc_cpu_t
, int *);
114 static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t
, const char **);
115 static long extract_vlensi (unsigned long, ppc_cpu_t
, int *);
116 static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t
, const char **);
117 static long extract_vleui (unsigned long, ppc_cpu_t
, int *);
118 static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t
, const char **);
119 static long extract_vleil (unsigned long, ppc_cpu_t
, int *);
121 /* The operands table.
123 The fields are bitm, shift, insert, extract, flags.
125 We used to put parens around the various additions, like the one
126 for BA just below. However, that caused trouble with feeble
127 compilers with a limit on depth of a parenthesized expression, like
128 (reportedly) the compiler in Microsoft Developer Studio 5. So we
129 omit the parens, since the macros are never used in a context where
130 the addition will be ambiguous. */
132 const struct powerpc_operand powerpc_operands
[] =
134 /* The zero index is used to indicate the end of the list of
137 { 0, 0, NULL
, NULL
, 0 },
139 /* The BA field in an XL form instruction. */
140 #define BA UNUSED + 1
141 /* The BI field in a B form or XL form instruction. */
143 #define BI_MASK (0x1f << 16)
144 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
146 /* The BA field in an XL form instruction when it must be the same
147 as the BT field in the same instruction. */
149 { 0x1f, 16, insert_bat
, extract_bat
, PPC_OPERAND_FAKE
},
151 /* The BB field in an XL form instruction. */
153 #define BB_MASK (0x1f << 11)
154 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
156 /* The BB field in an XL form instruction when it must be the same
157 as the BA field in the same instruction. */
159 /* The VB field in a VX form instruction when it must be the same
160 as the VA field in the same instruction. */
162 { 0x1f, 11, insert_bba
, extract_bba
, PPC_OPERAND_FAKE
},
164 /* The BD field in a B form instruction. The lower two bits are
167 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
169 /* The BD field in a B form instruction when absolute addressing is
172 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
174 /* The BD field in a B form instruction when the - modifier is used.
175 This sets the y bit of the BO field appropriately. */
177 { 0xfffc, 0, insert_bdm
, extract_bdm
,
178 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
180 /* The BD field in a B form instruction when the - modifier is used
181 and absolute address is used. */
183 { 0xfffc, 0, insert_bdm
, extract_bdm
,
184 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
186 /* The BD field in a B form instruction when the + modifier is used.
187 This sets the y bit of the BO field appropriately. */
189 { 0xfffc, 0, insert_bdp
, extract_bdp
,
190 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
192 /* The BD field in a B form instruction when the + modifier is used
193 and absolute addressing is used. */
195 { 0xfffc, 0, insert_bdp
, extract_bdp
,
196 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
198 /* The BF field in an X or XL form instruction. */
200 /* The CRFD field in an X form instruction. */
202 /* The CRD field in an XL form instruction. */
204 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
},
206 /* The BF field in an X or XL form instruction. */
208 { 0x7, 23, NULL
, NULL
, 0 },
210 /* An optional BF field. This is used for comparison instructions,
211 in which an omitted BF field is taken as zero. */
213 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
215 /* The BFA field in an X or XL form instruction. */
217 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
},
219 /* The BO field in a B form instruction. Certain values are
222 #define BO_MASK (0x1f << 21)
223 { 0x1f, 21, insert_bo
, extract_bo
, 0 },
225 /* The BO field in a B form instruction when the + or - modifier is
226 used. This is like the BO field, but it must be even. */
228 { 0x1e, 21, insert_boe
, extract_boe
, 0 },
231 { 0x3, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
233 /* The BT field in an X or XL form instruction. */
235 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
237 /* The BI16 field in a BD8 form instruction. */
239 { 0x3, 8, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
241 /* The BI32 field in a BD15 form instruction. */
242 #define BI32 BI16 + 1
243 { 0xf, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
245 /* The BO32 field in a BD15 form instruction. */
246 #define BO32 BI32 + 1
247 { 0x3, 20, NULL
, NULL
, 0 },
249 /* The B8 field in a BD8 form instruction. */
251 { 0x1fe, -1, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
253 /* The B15 field in a BD15 form instruction. The lowest bit is
256 { 0xfffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
258 /* The B24 field in a BD24 form instruction. The lowest bit is
261 { 0x1fffffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
263 /* The condition register number portion of the BI field in a B form
264 or XL form instruction. This is used for the extended
265 conditional branch mnemonics, which set the lower two bits of the
266 BI field. This field is optional. */
268 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
270 /* The CRB field in an X form instruction. */
272 /* The MB field in an M form instruction. */
274 #define MB_MASK (0x1f << 6)
275 { 0x1f, 6, NULL
, NULL
, 0 },
277 /* The CRD32 field in an XL form instruction. */
278 #define CRD32 CRB + 1
279 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_CR_REG
},
281 /* The CRFS field in an X form instruction. */
282 #define CRFS CRD32 + 1
283 { 0x7, 0, NULL
, NULL
, PPC_OPERAND_CR_REG
},
286 { 0x3, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
288 /* The CT field in an X form instruction. */
290 /* The MO field in an mbar instruction. */
292 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
294 /* The D field in a D form instruction. This is a displacement off
295 a register, and implies that the next operand is a register in
298 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
300 /* The D8 field in a D form instruction. This is a displacement off
301 a register, and implies that the next operand is a register in
304 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
306 /* The DQ field in a DQ form instruction. This is like D, but the
307 lower four bits are forced to zero. */
309 { 0xfff0, 0, NULL
, NULL
,
310 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DQ
},
312 /* The DS field in a DS form instruction. This is like D, but the
313 lower two bits are forced to zero. */
315 { 0xfffc, 0, NULL
, NULL
,
316 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DS
},
318 /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
320 { 0x3ff, 11, NULL
, NULL
, 0 },
322 /* The E field in a wrteei instruction. */
323 /* And the W bit in the pair singles instructions. */
326 { 0x1, 15, NULL
, NULL
, 0 },
328 /* The FL1 field in a POWER SC form instruction. */
330 /* The U field in an X form instruction. */
332 { 0xf, 12, NULL
, NULL
, 0 },
334 /* The FL2 field in a POWER SC form instruction. */
336 { 0x7, 2, NULL
, NULL
, 0 },
338 /* The FLM field in an XFL form instruction. */
340 { 0xff, 17, NULL
, NULL
, 0 },
342 /* The FRA field in an X or A form instruction. */
344 #define FRA_MASK (0x1f << 16)
345 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
347 /* The FRAp field of DFP instructions. */
349 { 0x1e, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
351 /* The FRB field in an X or A form instruction. */
353 #define FRB_MASK (0x1f << 11)
354 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
356 /* The FRBp field of DFP instructions. */
358 { 0x1e, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
360 /* The FRC field in an A form instruction. */
362 #define FRC_MASK (0x1f << 6)
363 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_FPR
},
365 /* The FRS field in an X form instruction or the FRT field in a D, X
366 or A form instruction. */
369 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
371 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
375 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
377 /* The FXM field in an XFX instruction. */
379 { 0xff, 12, insert_fxm
, extract_fxm
, 0 },
381 /* Power4 version for mfcr. */
383 { 0xff, 12, insert_fxm
, extract_fxm
, PPC_OPERAND_OPTIONAL
},
385 /* The IMM20 field in an LI instruction. */
386 #define IMM20 FXM4 + 1
387 { 0xfffff, PPC_OPSHIFT_INV
, insert_li20
, extract_li20
, PPC_OPERAND_SIGNED
},
389 /* The L field in a D or X form instruction. */
391 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
393 /* The LEV field in a POWER SVC form instruction. */
394 #define SVC_LEV L + 1
395 { 0x7f, 5, NULL
, NULL
, 0 },
397 /* The LEV field in an SC form instruction. */
398 #define LEV SVC_LEV + 1
399 { 0x7f, 5, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
401 /* The LI field in an I form instruction. The lower two bits are
404 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
406 /* The LI field in an I form instruction when used as an absolute
409 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
411 /* The LS or WC field in an X (sync or wait) form instruction. */
414 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
416 /* The ME field in an M form instruction. */
418 #define ME_MASK (0x1f << 1)
419 { 0x1f, 1, NULL
, NULL
, 0 },
421 /* The MB and ME fields in an M form instruction expressed a single
422 operand which is a bitmask indicating which bits to select. This
423 is a two operand form using PPC_OPERAND_NEXT. See the
424 description in opcode/ppc.h for what this means. */
426 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
427 { -1, 0, insert_mbe
, extract_mbe
, 0 },
429 /* The MB or ME field in an MD or MDS form instruction. The high
430 bit is wrapped to the low end. */
433 #define MB6_MASK (0x3f << 5)
434 { 0x3f, 5, insert_mb6
, extract_mb6
, 0 },
436 /* The NB field in an X form instruction. The value 32 is stored as
439 { 0x1f, 11, NULL
, extract_nb
, PPC_OPERAND_PLUS1
},
441 /* The NBI field in an lswi instruction, which has special value
442 restrictions. The value 32 is stored as 0. */
444 { 0x1f, 11, insert_nbi
, extract_nb
, PPC_OPERAND_PLUS1
},
446 /* The NSI field in a D form instruction. This is the same as the
447 SI field, only negated. */
449 { 0xffff, 0, insert_nsi
, extract_nsi
,
450 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
452 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
454 #define RA_MASK (0x1f << 16)
455 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
},
457 /* As above, but 0 in the RA field means zero, not r0. */
459 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR_0
},
461 /* The RA field in the DQ form lq or an lswx instruction, which have special
462 value restrictions. */
465 { 0x1f, 16, insert_raq
, NULL
, PPC_OPERAND_GPR_0
},
467 /* The RA field in a D or X form instruction which is an updating
468 load, which means that the RA field may not be zero and may not
469 equal the RT field. */
471 { 0x1f, 16, insert_ral
, NULL
, PPC_OPERAND_GPR_0
},
473 /* The RA field in an lmw instruction, which has special value
476 { 0x1f, 16, insert_ram
, NULL
, PPC_OPERAND_GPR_0
},
478 /* The RA field in a D or X form instruction which is an updating
479 store or an updating floating point load, which means that the RA
480 field may not be zero. */
482 { 0x1f, 16, insert_ras
, NULL
, PPC_OPERAND_GPR_0
},
484 /* The RA field of the tlbwe, dccci and iccci instructions,
485 which are optional. */
486 #define RAOPT RAS + 1
487 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
489 /* The RB field in an X, XO, M, or MDS form instruction. */
491 #define RB_MASK (0x1f << 11)
492 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
},
494 /* The RB field in an X form instruction when it must be the same as
495 the RS field in the instruction. This is used for extended
496 mnemonics like mr. */
498 { 0x1f, 11, insert_rbs
, extract_rbs
, PPC_OPERAND_FAKE
},
500 /* The RB field in an lswx instruction, which has special value
503 { 0x1f, 11, insert_rbx
, NULL
, PPC_OPERAND_GPR
},
505 /* The RB field of the dccci and iccci instructions, which are optional. */
506 #define RBOPT RBX + 1
507 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
509 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
510 instruction or the RT field in a D, DS, X, XFX or XO form
514 #define RT_MASK (0x1f << 21)
516 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
518 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
519 which have special value restrictions. */
522 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
524 /* The RS field of the tlbwe instruction, which is optional. */
527 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
529 /* The RX field of the SE_RR form instruction. */
531 { 0x1f, PPC_OPSHIFT_INV
, insert_rx
, extract_rx
, PPC_OPERAND_GPR
},
533 /* The ARX field of the SE_RR form instruction. */
535 { 0x1f, PPC_OPSHIFT_INV
, insert_arx
, extract_arx
, PPC_OPERAND_GPR
},
537 /* The RY field of the SE_RR form instruction. */
540 { 0x1f, PPC_OPSHIFT_INV
, insert_ry
, extract_ry
, PPC_OPERAND_GPR
},
542 /* The ARY field of the SE_RR form instruction. */
544 { 0x1f, PPC_OPSHIFT_INV
, insert_ary
, extract_ary
, PPC_OPERAND_GPR
},
546 /* The SCLSCI8 field in a D form instruction. */
547 #define SCLSCI8 ARY + 1
548 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8
, extract_sci8
, 0 },
550 /* The SCLSCI8N field in a D form instruction. This is the same as the
551 SCLSCI8 field, only negated. */
552 #define SCLSCI8N SCLSCI8 + 1
553 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8n
, extract_sci8n
,
554 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
556 /* The SD field of the SD4 form instruction. */
557 #define SE_SD SCLSCI8N + 1
558 { 0xf, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
560 /* The SD field of the SD4 form instruction, for halfword. */
561 #define SE_SDH SE_SD + 1
562 { 0x1e, PPC_OPSHIFT_INV
, insert_sd4h
, extract_sd4h
, PPC_OPERAND_PARENS
},
564 /* The SD field of the SD4 form instruction, for word. */
565 #define SE_SDW SE_SDH + 1
566 { 0x3c, PPC_OPSHIFT_INV
, insert_sd4w
, extract_sd4w
, PPC_OPERAND_PARENS
},
568 /* The SH field in an X or M form instruction. */
569 #define SH SE_SDW + 1
570 #define SH_MASK (0x1f << 11)
571 /* The other UIMM field in a EVX form instruction. */
573 { 0x1f, 11, NULL
, NULL
, 0 },
575 /* The SH field in an MD form instruction. This is split. */
577 #define SH6_MASK ((0x1f << 11) | (1 << 1))
578 { 0x3f, PPC_OPSHIFT_INV
, insert_sh6
, extract_sh6
, 0 },
580 /* The SH field of the tlbwe instruction, which is optional. */
582 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
584 /* The SI field in a D form instruction. */
586 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
588 /* The SI field in a D form instruction when we accept a wide range
589 of positive values. */
590 #define SISIGNOPT SI + 1
591 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
593 /* The SI8 field in a D form instruction. */
594 #define SI8 SISIGNOPT + 1
595 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
597 /* The SPR field in an XFX form instruction. This is flipped--the
598 lower 5 bits are stored in the upper 5 and vice- versa. */
602 #define SPR_MASK (0x3ff << 11)
603 { 0x3ff, 11, insert_spr
, extract_spr
, 0 },
605 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
606 #define SPRBAT SPR + 1
607 #define SPRBAT_MASK (0x3 << 17)
608 { 0x3, 17, NULL
, NULL
, 0 },
610 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
611 #define SPRG SPRBAT + 1
612 { 0x1f, 16, insert_sprg
, extract_sprg
, 0 },
614 /* The SR field in an X form instruction. */
616 /* The 4-bit UIMM field in a VX form instruction. */
618 { 0xf, 16, NULL
, NULL
, 0 },
620 /* The STRM field in an X AltiVec form instruction. */
622 /* The T field in a tlbilx form instruction. */
624 { 0x3, 21, NULL
, NULL
, 0 },
626 /* The ESYNC field in an X (sync) form instruction. */
627 #define ESYNC STRM + 1
628 { 0xf, 16, insert_ls
, NULL
, PPC_OPERAND_OPTIONAL
},
630 /* The SV field in a POWER SC form instruction. */
632 { 0x3fff, 2, NULL
, NULL
, 0 },
634 /* The TBR field in an XFX form instruction. This is like the SPR
635 field, but it is optional. */
637 { 0x3ff, 11, insert_tbr
, extract_tbr
, PPC_OPERAND_OPTIONAL
},
639 /* The TO field in a D or X form instruction. */
642 #define TO_MASK (0x1f << 21)
643 { 0x1f, 21, NULL
, NULL
, 0 },
645 /* The UI field in a D form instruction. */
647 { 0xffff, 0, NULL
, NULL
, 0 },
649 /* The IMM field in an SE_IM5 instruction. */
651 { 0x1f, 4, NULL
, NULL
, 0 },
653 /* The OIMM field in an SE_OIM5 instruction. */
654 #define OIMM5 UI5 + 1
655 { 0x1f, PPC_OPSHIFT_INV
, insert_oimm
, extract_oimm
, PPC_OPERAND_PLUS1
},
657 /* The UI7 field in an SE_LI instruction. */
658 #define UI7 OIMM5 + 1
659 { 0x7f, 4, NULL
, NULL
, 0 },
661 /* The VA field in a VA, VX or VXR form instruction. */
663 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_VR
},
665 /* The VB field in a VA, VX or VXR form instruction. */
667 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_VR
},
669 /* The VC field in a VA form instruction. */
671 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_VR
},
673 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
676 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_VR
},
678 /* The SIMM field in a VX form instruction, and TE in Z form. */
681 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_SIGNED
},
683 /* The UIMM field in a VX form instruction. */
684 #define UIMM SIMM + 1
686 { 0x1f, 16, NULL
, NULL
, 0 },
688 /* The 3-bit UIMM field in a VX form instruction. */
689 #define UIMM3 UIMM + 1
690 { 0x7, 16, NULL
, NULL
, 0 },
692 /* The SHB field in a VA form instruction. */
693 #define SHB UIMM3 + 1
694 { 0xf, 6, NULL
, NULL
, 0 },
696 /* The other UIMM field in a half word EVX form instruction. */
697 #define EVUIMM_2 SHB + 1
698 { 0x3e, 10, NULL
, NULL
, PPC_OPERAND_PARENS
},
700 /* The other UIMM field in a word EVX form instruction. */
701 #define EVUIMM_4 EVUIMM_2 + 1
702 { 0x7c, 9, NULL
, NULL
, PPC_OPERAND_PARENS
},
704 /* The other UIMM field in a double EVX form instruction. */
705 #define EVUIMM_8 EVUIMM_4 + 1
706 { 0xf8, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
709 #define WS EVUIMM_8 + 1
710 { 0x7, 11, NULL
, NULL
, 0 },
712 /* PowerPC paired singles extensions. */
713 /* W bit in the pair singles instructions for x type instructions. */
715 /* The BO16 field in a BD8 form instruction. */
717 { 0x1, 10, 0, 0, 0 },
719 /* IDX bits for quantization in the pair singles instructions. */
721 { 0x7, 12, 0, 0, 0 },
723 /* IDX bits for quantization in the pair singles x-type instructions. */
727 /* Smaller D field for quantization in the pair singles instructions. */
729 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
734 { 0x1, 16, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
736 #define RMC MTMSRD_L + 1
737 { 0x3, 9, NULL
, NULL
, 0 },
740 { 0x1, 16, NULL
, NULL
, 0 },
743 { 0x3, 19, NULL
, NULL
, 0 },
746 { 0x1, 20, NULL
, NULL
, 0 },
748 /* SH field starting at bit position 16. */
750 /* The DCM and DGM fields in a Z form instruction. */
753 { 0x3f, 10, NULL
, NULL
, 0 },
755 /* The EH field in larx instruction. */
757 { 0x1, 0, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
759 /* The L field in an mtfsf or XFL form instruction. */
761 { 0x1, 25, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
763 /* Xilinx APU related masks and macros */
764 #define FCRT XFL_L + 1
765 #define FCRT_MASK (0x1f << 21)
766 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR
},
768 /* Xilinx FSL related masks and macros */
770 #define FSL_MASK (0x1f << 11)
771 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL
},
773 /* Xilinx UDI related masks and macros */
775 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI
},
778 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI
},
781 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI
},
784 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI
},
786 /* The VLESIMM field in a D form instruction. */
787 #define VLESIMM URC + 1
788 { 0xffff, PPC_OPSHIFT_INV
, insert_vlesi
, extract_vlesi
,
789 PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
791 /* The VLENSIMM field in a D form instruction. */
792 #define VLENSIMM VLESIMM + 1
793 { 0xffff, PPC_OPSHIFT_INV
, insert_vlensi
, extract_vlensi
,
794 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
796 /* The VLEUIMM field in a D form instruction. */
797 #define VLEUIMM VLENSIMM + 1
798 { 0xffff, PPC_OPSHIFT_INV
, insert_vleui
, extract_vleui
, 0 },
800 /* The VLEUIMML field in a D form instruction. */
801 #define VLEUIMML VLEUIMM + 1
802 { 0xffff, PPC_OPSHIFT_INV
, insert_vleil
, extract_vleil
, 0 },
804 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
805 #define XS6 VLEUIMML + 1
807 { 0x3f, PPC_OPSHIFT_INV
, insert_xt6
, extract_xt6
, PPC_OPERAND_VSR
},
809 /* The XA field in an XX3 form instruction. This is split. */
811 { 0x3f, PPC_OPSHIFT_INV
, insert_xa6
, extract_xa6
, PPC_OPERAND_VSR
},
813 /* The XB field in an XX2 or XX3 form instruction. This is split. */
815 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6
, extract_xb6
, PPC_OPERAND_VSR
},
817 /* The XB field in an XX3 form instruction when it must be the same as
818 the XA field in the instruction. This is used in extended mnemonics
819 like xvmovdp. This is split. */
821 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6s
, extract_xb6s
, PPC_OPERAND_FAKE
},
823 /* The XC field in an XX4 form instruction. This is split. */
825 { 0x3f, PPC_OPSHIFT_INV
, insert_xc6
, extract_xc6
, PPC_OPERAND_VSR
},
827 /* The DM or SHW field in an XX3 form instruction. */
830 { 0x3, 8, NULL
, NULL
, 0 },
832 /* The DM field in an extended mnemonic XX3 form instruction. */
834 { 0x3, 8, insert_dm
, extract_dm
, 0 },
836 /* The UIM field in an XX2 form instruction. */
838 /* The 2-bit UIMM field in a VX form instruction. */
840 { 0x3, 16, NULL
, NULL
, 0 },
842 #define ERAT_T UIM + 1
843 { 0x7, 21, NULL
, NULL
, 0 },
846 const unsigned int num_powerpc_operands
= (sizeof (powerpc_operands
)
847 / sizeof (powerpc_operands
[0]));
849 /* The functions used to insert and extract complicated operands. */
851 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
854 insert_arx (unsigned long insn
,
856 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
857 const char **errmsg ATTRIBUTE_UNUSED
)
859 if (value
>= 8 && value
< 24)
860 return insn
| ((value
- 8) & 0xf);
863 *errmsg
= _("invalid register");
869 extract_arx (unsigned long insn
,
870 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
871 int *invalid ATTRIBUTE_UNUSED
)
873 return (insn
& 0xf) + 8;
877 insert_ary (unsigned long insn
,
879 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
880 const char **errmsg ATTRIBUTE_UNUSED
)
882 if (value
>= 8 && value
< 24)
883 return insn
| (((value
- 8) & 0xf) << 4);
886 *errmsg
= _("invalid register");
892 extract_ary (unsigned long insn
,
893 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
894 int *invalid ATTRIBUTE_UNUSED
)
896 return ((insn
>> 4) & 0xf) + 8;
900 insert_rx (unsigned long insn
,
902 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
905 if (value
>= 0 && value
< 8)
907 else if (value
>= 24 && value
<= 31)
908 return insn
| (value
- 16);
911 *errmsg
= _("invalid register");
917 extract_rx (unsigned long insn
,
918 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
919 int *invalid ATTRIBUTE_UNUSED
)
921 int value
= insn
& 0xf;
922 if (value
>= 0 && value
< 8)
929 insert_ry (unsigned long insn
,
931 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
934 if (value
>= 0 && value
< 8)
935 return insn
| (value
<< 4);
936 else if (value
>= 24 && value
<= 31)
937 return insn
| ((value
- 16) << 4);
940 *errmsg
= _("invalid register");
946 extract_ry (unsigned long insn
,
947 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
948 int *invalid ATTRIBUTE_UNUSED
)
950 int value
= (insn
>> 4) & 0xf;
951 if (value
>= 0 && value
< 8)
957 /* The BA field in an XL form instruction when it must be the same as
958 the BT field in the same instruction. This operand is marked FAKE.
959 The insertion function just copies the BT field into the BA field,
960 and the extraction function just checks that the fields are the
964 insert_bat (unsigned long insn
,
965 long value ATTRIBUTE_UNUSED
,
966 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
967 const char **errmsg ATTRIBUTE_UNUSED
)
969 return insn
| (((insn
>> 21) & 0x1f) << 16);
973 extract_bat (unsigned long insn
,
974 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
977 if (((insn
>> 21) & 0x1f) != ((insn
>> 16) & 0x1f))
982 /* The BB field in an XL form instruction when it must be the same as
983 the BA field in the same instruction. This operand is marked FAKE.
984 The insertion function just copies the BA field into the BB field,
985 and the extraction function just checks that the fields are the
989 insert_bba (unsigned long insn
,
990 long value ATTRIBUTE_UNUSED
,
991 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
992 const char **errmsg ATTRIBUTE_UNUSED
)
994 return insn
| (((insn
>> 16) & 0x1f) << 11);
998 extract_bba (unsigned long insn
,
999 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1002 if (((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
1007 /* The BD field in a B form instruction when the - modifier is used.
1008 This modifier means that the branch is not expected to be taken.
1009 For chips built to versions of the architecture prior to version 2
1010 (ie. not Power4 compatible), we set the y bit of the BO field to 1
1011 if the offset is negative. When extracting, we require that the y
1012 bit be 1 and that the offset be positive, since if the y bit is 0
1013 we just want to print the normal form of the instruction.
1014 Power4 compatible targets use two bits, "a", and "t", instead of
1015 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
1016 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
1017 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
1018 for branch on CTR. We only handle the taken/not-taken hint here.
1019 Note that we don't relax the conditions tested here when
1020 disassembling with -Many because insns using extract_bdm and
1021 extract_bdp always occur in pairs. One or the other will always
1024 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1026 static unsigned long
1027 insert_bdm (unsigned long insn
,
1030 const char **errmsg ATTRIBUTE_UNUSED
)
1032 if ((dialect
& ISA_V2
) == 0)
1034 if ((value
& 0x8000) != 0)
1039 if ((insn
& (0x14 << 21)) == (0x04 << 21))
1041 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
1044 return insn
| (value
& 0xfffc);
1048 extract_bdm (unsigned long insn
,
1052 if ((dialect
& ISA_V2
) == 0)
1054 if (((insn
& (1 << 21)) == 0) != ((insn
& (1 << 15)) == 0))
1059 if ((insn
& (0x17 << 21)) != (0x06 << 21)
1060 && (insn
& (0x1d << 21)) != (0x18 << 21))
1064 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1067 /* The BD field in a B form instruction when the + modifier is used.
1068 This is like BDM, above, except that the branch is expected to be
1071 static unsigned long
1072 insert_bdp (unsigned long insn
,
1075 const char **errmsg ATTRIBUTE_UNUSED
)
1077 if ((dialect
& ISA_V2
) == 0)
1079 if ((value
& 0x8000) == 0)
1084 if ((insn
& (0x14 << 21)) == (0x04 << 21))
1086 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
1089 return insn
| (value
& 0xfffc);
1093 extract_bdp (unsigned long insn
,
1097 if ((dialect
& ISA_V2
) == 0)
1099 if (((insn
& (1 << 21)) == 0) == ((insn
& (1 << 15)) == 0))
1104 if ((insn
& (0x17 << 21)) != (0x07 << 21)
1105 && (insn
& (0x1d << 21)) != (0x19 << 21))
1109 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1113 valid_bo_pre_v2 (long value
)
1115 /* Certain encodings have bits that are required to be zero.
1116 These are (z must be zero, y may be anything):
1127 if ((value
& 0x14) == 0)
1129 else if ((value
& 0x14) == 0x4)
1130 return (value
& 0x2) == 0;
1131 else if ((value
& 0x14) == 0x10)
1132 return (value
& 0x8) == 0;
1134 return value
== 0x14;
1138 valid_bo_post_v2 (long value
)
1140 /* Certain encodings have bits that are required to be zero.
1141 These are (z must be zero, a & t may be anything):
1152 if ((value
& 0x14) == 0)
1153 return (value
& 0x1) == 0;
1154 else if ((value
& 0x14) == 0x14)
1155 return value
== 0x14;
1160 /* Check for legal values of a BO field. */
1163 valid_bo (long value
, ppc_cpu_t dialect
, int extract
)
1165 int valid_y
= valid_bo_pre_v2 (value
);
1166 int valid_at
= valid_bo_post_v2 (value
);
1168 /* When disassembling with -Many, accept either encoding on the
1169 second pass through opcodes. */
1170 if (extract
&& dialect
== ~(ppc_cpu_t
) PPC_OPCODE_ANY
)
1171 return valid_y
|| valid_at
;
1172 if ((dialect
& ISA_V2
) == 0)
1178 /* The BO field in a B form instruction. Warn about attempts to set
1179 the field to an illegal value. */
1181 static unsigned long
1182 insert_bo (unsigned long insn
,
1185 const char **errmsg
)
1187 if (!valid_bo (value
, dialect
, 0))
1188 *errmsg
= _("invalid conditional option");
1189 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
1190 *errmsg
= _("invalid counter access");
1191 return insn
| ((value
& 0x1f) << 21);
1195 extract_bo (unsigned long insn
,
1201 value
= (insn
>> 21) & 0x1f;
1202 if (!valid_bo (value
, dialect
, 1))
1207 /* The BO field in a B form instruction when the + or - modifier is
1208 used. This is like the BO field, but it must be even. When
1209 extracting it, we force it to be even. */
1211 static unsigned long
1212 insert_boe (unsigned long insn
,
1215 const char **errmsg
)
1217 if (!valid_bo (value
, dialect
, 0))
1218 *errmsg
= _("invalid conditional option");
1219 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
1220 *errmsg
= _("invalid counter access");
1221 else if ((value
& 1) != 0)
1222 *errmsg
= _("attempt to set y bit when using + or - modifier");
1224 return insn
| ((value
& 0x1f) << 21);
1228 extract_boe (unsigned long insn
,
1234 value
= (insn
>> 21) & 0x1f;
1235 if (!valid_bo (value
, dialect
, 1))
1237 return value
& 0x1e;
1240 /* FXM mask in mfcr and mtcrf instructions. */
1242 static unsigned long
1243 insert_fxm (unsigned long insn
,
1246 const char **errmsg
)
1248 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1249 one bit of the mask field is set. */
1250 if ((insn
& (1 << 20)) != 0)
1252 if (value
== 0 || (value
& -value
) != value
)
1254 *errmsg
= _("invalid mask field");
1259 /* If the optional field on mfcr is missing that means we want to use
1260 the old form of the instruction that moves the whole cr. In that
1261 case we'll have VALUE zero. There doesn't seem to be a way to
1262 distinguish this from the case where someone writes mfcr %r3,0. */
1263 else if (value
== 0)
1266 /* If only one bit of the FXM field is set, we can use the new form
1267 of the instruction, which is faster. Unlike the Power4 branch hint
1268 encoding, this is not backward compatible. Do not generate the
1269 new form unless -mpower4 has been given, or -many and the two
1270 operand form of mfcr was used. */
1271 else if ((value
& -value
) == value
1272 && ((dialect
& PPC_OPCODE_POWER4
) != 0
1273 || ((dialect
& PPC_OPCODE_ANY
) != 0
1274 && (insn
& (0x3ff << 1)) == 19 << 1)))
1277 /* Any other value on mfcr is an error. */
1278 else if ((insn
& (0x3ff << 1)) == 19 << 1)
1280 *errmsg
= _("ignoring invalid mfcr mask");
1284 return insn
| ((value
& 0xff) << 12);
1288 extract_fxm (unsigned long insn
,
1289 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1292 long mask
= (insn
>> 12) & 0xff;
1294 /* Is this a Power4 insn? */
1295 if ((insn
& (1 << 20)) != 0)
1297 /* Exactly one bit of MASK should be set. */
1298 if (mask
== 0 || (mask
& -mask
) != mask
)
1302 /* Check that non-power4 form of mfcr has a zero MASK. */
1303 else if ((insn
& (0x3ff << 1)) == 19 << 1)
1312 static unsigned long
1313 insert_li20 (unsigned long insn
,
1315 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1316 const char **errmsg ATTRIBUTE_UNUSED
)
1318 return insn
| ((value
& 0xf0000) >> 5) | ((value
& 0x0f800) << 5) | (value
& 0x7ff);
1322 extract_li20 (unsigned long insn
,
1323 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1324 int *invalid ATTRIBUTE_UNUSED
)
1326 long ext
= ((insn
& 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1329 | (((insn
>> 11) & 0xf) << 16)
1330 | (((insn
>> 17) & 0xf) << 12)
1331 | (((insn
>> 16) & 0x1) << 11)
1335 /* The LS field in a sync instruction that accepts 2 operands
1336 Values 2 and 3 are reserved,
1337 must be treated as 0 for future compatibility
1338 Values 0 and 1 can be accepted, if field ESYNC is zero
1339 Otherwise L = complement of ESYNC-bit2 (1<<18) */
1341 static unsigned long
1342 insert_ls (unsigned long insn
,
1344 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1345 const char **errmsg ATTRIBUTE_UNUSED
)
1349 ls
= (insn
>> 21) & 0x03;
1353 return insn
& ~(0x3 << 21);
1356 if ((value
& 0x2) != 0)
1357 return (insn
& ~(0x3 << 21)) | ((value
& 0xf) << 16);
1358 return (insn
& ~(0x3 << 21)) | (0x1 << 21) | ((value
& 0xf) << 16);
1361 /* The MB and ME fields in an M form instruction expressed as a single
1362 operand which is itself a bitmask. The extraction function always
1363 marks it as invalid, since we never want to recognize an
1364 instruction which uses a field of this type. */
1366 static unsigned long
1367 insert_mbe (unsigned long insn
,
1369 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1370 const char **errmsg
)
1372 unsigned long uval
, mask
;
1373 int mb
, me
, mx
, count
, last
;
1379 *errmsg
= _("illegal bitmask");
1385 if ((uval
& 1) != 0)
1391 /* mb: location of last 0->1 transition */
1392 /* me: location of last 1->0 transition */
1393 /* count: # transitions */
1395 for (mx
= 0, mask
= 1L << 31; mx
< 32; ++mx
, mask
>>= 1)
1397 if ((uval
& mask
) && !last
)
1403 else if (!(uval
& mask
) && last
)
1413 if (count
!= 2 && (count
!= 0 || ! last
))
1414 *errmsg
= _("illegal bitmask");
1416 return insn
| (mb
<< 6) | ((me
- 1) << 1);
1420 extract_mbe (unsigned long insn
,
1421 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1430 mb
= (insn
>> 6) & 0x1f;
1431 me
= (insn
>> 1) & 0x1f;
1435 for (i
= mb
; i
<= me
; i
++)
1436 ret
|= 1L << (31 - i
);
1438 else if (mb
== me
+ 1)
1440 else /* (mb > me + 1) */
1443 for (i
= me
+ 1; i
< mb
; i
++)
1444 ret
&= ~(1L << (31 - i
));
1449 /* The MB or ME field in an MD or MDS form instruction. The high bit
1450 is wrapped to the low end. */
1452 static unsigned long
1453 insert_mb6 (unsigned long insn
,
1455 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1456 const char **errmsg ATTRIBUTE_UNUSED
)
1458 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
1462 extract_mb6 (unsigned long insn
,
1463 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1464 int *invalid ATTRIBUTE_UNUSED
)
1466 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
1469 /* The NB field in an X form instruction. The value 32 is stored as
1473 extract_nb (unsigned long insn
,
1474 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1475 int *invalid ATTRIBUTE_UNUSED
)
1479 ret
= (insn
>> 11) & 0x1f;
1485 /* The NB field in an lswi instruction, which has special value
1486 restrictions. The value 32 is stored as 0. */
1488 static unsigned long
1489 insert_nbi (unsigned long insn
,
1491 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1492 const char **errmsg ATTRIBUTE_UNUSED
)
1494 long rtvalue
= (insn
& RT_MASK
) >> 21;
1495 long ravalue
= (insn
& RA_MASK
) >> 16;
1499 if (rtvalue
+ (value
+ 3) / 4 > (rtvalue
> ravalue
? ravalue
+ 32
1501 *errmsg
= _("address register in load range");
1502 return insn
| ((value
& 0x1f) << 11);
1505 /* The NSI field in a D form instruction. This is the same as the SI
1506 field, only negated. The extraction function always marks it as
1507 invalid, since we never want to recognize an instruction which uses
1508 a field of this type. */
1510 static unsigned long
1511 insert_nsi (unsigned long insn
,
1513 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1514 const char **errmsg ATTRIBUTE_UNUSED
)
1516 return insn
| (-value
& 0xffff);
1520 extract_nsi (unsigned long insn
,
1521 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1525 return -(((insn
& 0xffff) ^ 0x8000) - 0x8000);
1528 /* The RA field in a D or X form instruction which is an updating
1529 load, which means that the RA field may not be zero and may not
1530 equal the RT field. */
1532 static unsigned long
1533 insert_ral (unsigned long insn
,
1535 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1536 const char **errmsg
)
1539 || (unsigned long) value
== ((insn
>> 21) & 0x1f))
1540 *errmsg
= "invalid register operand when updating";
1541 return insn
| ((value
& 0x1f) << 16);
1544 /* The RA field in an lmw instruction, which has special value
1547 static unsigned long
1548 insert_ram (unsigned long insn
,
1550 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1551 const char **errmsg
)
1553 if ((unsigned long) value
>= ((insn
>> 21) & 0x1f))
1554 *errmsg
= _("index register in load range");
1555 return insn
| ((value
& 0x1f) << 16);
1558 /* The RA field in the DQ form lq or an lswx instruction, which have special
1559 value restrictions. */
1561 static unsigned long
1562 insert_raq (unsigned long insn
,
1564 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1565 const char **errmsg
)
1567 long rtvalue
= (insn
& RT_MASK
) >> 21;
1569 if (value
== rtvalue
)
1570 *errmsg
= _("source and target register operands must be different");
1571 return insn
| ((value
& 0x1f) << 16);
1574 /* The RA field in a D or X form instruction which is an updating
1575 store or an updating floating point load, which means that the RA
1576 field may not be zero. */
1578 static unsigned long
1579 insert_ras (unsigned long insn
,
1581 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1582 const char **errmsg
)
1585 *errmsg
= _("invalid register operand when updating");
1586 return insn
| ((value
& 0x1f) << 16);
1589 /* The RB field in an X form instruction when it must be the same as
1590 the RS field in the instruction. This is used for extended
1591 mnemonics like mr. This operand is marked FAKE. The insertion
1592 function just copies the BT field into the BA field, and the
1593 extraction function just checks that the fields are the same. */
1595 static unsigned long
1596 insert_rbs (unsigned long insn
,
1597 long value ATTRIBUTE_UNUSED
,
1598 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1599 const char **errmsg ATTRIBUTE_UNUSED
)
1601 return insn
| (((insn
>> 21) & 0x1f) << 11);
1605 extract_rbs (unsigned long insn
,
1606 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1609 if (((insn
>> 21) & 0x1f) != ((insn
>> 11) & 0x1f))
1614 /* The RB field in an lswx instruction, which has special value
1617 static unsigned long
1618 insert_rbx (unsigned long insn
,
1620 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1621 const char **errmsg
)
1623 long rtvalue
= (insn
& RT_MASK
) >> 21;
1625 if (value
== rtvalue
)
1626 *errmsg
= _("source and target register operands must be different");
1627 return insn
| ((value
& 0x1f) << 11);
1630 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1631 static unsigned long
1632 insert_sci8 (unsigned long insn
,
1634 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1635 const char **errmsg
)
1638 int scale_factor
= 0;
1641 if ((value
& 0xff000000) == (unsigned int) value
)
1647 else if ((value
& 0xff0000) == (unsigned int) value
)
1653 else if ((value
& 0xff00) == (unsigned int) value
)
1659 else if ((value
& 0xff) == value
)
1665 else if ((value
& 0xffffff00) == 0xffffff00)
1668 ui8
= (value
& 0xff);
1671 else if ((value
& 0xffff00ff) == 0xffff00ff)
1674 ui8
= (value
& 0xff00) >> 8;
1677 else if ((value
& 0xff00ffff) == 0xff00ffff)
1680 ui8
= (value
& 0xff0000) >> 16;
1683 else if ((value
& 0x00ffffff) == 0x00ffffff)
1686 ui8
= (value
& 0xff000000) >> 24;
1690 *errmsg
= _("illegal immediate value");
1692 return insn
| (fill
<< 10) | (scale_factor
<< 8) | (ui8
& 0xff);
1696 extract_sci8 (unsigned long insn
,
1697 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1698 int *invalid ATTRIBUTE_UNUSED
)
1700 int scale_factor
, fill
;
1701 scale_factor
= (insn
& 0x300) >> 8;
1702 fill
= (insn
& 0x00000400) >> 10;
1705 return (insn
& 0xff) << (scale_factor
<< 3);
1708 if (scale_factor
== 0)
1709 return (insn
& 0xff) | 0xffffff00;
1710 else if (scale_factor
== 1)
1711 return 0xffff00ff | ((insn
& 0xff) << (scale_factor
<< 3));
1712 else if (scale_factor
== 2)
1713 return 0xff00ffff | (insn
& 0xff << (scale_factor
<< 3));
1714 else /* scale_factor 3 */
1715 return 0x00ffffff | (insn
& 0xff << (scale_factor
<< 3));
1718 static unsigned long
1719 insert_sci8n (unsigned long insn
,
1721 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1722 const char **errmsg
)
1724 insn
= insert_sci8 (insn
, -(value
& 0xff) & 0xff, 0, errmsg
);
1725 /* Set the F bit. */
1726 return insn
| 0x400;
1730 extract_sci8n (unsigned long insn
,
1731 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1732 int *invalid ATTRIBUTE_UNUSED
)
1735 scale_factor
= (insn
& 0x300) >> 8;
1736 return -(((insn
& 0xff) ^ 0x80) - 0x80) << (scale_factor
<< 3);
1739 static unsigned long
1740 insert_sd4h (unsigned long insn
,
1742 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1743 const char **errmsg ATTRIBUTE_UNUSED
)
1745 return insn
| ((value
& 0x1e) << 7);
1749 extract_sd4h (unsigned long insn
,
1750 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1751 int *invalid ATTRIBUTE_UNUSED
)
1753 return ((insn
>> 8) & 0xf) << 1;
1756 static unsigned long
1757 insert_sd4w (unsigned long insn
,
1759 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1760 const char **errmsg ATTRIBUTE_UNUSED
)
1762 return insn
| ((value
& 0x3c) << 6);
1766 extract_sd4w (unsigned long insn
,
1767 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1768 int *invalid ATTRIBUTE_UNUSED
)
1770 return ((insn
>> 8) & 0xf) << 2;
1773 static unsigned long
1774 insert_oimm (unsigned long insn
,
1776 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1777 const char **errmsg ATTRIBUTE_UNUSED
)
1779 return insn
| (((value
- 1) & 0x1f) << 4);
1783 extract_oimm (unsigned long insn
,
1784 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1785 int *invalid ATTRIBUTE_UNUSED
)
1787 return ((insn
>> 4) & 0x1f) + 1;
1790 /* The SH field in an MD form instruction. This is split. */
1792 static unsigned long
1793 insert_sh6 (unsigned long insn
,
1795 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1796 const char **errmsg ATTRIBUTE_UNUSED
)
1798 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1802 extract_sh6 (unsigned long insn
,
1803 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1804 int *invalid ATTRIBUTE_UNUSED
)
1806 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
1809 /* The SPR field in an XFX form instruction. This is flipped--the
1810 lower 5 bits are stored in the upper 5 and vice- versa. */
1812 static unsigned long
1813 insert_spr (unsigned long insn
,
1815 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1816 const char **errmsg ATTRIBUTE_UNUSED
)
1818 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1822 extract_spr (unsigned long insn
,
1823 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1824 int *invalid ATTRIBUTE_UNUSED
)
1826 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1829 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1830 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE)
1832 static unsigned long
1833 insert_sprg (unsigned long insn
,
1836 const char **errmsg
)
1839 || (value
> 3 && (dialect
& ALLOW8_SPRG
) == 0))
1840 *errmsg
= _("invalid sprg number");
1842 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1843 user mode. Anything else must use spr 272..279. */
1844 if (value
<= 3 || (insn
& 0x100) != 0)
1847 return insn
| ((value
& 0x17) << 16);
1851 extract_sprg (unsigned long insn
,
1855 unsigned long val
= (insn
>> 16) & 0x1f;
1857 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1858 If not BOOKE, 405 or VLE, then both use only 272..275. */
1859 if ((val
- 0x10 > 3 && (dialect
& ALLOW8_SPRG
) == 0)
1860 || (val
- 0x10 > 7 && (insn
& 0x100) != 0)
1867 /* The TBR field in an XFX instruction. This is just like SPR, but it
1868 is optional. When TBR is omitted, it must be inserted as 268 (the
1869 magic number of the TB register). These functions treat 0
1870 (indicating an omitted optional operand) as 268. This means that
1871 ``mftb 4,0'' is not handled correctly. This does not matter very
1872 much, since the architecture manual does not define mftb as
1873 accepting any values other than 268 or 269. */
1877 static unsigned long
1878 insert_tbr (unsigned long insn
,
1880 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1881 const char **errmsg ATTRIBUTE_UNUSED
)
1885 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1889 extract_tbr (unsigned long insn
,
1890 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1891 int *invalid ATTRIBUTE_UNUSED
)
1895 ret
= ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1901 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
1903 static unsigned long
1904 insert_xt6 (unsigned long insn
,
1906 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1907 const char **errmsg ATTRIBUTE_UNUSED
)
1909 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) >> 5);
1913 extract_xt6 (unsigned long insn
,
1914 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1915 int *invalid ATTRIBUTE_UNUSED
)
1917 return ((insn
<< 5) & 0x20) | ((insn
>> 21) & 0x1f);
1920 /* The XA field in an XX3 form instruction. This is split. */
1922 static unsigned long
1923 insert_xa6 (unsigned long insn
,
1925 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1926 const char **errmsg ATTRIBUTE_UNUSED
)
1928 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x20) >> 3);
1932 extract_xa6 (unsigned long insn
,
1933 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1934 int *invalid ATTRIBUTE_UNUSED
)
1936 return ((insn
<< 3) & 0x20) | ((insn
>> 16) & 0x1f);
1939 /* The XB field in an XX3 form instruction. This is split. */
1941 static unsigned long
1942 insert_xb6 (unsigned long insn
,
1944 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1945 const char **errmsg ATTRIBUTE_UNUSED
)
1947 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1951 extract_xb6 (unsigned long insn
,
1952 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1953 int *invalid ATTRIBUTE_UNUSED
)
1955 return ((insn
<< 4) & 0x20) | ((insn
>> 11) & 0x1f);
1958 /* The XB field in an XX3 form instruction when it must be the same as
1959 the XA field in the instruction. This is used for extended
1960 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
1961 function just copies the XA field into the XB field, and the
1962 extraction function just checks that the fields are the same. */
1964 static unsigned long
1965 insert_xb6s (unsigned long insn
,
1966 long value ATTRIBUTE_UNUSED
,
1967 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1968 const char **errmsg ATTRIBUTE_UNUSED
)
1970 return insn
| (((insn
>> 16) & 0x1f) << 11) | (((insn
>> 2) & 0x1) << 1);
1974 extract_xb6s (unsigned long insn
,
1975 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1978 if ((((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
1979 || (((insn
>> 2) & 0x1) != ((insn
>> 1) & 0x1)))
1984 /* The XC field in an XX4 form instruction. This is split. */
1986 static unsigned long
1987 insert_xc6 (unsigned long insn
,
1989 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1990 const char **errmsg ATTRIBUTE_UNUSED
)
1992 return insn
| ((value
& 0x1f) << 6) | ((value
& 0x20) >> 2);
1996 extract_xc6 (unsigned long insn
,
1997 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1998 int *invalid ATTRIBUTE_UNUSED
)
2000 return ((insn
<< 2) & 0x20) | ((insn
>> 6) & 0x1f);
2003 static unsigned long
2004 insert_dm (unsigned long insn
,
2006 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2007 const char **errmsg
)
2009 if (value
!= 0 && value
!= 1)
2010 *errmsg
= _("invalid constant");
2011 return insn
| (((value
) ? 3 : 0) << 8);
2015 extract_dm (unsigned long insn
,
2016 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2021 value
= (insn
>> 8) & 3;
2022 if (value
!= 0 && value
!= 3)
2024 return (value
) ? 1 : 0;
2026 /* The VLESIMM field in an I16A form instruction. This is split. */
2028 static unsigned long
2029 insert_vlesi (unsigned long insn
,
2031 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2032 const char **errmsg ATTRIBUTE_UNUSED
)
2034 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2038 extract_vlesi (unsigned long insn
,
2039 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2040 int *invalid ATTRIBUTE_UNUSED
)
2042 /* RWRW Because I don't know how to make int be 16 and long be 32 */
2043 /* I can't rely on casting an int to long to get sign extension. */
2044 long value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2046 value
|= 0xffff0000;
2050 static unsigned long
2051 insert_vlensi (unsigned long insn
,
2053 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2054 const char **errmsg ATTRIBUTE_UNUSED
)
2057 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2060 extract_vlensi (unsigned long insn
,
2061 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2062 int *invalid ATTRIBUTE_UNUSED
)
2064 long value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2066 value
|= 0xffff0000;
2071 /* The VLEUIMM field in an I16A form instruction. This is split. */
2073 static unsigned long
2074 insert_vleui (unsigned long insn
,
2076 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2077 const char **errmsg ATTRIBUTE_UNUSED
)
2079 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2083 extract_vleui (unsigned long insn
,
2084 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2085 int *invalid ATTRIBUTE_UNUSED
)
2087 return ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2090 /* The VLEUIMML field in an I16L form instruction. This is split. */
2092 static unsigned long
2093 insert_vleil (unsigned long insn
,
2095 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2096 const char **errmsg ATTRIBUTE_UNUSED
)
2098 return insn
| ((value
& 0xf800) << 5) | (value
& 0x7ff);
2102 extract_vleil (unsigned long insn
,
2103 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2104 int *invalid ATTRIBUTE_UNUSED
)
2106 return ((insn
>> 5) & 0xf800) | (insn
& 0x7ff);
2110 /* Macros used to form opcodes. */
2112 /* The main opcode. */
2113 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2114 #define OP_MASK OP (0x3f)
2116 /* The main opcode combined with a trap code in the TO field of a D
2117 form instruction. Used for extended mnemonics for the trap
2119 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2120 #define OPTO_MASK (OP_MASK | TO_MASK)
2122 /* The main opcode combined with a comparison size bit in the L field
2123 of a D form or X form instruction. Used for extended mnemonics for
2124 the comparison instructions. */
2125 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2126 #define OPL_MASK OPL (0x3f,1)
2128 /* The main opcode combined with an update code in D form instruction.
2129 Used for extended mnemonics for VLE memory instructions. */
2130 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2131 #define OPVUP_MASK OPVUP (0x3f, 0xff)
2133 /* An A form instruction. */
2134 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2135 #define A_MASK A (0x3f, 0x1f, 1)
2137 /* An A_MASK with the FRB field fixed. */
2138 #define AFRB_MASK (A_MASK | FRB_MASK)
2140 /* An A_MASK with the FRC field fixed. */
2141 #define AFRC_MASK (A_MASK | FRC_MASK)
2143 /* An A_MASK with the FRA and FRC fields fixed. */
2144 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2146 /* An AFRAFRC_MASK, but with L bit clear. */
2147 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2149 /* A B form instruction. */
2150 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2151 #define B_MASK B (0x3f, 1, 1)
2153 /* A BD8 form instruction. This is a 16-bit instruction. */
2154 #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2155 #define BD8_MASK BD8 (0x3f, 1, 1)
2157 /* Another BD8 form instruction. This is a 16-bit instruction. */
2158 #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2159 #define BD8IO_MASK BD8IO (0x1f)
2161 /* A BD8 form instruction for simplified mnemonics. */
2162 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2163 /* A mask that excludes BO32 and BI32. */
2164 #define EBD8IO1_MASK 0xf800
2165 /* A mask that includes BO32 and excludes BI32. */
2166 #define EBD8IO2_MASK 0xfc00
2167 /* A mask that include BO32 AND BI32. */
2168 #define EBD8IO3_MASK 0xff00
2170 /* A BD15 form instruction. */
2171 #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2172 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2174 /* A BD15 form instruction for extended conditional branch mnemonics. */
2175 #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2176 #define EBD15_MASK 0xfff00001
2178 /* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2179 #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2180 | (((aa) & 0xf) << 22) \
2181 | (((bo) & 0x3) << 20) \
2182 | (((bi) & 0x3) << 16) \
2184 #define EBD15BI_MASK 0xfff30001
2186 /* A BD24 form instruction. */
2187 #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2188 #define BD24_MASK BD24 (0x3f, 1, 1)
2190 /* A B form instruction setting the BO field. */
2191 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2192 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2194 /* A BBO_MASK with the y bit of the BO field removed. This permits
2195 matching a conditional branch regardless of the setting of the y
2196 bit. Similarly for the 'at' bits used for power4 branch hints. */
2197 #define Y_MASK (((unsigned long) 1) << 21)
2198 #define AT1_MASK (((unsigned long) 3) << 21)
2199 #define AT2_MASK (((unsigned long) 9) << 21)
2200 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
2201 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2203 /* A B form instruction setting the BO field and the condition bits of
2205 #define BBOCB(op, bo, cb, aa, lk) \
2206 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2207 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2209 /* A BBOCB_MASK with the y bit of the BO field removed. */
2210 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2211 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2212 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2214 /* A BBOYCB_MASK in which the BI field is fixed. */
2215 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2216 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2218 /* A VLE C form instruction. */
2219 #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2220 #define C_LK_MASK C_LK(0x7fff, 1)
2221 #define C(x) ((((unsigned long)(x)) & 0xffff))
2222 #define C_MASK C(0xffff)
2224 /* An Context form instruction. */
2225 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
2226 #define CTX_MASK CTX(0x3f, 0x7)
2228 /* An User Context form instruction. */
2229 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2230 #define UCTX_MASK UCTX(0x3f, 0x1f)
2232 /* The main opcode mask with the RA field clear. */
2233 #define DRA_MASK (OP_MASK | RA_MASK)
2235 /* A DS form instruction. */
2236 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2237 #define DS_MASK DSO (0x3f, 3)
2239 /* An EVSEL form instruction. */
2240 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2241 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2243 /* An IA16 form instruction. */
2244 #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2245 #define IA16_MASK IA16(0x3f, 0x1f)
2247 /* An I16A form instruction. */
2248 #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2249 #define I16A_MASK I16A(0x3f, 0x1f)
2251 /* An I16L form instruction. */
2252 #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2253 #define I16L_MASK I16L(0x3f, 0x1f)
2255 /* An IM7 form instruction. */
2256 #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2257 #define IM7_MASK IM7(0x1f)
2259 /* An M form instruction. */
2260 #define M(op, rc) (OP (op) | ((rc) & 1))
2261 #define M_MASK M (0x3f, 1)
2263 /* An LI20 form instruction. */
2264 #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2265 #define LI20_MASK LI20(0x3f, 0x1)
2267 /* An M form instruction with the ME field specified. */
2268 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2270 /* An M_MASK with the MB and ME fields fixed. */
2271 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2273 /* An M_MASK with the SH and ME fields fixed. */
2274 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2276 /* An MD form instruction. */
2277 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2278 #define MD_MASK MD (0x3f, 0x7, 1)
2280 /* An MD_MASK with the MB field fixed. */
2281 #define MDMB_MASK (MD_MASK | MB6_MASK)
2283 /* An MD_MASK with the SH field fixed. */
2284 #define MDSH_MASK (MD_MASK | SH6_MASK)
2286 /* An MDS form instruction. */
2287 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2288 #define MDS_MASK MDS (0x3f, 0xf, 1)
2290 /* An MDS_MASK with the MB field fixed. */
2291 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2293 /* An SC form instruction. */
2294 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2295 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2297 /* An SCI8 form instruction. */
2298 #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2299 #define SCI8_MASK SCI8(0x3f, 0x1f)
2301 /* An SCI8 form instruction. */
2302 #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2303 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2305 /* An SD4 form instruction. This is a 16-bit instruction. */
2306 #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2307 #define SD4_MASK SD4(0xf)
2309 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
2310 #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2311 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2313 /* An SE_R form instruction. This is a 16-bit instruction. */
2314 #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2315 #define SE_R_MASK SE_R(0x3f, 0x3f)
2317 /* An SE_RR form instruction. This is a 16-bit instruction. */
2318 #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2319 #define SE_RR_MASK SE_RR(0x3f, 3)
2321 /* A VX form instruction. */
2322 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2324 /* The mask for an VX form instruction. */
2325 #define VX_MASK VX(0x3f, 0x7ff)
2327 /* A VX_MASK with the VA field fixed. */
2328 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2330 /* A VX_MASK with the VB field fixed. */
2331 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2333 /* A VX_MASK with the VA and VB fields fixed. */
2334 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2336 /* A VX_MASK with the VD and VA fields fixed. */
2337 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2339 /* A VX_MASK with a UIMM4 field. */
2340 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2342 /* A VX_MASK with a UIMM3 field. */
2343 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2345 /* A VX_MASK with a UIMM2 field. */
2346 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2348 /* A VA form instruction. */
2349 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
2351 /* The mask for an VA form instruction. */
2352 #define VXA_MASK VXA(0x3f, 0x3f)
2354 /* A VXA_MASK with a SHB field. */
2355 #define VXASHB_MASK (VXA_MASK | (1 << 10))
2357 /* A VXR form instruction. */
2358 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2360 /* The mask for a VXR form instruction. */
2361 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
2363 /* An X form instruction. */
2364 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2366 /* An EX form instruction. */
2367 #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2369 /* The mask for an EX form instruction. */
2370 #define EX_MASK EX (0x3f, 0x7ff)
2372 /* An XX2 form instruction. */
2373 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2375 /* An XX3 form instruction. */
2376 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2378 /* An XX3 form instruction with the RC bit specified. */
2379 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2381 /* An XX4 form instruction. */
2382 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2384 /* A Z form instruction. */
2385 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2387 /* An X form instruction with the RC bit specified. */
2388 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2390 /* A Z form instruction with the RC bit specified. */
2391 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2393 /* The mask for an X form instruction. */
2394 #define X_MASK XRC (0x3f, 0x3ff, 1)
2396 /* An X form wait instruction with everything filled in except the WC field. */
2397 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2399 /* The mask for an XX1 form instruction. */
2400 #define XX1_MASK X (0x3f, 0x3ff)
2402 /* The mask for an XX2 form instruction. */
2403 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2405 /* The mask for an XX2 form instruction with the UIM bits specified. */
2406 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2408 /* The mask for an XX2 form instruction with the BF bits specified. */
2409 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2411 /* The mask for an XX3 form instruction. */
2412 #define XX3_MASK XX3 (0x3f, 0xff)
2414 /* The mask for an XX3 form instruction with the BF bits specified. */
2415 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2417 /* The mask for an XX3 form instruction with the DM or SHW bits specified. */
2418 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2419 #define XX3SHW_MASK XX3DM_MASK
2421 /* The mask for an XX4 form instruction. */
2422 #define XX4_MASK XX4 (0x3f, 0x3)
2424 /* An X form wait instruction with everything filled in except the WC field. */
2425 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2427 /* The mask for a Z form instruction. */
2428 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2429 #define Z2_MASK ZRC (0x3f, 0xff, 1)
2431 /* An X_MASK with the RA field fixed. */
2432 #define XRA_MASK (X_MASK | RA_MASK)
2434 /* An XRA_MASK with the W field clear. */
2435 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2437 /* An X_MASK with the RB field fixed. */
2438 #define XRB_MASK (X_MASK | RB_MASK)
2440 /* An X_MASK with the RT field fixed. */
2441 #define XRT_MASK (X_MASK | RT_MASK)
2443 /* An XRT_MASK mask with the L bits clear. */
2444 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2446 /* An X_MASK with the RA and RB fields fixed. */
2447 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2449 /* An XRARB_MASK, but with the L bit clear. */
2450 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2452 /* An X_MASK with the RT and RA fields fixed. */
2453 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2455 /* An XRTRA_MASK, but with L bit clear. */
2456 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2458 /* An X form instruction with the L bit specified. */
2459 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
2461 /* An X form instruction with the L bits specified. */
2462 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2464 /* An X form instruction with RT fields specified */
2465 #define XRT(op, xop, rt) (X ((op), (xop)) \
2466 | ((((unsigned long)(rt)) & 0x1f) << 21))
2468 /* An X form instruction with RT and RA fields specified */
2469 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2470 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2471 | ((((unsigned long)(ra)) & 0x1f) << 16))
2473 /* The mask for an X form comparison instruction. */
2474 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2476 /* The mask for an X form comparison instruction with the L field
2478 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
2480 /* An X form trap instruction with the TO field specified. */
2481 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2482 #define XTO_MASK (X_MASK | TO_MASK)
2484 /* An X form tlb instruction with the SH field specified. */
2485 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2486 #define XTLB_MASK (X_MASK | SH_MASK)
2488 /* An X form sync instruction. */
2489 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2491 /* An X form sync instruction with everything filled in except the LS field. */
2492 #define XSYNC_MASK (0xff9fffff)
2494 /* An X form sync instruction with everything filled in except the L and E fields. */
2495 #define XSYNCLE_MASK (0xff90ffff)
2497 /* An X_MASK, but with the EH bit clear. */
2498 #define XEH_MASK (X_MASK & ~((unsigned long )1))
2500 /* An X form AltiVec dss instruction. */
2501 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2502 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2504 /* An XFL form instruction. */
2505 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2506 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
2508 /* An X form isel instruction. */
2509 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2510 #define XISEL_MASK XISEL(0x3f, 0x1f)
2512 /* An XL form instruction with the LK field set to 0. */
2513 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2515 /* An XL form instruction which uses the LK field. */
2516 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2518 /* The mask for an XL form instruction. */
2519 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
2521 /* An XL form instruction which explicitly sets the BO field. */
2522 #define XLO(op, bo, xop, lk) \
2523 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2524 #define XLO_MASK (XL_MASK | BO_MASK)
2526 /* An XL form instruction which explicitly sets the y bit of the BO
2528 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2529 #define XLYLK_MASK (XL_MASK | Y_MASK)
2531 /* An XL form instruction which sets the BO field and the condition
2532 bits of the BI field. */
2533 #define XLOCB(op, bo, cb, xop, lk) \
2534 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2535 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2537 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
2538 #define XLBB_MASK (XL_MASK | BB_MASK)
2539 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2540 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2542 /* A mask for branch instructions using the BH field. */
2543 #define XLBH_MASK (XL_MASK | (0x1c << 11))
2545 /* An XL_MASK with the BO and BB fields fixed. */
2546 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2548 /* An XL_MASK with the BO, BI and BB fields fixed. */
2549 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2551 /* An X form mbar instruction with MO field. */
2552 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2554 /* An XO form instruction. */
2555 #define XO(op, xop, oe, rc) \
2556 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2557 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2559 /* An XO_MASK with the RB field fixed. */
2560 #define XORB_MASK (XO_MASK | RB_MASK)
2562 /* An XOPS form instruction for paired singles. */
2563 #define XOPS(op, xop, rc) \
2564 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2565 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2568 /* An XS form instruction. */
2569 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2570 #define XS_MASK XS (0x3f, 0x1ff, 1)
2572 /* A mask for the FXM version of an XFX form instruction. */
2573 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
2575 /* An XFX form instruction with the FXM field filled in. */
2576 #define XFXM(op, xop, fxm, p4) \
2577 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2578 | ((unsigned long)(p4) << 20))
2580 /* An XFX form instruction with the SPR field filled in. */
2581 #define XSPR(op, xop, spr) \
2582 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2583 #define XSPR_MASK (X_MASK | SPR_MASK)
2585 /* An XFX form instruction with the SPR field filled in except for the
2587 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2589 /* An XFX form instruction with the SPR field filled in except for the
2591 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
2593 /* An X form instruction with everything filled in except the E field. */
2594 #define XE_MASK (0xffff7fff)
2596 /* An X form user context instruction. */
2597 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2598 #define XUC_MASK XUC(0x3f, 0x1f)
2600 /* An XW form instruction. */
2601 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2602 /* The mask for a G form instruction. rc not supported at present. */
2603 #define XW_MASK XW (0x3f, 0x3f, 0)
2605 /* An APU form instruction. */
2606 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2608 /* The mask for an APU form instruction. */
2609 #define APU_MASK APU (0x3f, 0x3ff, 1)
2610 #define APU_RT_MASK (APU_MASK | RT_MASK)
2611 #define APU_RA_MASK (APU_MASK | RA_MASK)
2613 /* The BO encodings used in extended conditional branch mnemonics. */
2614 #define BODNZF (0x0)
2615 #define BODNZFP (0x1)
2617 #define BODZFP (0x3)
2618 #define BODNZT (0x8)
2619 #define BODNZTP (0x9)
2621 #define BODZTP (0xb)
2632 #define BODNZ (0x10)
2633 #define BODNZP (0x11)
2635 #define BODZP (0x13)
2636 #define BODNZM4 (0x18)
2637 #define BODNZP4 (0x19)
2638 #define BODZM4 (0x1a)
2639 #define BODZP4 (0x1b)
2643 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
2647 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
2650 #define BO32DNZ (0x2)
2651 #define BO32DZ (0x3)
2653 /* The BI condition bit encodings used in extended conditional branch
2660 /* The TO encodings used in extended trap mnemonics. */
2677 /* Smaller names for the flags so each entry in the opcodes table will
2678 fit on a single line. */
2681 #define PPC PPC_OPCODE_PPC
2682 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2683 #define POWER4 PPC_OPCODE_POWER4
2684 #define POWER5 PPC_OPCODE_POWER5
2685 #define POWER6 PPC_OPCODE_POWER6
2686 #define POWER7 PPC_OPCODE_POWER7
2687 #define CELL PPC_OPCODE_CELL
2688 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
2689 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
2690 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
2691 #define PPC403 PPC_OPCODE_403
2692 #define PPC405 PPC_OPCODE_405
2693 #define PPC440 PPC_OPCODE_440
2694 #define PPC464 PPC440
2695 #define PPC476 PPC_OPCODE_476
2699 #define PPCPS PPC_OPCODE_PPCPS
2700 #define PPCVEC PPC_OPCODE_ALTIVEC
2701 #define PPCVEC2 PPC_OPCODE_ALTIVEC2
2702 #define PPCVSX PPC_OPCODE_VSX
2703 #define POWER PPC_OPCODE_POWER
2704 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
2705 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2706 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2707 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2708 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
2709 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
2710 #define MFDEC1 PPC_OPCODE_POWER
2711 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
2712 #define BOOKE PPC_OPCODE_BOOKE
2713 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS | PPC_OPCODE_VLE
2714 #define PPCE300 PPC_OPCODE_E300
2715 #define PPCSPE PPC_OPCODE_SPE | PPC_OPCODE_VLE
2716 #define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE
2717 #define PPCEFS PPC_OPCODE_EFS | PPC_OPCODE_VLE
2718 #define PPCBRLK PPC_OPCODE_BRLOCK
2719 #define PPCPMR PPC_OPCODE_PMR
2720 #define PPCTMR PPC_OPCODE_TMR
2721 #define PPCCHLK PPC_OPCODE_CACHELCK
2722 #define PPCRFMCI PPC_OPCODE_RFMCI
2723 #define E500MC PPC_OPCODE_E500MC
2724 #define PPCA2 PPC_OPCODE_A2
2725 #define TITAN PPC_OPCODE_TITAN
2726 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
2727 #define E500 PPC_OPCODE_E500
2728 #define E6500 PPC_OPCODE_E6500
2729 #define PPCVLE PPC_OPCODE_VLE
2731 /* The opcode table.
2733 The format of the opcode table is:
2735 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
2737 NAME is the name of the instruction.
2738 OPCODE is the instruction opcode.
2739 MASK is the opcode mask; this is used to tell the disassembler
2740 which bits in the actual opcode must match OPCODE.
2741 FLAGS are flags indicating which processors support the instruction.
2742 ANTI indicates which processors don't support the instruction.
2743 OPERANDS is the list of operands.
2745 The disassembler reads the table in order and prints the first
2746 instruction which matches, so this table is sorted to put more
2747 specific instructions before more general instructions.
2749 This table must be sorted by major opcode. Please try to keep it
2750 vaguely sorted within major opcode too, except of course where
2751 constrained otherwise by disassembler operation. */
2753 const struct powerpc_opcode powerpc_opcodes
[] = {
2754 {"attn", X(0,256), X_MASK
, POWER4
|PPCA2
, PPC476
, {0}},
2755 {"tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2756 {"tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2757 {"tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2758 {"tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2759 {"tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2760 {"tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2761 {"tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2762 {"tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2763 {"tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2764 {"tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2765 {"tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2766 {"tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2767 {"tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2768 {"tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2769 {"tdi", OP(2), OP_MASK
, PPC64
, PPCNONE
, {TO
, RA
, SI
}},
2771 {"twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2772 {"tlgti", OPTO(3,TOLGT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2773 {"twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2774 {"tllti", OPTO(3,TOLLT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2775 {"tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2776 {"teqi", OPTO(3,TOEQ
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2777 {"twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2778 {"tlgei", OPTO(3,TOLGE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2779 {"twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2780 {"tlnli", OPTO(3,TOLNL
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2781 {"twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2782 {"tllei", OPTO(3,TOLLE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2783 {"twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2784 {"tlngi", OPTO(3,TOLNG
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2785 {"twgti", OPTO(3,TOGT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2786 {"tgti", OPTO(3,TOGT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2787 {"twgei", OPTO(3,TOGE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2788 {"tgei", OPTO(3,TOGE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2789 {"twnli", OPTO(3,TONL
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2790 {"tnli", OPTO(3,TONL
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2791 {"twlti", OPTO(3,TOLT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2792 {"tlti", OPTO(3,TOLT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2793 {"twlei", OPTO(3,TOLE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2794 {"tlei", OPTO(3,TOLE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2795 {"twngi", OPTO(3,TONG
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2796 {"tngi", OPTO(3,TONG
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2797 {"twnei", OPTO(3,TONE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2798 {"tnei", OPTO(3,TONE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2799 {"twi", OP(3), OP_MASK
, PPCCOM
, PPCNONE
, {TO
, RA
, SI
}},
2800 {"ti", OP(3), OP_MASK
, PWRCOM
, PPCNONE
, {TO
, RA
, SI
}},
2802 {"ps_cmpu0", X (4, 0), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2803 {"vaddubm", VX (4, 0), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2804 {"vmaxub", VX (4, 2), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2805 {"vrlb", VX (4, 4), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2806 {"vcmpequb", VXR(4, 6,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2807 {"vmuloub", VX (4, 8), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2808 {"vaddfp", VX (4, 10), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2809 {"psq_lx", XW (4, 6,0), XW_MASK
, PPCPS
, PPCNONE
, {FRT
,RA
,RB
,PSWM
,PSQM
}},
2810 {"vmrghb", VX (4, 12), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2811 {"psq_stx", XW (4, 7,0), XW_MASK
, PPCPS
, PPCNONE
, {FRS
,RA
,RB
,PSWM
,PSQM
}},
2812 {"vpkuhum", VX (4, 14), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2813 {"mulhhwu", XRC(4, 8,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2814 {"mulhhwu.", XRC(4, 8,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2815 {"ps_sum0", A (4, 10,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2816 {"ps_sum0.", A (4, 10,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2817 {"ps_sum1", A (4, 11,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2818 {"ps_sum1.", A (4, 11,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2819 {"ps_muls0", A (4, 12,0), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2820 {"machhwu", XO (4, 12,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2821 {"ps_muls0.", A (4, 12,1), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2822 {"machhwu.", XO (4, 12,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2823 {"ps_muls1", A (4, 13,0), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2824 {"ps_muls1.", A (4, 13,1), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2825 {"ps_madds0", A (4, 14,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2826 {"ps_madds0.", A (4, 14,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2827 {"ps_madds1", A (4, 15,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2828 {"ps_madds1.", A (4, 15,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2829 {"vmhaddshs", VXA(4, 32), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2830 {"vmhraddshs", VXA(4, 33), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2831 {"vmladduhm", VXA(4, 34), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2832 {"ps_div", A (4, 18,0), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2833 {"vmsumubm", VXA(4, 36), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2834 {"ps_div.", A (4, 18,1), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2835 {"vmsummbm", VXA(4, 37), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2836 {"vmsumuhm", VXA(4, 38), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2837 {"vmsumuhs", VXA(4, 39), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2838 {"ps_sub", A (4, 20,0), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2839 {"vmsumshm", VXA(4, 40), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2840 {"ps_sub.", A (4, 20,1), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2841 {"vmsumshs", VXA(4, 41), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2842 {"ps_add", A (4, 21,0), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2843 {"vsel", VXA(4, 42), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2844 {"ps_add.", A (4, 21,1), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2845 {"vperm", VXA(4, 43), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2846 {"vsldoi", VXA(4, 44), VXASHB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, SHB
}},
2847 {"ps_sel", A (4, 23,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2848 {"vmaddfp", VXA(4, 46), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VC
, VB
}},
2849 {"ps_sel.", A (4, 23,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2850 {"vnmsubfp", VXA(4, 47), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VC
, VB
}},
2851 {"ps_res", A (4, 24,0), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2852 {"ps_res.", A (4, 24,1), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2853 {"ps_mul", A (4, 25,0), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2854 {"ps_mul.", A (4, 25,1), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2855 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2856 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2857 {"ps_msub", A (4, 28,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2858 {"ps_msub.", A (4, 28,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2859 {"ps_madd", A (4, 29,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2860 {"ps_madd.", A (4, 29,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2861 {"ps_nmsub", A (4, 30,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2862 {"ps_nmsub.", A (4, 30,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2863 {"ps_nmadd", A (4, 31,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2864 {"ps_nmadd.", A (4, 31,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2865 {"ps_cmpo0", X (4, 32), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2866 {"vadduhm", VX (4, 64), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2867 {"vmaxuh", VX (4, 66), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2868 {"vrlh", VX (4, 68), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2869 {"vcmpequh", VXR(4, 70,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2870 {"vmulouh", VX (4, 72), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2871 {"vsubfp", VX (4, 74), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2872 {"psq_lux", XW (4, 38,0), XW_MASK
, PPCPS
, PPCNONE
, {FRT
,RA
,RB
,PSWM
,PSQM
}},
2873 {"vmrghh", VX (4, 76), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2874 {"psq_stux", XW (4, 39,0), XW_MASK
, PPCPS
, PPCNONE
, {FRS
,RA
,RB
,PSWM
,PSQM
}},
2875 {"vpkuwum", VX (4, 78), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2876 {"ps_neg", XRC(4, 40,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2877 {"mulhhw", XRC(4, 40,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2878 {"ps_neg.", XRC(4, 40,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2879 {"mulhhw.", XRC(4, 40,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2880 {"machhw", XO (4, 44,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2881 {"machhw.", XO (4, 44,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2882 {"nmachhw", XO (4, 46,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2883 {"nmachhw.", XO (4, 46,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2884 {"ps_cmpu1", X (4, 64), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2885 {"vadduwm", VX (4, 128), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2886 {"vmaxuw", VX (4, 130), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2887 {"vrlw", VX (4, 132), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2888 {"vcmpequw", VXR(4, 134,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2889 {"vmrghw", VX (4, 140), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2890 {"vpkuhus", VX (4, 142), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2891 {"ps_mr", XRC(4, 72,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2892 {"ps_mr.", XRC(4, 72,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2893 {"machhwsu", XO (4, 76,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2894 {"machhwsu.", XO (4, 76,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2895 {"ps_cmpo1", X (4, 96), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2896 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2897 {"vpkuwus", VX (4, 206), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2898 {"machhws", XO (4, 108,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2899 {"machhws.", XO (4, 108,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2900 {"nmachhws", XO (4, 110,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2901 {"nmachhws.", XO (4, 110,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2902 {"vmaxsb", VX (4, 258), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2903 {"vslb", VX (4, 260), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2904 {"vmulosb", VX (4, 264), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2905 {"vrefp", VX (4, 266), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2906 {"vmrglb", VX (4, 268), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2907 {"vpkshus", VX (4, 270), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2908 {"ps_nabs", XRC(4, 136,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2909 {"mulchwu", XRC(4, 136,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2910 {"ps_nabs.", XRC(4, 136,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2911 {"mulchwu.", XRC(4, 136,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2912 {"macchwu", XO (4, 140,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2913 {"macchwu.", XO (4, 140,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2914 {"vmaxsh", VX (4, 322), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2915 {"vslh", VX (4, 324), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2916 {"vmulosh", VX (4, 328), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2917 {"vrsqrtefp", VX (4, 330), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2918 {"vmrglh", VX (4, 332), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2919 {"vpkswus", VX (4, 334), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2920 {"mulchw", XRC(4, 168,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2921 {"mulchw.", XRC(4, 168,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2922 {"macchw", XO (4, 172,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2923 {"macchw.", XO (4, 172,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2924 {"nmacchw", XO (4, 174,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2925 {"nmacchw.", XO (4, 174,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2926 {"vaddcuw", VX (4, 384), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2927 {"vmaxsw", VX (4, 386), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2928 {"vslw", VX (4, 388), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2929 {"vexptefp", VX (4, 394), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2930 {"vmrglw", VX (4, 396), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2931 {"vpkshss", VX (4, 398), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2932 {"macchwsu", XO (4, 204,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2933 {"macchwsu.", XO (4, 204,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2934 {"vsl", VX (4, 452), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2935 {"vcmpgefp", VXR(4, 454,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2936 {"vlogefp", VX (4, 458), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2937 {"vpkswss", VX (4, 462), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2938 {"macchws", XO (4, 236,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2939 {"macchws.", XO (4, 236,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2940 {"nmacchws", XO (4, 238,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2941 {"nmacchws.", XO (4, 238,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2942 {"evaddw", VX (4, 512), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2943 {"vaddubs", VX (4, 512), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2944 {"evaddiw", VX (4, 514), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
, UIMM
}},
2945 {"vminub", VX (4, 514), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2946 {"evsubfw", VX (4, 516), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2947 {"evsubw", VX (4, 516), VX_MASK
, PPCSPE
, PPCNONE
, {RS
, RB
, RA
}},
2948 {"vsrb", VX (4, 516), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2949 {"evsubifw", VX (4, 518), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, UIMM
, RB
}},
2950 {"evsubiw", VX (4, 518), VX_MASK
, PPCSPE
, PPCNONE
, {RS
, RB
, UIMM
}},
2951 {"vcmpgtub", VXR(4, 518,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2952 {"evabs", VX (4, 520), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2953 {"vmuleub", VX (4, 520), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2954 {"evneg", VX (4, 521), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2955 {"evextsb", VX (4, 522), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2956 {"vrfin", VX (4, 522), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2957 {"evextsh", VX (4, 523), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2958 {"evrndw", VX (4, 524), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2959 {"vspltb", VX (4, 524), VXUIMM4_MASK
,PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM4
}},
2960 {"evcntlzw", VX (4, 525), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2961 {"evcntlsw", VX (4, 526), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2962 {"vupkhsb", VX (4, 526), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2963 {"brinc", VX (4, 527), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2964 {"ps_abs", XRC(4, 264,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2965 {"ps_abs.", XRC(4, 264,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2966 {"evand", VX (4, 529), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2967 {"evandc", VX (4, 530), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2968 {"evxor", VX (4, 534), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2969 {"evmr", VX (4, 535), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, BBA
}},
2970 {"evor", VX (4, 535), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2971 {"evnor", VX (4, 536), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2972 {"evnot", VX (4, 536), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, BBA
}},
2973 {"get", APU(4, 268,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
2974 {"eveqv", VX (4, 537), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2975 {"evorc", VX (4, 539), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2976 {"evnand", VX (4, 542), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2977 {"evsrwu", VX (4, 544), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2978 {"evsrws", VX (4, 545), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2979 {"evsrwiu", VX (4, 546), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
2980 {"evsrwis", VX (4, 547), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
2981 {"evslw", VX (4, 548), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2982 {"evslwi", VX (4, 550), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
2983 {"evrlw", VX (4, 552), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2984 {"evsplati", VX (4, 553), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, SIMM
}},
2985 {"evrlwi", VX (4, 554), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
2986 {"evsplatfi", VX (4, 555), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, SIMM
}},
2987 {"evmergehi", VX (4, 556), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2988 {"evmergelo", VX (4, 557), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2989 {"evmergehilo", VX (4, 558), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2990 {"evmergelohi", VX (4, 559), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2991 {"evcmpgtu", VX (4, 560), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
2992 {"evcmpgts", VX (4, 561), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
2993 {"evcmpltu", VX (4, 562), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
2994 {"evcmplts", VX (4, 563), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
2995 {"evcmpeq", VX (4, 564), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
2996 {"cget", APU(4, 284,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
2997 {"vadduhs", VX (4, 576), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2998 {"vminuh", VX (4, 578), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2999 {"vsrh", VX (4, 580), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3000 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3001 {"vmuleuh", VX (4, 584), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3002 {"vrfiz", VX (4, 586), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3003 {"vsplth", VX (4, 588), VXUIMM3_MASK
,PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM3
}},
3004 {"vupkhsh", VX (4, 590), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3005 {"nget", APU(4, 300,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3006 {"evsel", EVSEL(4,79), EVSEL_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
, CRFS
}},
3007 {"ncget", APU(4, 316,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3008 {"evfsadd", VX (4, 640), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3009 {"vadduws", VX (4, 640), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3010 {"evfssub", VX (4, 641), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3011 {"vminuw", VX (4, 642), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3012 {"evfsabs", VX (4, 644), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3013 {"vsrw", VX (4, 644), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3014 {"evfsnabs", VX (4, 645), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3015 {"evfsneg", VX (4, 646), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3016 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3017 {"evfsmul", VX (4, 648), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3018 {"evfsdiv", VX (4, 649), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3019 {"vrfip", VX (4, 650), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3020 {"evfscmpgt", VX (4, 652), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3021 {"vspltw", VX (4, 652), VXUIMM2_MASK
,PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM2
}},
3022 {"evfscmplt", VX (4, 653), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3023 {"evfscmpeq", VX (4, 654), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3024 {"vupklsb", VX (4, 654), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3025 {"evfscfui", VX (4, 656), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3026 {"evfscfsi", VX (4, 657), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3027 {"evfscfuf", VX (4, 658), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3028 {"evfscfsf", VX (4, 659), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3029 {"evfsctui", VX (4, 660), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3030 {"evfsctsi", VX (4, 661), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3031 {"evfsctuf", VX (4, 662), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3032 {"evfsctsf", VX (4, 663), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3033 {"evfsctuiz", VX (4, 664), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3034 {"put", APU(4, 332,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3035 {"evfsctsiz", VX (4, 666), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3036 {"evfststgt", VX (4, 668), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3037 {"evfststlt", VX (4, 669), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3038 {"evfststeq", VX (4, 670), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3039 {"cput", APU(4, 348,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3040 {"efsadd", VX (4, 704), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3041 {"efssub", VX (4, 705), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3042 {"efsabs", VX (4, 708), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3043 {"vsr", VX (4, 708), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3044 {"efsnabs", VX (4, 709), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3045 {"efsneg", VX (4, 710), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3046 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3047 {"efsmul", VX (4, 712), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3048 {"efsdiv", VX (4, 713), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3049 {"vrfim", VX (4, 714), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3050 {"efscmpgt", VX (4, 716), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3051 {"efscmplt", VX (4, 717), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3052 {"efscmpeq", VX (4, 718), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3053 {"vupklsh", VX (4, 718), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3054 {"efscfd", VX (4, 719), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3055 {"efscfui", VX (4, 720), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3056 {"efscfsi", VX (4, 721), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3057 {"efscfuf", VX (4, 722), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3058 {"efscfsf", VX (4, 723), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3059 {"efsctui", VX (4, 724), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3060 {"efsctsi", VX (4, 725), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3061 {"efsctuf", VX (4, 726), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3062 {"efsctsf", VX (4, 727), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3063 {"efsctuiz", VX (4, 728), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3064 {"nput", APU(4, 364,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3065 {"efsctsiz", VX (4, 730), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3066 {"efststgt", VX (4, 732), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3067 {"efststlt", VX (4, 733), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3068 {"efststeq", VX (4, 734), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3069 {"efdadd", VX (4, 736), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3070 {"efdsub", VX (4, 737), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3071 {"efdcfuid", VX (4, 738), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3072 {"efdcfsid", VX (4, 739), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3073 {"efdabs", VX (4, 740), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3074 {"efdnabs", VX (4, 741), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3075 {"efdneg", VX (4, 742), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3076 {"efdmul", VX (4, 744), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3077 {"efddiv", VX (4, 745), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3078 {"efdctuidz", VX (4, 746), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3079 {"efdctsidz", VX (4, 747), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3080 {"efdcmpgt", VX (4, 748), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3081 {"efdcmplt", VX (4, 749), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3082 {"efdcmpeq", VX (4, 750), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3083 {"efdcfs", VX (4, 751), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3084 {"efdcfui", VX (4, 752), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3085 {"efdcfsi", VX (4, 753), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3086 {"efdcfuf", VX (4, 754), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3087 {"efdcfsf", VX (4, 755), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3088 {"efdctui", VX (4, 756), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3089 {"efdctsi", VX (4, 757), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3090 {"efdctuf", VX (4, 758), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3091 {"efdctsf", VX (4, 759), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3092 {"efdctuiz", VX (4, 760), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3093 {"ncput", APU(4, 380,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3094 {"efdctsiz", VX (4, 762), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3095 {"efdtstgt", VX (4, 764), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3096 {"efdtstlt", VX (4, 765), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3097 {"efdtsteq", VX (4, 766), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3098 {"evlddx", VX (4, 768), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3099 {"vaddsbs", VX (4, 768), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3100 {"evldd", VX (4, 769), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3101 {"evldwx", VX (4, 770), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3102 {"vminsb", VX (4, 770), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3103 {"evldw", VX (4, 771), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3104 {"evldhx", VX (4, 772), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3105 {"vsrab", VX (4, 772), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3106 {"evldh", VX (4, 773), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3107 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3108 {"evlhhesplatx",VX (4, 776), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3109 {"vmulesb", VX (4, 776), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3110 {"evlhhesplat", VX (4, 777), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_2
, RA
}},
3111 {"vcfux", VX (4, 778), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3112 {"vcuxwfp", VX (4, 778), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3113 {"evlhhousplatx",VX(4, 780), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3114 {"vspltisb", VX (4, 780), VXVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, SIMM
}},
3115 {"evlhhousplat",VX (4, 781), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_2
, RA
}},
3116 {"evlhhossplatx",VX(4, 782), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3117 {"vpkpx", VX (4, 782), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3118 {"evlhhossplat",VX (4, 783), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_2
, RA
}},
3119 {"mullhwu", XRC(4, 392,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3120 {"evlwhex", VX (4, 784), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3121 {"mullhwu.", XRC(4, 392,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3122 {"evlwhe", VX (4, 785), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3123 {"evlwhoux", VX (4, 788), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3124 {"evlwhou", VX (4, 789), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3125 {"evlwhosx", VX (4, 790), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3126 {"evlwhos", VX (4, 791), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3127 {"maclhwu", XO (4, 396,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3128 {"evlwwsplatx", VX (4, 792), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3129 {"maclhwu.", XO (4, 396,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3130 {"evlwwsplat", VX (4, 793), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3131 {"evlwhsplatx", VX (4, 796), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3132 {"evlwhsplat", VX (4, 797), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3133 {"evstddx", VX (4, 800), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3134 {"evstdd", VX (4, 801), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3135 {"evstdwx", VX (4, 802), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3136 {"evstdw", VX (4, 803), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3137 {"evstdhx", VX (4, 804), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3138 {"evstdh", VX (4, 805), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3139 {"evstwhex", VX (4, 816), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3140 {"evstwhe", VX (4, 817), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3141 {"evstwhox", VX (4, 820), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3142 {"evstwho", VX (4, 821), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3143 {"evstwwex", VX (4, 824), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3144 {"evstwwe", VX (4, 825), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3145 {"evstwwox", VX (4, 828), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3146 {"evstwwo", VX (4, 829), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3147 {"vaddshs", VX (4, 832), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3148 {"vminsh", VX (4, 834), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3149 {"vsrah", VX (4, 836), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3150 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3151 {"vmulesh", VX (4, 840), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3152 {"vcfsx", VX (4, 842), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3153 {"vcsxwfp", VX (4, 842), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3154 {"vspltish", VX (4, 844), VXVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, SIMM
}},
3155 {"vupkhpx", VX (4, 846), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3156 {"mullhw", XRC(4, 424,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3157 {"mullhw.", XRC(4, 424,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3158 {"maclhw", XO (4, 428,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3159 {"maclhw.", XO (4, 428,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3160 {"nmaclhw", XO (4, 430,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3161 {"nmaclhw.", XO (4, 430,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3162 {"vaddsws", VX (4, 896), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3163 {"vminsw", VX (4, 898), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3164 {"vsraw", VX (4, 900), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3165 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3166 {"vctuxs", VX (4, 906), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3167 {"vcfpuxws", VX (4, 906), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3168 {"vspltisw", VX (4, 908), VXVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, SIMM
}},
3169 {"maclhwsu", XO (4, 460,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3170 {"maclhwsu.", XO (4, 460,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3171 {"vcmpbfp", VXR(4, 966,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3172 {"vctsxs", VX (4, 970), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3173 {"vcfpsxsw", VX (4, 970), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3174 {"vupklpx", VX (4, 974), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3175 {"maclhws", XO (4, 492,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3176 {"maclhws.", XO (4, 492,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3177 {"nmaclhws", XO (4, 494,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3178 {"nmaclhws.", XO (4, 494,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3179 {"vsububm", VX (4,1024), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3180 {"vavgub", VX (4,1026), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3181 {"vabsdub", VX (4,1027), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3182 {"evmhessf", VX (4,1027), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3183 {"vand", VX (4,1028), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3184 {"vcmpequb.", VXR(4, 6,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3185 {"udi0fcm.", APU(4, 515,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3186 {"udi0fcm", APU(4, 515,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3187 {"evmhossf", VX (4,1031), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3188 {"evmheumi", VX (4,1032), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3189 {"evmhesmi", VX (4,1033), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3190 {"vmaxfp", VX (4,1034), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3191 {"evmhesmf", VX (4,1035), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3192 {"evmhoumi", VX (4,1036), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3193 {"vslo", VX (4,1036), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3194 {"evmhosmi", VX (4,1037), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3195 {"evmhosmf", VX (4,1039), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3196 {"machhwuo", XO (4, 12,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3197 {"machhwuo.", XO (4, 12,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3198 {"ps_merge00", XOPS(4,528,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3199 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3200 {"evmhessfa", VX (4,1059), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3201 {"evmhossfa", VX (4,1063), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3202 {"evmheumia", VX (4,1064), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3203 {"evmhesmia", VX (4,1065), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3204 {"evmhesmfa", VX (4,1067), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3205 {"evmhoumia", VX (4,1068), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3206 {"evmhosmia", VX (4,1069), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3207 {"evmhosmfa", VX (4,1071), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3208 {"vsubuhm", VX (4,1088), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3209 {"vavguh", VX (4,1090), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3210 {"vabsduh", VX (4,1091), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3211 {"vandc", VX (4,1092), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3212 {"vcmpequh.", VXR(4, 70,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3213 {"udi1fcm.", APU(4, 547,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3214 {"udi1fcm", APU(4, 547,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3215 {"evmwhssf", VX (4,1095), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3216 {"evmwlumi", VX (4,1096), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3217 {"vminfp", VX (4,1098), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3218 {"evmwhumi", VX (4,1100), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3219 {"vsro", VX (4,1100), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3220 {"evmwhsmi", VX (4,1101), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3221 {"evmwhsmf", VX (4,1103), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3222 {"evmwssf", VX (4,1107), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3223 {"machhwo", XO (4, 44,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3224 {"evmwumi", VX (4,1112), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3225 {"machhwo.", XO (4, 44,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3226 {"evmwsmi", VX (4,1113), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3227 {"evmwsmf", VX (4,1115), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3228 {"nmachhwo", XO (4, 46,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3229 {"nmachhwo.", XO (4, 46,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3230 {"ps_merge01", XOPS(4,560,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3231 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3232 {"evmwhssfa", VX (4,1127), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3233 {"evmwlumia", VX (4,1128), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3234 {"evmwhumia", VX (4,1132), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3235 {"evmwhsmia", VX (4,1133), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3236 {"evmwhsmfa", VX (4,1135), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3237 {"evmwssfa", VX (4,1139), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3238 {"evmwumia", VX (4,1144), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3239 {"evmwsmia", VX (4,1145), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3240 {"evmwsmfa", VX (4,1147), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3241 {"vsubuwm", VX (4,1152), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3242 {"vavguw", VX (4,1154), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3243 {"vabsduw", VX (4,1155), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3244 {"vmr", VX (4,1156), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VBA
}},
3245 {"vor", VX (4,1156), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3246 {"vcmpequw.", VXR(4, 134,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3247 {"udi2fcm.", APU(4, 579,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3248 {"udi2fcm", APU(4, 579,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3249 {"machhwsuo", XO (4, 76,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3250 {"machhwsuo.", XO (4, 76,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3251 {"ps_merge10", XOPS(4,592,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3252 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3253 {"evaddusiaaw", VX (4,1216), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3254 {"evaddssiaaw", VX (4,1217), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3255 {"evsubfusiaaw",VX (4,1218), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3256 {"evsubfssiaaw",VX (4,1219), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3257 {"evmra", VX (4,1220), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3258 {"vxor", VX (4,1220), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3259 {"evdivws", VX (4,1222), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3260 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3261 {"udi3fcm.", APU(4, 611,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3262 {"udi3fcm", APU(4, 611,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3263 {"evdivwu", VX (4,1223), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3264 {"evaddumiaaw", VX (4,1224), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3265 {"evaddsmiaaw", VX (4,1225), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3266 {"evsubfumiaaw",VX (4,1226), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3267 {"evsubfsmiaaw",VX (4,1227), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3268 {"machhwso", XO (4, 108,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3269 {"machhwso.", XO (4, 108,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3270 {"nmachhwso", XO (4, 110,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3271 {"nmachhwso.", XO (4, 110,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3272 {"ps_merge11", XOPS(4,624,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3273 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3274 {"evmheusiaaw", VX (4,1280), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3275 {"evmhessiaaw", VX (4,1281), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3276 {"vavgsb", VX (4,1282), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3277 {"evmhessfaaw", VX (4,1283), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3278 {"evmhousiaaw", VX (4,1284), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3279 {"vnot", VX (4,1284), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VBA
}},
3280 {"vnor", VX (4,1284), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3281 {"evmhossiaaw", VX (4,1285), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3282 {"udi4fcm.", APU(4, 643,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3283 {"udi4fcm", APU(4, 643,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3284 {"evmhossfaaw", VX (4,1287), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3285 {"evmheumiaaw", VX (4,1288), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3286 {"evmhesmiaaw", VX (4,1289), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3287 {"evmhesmfaaw", VX (4,1291), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3288 {"evmhoumiaaw", VX (4,1292), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3289 {"evmhosmiaaw", VX (4,1293), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3290 {"evmhosmfaaw", VX (4,1295), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3291 {"macchwuo", XO (4, 140,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3292 {"macchwuo.", XO (4, 140,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3293 {"evmhegumiaa", VX (4,1320), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3294 {"evmhegsmiaa", VX (4,1321), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3295 {"evmhegsmfaa", VX (4,1323), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3296 {"evmhogumiaa", VX (4,1324), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3297 {"evmhogsmiaa", VX (4,1325), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3298 {"evmhogsmfaa", VX (4,1327), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3299 {"evmwlusiaaw", VX (4,1344), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3300 {"evmwlssiaaw", VX (4,1345), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3301 {"vavgsh", VX (4,1346), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3302 {"udi5fcm.", APU(4, 675,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3303 {"udi5fcm", APU(4, 675,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3304 {"evmwlumiaaw", VX (4,1352), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3305 {"evmwlsmiaaw", VX (4,1353), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3306 {"evmwssfaa", VX (4,1363), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3307 {"macchwo", XO (4, 172,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3308 {"evmwumiaa", VX (4,1368), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3309 {"macchwo.", XO (4, 172,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3310 {"evmwsmiaa", VX (4,1369), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3311 {"evmwsmfaa", VX (4,1371), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3312 {"nmacchwo", XO (4, 174,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3313 {"nmacchwo.", XO (4, 174,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3314 {"evmheusianw", VX (4,1408), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3315 {"vsubcuw", VX (4,1408), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3316 {"evmhessianw", VX (4,1409), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3317 {"vavgsw", VX (4,1410), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3318 {"evmhessfanw", VX (4,1411), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3319 {"evmhousianw", VX (4,1412), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3320 {"evmhossianw", VX (4,1413), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3321 {"udi6fcm.", APU(4, 707,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3322 {"udi6fcm", APU(4, 707,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3323 {"evmhossfanw", VX (4,1415), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3324 {"evmheumianw", VX (4,1416), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3325 {"evmhesmianw", VX (4,1417), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3326 {"evmhesmfanw", VX (4,1419), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3327 {"evmhoumianw", VX (4,1420), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3328 {"evmhosmianw", VX (4,1421), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3329 {"evmhosmfanw", VX (4,1423), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3330 {"macchwsuo", XO (4, 204,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3331 {"macchwsuo.", XO (4, 204,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3332 {"evmhegumian", VX (4,1448), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3333 {"evmhegsmian", VX (4,1449), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3334 {"evmhegsmfan", VX (4,1451), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3335 {"evmhogumian", VX (4,1452), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3336 {"evmhogsmian", VX (4,1453), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3337 {"evmhogsmfan", VX (4,1455), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3338 {"evmwlusianw", VX (4,1472), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3339 {"evmwlssianw", VX (4,1473), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3340 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3341 {"udi7fcm.", APU(4, 739,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3342 {"udi7fcm", APU(4, 739,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3343 {"evmwlumianw", VX (4,1480), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3344 {"evmwlsmianw", VX (4,1481), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3345 {"evmwssfan", VX (4,1491), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3346 {"macchwso", XO (4, 236,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3347 {"evmwumian", VX (4,1496), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3348 {"macchwso.", XO (4, 236,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3349 {"evmwsmian", VX (4,1497), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3350 {"evmwsmfan", VX (4,1499), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3351 {"nmacchwso", XO (4, 238,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3352 {"nmacchwso.", XO (4, 238,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3353 {"vsububs", VX (4,1536), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3354 {"mfvscr", VX (4,1540), VXVAVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
}},
3355 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3356 {"udi8fcm.", APU(4, 771,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3357 {"udi8fcm", APU(4, 771,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3358 {"vsum4ubs", VX (4,1544), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3359 {"vsubuhs", VX (4,1600), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3360 {"mtvscr", VX (4,1604), VXVDVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VB
}},
3361 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3362 {"vsum4shs", VX (4,1608), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3363 {"udi9fcm.", APU(4, 804,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3364 {"udi9fcm", APU(4, 804,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3365 {"vsubuws", VX (4,1664), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3366 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3367 {"udi10fcm.", APU(4, 835,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3368 {"udi10fcm", APU(4, 835,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3369 {"vsum2sws", VX (4,1672), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3370 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3371 {"udi11fcm.", APU(4, 867,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3372 {"udi11fcm", APU(4, 867,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3373 {"vsubsbs", VX (4,1792), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3374 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3375 {"udi12fcm.", APU(4, 899,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3376 {"udi12fcm", APU(4, 899,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3377 {"vsum4sbs", VX (4,1800), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3378 {"maclhwuo", XO (4, 396,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3379 {"maclhwuo.", XO (4, 396,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3380 {"vsubshs", VX (4,1856), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3381 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3382 {"udi13fcm.", APU(4, 931,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3383 {"udi13fcm", APU(4, 931,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3384 {"maclhwo", XO (4, 428,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3385 {"maclhwo.", XO (4, 428,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3386 {"nmaclhwo", XO (4, 430,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3387 {"nmaclhwo.", XO (4, 430,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3388 {"vsubsws", VX (4,1920), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3389 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3390 {"udi14fcm.", APU(4, 963,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3391 {"udi14fcm", APU(4, 963,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3392 {"vsumsws", VX (4,1928), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3393 {"maclhwsuo", XO (4, 460,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3394 {"maclhwsuo.", XO (4, 460,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3395 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK
, PPCVEC
, PPCNONE
, {VD
, VA
, VB
}},
3396 {"udi15fcm.", APU(4, 995,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3397 {"udi15fcm", APU(4, 995,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3398 {"maclhwso", XO (4, 492,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3399 {"maclhwso.", XO (4, 492,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3400 {"nmaclhwso", XO (4, 494,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3401 {"nmaclhwso.", XO (4, 494,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3402 {"dcbz_l", X (4,1014), XRT_MASK
, PPCPS
, PPCNONE
, {RA
, RB
}},
3404 {"mulli", OP(7), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3405 {"muli", OP(7), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3407 {"subfic", OP(8), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3408 {"sfi", OP(8), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3410 {"dozi", OP(9), OP_MASK
, M601
, PPCNONE
, {RT
, RA
, SI
}},
3412 {"cmplwi", OPL(10,0), OPL_MASK
, PPCCOM
, PPCNONE
, {OBF
, RA
, UI
}},
3413 {"cmpldi", OPL(10,1), OPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, UI
}},
3414 {"cmpli", OP(10), OP_MASK
, PPC
, PPCNONE
, {BF
, L
, RA
, UI
}},
3415 {"cmpli", OP(10), OP_MASK
, PWRCOM
, PPC
, {BF
, RA
, UI
}},
3417 {"cmpwi", OPL(11,0), OPL_MASK
, PPCCOM
, PPCNONE
, {OBF
, RA
, SI
}},
3418 {"cmpdi", OPL(11,1), OPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, SI
}},
3419 {"cmpi", OP(11), OP_MASK
, PPC
, PPCNONE
, {BF
, L
, RA
, SI
}},
3420 {"cmpi", OP(11), OP_MASK
, PWRCOM
, PPC
, {BF
, RA
, SI
}},
3422 {"addic", OP(12), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3423 {"ai", OP(12), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3424 {"subic", OP(12), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, NSI
}},
3426 {"addic.", OP(13), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3427 {"ai.", OP(13), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3428 {"subic.", OP(13), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, NSI
}},
3430 {"li", OP(14), DRA_MASK
, PPCCOM
, PPCNONE
, {RT
, SI
}},
3431 {"lil", OP(14), DRA_MASK
, PWRCOM
, PPCNONE
, {RT
, SI
}},
3432 {"addi", OP(14), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, SI
}},
3433 {"cal", OP(14), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
3434 {"subi", OP(14), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, NSI
}},
3435 {"la", OP(14), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RA0
}},
3437 {"lis", OP(15), DRA_MASK
, PPCCOM
, PPCNONE
, {RT
, SISIGNOPT
}},
3438 {"liu", OP(15), DRA_MASK
, PWRCOM
, PPCNONE
, {RT
, SISIGNOPT
}},
3439 {"addis", OP(15), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, SISIGNOPT
}},
3440 {"cau", OP(15), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA0
, SISIGNOPT
}},
3441 {"subis", OP(15), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, NSI
}},
3443 {"bdnz-", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3444 {"bdnz+", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3445 {"bdnz", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BD
}},
3446 {"bdn", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BD
}},
3447 {"bdnzl-", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3448 {"bdnzl+", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3449 {"bdnzl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BD
}},
3450 {"bdnl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BD
}},
3451 {"bdnza-", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3452 {"bdnza+", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3453 {"bdnza", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDA
}},
3454 {"bdna", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BDA
}},
3455 {"bdnzla-", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3456 {"bdnzla+", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3457 {"bdnzla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDA
}},
3458 {"bdnla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BDA
}},
3459 {"bdz-", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3460 {"bdz+", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3461 {"bdz", BBO(16,BODZ
,0,0), BBOATBI_MASK
, COM
, PPCNONE
, {BD
}},
3462 {"bdzl-", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3463 {"bdzl+", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3464 {"bdzl", BBO(16,BODZ
,0,1), BBOATBI_MASK
, COM
, PPCNONE
, {BD
}},
3465 {"bdza-", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3466 {"bdza+", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3467 {"bdza", BBO(16,BODZ
,1,0), BBOATBI_MASK
, COM
, PPCNONE
, {BDA
}},
3468 {"bdzla-", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3469 {"bdzla+", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3470 {"bdzla", BBO(16,BODZ
,1,1), BBOATBI_MASK
, COM
, PPCNONE
, {BDA
}},
3472 {"bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3473 {"bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3474 {"bge", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3475 {"bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3476 {"bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3477 {"bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3478 {"bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3479 {"bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3480 {"bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3481 {"bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3482 {"bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3483 {"bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3484 {"bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3485 {"bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3486 {"bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3487 {"bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3488 {"bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3489 {"bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3490 {"bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3491 {"bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3492 {"bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3493 {"bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3494 {"bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3495 {"bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3496 {"ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3497 {"ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3498 {"ble", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3499 {"bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3500 {"bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3501 {"bng", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3502 {"blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3503 {"blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3504 {"blel", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3505 {"bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3506 {"bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3507 {"bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3508 {"blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3509 {"blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3510 {"blea", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3511 {"bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3512 {"bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3513 {"bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3514 {"blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3515 {"blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3516 {"blela", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3517 {"bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3518 {"bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3519 {"bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3520 {"bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3521 {"bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3522 {"bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3523 {"bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3524 {"bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3525 {"bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3526 {"bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3527 {"bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3528 {"bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3529 {"bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3530 {"bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3531 {"bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3532 {"bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3533 {"bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3534 {"bns", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3535 {"bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3536 {"bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3537 {"bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3538 {"bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3539 {"bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3540 {"bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3541 {"bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3542 {"bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3543 {"bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3544 {"bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3545 {"bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3546 {"bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3547 {"bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3548 {"bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3549 {"bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3550 {"bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3551 {"bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3552 {"bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3553 {"bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3554 {"bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3555 {"bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3557 {"blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3558 {"blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3559 {"blt", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3560 {"bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3561 {"bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3562 {"bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3563 {"blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3564 {"blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3565 {"blta", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3566 {"bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3567 {"bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3568 {"bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3569 {"bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3570 {"bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3571 {"bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3572 {"bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3573 {"bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3574 {"bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3575 {"bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3576 {"bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3577 {"bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3578 {"bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3579 {"bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3580 {"bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3581 {"beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3582 {"beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3583 {"beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3584 {"beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3585 {"beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3586 {"beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3587 {"beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3588 {"beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3589 {"beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3590 {"beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3591 {"beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3592 {"beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3593 {"bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3594 {"bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3595 {"bso", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3596 {"bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3597 {"bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3598 {"bun", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3599 {"bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3600 {"bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3601 {"bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3602 {"bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3603 {"bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3604 {"bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3605 {"bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3606 {"bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3607 {"bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3608 {"buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3609 {"buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3610 {"buna", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3611 {"bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3612 {"bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3613 {"bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3614 {"bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3615 {"bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3616 {"bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3618 {"bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3619 {"bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3620 {"bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3621 {"bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3622 {"bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3623 {"bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3624 {"bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3625 {"bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3626 {"bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3627 {"bdnzfla-", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3628 {"bdnzfla+", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3629 {"bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3630 {"bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3631 {"bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3632 {"bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3633 {"bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3634 {"bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3635 {"bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3636 {"bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3637 {"bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3638 {"bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3639 {"bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3640 {"bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3641 {"bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3643 {"bf-", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3644 {"bf+", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3645 {"bf", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3646 {"bbf", BBO(16,BOF
,0,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3647 {"bfl-", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3648 {"bfl+", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3649 {"bfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3650 {"bbfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3651 {"bfa-", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3652 {"bfa+", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3653 {"bfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3654 {"bbfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3655 {"bfla-", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3656 {"bfla+", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3657 {"bfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3658 {"bbfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3660 {"bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3661 {"bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3662 {"bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3663 {"bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3664 {"bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3665 {"bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3666 {"bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3667 {"bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3668 {"bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3669 {"bdnztla-", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3670 {"bdnztla+", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3671 {"bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3672 {"bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3673 {"bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3674 {"bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3675 {"bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3676 {"bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3677 {"bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3678 {"bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3679 {"bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3680 {"bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3681 {"bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3682 {"bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3683 {"bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3685 {"bt-", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3686 {"bt+", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3687 {"bt", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3688 {"bbt", BBO(16,BOT
,0,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3689 {"btl-", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3690 {"btl+", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3691 {"btl", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3692 {"bbtl", BBO(16,BOT
,0,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3693 {"bta-", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3694 {"bta+", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3695 {"bta", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3696 {"bbta", BBO(16,BOT
,1,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3697 {"btla-", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3698 {"btla+", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3699 {"btla", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3700 {"bbtla", BBO(16,BOT
,1,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3702 {"bc-", B(16,0,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDM
}},
3703 {"bc+", B(16,0,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDP
}},
3704 {"bc", B(16,0,0), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BD
}},
3705 {"bcl-", B(16,0,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDM
}},
3706 {"bcl+", B(16,0,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDP
}},
3707 {"bcl", B(16,0,1), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BD
}},
3708 {"bca-", B(16,1,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDMA
}},
3709 {"bca+", B(16,1,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDPA
}},
3710 {"bca", B(16,1,0), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BDA
}},
3711 {"bcla-", B(16,1,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDMA
}},
3712 {"bcla+", B(16,1,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDPA
}},
3713 {"bcla", B(16,1,1), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BDA
}},
3715 {"svc", SC(17,0,0), SC_MASK
, POWER
, PPCNONE
, {SVC_LEV
, FL1
, FL2
}},
3716 {"svcl", SC(17,0,1), SC_MASK
, POWER
, PPCNONE
, {SVC_LEV
, FL1
, FL2
}},
3717 {"sc", SC(17,1,0), SC_MASK
, PPC
, PPCNONE
, {LEV
}},
3718 {"svca", SC(17,1,0), SC_MASK
, PWRCOM
, PPCNONE
, {SV
}},
3719 {"svcla", SC(17,1,1), SC_MASK
, POWER
, PPCNONE
, {SV
}},
3721 {"b", B(18,0,0), B_MASK
, COM
, PPCNONE
, {LI
}},
3722 {"bl", B(18,0,1), B_MASK
, COM
, PPCNONE
, {LI
}},
3723 {"ba", B(18,1,0), B_MASK
, COM
, PPCNONE
, {LIA
}},
3724 {"bla", B(18,1,1), B_MASK
, COM
, PPCNONE
, {LIA
}},
3726 {"mcrf", XL(19,0), XLBB_MASK
|(3<<21)|(3<<16), COM
, PPCNONE
, {BF
, BFA
}},
3728 {"bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3729 {"bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3730 {"bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3731 {"bdnzlrl-", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3732 {"bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3733 {"bdnzlrl+", XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3734 {"bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3735 {"bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3736 {"bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3737 {"bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3738 {"bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3739 {"bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3740 {"blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3741 {"br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PWRCOM
, PPCNONE
, {0}},
3742 {"blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3743 {"brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PWRCOM
, PPCNONE
, {0}},
3744 {"bdnzlr-", XLO(19,BODNZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3745 {"bdnzlrl-", XLO(19,BODNZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3746 {"bdnzlr+", XLO(19,BODNZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3747 {"bdnzlrl+", XLO(19,BODNZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3748 {"bdzlr-", XLO(19,BODZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3749 {"bdzlrl-", XLO(19,BODZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3750 {"bdzlr+", XLO(19,BODZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3751 {"bdzlrl+", XLO(19,BODZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3753 {"bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3754 {"bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3755 {"bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3756 {"bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3757 {"bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3758 {"bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3759 {"bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3760 {"bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3761 {"bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3762 {"bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3763 {"bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3764 {"bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3765 {"blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3766 {"blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3767 {"bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3768 {"bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3769 {"bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3770 {"bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3771 {"blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3772 {"blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3773 {"blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3774 {"bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3775 {"bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3776 {"bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3777 {"bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3778 {"bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3779 {"bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3780 {"bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3781 {"bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3782 {"bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3783 {"bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3784 {"bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3785 {"bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3786 {"bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3787 {"bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3788 {"bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3789 {"bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3790 {"bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3791 {"bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3792 {"bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3793 {"bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3794 {"bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3795 {"bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3796 {"bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3797 {"blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3798 {"bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3799 {"blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3800 {"bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3801 {"bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3802 {"bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3803 {"bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3804 {"bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3805 {"bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3806 {"bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3807 {"bgelr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3808 {"bnllr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3809 {"bgelrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3810 {"bnllrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3811 {"blelr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3812 {"bnglr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3813 {"blelrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3814 {"bnglrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3815 {"bnelr-", XLOCB(19,BOFM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3816 {"bnelrl-", XLOCB(19,BOFM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3817 {"bnslr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3818 {"bnulr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3819 {"bnslrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3820 {"bnulrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3821 {"bgelr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3822 {"bnllr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3823 {"bgelrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3824 {"bnllrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3825 {"blelr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3826 {"bnglr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3827 {"blelrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3828 {"bnglrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3829 {"bnelr+", XLOCB(19,BOFP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3830 {"bnelrl+", XLOCB(19,BOFP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3831 {"bnslr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3832 {"bnulr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3833 {"bnslrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3834 {"bnulrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3835 {"bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3836 {"bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3837 {"bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3838 {"bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3839 {"bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3840 {"bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3841 {"bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3842 {"bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3843 {"bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3844 {"bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3845 {"bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3846 {"bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3847 {"beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3848 {"beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3849 {"beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3850 {"beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3851 {"beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3852 {"beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3853 {"bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3854 {"bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3855 {"bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3856 {"bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3857 {"bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3858 {"bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3859 {"bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3860 {"bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3861 {"bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3862 {"bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3863 {"bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3864 {"bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3865 {"bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3866 {"bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3867 {"beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3868 {"beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3869 {"bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3870 {"bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3871 {"bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3872 {"bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3873 {"bltlr-", XLOCB(19,BOTM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3874 {"bltlrl-", XLOCB(19,BOTM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3875 {"bgtlr-", XLOCB(19,BOTM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3876 {"bgtlrl-", XLOCB(19,BOTM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3877 {"beqlr-", XLOCB(19,BOTM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3878 {"beqlrl-", XLOCB(19,BOTM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3879 {"bsolr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3880 {"bunlr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3881 {"bsolrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3882 {"bunlrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3883 {"bltlr+", XLOCB(19,BOTP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3884 {"bltlrl+", XLOCB(19,BOTP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3885 {"bgtlr+", XLOCB(19,BOTP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3886 {"bgtlrl+", XLOCB(19,BOTP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3887 {"beqlr+", XLOCB(19,BOTP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3888 {"beqlrl+", XLOCB(19,BOTP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3889 {"bsolr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3890 {"bunlr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3891 {"bsolrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3892 {"bunlrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3894 {"bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3895 {"bdnzflr-", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3896 {"bdnzflrl", XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3897 {"bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3898 {"bdnzflr+", XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3899 {"bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3900 {"bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3901 {"bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3902 {"bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3903 {"bdzflrl-", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3904 {"bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3905 {"bdzflrl+", XLO(19,BODZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3906 {"bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3907 {"bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3908 {"bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
3909 {"bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3910 {"bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3911 {"bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
3912 {"bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3913 {"bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3914 {"bflr-", XLO(19,BOFM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3915 {"bflrl-", XLO(19,BOFM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3916 {"bflr+", XLO(19,BOFP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3917 {"bflrl+", XLO(19,BOFP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3918 {"bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3919 {"bdnztlr-", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3920 {"bdnztlrl", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3921 {"bdnztlrl-",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3922 {"bdnztlr+", XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3923 {"bdnztlrl+",XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3924 {"bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3925 {"bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3926 {"bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3927 {"bdztlrl-", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3928 {"bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3929 {"bdztlrl+", XLO(19,BODZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3930 {"btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3931 {"btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3932 {"bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
3933 {"btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3934 {"btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3935 {"bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
3936 {"btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3937 {"btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3938 {"btlr-", XLO(19,BOTM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3939 {"btlrl-", XLO(19,BOTM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3940 {"btlr+", XLO(19,BOTP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3941 {"btlrl+", XLO(19,BOTP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3943 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
3944 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
3945 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
3946 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
3947 {"bclr", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
3948 {"bcr", XLLK(19,16,0), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
3949 {"bclrl", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
3950 {"bcrl", XLLK(19,16,1), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
3952 {"rfid", XL(19,18), 0xffffffff, PPC64
, PPCNONE
, {0}},
3954 {"crnot", XL(19,33), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BA
, BBA
}},
3955 {"crnor", XL(19,33), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3956 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI
|PPCA2
|PPC476
, PPCNONE
, {0}},
3958 {"rfdi", XL(19,39), 0xffffffff, E500MC
, PPCNONE
, {0}},
3959 {"rfi", XL(19,50), 0xffffffff, COM
, PPCNONE
, {0}},
3960 {"rfci", XL(19,51), 0xffffffff, PPC403
|BOOKE
|PPCE300
|PPCA2
|PPC476
, PPCNONE
, {0}},
3962 {"rfsvc", XL(19,82), 0xffffffff, POWER
, PPCNONE
, {0}},
3964 {"rfgi", XL(19,102), 0xffffffff, E500MC
|PPCA2
, PPCNONE
, {0}},
3966 {"crandc", XL(19,129), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3968 {"isync", XL(19,150), 0xffffffff, PPCCOM
, PPCNONE
, {0}},
3969 {"ics", XL(19,150), 0xffffffff, PWRCOM
, PPCNONE
, {0}},
3971 {"crclr", XL(19,193), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BAT
, BBA
}},
3972 {"crxor", XL(19,193), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3974 {"dnh", X(19,198), X_MASK
, E500MC
, PPCNONE
, {DUI
, DUIS
}},
3976 {"crnand", XL(19,225), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3978 {"crand", XL(19,257), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3980 {"hrfid", XL(19,274), 0xffffffff, POWER5
|CELL
, PPC476
, {0}},
3982 {"crset", XL(19,289), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BAT
, BBA
}},
3983 {"creqv", XL(19,289), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3985 {"doze", XL(19,402), 0xffffffff, POWER6
, PPCNONE
, {0}},
3987 {"crorc", XL(19,417), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3989 {"nap", XL(19,434), 0xffffffff, POWER6
, PPCNONE
, {0}},
3991 {"crmove", XL(19,449), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BA
, BBA
}},
3992 {"cror", XL(19,449), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3994 {"sleep", XL(19,466), 0xffffffff, POWER6
, PPCNONE
, {0}},
3995 {"rvwinkle", XL(19,498), 0xffffffff, POWER6
, PPCNONE
, {0}},
3997 {"bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, COM
, PPCNONE
, {0}},
3998 {"bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, COM
, PPCNONE
, {0}},
4000 {"bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4001 {"bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4002 {"bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4003 {"bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4004 {"bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4005 {"bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4006 {"bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4007 {"bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4008 {"blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4009 {"blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4010 {"bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4011 {"bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4012 {"blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4013 {"blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4014 {"bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4015 {"bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4016 {"bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4017 {"bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4018 {"bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4019 {"bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4020 {"bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4021 {"bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4022 {"bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4023 {"bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4024 {"bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4025 {"bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4026 {"bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4027 {"bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4028 {"bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4029 {"bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4030 {"bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4031 {"bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4032 {"blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4033 {"bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4034 {"blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4035 {"bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4036 {"bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4037 {"bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4038 {"bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4039 {"bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4040 {"bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4041 {"bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4042 {"bgectr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4043 {"bnlctr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4044 {"bgectrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4045 {"bnlctrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4046 {"blectr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4047 {"bngctr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4048 {"blectrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4049 {"bngctrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4050 {"bnectr-", XLOCB(19,BOFM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4051 {"bnectrl-",XLOCB(19,BOFM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4052 {"bnsctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4053 {"bnuctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4054 {"bnsctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4055 {"bnuctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4056 {"bgectr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4057 {"bnlctr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4058 {"bgectrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4059 {"bnlctrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4060 {"blectr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4061 {"bngctr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4062 {"blectrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4063 {"bngctrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4064 {"bnectr+", XLOCB(19,BOFP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4065 {"bnectrl+",XLOCB(19,BOFP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4066 {"bnsctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4067 {"bnuctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4068 {"bnsctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4069 {"bnuctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4070 {"bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4071 {"bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4072 {"bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4073 {"bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4074 {"bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4075 {"bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4076 {"bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4077 {"bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4078 {"beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4079 {"beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4080 {"beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4081 {"beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4082 {"bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4083 {"bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4084 {"bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4085 {"bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4086 {"bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4087 {"bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4088 {"bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4089 {"bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4090 {"bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4091 {"bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4092 {"bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4093 {"bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4094 {"beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4095 {"beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4096 {"bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4097 {"bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4098 {"bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4099 {"bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4100 {"bltctr-", XLOCB(19,BOTM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4101 {"bltctrl-",XLOCB(19,BOTM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4102 {"bgtctr-", XLOCB(19,BOTM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4103 {"bgtctrl-",XLOCB(19,BOTM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4104 {"beqctr-", XLOCB(19,BOTM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4105 {"beqctrl-",XLOCB(19,BOTM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4106 {"bsoctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4107 {"bunctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4108 {"bsoctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4109 {"bunctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4110 {"bltctr+", XLOCB(19,BOTP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4111 {"bltctrl+",XLOCB(19,BOTP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4112 {"bgtctr+", XLOCB(19,BOTP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4113 {"bgtctrl+",XLOCB(19,BOTP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4114 {"beqctr+", XLOCB(19,BOTP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4115 {"beqctrl+",XLOCB(19,BOTP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4116 {"bsoctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4117 {"bunctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4118 {"bsoctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4119 {"bunctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4121 {"bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4122 {"bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4123 {"bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4124 {"bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4125 {"bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4126 {"bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4127 {"bfctr-", XLO(19,BOFM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4128 {"bfctrl-", XLO(19,BOFM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4129 {"bfctr+", XLO(19,BOFP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4130 {"bfctrl+", XLO(19,BOFP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4131 {"btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4132 {"btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4133 {"btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4134 {"btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4135 {"btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4136 {"btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4137 {"btctr-", XLO(19,BOTM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4138 {"btctrl-", XLO(19,BOTM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4139 {"btctr+", XLO(19,BOTP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4140 {"btctrl+", XLO(19,BOTP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4142 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4143 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4144 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4145 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4146 {"bcctr", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4147 {"bcc", XLLK(19,528,0), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4148 {"bcctrl", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4149 {"bccl", XLLK(19,528,1), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4151 {"rlwimi", M(20,0), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4152 {"rlimi", M(20,0), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4154 {"rlwimi.", M(20,1), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4155 {"rlimi.", M(20,1), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4157 {"rotlwi", MME(21,31,0), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
}},
4158 {"clrlwi", MME(21,31,0), MSHME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, MB
}},
4159 {"rlwinm", M(21,0), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4160 {"rlinm", M(21,0), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4161 {"rotlwi.", MME(21,31,1), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
}},
4162 {"clrlwi.", MME(21,31,1), MSHME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, MB
}},
4163 {"rlwinm.", M(21,1), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4164 {"rlinm.", M(21,1), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4166 {"rlmi", M(22,0), M_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4167 {"rlmi.", M(22,1), M_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4169 {"rotlw", MME(23,31,0), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
}},
4170 {"rlwnm", M(23,0), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4171 {"rlnm", M(23,0), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4172 {"rotlw.", MME(23,31,1), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
}},
4173 {"rlwnm.", M(23,1), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4174 {"rlnm.", M(23,1), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4176 {"nop", OP(24), 0xffffffff, PPCCOM
, PPCNONE
, {0}},
4177 {"ori", OP(24), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4178 {"oril", OP(24), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4180 {"oris", OP(25), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4181 {"oriu", OP(25), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4183 {"xnop", OP(26), 0xffffffff, PPCCOM
, PPCNONE
, {0}},
4184 {"xori", OP(26), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4185 {"xoril", OP(26), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4187 {"xoris", OP(27), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4188 {"xoriu", OP(27), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4190 {"andi.", OP(28), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4191 {"andil.", OP(28), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4193 {"andis.", OP(29), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4194 {"andiu.", OP(29), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4196 {"rotldi", MD(30,0,0), MDMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
}},
4197 {"clrldi", MD(30,0,0), MDSH_MASK
, PPC64
, PPCNONE
, {RA
, RS
, MB6
}},
4198 {"rldicl", MD(30,0,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4199 {"rotldi.", MD(30,0,1), MDMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
}},
4200 {"clrldi.", MD(30,0,1), MDSH_MASK
, PPC64
, PPCNONE
, {RA
, RS
, MB6
}},
4201 {"rldicl.", MD(30,0,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4203 {"rldicr", MD(30,1,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, ME6
}},
4204 {"rldicr.", MD(30,1,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, ME6
}},
4206 {"rldic", MD(30,2,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4207 {"rldic.", MD(30,2,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4209 {"rldimi", MD(30,3,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4210 {"rldimi.", MD(30,3,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4212 {"rotld", MDS(30,8,0), MDSMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4213 {"rldcl", MDS(30,8,0), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, MB6
}},
4214 {"rotld.", MDS(30,8,1), MDSMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4215 {"rldcl.", MDS(30,8,1), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, MB6
}},
4217 {"rldcr", MDS(30,9,0), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, ME6
}},
4218 {"rldcr.", MDS(30,9,1), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, ME6
}},
4220 {"cmpw", XOPL(31,0,0), XCMPL_MASK
, PPCCOM
, PPCNONE
, {OBF
, RA
, RB
}},
4221 {"cmpd", XOPL(31,0,1), XCMPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, RB
}},
4222 {"cmp", X(31,0), XCMP_MASK
, PPC
|PPCVLE
, PPCNONE
, {BF
, L
, RA
, RB
}},
4223 {"cmp", X(31,0), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
4225 {"twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4226 {"tlgt", XTO(31,4,TOLGT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4227 {"twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4228 {"tllt", XTO(31,4,TOLLT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4229 {"tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4230 {"teq", XTO(31,4,TOEQ
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4231 {"twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4232 {"tlge", XTO(31,4,TOLGE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4233 {"twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4234 {"tlnl", XTO(31,4,TOLNL
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4235 {"twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4236 {"tlle", XTO(31,4,TOLLE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4237 {"twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4238 {"tlng", XTO(31,4,TOLNG
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4239 {"twgt", XTO(31,4,TOGT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4240 {"tgt", XTO(31,4,TOGT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4241 {"twge", XTO(31,4,TOGE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4242 {"tge", XTO(31,4,TOGE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4243 {"twnl", XTO(31,4,TONL
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4244 {"tnl", XTO(31,4,TONL
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4245 {"twlt", XTO(31,4,TOLT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4246 {"tlt", XTO(31,4,TOLT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4247 {"twle", XTO(31,4,TOLE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4248 {"tle", XTO(31,4,TOLE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4249 {"twng", XTO(31,4,TONG
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4250 {"tng", XTO(31,4,TONG
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4251 {"twne", XTO(31,4,TONE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4252 {"tne", XTO(31,4,TONE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4253 {"trap", XTO(31,4,TOU
), 0xffffffff, PPCCOM
|PPCVLE
, PPCNONE
, {0}},
4254 {"tw", X(31,4), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {TO
, RA
, RB
}},
4255 {"t", X(31,4), X_MASK
, PWRCOM
, PPCNONE
, {TO
, RA
, RB
}},
4257 {"lvsl", X(31,6), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4258 {"lvebx", X(31,7), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4259 {"lbfcmx", APU(31,7,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4261 {"subfc", XO(31,8,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4262 {"sf", XO(31,8,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4263 {"subc", XO(31,8,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4264 {"subfc.", XO(31,8,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4265 {"sf.", XO(31,8,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4266 {"subc.", XO(31,8,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4268 {"mulhdu", XO(31,9,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4269 {"mulhdu.", XO(31,9,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4271 {"addc", XO(31,10,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4272 {"a", XO(31,10,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4273 {"addc.", XO(31,10,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4274 {"a.", XO(31,10,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4276 {"mulhwu", XO(31,11,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4277 {"mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4279 {"isellt", X(31,15), X_MASK
, PPCISEL
, PPCNONE
, {RT
, RA0
, RB
}},
4281 {"tlbilxlpid", XTO(31,18,0), XTO_MASK
, E500MC
|PPCA2
, PPCNONE
, {0}},
4282 {"tlbilxpid", XTO(31,18,1), XTO_MASK
, E500MC
|PPCA2
, PPCNONE
, {0}},
4283 {"tlbilxva", XTO(31,18,3), XTO_MASK
, E500MC
|PPCA2
, PPCNONE
, {RA0
, RB
}},
4284 {"tlbilx", X(31,18), X_MASK
, E500MC
|PPCA2
, PPCNONE
, {T
, RA0
, RB
}},
4286 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK
, POWER4
, PPCNONE
, {RT
, FXM4
}},
4287 {"mfcr", XFXM(31,19,0,0), XRARB_MASK
, COM
|PPCVLE
, POWER4
, {RT
}},
4288 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, FXM
}},
4290 {"lwarx", X(31,20), XEH_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4292 {"ldx", X(31,21), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4294 {"icbt", X(31,22), X_MASK
, BOOKE
|PPCE300
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4296 {"lwzx", X(31,23), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4297 {"lx", X(31,23), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4299 {"slw", XRC(31,24,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4300 {"sl", XRC(31,24,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
4301 {"slw.", XRC(31,24,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4302 {"sl.", XRC(31,24,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
4304 {"cntlzw", XRC(31,26,0), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4305 {"cntlz", XRC(31,26,0), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
4306 {"cntlzw.", XRC(31,26,1), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4307 {"cntlz.", XRC(31,26,1), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
4309 {"sld", XRC(31,27,0), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4310 {"sld.", XRC(31,27,1), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4312 {"and", XRC(31,28,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4313 {"and.", XRC(31,28,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4315 {"maskg", XRC(31,29,0), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
4316 {"maskg.", XRC(31,29,1), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
4318 {"ldepx", X(31,29), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4319 {"lwepx", X(31,31), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4321 {"cmplw", XOPL(31,32,0), XCMPL_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {OBF
, RA
, RB
}},
4322 {"cmpld", XOPL(31,32,1), XCMPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, RB
}},
4323 {"cmpl", X(31,32), XCMP_MASK
, PPC
|PPCVLE
, PPCNONE
, {BF
, L
, RA
, RB
}},
4324 {"cmpl", X(31,32), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
4326 {"lvsr", X(31,38), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4327 {"lvehx", X(31,39), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4328 {"lhfcmx", APU(31,39,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4330 {"mviwsplt", X(31,46), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA
, RB
}},
4332 {"iselgt", X(31,47), X_MASK
, PPCISEL
, PPCNONE
, {RT
, RA0
, RB
}},
4334 {"lvewx", X(31,71), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4336 {"addg6s", XO(31,74,0,0), XO_MASK
, POWER6
, PPCNONE
, {RT
, RA
, RB
}},
4338 {"iseleq", X(31,79), X_MASK
, PPCISEL
, PPCNONE
, {RT
, RA0
, RB
}},
4340 {"isel", XISEL(31,15), XISEL_MASK
, PPCISEL
|TITAN
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, CRB
}},
4342 {"subf", XO(31,40,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4343 {"sub", XO(31,40,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4344 {"subf.", XO(31,40,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4345 {"sub.", XO(31,40,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4347 {"eratilx", X(31,51), X_MASK
, PPCA2
, PPCNONE
, {ERAT_T
, RA
, RB
}},
4349 {"lbarx", X(31,52), XEH_MASK
, POWER7
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4351 {"ldux", X(31,53), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4353 {"dcbst", X(31,54), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
4355 {"lwzux", X(31,55), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4356 {"lux", X(31,55), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4358 {"cntlzd", XRC(31,58,0), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4359 {"cntlzd.", XRC(31,58,1), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4361 {"andc", XRC(31,60,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4362 {"andc.", XRC(31,60,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4364 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7
|E500MC
|PPCA2
, PPCNONE
, {0}},
4365 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7
|E500MC
|PPCA2
, PPCNONE
, {0}},
4366 {"wait", X(31,62), XWC_MASK
, POWER7
|E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {WC
}},
4368 {"dcbstep", XRT(31,63,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
4370 {"tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4371 {"tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4372 {"tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4373 {"tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4374 {"tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4375 {"tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4376 {"tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4377 {"tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4378 {"tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4379 {"tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4380 {"tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4381 {"tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4382 {"tdng", XTO(31,68,TONG
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4383 {"tdne", XTO(31,68,TONE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4384 {"td", X(31,68), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {TO
, RA
, RB
}},
4386 {"lwfcmx", APU(31,71,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4387 {"mulhd", XO(31,73,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4388 {"mulhd.", XO(31,73,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4390 {"mulhw", XO(31,75,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4391 {"mulhw.", XO(31,75,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4393 {"dlmzb", XRC(31,78,0), X_MASK
, PPC403
|PPC440
|TITAN
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4394 {"dlmzb.", XRC(31,78,1), X_MASK
, PPC403
|PPC440
|TITAN
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4396 {"mtsrd", X(31,82), XRB_MASK
|(1<<20), PPC64
, PPCNONE
, {SR
, RS
}},
4398 {"mfmsr", X(31,83), XRARB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4400 {"ldarx", X(31,84), XEH_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4402 {"dcbfl", XOPL(31,86,1), XRT_MASK
, POWER5
, PPC476
, {RA0
, RB
}},
4403 {"dcbf", X(31,86), XLRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
, L
}},
4405 {"lbzx", X(31,87), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4407 {"lbepx", X(31,95), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4409 {"dni", XRC(31,97,1), XRB_MASK
, E6500
, PPCNONE
, {DUI
, DCTL
}},
4411 {"lvx", X(31,103), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4412 {"lqfcmx", APU(31,103,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4414 {"neg", XO(31,104,0,0), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4415 {"neg.", XO(31,104,0,1), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4417 {"mul", XO(31,107,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4418 {"mul.", XO(31,107,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4420 {"mvidsplt", X(31,110), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA
, RB
}},
4422 {"mtsrdin", X(31,114), XRA_MASK
, PPC64
, PPCNONE
, {RS
, RB
}},
4424 {"lharx", X(31,116), XEH_MASK
, POWER7
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4426 {"clf", X(31,118), XTO_MASK
, POWER
, PPCNONE
, {RA
, RB
}},
4428 {"lbzux", X(31,119), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4430 {"popcntb", X(31,122), XRB_MASK
, POWER5
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4432 {"not", XRC(31,124,0), X_MASK
, COM
, PPCNONE
, {RA
, RS
, RBS
}},
4433 {"nor", XRC(31,124,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4434 {"not.", XRC(31,124,1), X_MASK
, COM
, PPCNONE
, {RA
, RS
, RBS
}},
4435 {"nor.", XRC(31,124,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4437 {"dcbfep", XRT(31,127,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
4439 {"wrtee", X(31,131), XRARB_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {RS
}},
4441 {"dcbtstls", X(31,134), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4443 {"stvebx", X(31,135), X_MASK
, PPCVEC
, PPCNONE
, {VS
, RA0
, RB
}},
4444 {"stbfcmx", APU(31,135,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4446 {"subfe", XO(31,136,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4447 {"sfe", XO(31,136,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4448 {"subfe.", XO(31,136,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4449 {"sfe.", XO(31,136,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4451 {"adde", XO(31,138,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4452 {"ae", XO(31,138,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4453 {"adde.", XO(31,138,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4454 {"ae.", XO(31,138,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4456 {"dcbtstlse", X(31,142), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
4458 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK
, COM
, PPCNONE
, {RS
}},
4459 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK
, COM
|PPCVLE
, PPCNONE
, {FXM
, RS
}},
4460 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK
, COM
|PPCVLE
, PPCNONE
, {FXM
, RS
}},
4462 {"mtmsr", X(31,146), XRLARB_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, A_L
}},
4464 {"eratsx", XRC(31,147,0), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
4465 {"eratsx.", XRC(31,147,1), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
4467 {"stdx", X(31,149), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4469 {"stwcx.", XRC(31,150,1), X_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4471 {"stwx", X(31,151), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4472 {"stx", X(31,151), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA
, RB
}},
4474 {"slq", XRC(31,152,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4475 {"slq.", XRC(31,152,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4477 {"sle", XRC(31,153,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4478 {"sle.", XRC(31,153,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4480 {"prtyw", X(31,154), XRB_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {RA
, RS
}},
4482 {"stdepx", X(31,157), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4484 {"stwepx", X(31,159), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4486 {"wrteei", X(31,163), XE_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {E
}},
4488 {"dcbtls", X(31,166), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4490 {"stvehx", X(31,167), X_MASK
, PPCVEC
, PPCNONE
, {VS
, RA0
, RB
}},
4491 {"sthfcmx", APU(31,167,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4493 {"dcbtlse", X(31,174), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
4495 {"mtmsrd", X(31,178), XRLARB_MASK
, PPC64
, PPCNONE
, {RS
, A_L
}},
4497 {"eratre", X(31,179), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA
, WS
}},
4499 {"stdux", X(31,181), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4501 {"wchkall", X(31,182), X_MASK
, PPCA2
, PPCNONE
, {OBF
}},
4503 {"stwux", X(31,183), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4504 {"stux", X(31,183), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, RB
}},
4506 {"sliq", XRC(31,184,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4507 {"sliq.", XRC(31,184,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4509 {"prtyd", X(31,186), XRB_MASK
, POWER6
|PPCA2
, PPCNONE
, {RA
, RS
}},
4511 {"icblq.", XRC(31,198,1), X_MASK
, E6500
, PPCNONE
, {CT
, RA0
, RB
}},
4513 {"stvewx", X(31,199), X_MASK
, PPCVEC
, PPCNONE
, {VS
, RA0
, RB
}},
4514 {"stwfcmx", APU(31,199,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4516 {"subfze", XO(31,200,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4517 {"sfze", XO(31,200,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4518 {"subfze.", XO(31,200,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4519 {"sfze.", XO(31,200,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4521 {"addze", XO(31,202,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4522 {"aze", XO(31,202,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4523 {"addze.", XO(31,202,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4524 {"aze.", XO(31,202,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4526 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RB
}},
4528 {"mtsr", X(31,210), XRB_MASK
|(1<<20), COM
, NON32
, {SR
, RS
}},
4530 {"eratwe", X(31,211), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
, WS
}},
4532 {"ldawx.", XRC(31,212,1), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
4534 {"stdcx.", XRC(31,214,1), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4536 {"stbx", X(31,215), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4538 {"sllq", XRC(31,216,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4539 {"sllq.", XRC(31,216,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4541 {"sleq", XRC(31,217,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4542 {"sleq.", XRC(31,217,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4544 {"stbepx", X(31,223), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4546 {"icblc", X(31,230), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4548 {"stvx", X(31,231), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VS
, RA0
, RB
}},
4549 {"stqfcmx", APU(31,231,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4551 {"subfme", XO(31,232,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4552 {"sfme", XO(31,232,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4553 {"subfme.", XO(31,232,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4554 {"sfme.", XO(31,232,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4556 {"mulld", XO(31,233,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4557 {"mulld.", XO(31,233,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4559 {"addme", XO(31,234,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4560 {"ame", XO(31,234,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4561 {"addme.", XO(31,234,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4562 {"ame.", XO(31,234,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4564 {"mullw", XO(31,235,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4565 {"muls", XO(31,235,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4566 {"mullw.", XO(31,235,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4567 {"muls.", XO(31,235,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4569 {"icblce", X(31,238), X_MASK
, PPCCHLK
, E500MC
|PPCA2
, {CT
, RA
, RB
}},
4570 {"msgclr", XRTRA(31,238,0,0),XRTRA_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RB
}},
4571 {"mtsrin", X(31,242), XRA_MASK
, PPC
, NON32
, {RS
, RB
}},
4572 {"mtsri", X(31,242), XRA_MASK
, POWER
, NON32
, {RS
, RB
}},
4574 {"dcbtstt", XRT(31,246,0x10), XRT_MASK
, POWER7
, PPCNONE
, {RA0
, RB
}},
4575 {"dcbtst", X(31,246), X_MASK
, POWER4
, PPCNONE
, {RA0
, RB
, CT
}},
4576 {"dcbtst", X(31,246), X_MASK
, PPC
|PPCVLE
, POWER4
, {CT
, RA0
, RB
}},
4578 {"stbux", X(31,247), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4580 {"slliq", XRC(31,248,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4581 {"slliq.", XRC(31,248,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4583 {"bpermd", X(31,252), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {RA
, RS
, RB
}},
4585 {"dcbtstep", XRT(31,255,0), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4587 {"mfdcrx", X(31,259), X_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {RS
, RA
}},
4588 {"mfdcrx.", XRC(31,259,1), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
}},
4590 {"lvexbx", X(31,261), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
4592 {"icbt", X(31,262), XRT_MASK
, PPC403
, PPCNONE
, {RA
, RB
}},
4594 {"lvepxl", X(31,263), X_MASK
, PPCVEC2
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4596 {"ldfcmx", APU(31,263,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4597 {"doz", XO(31,264,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4598 {"doz.", XO(31,264,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4600 {"add", XO(31,266,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4601 {"cax", XO(31,266,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4602 {"add.", XO(31,266,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4603 {"cax.", XO(31,266,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4605 {"ehpriv", X(31,270), 0xffffffff, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {0}},
4607 {"tlbiel", X(31,274), XRTLRA_MASK
, POWER4
, PPC476
, {RB
, L
}},
4609 {"mfapidi", X(31,275), X_MASK
, BOOKE
, TITAN
, {RT
, RA
}},
4611 {"lscbx", XRC(31,277,0), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4612 {"lscbx.", XRC(31,277,1), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4614 {"dcbtt", XRT(31,278,0x10), XRT_MASK
, POWER7
, PPCNONE
, {RA0
, RB
}},
4615 {"dcbt", X(31,278), X_MASK
, POWER4
, PPCNONE
, {RA0
, RB
, CT
}},
4616 {"dcbt", X(31,278), X_MASK
, PPC
|PPCVLE
, POWER4
, {CT
, RA0
, RB
}},
4618 {"lhzx", X(31,279), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4620 {"cdtbcd", X(31,282), XRB_MASK
, POWER6
, PPCNONE
, {RA
, RS
}},
4622 {"eqv", XRC(31,284,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4623 {"eqv.", XRC(31,284,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4625 {"lhepx", X(31,287), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4627 {"mfdcrux", X(31,291), X_MASK
, PPC464
|PPCVLE
, PPCNONE
, {RS
, RA
}},
4629 {"lvexhx", X(31,293), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
4630 {"lvepx", X(31,295), X_MASK
, PPCVEC2
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4632 {"tlbie", X(31,306), XRTLRA_MASK
, PPC
, TITAN
, {RB
, L
}},
4633 {"tlbi", X(31,306), XRT_MASK
, POWER
, PPCNONE
, {RA0
, RB
}},
4635 {"eciwx", X(31,310), X_MASK
, PPC
, TITAN
, {RT
, RA0
, RB
}},
4637 {"lhzux", X(31,311), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4639 {"cbcdtd", X(31,314), XRB_MASK
, POWER6
, PPCNONE
, {RA
, RS
}},
4641 {"xor", XRC(31,316,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4642 {"xor.", XRC(31,316,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4644 {"dcbtep", XRT(31,319,0), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4646 {"mfexisr", XSPR(31,323, 64), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4647 {"mfexier", XSPR(31,323, 66), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4648 {"mfbr0", XSPR(31,323,128), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4649 {"mfbr1", XSPR(31,323,129), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4650 {"mfbr2", XSPR(31,323,130), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4651 {"mfbr3", XSPR(31,323,131), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4652 {"mfbr4", XSPR(31,323,132), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4653 {"mfbr5", XSPR(31,323,133), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4654 {"mfbr6", XSPR(31,323,134), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4655 {"mfbr7", XSPR(31,323,135), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4656 {"mfbear", XSPR(31,323,144), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4657 {"mfbesr", XSPR(31,323,145), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4658 {"mfiocr", XSPR(31,323,160), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4659 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4660 {"mfdmact0", XSPR(31,323,193), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4661 {"mfdmada0", XSPR(31,323,194), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4662 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4663 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4664 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4665 {"mfdmact1", XSPR(31,323,201), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4666 {"mfdmada1", XSPR(31,323,202), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4667 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4668 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4669 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4670 {"mfdmact2", XSPR(31,323,209), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4671 {"mfdmada2", XSPR(31,323,210), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4672 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4673 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4674 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4675 {"mfdmact3", XSPR(31,323,217), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4676 {"mfdmada3", XSPR(31,323,218), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4677 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4678 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4679 {"mfdmasr", XSPR(31,323,224), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4680 {"mfdcr", X(31,323), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {RT
, SPR
}},
4681 {"mfdcr.", XRC(31,323,1), X_MASK
, PPCA2
, PPCNONE
, {RT
, SPR
}},
4683 {"lvexwx", X(31,325), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
4685 {"dcread", X(31,326), X_MASK
, PPC476
|TITAN
, PPCNONE
, {RT
, RA0
, RB
}},
4687 {"div", XO(31,331,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4688 {"div.", XO(31,331,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4690 {"lxvdsx", X(31,332), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
4692 {"mfpmr", X(31,334), X_MASK
, PPCPMR
|PPCE300
|PPCVLE
, PPCNONE
, {RT
, PMR
}},
4693 {"mftmr", X(31,366), X_MASK
, PPCTMR
|E6500
, PPCNONE
, {RT
, TMR
}},
4695 {"mfmq", XSPR(31,339, 0), XSPR_MASK
, M601
, PPCNONE
, {RT
}},
4696 {"mfxer", XSPR(31,339, 1), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4697 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK
, COM
, TITAN
, {RT
}},
4698 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK
, COM
, TITAN
, {RT
}},
4699 {"mfdec", XSPR(31,339, 6), XSPR_MASK
, MFDEC1
, PPCNONE
, {RT
}},
4700 {"mflr", XSPR(31,339, 8), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4701 {"mfctr", XSPR(31,339, 9), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4702 {"mftid", XSPR(31,339, 17), XSPR_MASK
, POWER
, PPCNONE
, {RT
}},
4703 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK
, COM
, TITAN
, {RT
}},
4704 {"mfdar", XSPR(31,339, 19), XSPR_MASK
, COM
, TITAN
, {RT
}},
4705 {"mfdec", XSPR(31,339, 22), XSPR_MASK
, MFDEC2
, MFDEC1
, {RT
}},
4706 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK
, POWER
, PPCNONE
, {RT
}},
4707 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK
, COM
, TITAN
, {RT
}},
4708 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK
, COM
, PPCNONE
, {RT
}},
4709 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK
, COM
, PPCNONE
, {RT
}},
4710 {"mfcfar", XSPR(31,339, 28), XSPR_MASK
, POWER6
, PPCNONE
, {RT
}},
4711 {"mfpid", XSPR(31,339, 48), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4712 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4713 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4714 {"mfdear", XSPR(31,339, 61), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4715 {"mfesr", XSPR(31,339, 62), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4716 {"mfivpr", XSPR(31,339, 63), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4717 {"mfcmpa", XSPR(31,339,144), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4718 {"mfcmpb", XSPR(31,339,145), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4719 {"mfcmpc", XSPR(31,339,146), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4720 {"mfcmpd", XSPR(31,339,147), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4721 {"mficr", XSPR(31,339,148), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4722 {"mfder", XSPR(31,339,149), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4723 {"mfcounta", XSPR(31,339,150), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4724 {"mfcountb", XSPR(31,339,151), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4725 {"mfcmpe", XSPR(31,339,152), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4726 {"mfcmpf", XSPR(31,339,153), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4727 {"mfcmpg", XSPR(31,339,154), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4728 {"mfcmph", XSPR(31,339,155), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4729 {"mflctrl1", XSPR(31,339,156), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4730 {"mflctrl2", XSPR(31,339,157), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4731 {"mfictrl", XSPR(31,339,158), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4732 {"mfbar", XSPR(31,339,159), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4733 {"mfvrsave", XSPR(31,339,256), XSPR_MASK
, PPCVEC
, PPCNONE
, {RT
}},
4734 {"mfusprg0", XSPR(31,339,256), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4735 {"mfsprg", XSPR(31,339,256), XSPRG_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, SPRG
}},
4736 {"mfsprg4", XSPR(31,339,260), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4737 {"mfsprg5", XSPR(31,339,261), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4738 {"mfsprg6", XSPR(31,339,262), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4739 {"mfsprg7", XSPR(31,339,263), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4740 {"mftb", XSPR(31,339,268), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4741 {"mftbl", XSPR(31,339,268), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4742 {"mftbu", XSPR(31,339,269), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4743 {"mfsprg0", XSPR(31,339,272), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4744 {"mfsprg1", XSPR(31,339,273), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4745 {"mfsprg2", XSPR(31,339,274), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4746 {"mfsprg3", XSPR(31,339,275), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4747 {"mfasr", XSPR(31,339,280), XSPR_MASK
, PPC64
, PPCNONE
, {RT
}},
4748 {"mfear", XSPR(31,339,282), XSPR_MASK
, PPC
, TITAN
, {RT
}},
4749 {"mfpir", XSPR(31,339,286), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4750 {"mfpvr", XSPR(31,339,287), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4751 {"mfdbsr", XSPR(31,339,304), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4752 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4753 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4754 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4755 {"mfiac1", XSPR(31,339,312), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4756 {"mfiac2", XSPR(31,339,313), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4757 {"mfiac3", XSPR(31,339,314), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4758 {"mfiac4", XSPR(31,339,315), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4759 {"mfdac1", XSPR(31,339,316), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4760 {"mfdac2", XSPR(31,339,317), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4761 {"mfdvc1", XSPR(31,339,318), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4762 {"mfdvc2", XSPR(31,339,319), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4763 {"mftsr", XSPR(31,339,336), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4764 {"mftcr", XSPR(31,339,340), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4765 {"mfivor0", XSPR(31,339,400), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4766 {"mfivor1", XSPR(31,339,401), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4767 {"mfivor2", XSPR(31,339,402), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4768 {"mfivor3", XSPR(31,339,403), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4769 {"mfivor4", XSPR(31,339,404), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4770 {"mfivor5", XSPR(31,339,405), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4771 {"mfivor6", XSPR(31,339,406), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4772 {"mfivor7", XSPR(31,339,407), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4773 {"mfivor8", XSPR(31,339,408), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4774 {"mfivor9", XSPR(31,339,409), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4775 {"mfivor10", XSPR(31,339,410), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4776 {"mfivor11", XSPR(31,339,411), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4777 {"mfivor12", XSPR(31,339,412), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4778 {"mfivor13", XSPR(31,339,413), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4779 {"mfivor14", XSPR(31,339,414), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4780 {"mfivor15", XSPR(31,339,415), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4781 {"mfspefscr", XSPR(31,339,512), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4782 {"mfbbear", XSPR(31,339,513), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RT
}},
4783 {"mfbbtar", XSPR(31,339,514), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RT
}},
4784 {"mfivor32", XSPR(31,339,528), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4785 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4786 {"mfivor33", XSPR(31,339,529), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4787 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4788 {"mfivor34", XSPR(31,339,530), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4789 {"mfivor35", XSPR(31,339,531), XSPR_MASK
, PPCPMR
, PPCNONE
, {RT
}},
4790 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4791 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4792 {"mfic_cst", XSPR(31,339,560), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4793 {"mfic_adr", XSPR(31,339,561), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4794 {"mfic_dat", XSPR(31,339,562), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4795 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4796 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4797 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4798 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RT
}},
4799 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RT
}},
4800 {"mfmcsr", XSPR(31,339,572), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RT
}},
4801 {"mfmcar", XSPR(31,339,573), XSPR_MASK
, PPCRFMCI
, TITAN
, {RT
}},
4802 {"mfdpdr", XSPR(31,339,630), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4803 {"mfdpir", XSPR(31,339,631), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4804 {"mfimmr", XSPR(31,339,638), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4805 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4806 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4807 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4808 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4809 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4810 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4811 {"mfm_casid", XSPR(31,339,793), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4812 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4813 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4814 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4815 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4816 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4817 {"mfm_tw", XSPR(31,339,799), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4818 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4819 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4820 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4821 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4822 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4823 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4824 {"mfivndx", XSPR(31,339,880), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4825 {"mfdvndx", XSPR(31,339,881), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4826 {"mfivlim", XSPR(31,339,882), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4827 {"mfdvlim", XSPR(31,339,883), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4828 {"mfclcsr", XSPR(31,339,884), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4829 {"mfccr1", XSPR(31,339,888), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4830 {"mfppr", XSPR(31,339,896), XSPR_MASK
, POWER7
, PPCNONE
, {RT
}},
4831 {"mfppr32", XSPR(31,339,898), XSPR_MASK
, POWER7
, PPCNONE
, {RT
}},
4832 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4833 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4834 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4835 {"mficdbtr", XSPR(31,339,927), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4836 {"mfummcr0", XSPR(31,339,936), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4837 {"mfupmc1", XSPR(31,339,937), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4838 {"mfupmc2", XSPR(31,339,938), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4839 {"mfusia", XSPR(31,339,939), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4840 {"mfummcr1", XSPR(31,339,940), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4841 {"mfupmc3", XSPR(31,339,941), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4842 {"mfupmc4", XSPR(31,339,942), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4843 {"mfzpr", XSPR(31,339,944), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4844 {"mfpid", XSPR(31,339,945), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4845 {"mfmmucr", XSPR(31,339,946), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4846 {"mfccr0", XSPR(31,339,947), XSPR_MASK
, PPC405
|TITAN
, PPCNONE
, {RT
}},
4847 {"mfiac3", XSPR(31,339,948), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4848 {"mfiac4", XSPR(31,339,949), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4849 {"mfdvc1", XSPR(31,339,950), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4850 {"mfdvc2", XSPR(31,339,951), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4851 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4852 {"mfpmc1", XSPR(31,339,953), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4853 {"mfsgr", XSPR(31,339,953), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4854 {"mfdcwr", XSPR(31,339,954), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4855 {"mfpmc2", XSPR(31,339,954), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4856 {"mfsia", XSPR(31,339,955), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4857 {"mfsler", XSPR(31,339,955), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4858 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4859 {"mfsu0r", XSPR(31,339,956), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4860 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4861 {"mfpmc3", XSPR(31,339,957), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4862 {"mfpmc4", XSPR(31,339,958), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4863 {"mficdbdr", XSPR(31,339,979), XSPR_MASK
, PPC403
|TITAN
, PPCNONE
, {RT
}},
4864 {"mfesr", XSPR(31,339,980), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4865 {"mfdear", XSPR(31,339,981), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4866 {"mfevpr", XSPR(31,339,982), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4867 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4868 {"mftsr", XSPR(31,339,984), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4869 {"mftcr", XSPR(31,339,986), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4870 {"mfpit", XSPR(31,339,987), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4871 {"mftbhi", XSPR(31,339,988), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4872 {"mftblo", XSPR(31,339,989), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4873 {"mfsrr2", XSPR(31,339,990), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4874 {"mfsrr3", XSPR(31,339,991), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4875 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4876 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4877 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
4878 {"mfiac1", XSPR(31,339,1012), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4879 {"mfiac2", XSPR(31,339,1013), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4880 {"mfdac1", XSPR(31,339,1014), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4881 {"mfdac2", XSPR(31,339,1015), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4882 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4883 {"mfdccr", XSPR(31,339,1018), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4884 {"mficcr", XSPR(31,339,1019), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4885 {"mfictc", XSPR(31,339,1019), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4886 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4887 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4888 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4889 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4890 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4891 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4892 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4893 {"mfspr", X(31,339), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, SPR
}},
4895 {"lwax", X(31,341), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4897 {"dst", XDSS(31,342,0), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
4899 {"lhax", X(31,343), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4901 {"lvxl", X(31,359), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4903 {"abs", XO(31,360,0,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
4904 {"abs.", XO(31,360,0,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
4906 {"divs", XO(31,363,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4907 {"divs.", XO(31,363,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4909 {"tlbia", X(31,370), 0xffffffff, PPC
, TITAN
, {0}},
4911 {"mftbl", XSPR(31,371,268), XSPR_MASK
, PPC
, NO371
, {RT
}},
4912 {"mftbu", XSPR(31,371,269), XSPR_MASK
, PPC
, NO371
, {RT
}},
4913 {"mftb", X(31,371), X_MASK
, PPC
|PPCA2
, NO371
|POWER7
, {RT
, TBR
}},
4915 {"lwaux", X(31,373), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4917 {"dstst", XDSS(31,374,0), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
4919 {"lhaux", X(31,375), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4921 {"popcntw", X(31,378), XRB_MASK
, POWER7
|PPCA2
, PPCNONE
, {RA
, RS
}},
4923 {"mtdcrx", X(31,387), X_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {RA
, RS
}},
4924 {"mtdcrx.", XRC(31,387,1), X_MASK
, PPCA2
, PPCNONE
, {RA
, RS
}},
4926 {"stvexbx", X(31,389), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
4928 {"dcblc", X(31,390), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4929 {"stdfcmx", APU(31,391,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4931 {"divdeu", XO(31,393,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4932 {"divdeu.", XO(31,393,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4933 {"divweu", XO(31,395,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4934 {"divweu.", XO(31,395,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4936 {"dcblce", X(31,398), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
4938 {"slbmte", X(31,402), XRA_MASK
, PPC64
, PPCNONE
, {RS
, RB
}},
4940 {"icswx", XRC(31,406,0), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
4941 {"icswx.", XRC(31,406,1), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
4943 {"sthx", X(31,407), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4945 {"orc", XRC(31,412,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4946 {"orc.", XRC(31,412,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4948 {"sthepx", X(31,415), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4950 {"mtdcrux", X(31,419), X_MASK
, PPC464
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4952 {"stvexhx", X(31,421), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
4954 {"dcblq.", XRC(31,422,1), X_MASK
, E6500
, PPCNONE
, {CT
, RA0
, RB
}},
4956 {"divde", XO(31,425,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4957 {"divde.", XO(31,425,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4958 {"divwe", XO(31,427,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4959 {"divwe.", XO(31,427,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4961 {"slbie", X(31,434), XRTRA_MASK
, PPC64
, PPCNONE
, {RB
}},
4963 {"ecowx", X(31,438), X_MASK
, PPC
, TITAN
, {RT
, RA0
, RB
}},
4965 {"sthux", X(31,439), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4967 {"mdors", 0x7f9ce378, 0xffffffff, E500MC
, PPCNONE
, {0}},
4969 {"miso", 0x7f5ad378, 0xffffffff, E6500
, PPCNONE
, {0}},
4971 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
4972 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
4973 {"yield", 0x7f7bdb78, 0xffffffff, POWER7
, PPCNONE
, {0}},
4974 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7
, PPCNONE
, {0}},
4975 {"mdoom", 0x7fdef378, 0xffffffff, POWER7
, PPCNONE
, {0}},
4976 {"mr", XRC(31,444,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RBS
}},
4977 {"or", XRC(31,444,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4978 {"mr.", XRC(31,444,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RBS
}},
4979 {"or.", XRC(31,444,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4981 {"mtexisr", XSPR(31,451, 64), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4982 {"mtexier", XSPR(31,451, 66), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4983 {"mtbr0", XSPR(31,451,128), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4984 {"mtbr1", XSPR(31,451,129), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4985 {"mtbr2", XSPR(31,451,130), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4986 {"mtbr3", XSPR(31,451,131), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4987 {"mtbr4", XSPR(31,451,132), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4988 {"mtbr5", XSPR(31,451,133), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4989 {"mtbr6", XSPR(31,451,134), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4990 {"mtbr7", XSPR(31,451,135), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4991 {"mtbear", XSPR(31,451,144), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4992 {"mtbesr", XSPR(31,451,145), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4993 {"mtiocr", XSPR(31,451,160), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4994 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4995 {"mtdmact0", XSPR(31,451,193), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4996 {"mtdmada0", XSPR(31,451,194), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4997 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4998 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4999 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5000 {"mtdmact1", XSPR(31,451,201), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5001 {"mtdmada1", XSPR(31,451,202), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5002 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5003 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5004 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5005 {"mtdmact2", XSPR(31,451,209), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5006 {"mtdmada2", XSPR(31,451,210), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5007 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5008 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5009 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5010 {"mtdmact3", XSPR(31,451,217), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5011 {"mtdmada3", XSPR(31,451,218), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5012 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5013 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5014 {"mtdmasr", XSPR(31,451,224), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5015 {"mtdcr", X(31,451), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {SPR
, RS
}},
5016 {"mtdcr.", XRC(31,451,1), X_MASK
, PPCA2
, PPCNONE
, {SPR
, RS
}},
5018 {"stvexwx", X(31,453), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5020 {"dccci", X(31,454), XRT_MASK
, PPC403
|PPC440
|TITAN
|PPCA2
, PPCNONE
, {RAOPT
, RBOPT
}},
5021 {"dci", X(31,454), XRARB_MASK
, PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {CT
}},
5023 {"divdu", XO(31,457,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5024 {"divdu.", XO(31,457,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5026 {"divwu", XO(31,459,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5027 {"divwu.", XO(31,459,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5029 {"mtpmr", X(31,462), X_MASK
, PPCPMR
|PPCE300
|PPCVLE
, PPCNONE
, {PMR
, RS
}},
5030 {"mttmr", X(31,494), X_MASK
, PPCTMR
|E6500
, PPCNONE
, {TMR
, RS
}},
5032 {"mtmq", XSPR(31,467, 0), XSPR_MASK
, M601
, PPCNONE
, {RS
}},
5033 {"mtxer", XSPR(31,467, 1), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5034 {"mtlr", XSPR(31,467, 8), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5035 {"mtctr", XSPR(31,467, 9), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5036 {"mttid", XSPR(31,467, 17), XSPR_MASK
, POWER
, PPCNONE
, {RS
}},
5037 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK
, COM
, TITAN
, {RS
}},
5038 {"mtdar", XSPR(31,467, 19), XSPR_MASK
, COM
, TITAN
, {RS
}},
5039 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK
, COM
, TITAN
, {RS
}},
5040 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK
, COM
, TITAN
, {RS
}},
5041 {"mtdec", XSPR(31,467, 22), XSPR_MASK
, COM
, PPCNONE
, {RS
}},
5042 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK
, POWER
, PPCNONE
, {RS
}},
5043 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK
, COM
, TITAN
, {RS
}},
5044 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5045 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5046 {"mtcfar", XSPR(31,467, 28), XSPR_MASK
, POWER6
, PPCNONE
, {RS
}},
5047 {"mtpid", XSPR(31,467, 48), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5048 {"mtdecar", XSPR(31,467, 54), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5049 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5050 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5051 {"mtdear", XSPR(31,467, 61), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5052 {"mtesr", XSPR(31,467, 62), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5053 {"mtivpr", XSPR(31,467, 63), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5054 {"mtcmpa", XSPR(31,467,144), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5055 {"mtcmpb", XSPR(31,467,145), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5056 {"mtcmpc", XSPR(31,467,146), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5057 {"mtcmpd", XSPR(31,467,147), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5058 {"mticr", XSPR(31,467,148), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5059 {"mtder", XSPR(31,467,149), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5060 {"mtcounta", XSPR(31,467,150), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5061 {"mtcountb", XSPR(31,467,151), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5062 {"mtcmpe", XSPR(31,467,152), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5063 {"mtcmpf", XSPR(31,467,153), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5064 {"mtcmpg", XSPR(31,467,154), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5065 {"mtcmph", XSPR(31,467,155), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5066 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5067 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5068 {"mtictrl", XSPR(31,467,158), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5069 {"mtbar", XSPR(31,467,159), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5070 {"mtvrsave", XSPR(31,467,256), XSPR_MASK
, PPCVEC
, PPCNONE
, {RS
}},
5071 {"mtusprg0", XSPR(31,467,256), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5072 {"mtsprg", XSPR(31,467,256), XSPRG_MASK
, PPC
|PPCVLE
, PPCNONE
, {SPRG
, RS
}},
5073 {"mtsprg0", XSPR(31,467,272), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5074 {"mtsprg1", XSPR(31,467,273), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5075 {"mtsprg2", XSPR(31,467,274), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5076 {"mtsprg3", XSPR(31,467,275), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5077 {"mtsprg4", XSPR(31,467,276), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5078 {"mtsprg5", XSPR(31,467,277), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5079 {"mtsprg6", XSPR(31,467,278), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5080 {"mtsprg7", XSPR(31,467,279), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5081 {"mtasr", XSPR(31,467,280), XSPR_MASK
, PPC64
, PPCNONE
, {RS
}},
5082 {"mtear", XSPR(31,467,282), XSPR_MASK
, PPC
, TITAN
, {RS
}},
5083 {"mttbl", XSPR(31,467,284), XSPR_MASK
, PPC
, PPCNONE
, {RS
}},
5084 {"mttbu", XSPR(31,467,285), XSPR_MASK
, PPC
, PPCNONE
, {RS
}},
5085 {"mtdbsr", XSPR(31,467,304), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5086 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5087 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5088 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5089 {"mtiac1", XSPR(31,467,312), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5090 {"mtiac2", XSPR(31,467,313), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5091 {"mtiac3", XSPR(31,467,314), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5092 {"mtiac4", XSPR(31,467,315), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5093 {"mtdac1", XSPR(31,467,316), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5094 {"mtdac2", XSPR(31,467,317), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5095 {"mtdvc1", XSPR(31,467,318), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5096 {"mtdvc2", XSPR(31,467,319), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5097 {"mttsr", XSPR(31,467,336), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5098 {"mttcr", XSPR(31,467,340), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5099 {"mtivor0", XSPR(31,467,400), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5100 {"mtivor1", XSPR(31,467,401), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5101 {"mtivor2", XSPR(31,467,402), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5102 {"mtivor3", XSPR(31,467,403), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5103 {"mtivor4", XSPR(31,467,404), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5104 {"mtivor5", XSPR(31,467,405), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5105 {"mtivor6", XSPR(31,467,406), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5106 {"mtivor7", XSPR(31,467,407), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5107 {"mtivor8", XSPR(31,467,408), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5108 {"mtivor9", XSPR(31,467,409), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5109 {"mtivor10", XSPR(31,467,410), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5110 {"mtivor11", XSPR(31,467,411), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5111 {"mtivor12", XSPR(31,467,412), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5112 {"mtivor13", XSPR(31,467,413), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5113 {"mtivor14", XSPR(31,467,414), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5114 {"mtivor15", XSPR(31,467,415), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5115 {"mtspefscr", XSPR(31,467,512), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5116 {"mtbbear", XSPR(31,467,513), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RS
}},
5117 {"mtbbtar", XSPR(31,467,514), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RS
}},
5118 {"mtivor32", XSPR(31,467,528), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5119 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5120 {"mtivor33", XSPR(31,467,529), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5121 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5122 {"mtivor34", XSPR(31,467,530), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5123 {"mtivor35", XSPR(31,467,531), XSPR_MASK
, PPCPMR
, PPCNONE
, {RS
}},
5124 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5125 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5126 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK
, PPCRFMCI
|PPCVLE
, PPCNONE
, {RS
}},
5127 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK
, PPCRFMCI
|PPCVLE
, PPCNONE
, {RS
}},
5128 {"mtmcsr", XSPR(31,467,572), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RS
}},
5129 {"mtivndx", XSPR(31,467,880), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5130 {"mtdvndx", XSPR(31,467,881), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5131 {"mtivlim", XSPR(31,467,882), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5132 {"mtdvlim", XSPR(31,467,883), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5133 {"mtclcsr", XSPR(31,467,884), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5134 {"mtccr1", XSPR(31,467,888), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5135 {"mtppr", XSPR(31,467,896), XSPR_MASK
, POWER7
, PPCNONE
, {RS
}},
5136 {"mtppr32", XSPR(31,467,898), XSPR_MASK
, POWER7
, PPCNONE
, {RS
}},
5137 {"mtummcr0", XSPR(31,467,936), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5138 {"mtupmc1", XSPR(31,467,937), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5139 {"mtupmc2", XSPR(31,467,938), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5140 {"mtusia", XSPR(31,467,939), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5141 {"mtummcr1", XSPR(31,467,940), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5142 {"mtupmc3", XSPR(31,467,941), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5143 {"mtupmc4", XSPR(31,467,942), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5144 {"mtzpr", XSPR(31,467,944), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5145 {"mtpid", XSPR(31,467,945), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5146 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5147 {"mtccr0", XSPR(31,467,947), XSPR_MASK
, PPC405
|TITAN
, PPCNONE
, {RS
}},
5148 {"mtiac3", XSPR(31,467,948), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5149 {"mtiac4", XSPR(31,467,949), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5150 {"mtdvc1", XSPR(31,467,950), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5151 {"mtdvc2", XSPR(31,467,951), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5152 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5153 {"mtpmc1", XSPR(31,467,953), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5154 {"mtsgr", XSPR(31,467,953), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5155 {"mtdcwr", XSPR(31,467,954), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5156 {"mtpmc2", XSPR(31,467,954), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5157 {"mtsia", XSPR(31,467,955), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5158 {"mtsler", XSPR(31,467,955), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5159 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5160 {"mtsu0r", XSPR(31,467,956), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5161 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5162 {"mtpmc3", XSPR(31,467,957), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5163 {"mtpmc4", XSPR(31,467,958), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5164 {"mticdbdr", XSPR(31,467,979), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5165 {"mtesr", XSPR(31,467,980), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5166 {"mtdear", XSPR(31,467,981), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5167 {"mtevpr", XSPR(31,467,982), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5168 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5169 {"mttsr", XSPR(31,467,984), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5170 {"mttcr", XSPR(31,467,986), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5171 {"mtpit", XSPR(31,467,987), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5172 {"mttbhi", XSPR(31,467,988), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5173 {"mttblo", XSPR(31,467,989), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5174 {"mtsrr2", XSPR(31,467,990), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5175 {"mtsrr3", XSPR(31,467,991), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5176 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5177 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5178 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5179 {"mtiac1", XSPR(31,467,1012), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5180 {"mtiac2", XSPR(31,467,1013), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5181 {"mtdac1", XSPR(31,467,1014), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5182 {"mtdac2", XSPR(31,467,1015), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5183 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5184 {"mtdccr", XSPR(31,467,1018), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5185 {"mticcr", XSPR(31,467,1019), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5186 {"mtictc", XSPR(31,467,1019), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5187 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5188 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5189 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5190 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5191 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5192 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5193 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5194 {"mtspr", X(31,467), X_MASK
, COM
|PPCVLE
, PPCNONE
, {SPR
, RS
}},
5196 {"dcbi", X(31,470), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5198 {"nand", XRC(31,476,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5199 {"nand.", XRC(31,476,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5201 {"dsn", X(31,483), XRT_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RA
, RB
}},
5203 {"dcread", X(31,486), X_MASK
, PPC403
|PPC440
|PPCVLE
, PPCA2
|PPC476
, {RT
, RA0
, RB
}},
5205 {"icbtls", X(31,486), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
5207 {"stvxl", X(31,487), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VS
, RA0
, RB
}},
5209 {"nabs", XO(31,488,0,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5210 {"nabs.", XO(31,488,0,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5212 {"divd", XO(31,489,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5213 {"divd.", XO(31,489,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5215 {"divw", XO(31,491,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5216 {"divw.", XO(31,491,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5218 {"icbtlse", X(31,494), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
5220 {"slbia", X(31,498), 0xffffffff, PPC64
, PPCNONE
, {0}},
5222 {"cli", X(31,502), XRB_MASK
, POWER
, PPCNONE
, {RT
, RA
}},
5224 {"popcntd", X(31,506), XRB_MASK
, POWER7
|PPCA2
, PPCNONE
, {RA
, RS
}},
5226 {"cmpb", X(31,508), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {RA
, RS
, RB
}},
5228 {"mcrxr", X(31,512), XRARB_MASK
|(3<<21), COM
|PPCVLE
, POWER7
, {BF
}},
5230 {"lbdx", X(31,515), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5232 {"bblels", X(31,518), X_MASK
, PPCBRLK
, PPCNONE
, {0}},
5234 {"lvlx", X(31,519), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5235 {"lbfcmux", APU(31,519,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5237 {"subfco", XO(31,8,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5238 {"sfo", XO(31,8,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5239 {"subco", XO(31,8,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
5240 {"subfco.", XO(31,8,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5241 {"sfo.", XO(31,8,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5242 {"subco.", XO(31,8,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
5244 {"addco", XO(31,10,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5245 {"ao", XO(31,10,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5246 {"addco.", XO(31,10,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5247 {"ao.", XO(31,10,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5249 {"clcs", X(31,531), XRB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5251 {"ldbrx", X(31,532), X_MASK
, CELL
|POWER7
|PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
5253 {"lswx", X(31,533), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RT
, RAX
, RBX
}},
5254 {"lsx", X(31,533), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5256 {"lwbrx", X(31,534), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5257 {"lbrx", X(31,534), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5259 {"lfsx", X(31,535), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
5261 {"srw", XRC(31,536,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5262 {"sr", XRC(31,536,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5263 {"srw.", XRC(31,536,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5264 {"sr.", XRC(31,536,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5266 {"rrib", XRC(31,537,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5267 {"rrib.", XRC(31,537,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5269 {"srd", XRC(31,539,0), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5270 {"srd.", XRC(31,539,1), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5272 {"maskir", XRC(31,541,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5273 {"maskir.", XRC(31,541,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5275 {"lhdx", X(31,547), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5277 {"lvtrx", X(31,549), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5279 {"bbelr", X(31,550), X_MASK
, PPCBRLK
, PPCNONE
, {0}},
5281 {"lvrx", X(31,551), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5282 {"lhfcmux", APU(31,551,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5284 {"subfo", XO(31,40,1,0), XO_MASK
, PPC
, PPCNONE
, {RT
, RA
, RB
}},
5285 {"subo", XO(31,40,1,0), XO_MASK
, PPC
, PPCNONE
, {RT
, RB
, RA
}},
5286 {"subfo.", XO(31,40,1,1), XO_MASK
, PPC
, PPCNONE
, {RT
, RA
, RB
}},
5287 {"subo.", XO(31,40,1,1), XO_MASK
, PPC
, PPCNONE
, {RT
, RB
, RA
}},
5289 {"tlbsync", X(31,566), 0xffffffff, PPC
|PPCVLE
, PPCNONE
, {0}},
5291 {"lfsux", X(31,567), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
5293 {"lwdx", X(31,579), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5295 {"lvtlx", X(31,581), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5297 {"lwfcmux", APU(31,583,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5299 {"lxsdx", X(31,588), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5301 {"mfsr", X(31,595), XRB_MASK
|(1<<20), COM
, NON32
, {RT
, SR
}},
5303 {"lswi", X(31,597), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RT
, RAX
, NBI
}},
5304 {"lsi", X(31,597), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA0
, NB
}},
5306 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC
, E500
, {0}},
5307 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64
, PPCNONE
, {0}},
5308 {"sync", X(31,598), XSYNCLE_MASK
,E6500
, PPCNONE
, {LS
, ESYNC
}},
5309 {"sync", X(31,598), XSYNC_MASK
, PPCCOM
|PPCVLE
, BOOKE
|PPC476
, {LS
}},
5310 {"msync", X(31,598), 0xffffffff, BOOKE
|PPCA2
|PPC476
, PPCNONE
, {0}},
5311 {"sync", X(31,598), 0xffffffff, BOOKE
|PPC476
, E6500
, {0}},
5312 {"lwsync", X(31,598), 0xffffffff, E500
, PPCNONE
, {0}},
5313 {"dcs", X(31,598), 0xffffffff, PWRCOM
, PPCNONE
, {0}},
5315 {"lfdx", X(31,599), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
5317 {"mffgpr", XRC(31,607,0), XRA_MASK
, POWER6
, POWER7
, {FRT
, RB
}},
5318 {"lfdepx", X(31,607), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {FRT
, RA0
, RB
}},
5320 {"lddx", X(31,611), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5322 {"lvswx", X(31,613), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5324 {"lqfcmux", APU(31,615,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5326 {"nego", XO(31,104,1,0), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5327 {"nego.", XO(31,104,1,1), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5329 {"mulo", XO(31,107,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5330 {"mulo.", XO(31,107,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5332 {"mfsri", X(31,627), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5334 {"dclst", X(31,630), XRB_MASK
, M601
, PPCNONE
, {RS
, RA
}},
5336 {"lfdux", X(31,631), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
5338 {"stbdx", X(31,643), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5340 {"stvlx", X(31,647), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5341 {"stbfcmux", APU(31,647,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5343 {"subfeo", XO(31,136,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5344 {"sfeo", XO(31,136,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5345 {"subfeo.", XO(31,136,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5346 {"sfeo.", XO(31,136,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5348 {"addeo", XO(31,138,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5349 {"aeo", XO(31,138,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5350 {"addeo.", XO(31,138,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5351 {"aeo.", XO(31,138,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5353 {"mfsrin", X(31,659), XRA_MASK
, PPC
, NON32
, {RT
, RB
}},
5355 {"stdbrx", X(31,660), X_MASK
, CELL
|POWER7
|PPCA2
, PPCNONE
, {RS
, RA0
, RB
}},
5357 {"stswx", X(31,661), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RS
, RA0
, RB
}},
5358 {"stsx", X(31,661), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, RB
}},
5360 {"stwbrx", X(31,662), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
5361 {"stbrx", X(31,662), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, RB
}},
5363 {"stfsx", X(31,663), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
5365 {"srq", XRC(31,664,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5366 {"srq.", XRC(31,664,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5368 {"sre", XRC(31,665,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5369 {"sre.", XRC(31,665,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5371 {"sthdx", X(31,675), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5373 {"stvfrx", X(31,677), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5375 {"stvrx", X(31,679), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5376 {"sthfcmux", APU(31,679,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5378 {"stbcx.", XRC(31,694,1), X_MASK
, POWER7
, PPCNONE
, {RS
, RA0
, RB
}},
5380 {"stfsux", X(31,695), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
5382 {"sriq", XRC(31,696,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5383 {"sriq.", XRC(31,696,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5385 {"stwdx", X(31,707), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5387 {"stvflx", X(31,709), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5389 {"stwfcmux", APU(31,711,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5391 {"stxsdx", X(31,716), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5393 {"subfzeo", XO(31,200,1,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5394 {"sfzeo", XO(31,200,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5395 {"subfzeo.", XO(31,200,1,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5396 {"sfzeo.", XO(31,200,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5398 {"addzeo", XO(31,202,1,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5399 {"azeo", XO(31,202,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5400 {"addzeo.", XO(31,202,1,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5401 {"azeo.", XO(31,202,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5403 {"stswi", X(31,725), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RS
, RA0
, NB
}},
5404 {"stsi", X(31,725), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, NB
}},
5406 {"sthcx.", XRC(31,726,1), X_MASK
, POWER7
, PPCNONE
, {RS
, RA0
, RB
}},
5408 {"stfdx", X(31,727), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
5410 {"srlq", XRC(31,728,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5411 {"srlq.", XRC(31,728,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5413 {"sreq", XRC(31,729,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5414 {"sreq.", XRC(31,729,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5416 {"mftgpr", XRC(31,735,0), XRA_MASK
, POWER6
, POWER7
, {RT
, FRB
}},
5417 {"stfdepx", X(31,735), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {FRS
, RA0
, RB
}},
5419 {"stddx", X(31,739), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5421 {"stvswx", X(31,741), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5423 {"stqfcmux", APU(31,743,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5425 {"subfmeo", XO(31,232,1,0), XORB_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
}},
5426 {"sfmeo", XO(31,232,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5427 {"subfmeo.", XO(31,232,1,1), XORB_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
}},
5428 {"sfmeo.", XO(31,232,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5430 {"mulldo", XO(31,233,1,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5431 {"mulldo.", XO(31,233,1,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5433 {"addmeo", XO(31,234,1,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5434 {"ameo", XO(31,234,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5435 {"addmeo.", XO(31,234,1,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5436 {"ameo.", XO(31,234,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5438 {"mullwo", XO(31,235,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5439 {"mulso", XO(31,235,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5440 {"mullwo.", XO(31,235,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5441 {"mulso.", XO(31,235,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5443 {"dcba", X(31,758), XRT_MASK
, PPC405
|PPC7450
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5444 {"dcbal", XOPL(31,758,1), XRT_MASK
, E500MC
, PPCNONE
, {RA0
, RB
}},
5446 {"stfdux", X(31,759), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
5448 {"srliq", XRC(31,760,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5449 {"srliq.", XRC(31,760,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5451 {"lvsm", X(31,773), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5452 {"stvepxl", X(31,775), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5453 {"lvlxl", X(31,775), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5454 {"ldfcmux", APU(31,775,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5456 {"dozo", XO(31,264,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5457 {"dozo.", XO(31,264,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5459 {"addo", XO(31,266,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5460 {"caxo", XO(31,266,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5461 {"addo.", XO(31,266,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5462 {"caxo.", XO(31,266,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5464 {"lxvw4x", X(31,780), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5466 {"tlbivax", X(31,786), XRT_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5468 {"lwzcix", X(31,789), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5470 {"lhbrx", X(31,790), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5472 {"lfdpx", X(31,791), X_MASK
, POWER6
, POWER7
, {FRTp
, RA0
, RB
}},
5473 {"lfqx", X(31,791), X_MASK
, POWER2
, PPCNONE
, {FRT
, RA
, RB
}},
5475 {"sraw", XRC(31,792,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5476 {"sra", XRC(31,792,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5477 {"sraw.", XRC(31,792,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5478 {"sra.", XRC(31,792,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5480 {"srad", XRC(31,794,0), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5481 {"srad.", XRC(31,794,1), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5483 {"lfddx", X(31,803), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {FRT
, RA
, RB
}},
5485 {"lvtrxl", X(31,805), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5486 {"stvepx", X(31,807), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5487 {"lvrxl", X(31,807), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5489 {"rac", X(31,818), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5491 {"erativax", X(31,819), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA0
, RB
}},
5493 {"lhzcix", X(31,821), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5495 {"dss", XDSS(31,822,0), XDSS_MASK
, PPCVEC
, PPCNONE
, {STRM
}},
5497 {"lfqux", X(31,823), X_MASK
, POWER2
, PPCNONE
, {FRT
, RA
, RB
}},
5499 {"srawi", XRC(31,824,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
5500 {"srai", XRC(31,824,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
}},
5501 {"srawi.", XRC(31,824,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
5502 {"srai.", XRC(31,824,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
}},
5504 {"sradi", XS(31,413,0), XS_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
, SH6
}},
5505 {"sradi.", XS(31,413,1), XS_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
, SH6
}},
5507 {"lvtlxl", X(31,837), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5509 {"divo", XO(31,331,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5510 {"divo.", XO(31,331,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5512 {"lxvd2x", X(31,844), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5514 {"tlbsrx.", XRC(31,850,1), XRT_MASK
, PPCA2
, PPCNONE
, {RA0
, RB
}},
5516 {"slbmfev", X(31,851), XRA_MASK
, PPC64
, PPCNONE
, {RT
, RB
}},
5518 {"lbzcix", X(31,853), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5520 {"eieio", X(31,854), 0xffffffff, PPC
, BOOKE
|PPCA2
|PPC476
, {0}},
5521 {"mbar", X(31,854), X_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {MO
}},
5522 {"eieio", XMBAR(31,854,1),0xffffffff, E500
, PPCNONE
, {0}},
5523 {"eieio", X(31,854), 0xffffffff, PPCA2
|PPC476
, PPCNONE
, {0}},
5525 {"lfiwax", X(31,855), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FRT
, RA0
, RB
}},
5527 {"lvswxl", X(31,869), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5529 {"abso", XO(31,360,1,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5530 {"abso.", XO(31,360,1,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5532 {"divso", XO(31,363,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5533 {"divso.", XO(31,363,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5535 {"ldcix", X(31,885), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5537 {"lfiwzx", X(31,887), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, RA0
, RB
}},
5539 {"stvlxl", X(31,903), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5540 {"stdfcmux", APU(31,903,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5542 {"divdeuo", XO(31,393,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5543 {"divdeuo.", XO(31,393,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5544 {"divweuo", XO(31,395,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5545 {"divweuo.", XO(31,395,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5547 {"stxvw4x", X(31,908), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5549 {"tlbsx", XRC(31,914,0), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RTO
, RA0
, RB
}},
5550 {"tlbsx.", XRC(31,914,1), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RTO
, RA0
, RB
}},
5552 {"slbmfee", X(31,915), XRA_MASK
, PPC64
, PPCNONE
, {RT
, RB
}},
5554 {"stwcix", X(31,917), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5556 {"sthbrx", X(31,918), X_MASK
, COM
, PPCNONE
, {RS
, RA0
, RB
}},
5558 {"stfdpx", X(31,919), X_MASK
, POWER6
, POWER7
, {FRSp
, RA0
, RB
}},
5559 {"stfqx", X(31,919), X_MASK
, POWER2
, PPCNONE
, {FRS
, RA0
, RB
}},
5561 {"sraq", XRC(31,920,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5562 {"sraq.", XRC(31,920,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5564 {"srea", XRC(31,921,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5565 {"srea.", XRC(31,921,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5567 {"extsh", XRC(31,922,0), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5568 {"exts", XRC(31,922,0), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
5569 {"extsh.", XRC(31,922,1), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5570 {"exts.", XRC(31,922,1), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
5572 {"stfddx", X(31,931), X_MASK
, E500MC
, PPCNONE
, {FRS
, RA
, RB
}},
5574 {"stvfrxl", X(31,933), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5576 {"wclrone", XOPL2(31,934,2),XRT_MASK
, PPCA2
, PPCNONE
, {RA0
, RB
}},
5577 {"wclrall", X(31,934), XRARB_MASK
, PPCA2
, PPCNONE
, {L
}},
5578 {"wclr", X(31,934), X_MASK
, PPCA2
, PPCNONE
, {L
, RA0
, RB
}},
5580 {"stvrxl", X(31,935), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5582 {"divdeo", XO(31,425,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5583 {"divdeo.", XO(31,425,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5584 {"divweo", XO(31,427,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5585 {"divweo.", XO(31,427,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5587 {"tlbrehi", XTLB(31,946,0), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
5588 {"tlbrelo", XTLB(31,946,1), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
5589 {"tlbre", X(31,946), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RSO
, RAOPT
, SHO
}},
5591 {"sthcix", X(31,949), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5593 {"icswepx", XRC(31,950,0), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5594 {"icswepx.", XRC(31,950,1), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5596 {"stfqux", X(31,951), X_MASK
, POWER2
, PPCNONE
, {FRS
, RA
, RB
}},
5598 {"sraiq", XRC(31,952,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5599 {"sraiq.", XRC(31,952,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5601 {"extsb", XRC(31,954,0), XRB_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5602 {"extsb.", XRC(31,954,1), XRB_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5604 {"stvflxl", X(31,965), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5606 {"iccci", X(31,966), XRT_MASK
, PPC403
|PPC440
|TITAN
|PPCA2
, PPCNONE
, {RAOPT
, RBOPT
}},
5607 {"ici", X(31,966), XRARB_MASK
, PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {CT
}},
5609 {"divduo", XO(31,457,1,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5610 {"divduo.", XO(31,457,1,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5612 {"divwuo", XO(31,459,1,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5613 {"divwuo.", XO(31,459,1,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5615 {"stxvd2x", X(31,972), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5617 {"tlbld", X(31,978), XRTRA_MASK
, PPC
, PPC403
|BOOKE
|PPCA2
|PPC476
, {RB
}},
5618 {"tlbwehi", XTLB(31,978,0), XTLB_MASK
, PPC403
, PPCNONE
, {RT
, RA
}},
5619 {"tlbwelo", XTLB(31,978,1), XTLB_MASK
, PPC403
, PPCNONE
, {RT
, RA
}},
5620 {"tlbwe", X(31,978), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RSO
, RAOPT
, SHO
}},
5622 {"stbcix", X(31,981), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5624 {"icbi", X(31,982), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5626 {"stfiwx", X(31,983), X_MASK
, PPC
, PPCEFS
, {FRS
, RA0
, RB
}},
5628 {"extsw", XRC(31,986,0), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5629 {"extsw.", XRC(31,986,1), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5631 {"icbiep", XRT(31,991,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5633 {"stvswxl", X(31,997), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5635 {"icread", X(31,998), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5637 {"nabso", XO(31,488,1,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5638 {"nabso.", XO(31,488,1,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5640 {"divdo", XO(31,489,1,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5641 {"divdo.", XO(31,489,1,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5643 {"divwo", XO(31,491,1,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5644 {"divwo.", XO(31,491,1,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5647 {"tlbli", X(31,1010), XRTRA_MASK
, PPC
, TITAN
, {RB
}},
5649 {"stdcix", X(31,1013), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5651 {"dcbz", X(31,1014), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5652 {"dclz", X(31,1014), XRT_MASK
, PPC
, PPCNONE
, {RA0
, RB
}},
5654 {"dcbzep", XRT(31,1023,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5656 {"dcbzl", XOPL(31,1014,1), XRT_MASK
, POWER4
|E500MC
, PPC476
, {RA0
, RB
}},
5658 {"cctpl", 0x7c210b78, 0xffffffff, CELL
, PPCNONE
, {0}},
5659 {"cctpm", 0x7c421378, 0xffffffff, CELL
, PPCNONE
, {0}},
5660 {"cctph", 0x7c631b78, 0xffffffff, CELL
, PPCNONE
, {0}},
5662 {"dstt", XDSS(31,342,1), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5663 {"dststt", XDSS(31,374,1), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5664 {"dssall", XDSS(31,822,1), XDSS_MASK
, PPCVEC
, PPCNONE
, {0}},
5666 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL
, PPCNONE
, {0}},
5667 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL
, PPCNONE
, {0}},
5668 {"db12cyc", 0x7fdef378, 0xffffffff, CELL
, PPCNONE
, {0}},
5669 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL
, PPCNONE
, {0}},
5671 {"lwz", OP(32), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RA0
}},
5672 {"l", OP(32), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
5674 {"lwzu", OP(33), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RAL
}},
5675 {"lu", OP(33), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
5677 {"lbz", OP(34), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RA0
}},
5679 {"lbzu", OP(35), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RAL
}},
5681 {"stw", OP(36), OP_MASK
, PPCCOM
, PPCNONE
, {RS
, D
, RA0
}},
5682 {"st", OP(36), OP_MASK
, PWRCOM
, PPCNONE
, {RS
, D
, RA0
}},
5684 {"stwu", OP(37), OP_MASK
, PPCCOM
, PPCNONE
, {RS
, D
, RAS
}},
5685 {"stu", OP(37), OP_MASK
, PWRCOM
, PPCNONE
, {RS
, D
, RA0
}},
5687 {"stb", OP(38), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RA0
}},
5689 {"stbu", OP(39), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RAS
}},
5691 {"lhz", OP(40), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RA0
}},
5693 {"lhzu", OP(41), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RAL
}},
5695 {"lha", OP(42), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RA0
}},
5697 {"lhau", OP(43), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RAL
}},
5699 {"sth", OP(44), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RA0
}},
5701 {"sthu", OP(45), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RAS
}},
5703 {"lmw", OP(46), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RAM
}},
5704 {"lm", OP(46), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
5706 {"stmw", OP(47), OP_MASK
, PPCCOM
, PPCNONE
, {RS
, D
, RA0
}},
5707 {"stm", OP(47), OP_MASK
, PWRCOM
, PPCNONE
, {RS
, D
, RA0
}},
5709 {"lfs", OP(48), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RA0
}},
5711 {"lfsu", OP(49), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RAS
}},
5713 {"lfd", OP(50), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RA0
}},
5715 {"lfdu", OP(51), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RAS
}},
5717 {"stfs", OP(52), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RA0
}},
5719 {"stfsu", OP(53), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RAS
}},
5721 {"stfd", OP(54), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RA0
}},
5723 {"stfdu", OP(55), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RAS
}},
5725 {"lq", OP(56), OP_MASK
, POWER4
, PPC476
, {RTQ
, DQ
, RAQ
}},
5726 {"psq_l", OP(56), OP_MASK
, PPCPS
, PPCNONE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
5727 {"lfq", OP(56), OP_MASK
, POWER2
, PPCNONE
, {FRT
, D
, RA0
}},
5729 {"lfdp", OP(57), OP_MASK
, POWER6
, POWER7
, {FRTp
, D
, RA0
}},
5730 {"psq_lu", OP(57), OP_MASK
, PPCPS
, PPCNONE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
5731 {"lfqu", OP(57), OP_MASK
, POWER2
, PPCNONE
, {FRT
, D
, RA0
}},
5733 {"ld", DSO(58,0), DS_MASK
, PPC64
, PPCNONE
, {RT
, DS
, RA0
}},
5734 {"ldu", DSO(58,1), DS_MASK
, PPC64
, PPCNONE
, {RT
, DS
, RAL
}},
5735 {"lwa", DSO(58,2), DS_MASK
, PPC64
, PPCNONE
, {RT
, DS
, RA0
}},
5737 {"dadd", XRC(59,2,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5738 {"dadd.", XRC(59,2,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5740 {"dqua", ZRC(59,3,0), Z2_MASK
, POWER6
, PPCNONE
, {FRT
,FRA
,FRB
,RMC
}},
5741 {"dqua.", ZRC(59,3,1), Z2_MASK
, POWER6
, PPCNONE
, {FRT
,FRA
,FRB
,RMC
}},
5743 {"fdivs", A(59,18,0), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5744 {"fdivs.", A(59,18,1), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5746 {"fsubs", A(59,20,0), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5747 {"fsubs.", A(59,20,1), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5749 {"fadds", A(59,21,0), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5750 {"fadds.", A(59,21,1), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5752 {"fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, TITAN
, {FRT
, FRB
}},
5753 {"fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, TITAN
, {FRT
, FRB
}},
5755 {"fres", A(59,24,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5756 {"fres", A(59,24,0), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
5757 {"fres.", A(59,24,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5758 {"fres.", A(59,24,1), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
5760 {"fmuls", A(59,25,0), AFRB_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
}},
5761 {"fmuls.", A(59,25,1), AFRB_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
}},
5763 {"frsqrtes", A(59,26,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5764 {"frsqrtes", A(59,26,0), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
5765 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5766 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
5768 {"fmsubs", A(59,28,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5769 {"fmsubs.", A(59,28,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5771 {"fmadds", A(59,29,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5772 {"fmadds.", A(59,29,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5774 {"fnmsubs", A(59,30,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5775 {"fnmsubs.", A(59,30,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5777 {"fnmadds", A(59,31,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5778 {"fnmadds.", A(59,31,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5780 {"dmul", XRC(59,34,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5781 {"dmul.", XRC(59,34,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5783 {"drrnd", ZRC(59,35,0), Z2_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
, RMC
}},
5784 {"drrnd.", ZRC(59,35,1), Z2_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
, RMC
}},
5786 {"dscli", ZRC(59,66,0), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5787 {"dscli.", ZRC(59,66,1), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5789 {"dquai", ZRC(59,67,0), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRT
,FRB
,RMC
}},
5790 {"dquai.", ZRC(59,67,1), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRT
,FRB
,RMC
}},
5792 {"dscri", ZRC(59,98,0), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5793 {"dscri.", ZRC(59,98,1), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5795 {"drintx", ZRC(59,99,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5796 {"drintx.", ZRC(59,99,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5798 {"dcmpo", X(59,130), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
5800 {"dtstex", X(59,162), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
5801 {"dtstdc", Z(59,194), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, DCM
}},
5802 {"dtstdg", Z(59,226), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, DGM
}},
5804 {"drintn", ZRC(59,227,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5805 {"drintn.", ZRC(59,227,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5807 {"dctdp", XRC(59,258,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5808 {"dctdp.", XRC(59,258,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5810 {"dctfix", XRC(59,290,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5811 {"dctfix.", XRC(59,290,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5813 {"ddedpd", XRC(59,322,0), X_MASK
, POWER6
, PPCNONE
, {SP
, FRT
, FRB
}},
5814 {"ddedpd.", XRC(59,322,1), X_MASK
, POWER6
, PPCNONE
, {SP
, FRT
, FRB
}},
5816 {"dxex", XRC(59,354,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5817 {"dxex.", XRC(59,354,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5819 {"dsub", XRC(59,514,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5820 {"dsub.", XRC(59,514,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5822 {"ddiv", XRC(59,546,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5823 {"ddiv.", XRC(59,546,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5825 {"dcmpu", X(59,642), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
5827 {"dtstsf", X(59,674), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
5829 {"drsp", XRC(59,770,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5830 {"drsp.", XRC(59,770,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5832 {"dcffix", XRC(59,802,0), X_MASK
|FRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5833 {"dcffix.", XRC(59,802,1), X_MASK
|FRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5835 {"denbcd", XRC(59,834,0), X_MASK
, POWER6
, PPCNONE
, {S
, FRT
, FRB
}},
5836 {"denbcd.", XRC(59,834,1), X_MASK
, POWER6
, PPCNONE
, {S
, FRT
, FRB
}},
5838 {"fcfids", XRC(59,846,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
5839 {"fcfids.", XRC(59,846,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
5841 {"diex", XRC(59,866,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5842 {"diex.", XRC(59,866,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5844 {"fcfidus", XRC(59,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
5845 {"fcfidus.", XRC(59,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
5847 {"xxsldwi", XX3(60,2), XX3SHW_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
, SHW
}},
5848 {"xxsel", XX4(60,3), XX4_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
, XC6
}},
5849 {"xxspltd", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
, DMEX
}},
5850 {"xxmrghd", XX3(60,10), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5851 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
}},
5852 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5853 {"xxpermdi", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
, DM
}},
5854 {"xxmrghw", XX3(60,18), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5855 {"xsadddp", XX3(60,32), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5856 {"xsmaddadp", XX3(60,33), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5857 {"xscmpudp", XX3(60,35), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
5858 {"xssubdp", XX3(60,40), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5859 {"xsmaddmdp", XX3(60,41), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5860 {"xscmpodp", XX3(60,43), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
5861 {"xsmuldp", XX3(60,48), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5862 {"xsmsubadp", XX3(60,49), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5863 {"xxmrglw", XX3(60,50), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5864 {"xsdivdp", XX3(60,56), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5865 {"xsmsubmdp", XX3(60,57), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5866 {"xstdivdp", XX3(60,61), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
5867 {"xvaddsp", XX3(60,64), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5868 {"xvmaddasp", XX3(60,65), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5869 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5870 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5871 {"xvsubsp", XX3(60,72), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5872 {"xscvdpuxws", XX2(60,72), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5873 {"xvmaddmsp", XX3(60,73), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5874 {"xsrdpi", XX2(60,73), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5875 {"xsrsqrtedp", XX2(60,74), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5876 {"xssqrtdp", XX2(60,75), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5877 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5878 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5879 {"xvmulsp", XX3(60,80), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5880 {"xvmsubasp", XX3(60,81), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5881 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5882 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5883 {"xvdivsp", XX3(60,88), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5884 {"xscvdpsxws", XX2(60,88), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5885 {"xvmsubmsp", XX3(60,89), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5886 {"xsrdpiz", XX2(60,89), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5887 {"xsredp", XX2(60,90), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5888 {"xvtdivsp", XX3(60,93), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
5889 {"xvadddp", XX3(60,96), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5890 {"xvmaddadp", XX3(60,97), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5891 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5892 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5893 {"xvsubdp", XX3(60,104), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5894 {"xvmaddmdp", XX3(60,105), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5895 {"xsrdpip", XX2(60,105), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5896 {"xstsqrtdp", XX2(60,106), XX2BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XB6
}},
5897 {"xsrdpic", XX2(60,107), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5898 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5899 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5900 {"xvmuldp", XX3(60,112), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5901 {"xvmsubadp", XX3(60,113), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5902 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5903 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5904 {"xvdivdp", XX3(60,120), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5905 {"xvmsubmdp", XX3(60,121), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5906 {"xsrdpim", XX2(60,121), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5907 {"xvtdivdp", XX3(60,125), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
5908 {"xxland", XX3(60,130), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5909 {"xvcvspuxws", XX2(60,136), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5910 {"xvrspi", XX2(60,137), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5911 {"xxlandc", XX3(60,138), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5912 {"xvrsqrtesp", XX2(60,138), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5913 {"xvsqrtsp", XX2(60,139), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5914 {"xxlor", XX3(60,146), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5915 {"xvcvspsxws", XX2(60,152), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5916 {"xvrspiz", XX2(60,153), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5917 {"xxlxor", XX3(60,154), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5918 {"xvresp", XX2(60,154), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5919 {"xsmaxdp", XX3(60,160), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5920 {"xsnmaddadp", XX3(60,161), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5921 {"xxlnor", XX3(60,162), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5922 {"xxspltw", XX2(60,164), XX2UIM_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
, UIM
}},
5923 {"xsmindp", XX3(60,168), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5924 {"xvcvuxwsp", XX2(60,168), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5925 {"xsnmaddmdp", XX3(60,169), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5926 {"xvrspip", XX2(60,169), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5927 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XB6
}},
5928 {"xvrspic", XX2(60,171), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5929 {"xscpsgndp", XX3(60,176), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5930 {"xsnmsubadp", XX3(60,177), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5931 {"xvcvsxwsp", XX2(60,184), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5932 {"xsnmsubmdp", XX3(60,185), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5933 {"xvrspim", XX2(60,185), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5934 {"xvmaxsp", XX3(60,192), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5935 {"xvnmaddasp", XX3(60,193), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5936 {"xvminsp", XX3(60,200), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5937 {"xvcvdpuxws", XX2(60,200), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5938 {"xvnmaddmsp", XX3(60,201), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5939 {"xvrdpi", XX2(60,201), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5940 {"xvrsqrtedp", XX2(60,202), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5941 {"xvsqrtdp", XX2(60,203), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5942 {"xvmovsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
}},
5943 {"xvcpsgnsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5944 {"xvnmsubasp", XX3(60,209), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5945 {"xvcvdpsxws", XX2(60,216), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5946 {"xvnmsubmsp", XX3(60,217), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5947 {"xvrdpiz", XX2(60,217), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5948 {"xvredp", XX2(60,218), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5949 {"xvmaxdp", XX3(60,224), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5950 {"xvnmaddadp", XX3(60,225), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5951 {"xvmindp", XX3(60,232), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5952 {"xvnmaddmdp", XX3(60,233), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5953 {"xvcvuxwdp", XX2(60,232), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5954 {"xvrdpip", XX2(60,233), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5955 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XB6
}},
5956 {"xvrdpic", XX2(60,235), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5957 {"xvmovdp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
}},
5958 {"xvcpsgndp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5959 {"xvnmsubadp", XX3(60,241), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5960 {"xvcvsxwdp", XX2(60,248), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5961 {"xvnmsubmdp", XX3(60,249), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5962 {"xvrdpim", XX2(60,249), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5963 {"xscvdpsp", XX2(60,265), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5964 {"xscvdpuxds", XX2(60,328), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5965 {"xscvspdp", XX2(60,329), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5966 {"xscvdpsxds", XX2(60,344), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5967 {"xsabsdp", XX2(60,345), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5968 {"xscvuxddp", XX2(60,360), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5969 {"xsnabsdp", XX2(60,361), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5970 {"xscvsxddp", XX2(60,376), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5971 {"xsnegdp", XX2(60,377), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5972 {"xvcvspuxds", XX2(60,392), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5973 {"xvcvdpsp", XX2(60,393), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5974 {"xvcvspsxds", XX2(60,408), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5975 {"xvabssp", XX2(60,409), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5976 {"xvcvuxdsp", XX2(60,424), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5977 {"xvnabssp", XX2(60,425), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5978 {"xvcvsxdsp", XX2(60,440), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5979 {"xvnegsp", XX2(60,441), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5980 {"xvcvdpuxds", XX2(60,456), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5981 {"xvcvspdp", XX2(60,457), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5982 {"xvcvdpsxds", XX2(60,472), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5983 {"xvabsdp", XX2(60,473), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5984 {"xvcvuxddp", XX2(60,488), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5985 {"xvnabsdp", XX2(60,489), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5986 {"xvcvsxddp", XX2(60,504), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5987 {"xvnegdp", XX2(60,505), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5989 {"psq_st", OP(60), OP_MASK
, PPCPS
, PPCNONE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
5990 {"stfq", OP(60), OP_MASK
, POWER2
, PPCNONE
, {FRS
, D
, RA
}},
5992 {"stfdp", OP(61), OP_MASK
, POWER6
, POWER7
, {FRSp
, D
, RA0
}},
5993 {"psq_stu", OP(61), OP_MASK
, PPCPS
, PPCNONE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
5994 {"stfqu", OP(61), OP_MASK
, POWER2
, PPCNONE
, {FRS
, D
, RA
}},
5996 {"std", DSO(62,0), DS_MASK
, PPC64
, PPCNONE
, {RS
, DS
, RA0
}},
5997 {"stdu", DSO(62,1), DS_MASK
, PPC64
, PPCNONE
, {RS
, DS
, RAS
}},
5998 {"stq", DSO(62,2), DS_MASK
, POWER4
, PPC476
, {RSQ
, DS
, RA0
}},
6000 {"fcmpu", X(63,0), X_MASK
|(3<<21), COM
, PPCEFS
, {BF
, FRA
, FRB
}},
6002 {"daddq", XRC(63,2,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6003 {"daddq.", XRC(63,2,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6005 {"dquaq", ZRC(63,3,0), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
, RMC
}},
6006 {"dquaq.", ZRC(63,3,1), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
, RMC
}},
6008 {"fcpsgn", XRC(63,8,0), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FRT
, FRA
, FRB
}},
6009 {"fcpsgn.", XRC(63,8,1), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FRT
, FRA
, FRB
}},
6011 {"frsp", XRC(63,12,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6012 {"frsp.", XRC(63,12,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6014 {"fctiw", XRC(63,14,0), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6015 {"fcir", XRC(63,14,0), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6016 {"fctiw.", XRC(63,14,1), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6017 {"fcir.", XRC(63,14,1), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6019 {"fctiwz", XRC(63,15,0), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6020 {"fcirz", XRC(63,15,0), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6021 {"fctiwz.", XRC(63,15,1), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6022 {"fcirz.", XRC(63,15,1), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6024 {"fdiv", A(63,18,0), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6025 {"fd", A(63,18,0), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6026 {"fdiv.", A(63,18,1), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6027 {"fd.", A(63,18,1), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6029 {"fsub", A(63,20,0), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6030 {"fs", A(63,20,0), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6031 {"fsub.", A(63,20,1), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6032 {"fs.", A(63,20,1), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6034 {"fadd", A(63,21,0), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6035 {"fa", A(63,21,0), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6036 {"fadd.", A(63,21,1), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6037 {"fa.", A(63,21,1), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6039 {"fsqrt", A(63,22,0), AFRAFRC_MASK
, PPCPWR2
, TITAN
, {FRT
, FRB
}},
6040 {"fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPCPWR2
, TITAN
, {FRT
, FRB
}},
6042 {"fsel", A(63,23,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6043 {"fsel.", A(63,23,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6045 {"fre", A(63,24,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6046 {"fre", A(63,24,0), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
6047 {"fre.", A(63,24,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6048 {"fre.", A(63,24,1), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
6050 {"fmul", A(63,25,0), AFRB_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
}},
6051 {"fm", A(63,25,0), AFRB_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
}},
6052 {"fmul.", A(63,25,1), AFRB_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
}},
6053 {"fm.", A(63,25,1), AFRB_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
}},
6055 {"frsqrte", A(63,26,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6056 {"frsqrte", A(63,26,0), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
6057 {"frsqrte.", A(63,26,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6058 {"frsqrte.", A(63,26,1), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
6060 {"fmsub", A(63,28,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6061 {"fms", A(63,28,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6062 {"fmsub.", A(63,28,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6063 {"fms.", A(63,28,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6065 {"fmadd", A(63,29,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6066 {"fma", A(63,29,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6067 {"fmadd.", A(63,29,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6068 {"fma.", A(63,29,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6070 {"fnmsub", A(63,30,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6071 {"fnms", A(63,30,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6072 {"fnmsub.", A(63,30,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6073 {"fnms.", A(63,30,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6075 {"fnmadd", A(63,31,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6076 {"fnma", A(63,31,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6077 {"fnmadd.", A(63,31,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6078 {"fnma.", A(63,31,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6080 {"fcmpo", X(63,32), X_MASK
|(3<<21), COM
, PPCEFS
, {BF
, FRA
, FRB
}},
6082 {"dmulq", XRC(63,34,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6083 {"dmulq.", XRC(63,34,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6085 {"drrndq", ZRC(63,35,0), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
, RMC
}},
6086 {"drrndq.", ZRC(63,35,1), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
, RMC
}},
6088 {"mtfsb1", XRC(63,38,0), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6089 {"mtfsb1.", XRC(63,38,1), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6091 {"fneg", XRC(63,40,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6092 {"fneg.", XRC(63,40,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6094 {"mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), COM
, PPCNONE
, {BF
, BFA
}},
6096 {"dscliq", ZRC(63,66,0), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6097 {"dscliq.", ZRC(63,66,1), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6099 {"dquaiq", ZRC(63,67,0), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRTp
, FRBp
, RMC
}},
6100 {"dquaiq.", ZRC(63,67,1), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRTp
, FRBp
, RMC
}},
6102 {"mtfsb0", XRC(63,70,0), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6103 {"mtfsb0.", XRC(63,70,1), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6105 {"fmr", XRC(63,72,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6106 {"fmr.", XRC(63,72,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6108 {"dscriq", ZRC(63,98,0), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6109 {"dscriq.", ZRC(63,98,1), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6111 {"drintxq", ZRC(63,99,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6112 {"drintxq.", ZRC(63,99,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6114 {"ftdiv", X(63,128), X_MASK
|(3<<21), POWER7
, PPCNONE
, {BF
, FRA
, FRB
}},
6116 {"dcmpoq", X(63,130), X_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, FRBp
}},
6118 {"mtfsfi", XRC(63,134,0), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCNONE
, {BFF
, U
, W
}},
6119 {"mtfsfi", XRC(63,134,0), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
, {BFF
, U
}},
6120 {"mtfsfi.", XRC(63,134,1), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCNONE
, {BFF
, U
, W
}},
6121 {"mtfsfi.", XRC(63,134,1), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
, {BFF
, U
}},
6123 {"fnabs", XRC(63,136,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6124 {"fnabs.", XRC(63,136,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6126 {"fctiwu", XRC(63,142,0), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6127 {"fctiwu.", XRC(63,142,1), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6128 {"fctiwuz", XRC(63,143,0), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6129 {"fctiwuz.", XRC(63,143,1), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6131 {"ftsqrt", X(63,160), X_MASK
|(3<<21|FRA_MASK
), POWER7
, PPCNONE
, {BF
, FRB
}},
6133 {"dtstexq", X(63,162), X_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, FRBp
}},
6134 {"dtstdcq", Z(63,194), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, DCM
}},
6135 {"dtstdgq", Z(63,226), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, DGM
}},
6137 {"drintnq", ZRC(63,227,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6138 {"drintnq.", ZRC(63,227,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6140 {"dctqpq", XRC(63,258,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6141 {"dctqpq.", XRC(63,258,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6143 {"fabs", XRC(63,264,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6144 {"fabs.", XRC(63,264,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6146 {"dctfixq", XRC(63,290,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6147 {"dctfixq.", XRC(63,290,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6149 {"ddedpdq", XRC(63,322,0), X_MASK
, POWER6
, PPCNONE
, {SP
, FRTp
, FRBp
}},
6150 {"ddedpdq.", XRC(63,322,1), X_MASK
, POWER6
, PPCNONE
, {SP
, FRTp
, FRBp
}},
6152 {"dxexq", XRC(63,354,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6153 {"dxexq.", XRC(63,354,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6155 {"frin", XRC(63,392,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6156 {"frin.", XRC(63,392,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6157 {"friz", XRC(63,424,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6158 {"friz.", XRC(63,424,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6159 {"frip", XRC(63,456,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6160 {"frip.", XRC(63,456,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6161 {"frim", XRC(63,488,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6162 {"frim.", XRC(63,488,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6164 {"dsubq", XRC(63,514,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6165 {"dsubq.", XRC(63,514,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6167 {"ddivq", XRC(63,546,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6168 {"ddivq.", XRC(63,546,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6170 {"mffs", XRC(63,583,0), XRARB_MASK
, COM
, PPCEFS
, {FRT
}},
6171 {"mffs.", XRC(63,583,1), XRARB_MASK
, COM
, PPCEFS
, {FRT
}},
6173 {"dcmpuq", X(63,642), X_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, FRBp
}},
6175 {"dtstsfq", X(63,674), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRBp
}},
6177 {"mtfsf", XFL(63,711,0), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FLM
, FRB
, XFL_L
, W
}},
6178 {"mtfsf", XFL(63,711,0), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
, {FLM
, FRB
}},
6179 {"mtfsf.", XFL(63,711,1), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FLM
, FRB
, XFL_L
, W
}},
6180 {"mtfsf.", XFL(63,711,1), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
, {FLM
, FRB
}},
6182 {"drdpq", XRC(63,770,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRBp
}},
6183 {"drdpq.", XRC(63,770,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRBp
}},
6185 {"dcffixq", XRC(63,802,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6186 {"dcffixq.", XRC(63,802,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6188 {"fctid", XRC(63,814,0), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6189 {"fctid", XRC(63,814,0), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6190 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6191 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6193 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6194 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6195 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6196 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6198 {"denbcdq", XRC(63,834,0), X_MASK
, POWER6
, PPCNONE
, {S
, FRTp
, FRBp
}},
6199 {"denbcdq.", XRC(63,834,1), X_MASK
, POWER6
, PPCNONE
, {S
, FRTp
, FRBp
}},
6201 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6202 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6203 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6204 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6206 {"diexq", XRC(63,866,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
}},
6207 {"diexq.", XRC(63,866,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
}},
6209 {"fctidu", XRC(63,942,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6210 {"fctidu.", XRC(63,942,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6212 {"fctiduz", XRC(63,943,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6213 {"fctiduz.", XRC(63,943,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6215 {"fcfidu", XRC(63,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6216 {"fcfidu.", XRC(63,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6219 const int powerpc_num_opcodes
=
6220 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
6222 /* The VLE opcode table.
6224 The format of this opcode table is the same as the main opcode table. */
6226 const struct powerpc_opcode vle_opcodes
[] = {
6228 {"se_illegal", C(0), C_MASK
, PPCVLE
, PPCNONE
, {}},
6229 {"se_isync", C(1), C_MASK
, PPCVLE
, PPCNONE
, {}},
6230 {"se_sc", C(2), C_MASK
, PPCVLE
, PPCNONE
, {}},
6231 {"se_blr", C_LK(2,0), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6232 {"se_blrl", C_LK(2,1), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6233 {"se_bctr", C_LK(3,0), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6234 {"se_bctrl", C_LK(3,1), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6235 {"se_rfi", C(8), C_MASK
, PPCVLE
, PPCNONE
, {}},
6236 {"se_rfci", C(9), C_MASK
, PPCVLE
, PPCNONE
, {}},
6237 {"se_rfdi", C(10), C_MASK
, PPCVLE
, PPCNONE
, {}},
6238 {"se_rfmci", C(11), C_MASK
, PPCVLE
, PPCNONE
, {}},
6239 {"se_not", SE_R(0,2), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6240 {"se_neg", SE_R(0,3), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6241 {"se_mflr", SE_R(0,8), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6242 {"se_mtlr", SE_R(0,9), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6243 {"se_mfctr", SE_R(0,10), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6244 {"se_mtctr", SE_R(0,11), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6245 {"se_extzb", SE_R(0,12), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6246 {"se_extsb", SE_R(0,13), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6247 {"se_extzh", SE_R(0,14), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6248 {"se_extsh", SE_R(0,15), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6249 {"se_mr", SE_RR(0,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6250 {"se_mtar", SE_RR(0,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {ARX
, RY
}},
6251 {"se_mfar", SE_RR(0,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, ARY
}},
6252 {"se_add", SE_RR(1,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6253 {"se_mullw", SE_RR(1,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6254 {"se_sub", SE_RR(1,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6255 {"se_subf", SE_RR(1,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6256 {"se_cmp", SE_RR(3,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6257 {"se_cmpl", SE_RR(3,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6258 {"se_cmph", SE_RR(3,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6259 {"se_cmphl", SE_RR(3,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6261 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK
, PPCVLE
, PPCNONE
, {CRD32
, RA
, SCLSCI8
}},
6262 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK
, PPCVLE
, PPCNONE
, {CRD32
, RA
, SCLSCI8
}},
6263 {"e_addi", SCI8(6,16), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6264 {"e_subi", SCI8(6,16), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8N
}},
6265 {"e_addi.", SCI8(6,17), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6266 {"e_addic", SCI8(6,18), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6267 {"e_subic", SCI8(6,18), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8N
}},
6268 {"e_addic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6269 {"e_subic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8N
}},
6270 {"e_mulli", SCI8(6,20), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6271 {"e_subfic", SCI8(6,22), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6272 {"e_subfic.", SCI8(6,23), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6273 {"e_andi", SCI8(6,24), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6274 {"e_andi.", SCI8(6,25), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6275 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE
, PPCNONE
, {0}},
6276 {"e_ori", SCI8(6,26), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6277 {"e_ori.", SCI8(6,27), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6278 {"e_xori", SCI8(6,28), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6279 {"e_xori.", SCI8(6,29), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6280 {"e_lbzu", OPVUP(6,0), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6281 {"e_lhau", OPVUP(6,3), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6282 {"e_lhzu", OPVUP(6,1), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6283 {"e_lmw", OPVUP(6,8), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6284 {"e_lwzu", OPVUP(6,2), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6285 {"e_stbu", OPVUP(6,4), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6286 {"e_sthu", OPVUP(6,5), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6287 {"e_stwu", OPVUP(6,6), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6288 {"e_stmw", OPVUP(6,9), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6289 {"e_add16i", OP(7), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SI
}},
6290 {"e_la", OP(7), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6291 {"e_sub16i", OP(7), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, NSI
}},
6293 {"se_addi", SE_IM5(8,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6294 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6295 {"se_subi", SE_IM5(9,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6296 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6297 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6298 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6299 {"se_andi", SE_IM5(11,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6301 {"e_lbz", OP(12), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6302 {"e_stb", OP(13), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6303 {"e_lha", OP(14), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6305 {"se_srw", SE_RR(16,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6306 {"se_sraw", SE_RR(16,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6307 {"se_slw", SE_RR(16,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6308 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE
, PPCNONE
, {0}},
6309 {"se_or", SE_RR(17,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6310 {"se_andc", SE_RR(17,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6311 {"se_and", SE_RR(17,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6312 {"se_and.", SE_RR(17,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6313 {"se_li", IM7(9), IM7_MASK
, PPCVLE
, PPCNONE
, {RX
, UI7
}},
6315 {"e_lwz", OP(20), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6316 {"e_stw", OP(21), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6317 {"e_lhz", OP(22), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6318 {"e_sth", OP(23), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6320 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6321 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6322 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6323 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6324 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6325 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6326 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6328 {"e_lis", I16L(28,28), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6329 {"e_and2is.", I16L(28,29), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6330 {"e_or2is", I16L(28,26), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6331 {"e_and2i.", I16L(28,25), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6332 {"e_or2i", I16L(28,24), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6333 {"e_cmphl16i", IA16(28,23), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLEUIMM
}},
6334 {"e_cmph16i", IA16(28,22), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6335 {"e_cmpl16i", I16A(28,21), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLEUIMM
}},
6336 {"e_cmplwi", I16A(28,21), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6337 {"e_mull2i", I16A(28,20), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6338 {"e_cmp16i", IA16(28,19), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6339 {"e_cmpwi", IA16(28,19), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6340 {"e_sub2is", I16A(28,18), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLENSIMM
}},
6341 {"e_add2is", I16A(28,18), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6342 {"e_sub2i.", I16A(28,17), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLENSIMM
}},
6343 {"e_add2i.", I16A(28,17), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6344 {"e_li", LI20(28,0), LI20_MASK
, PPCVLE
, PPCNONE
, {RT
, IMM20
}},
6345 {"e_rlwimi", M(29,0), M_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
, MB
, ME
}},
6346 {"e_rlwinm", M(29,1), M_MASK
, PPCVLE
, PPCNONE
, {RA
, RT
, SH
, MBE
, ME
}},
6347 {"e_b", BD24(30,0,0), BD24_MASK
, PPCVLE
, PPCNONE
, {B24
}},
6348 {"e_bl", BD24(30,0,1), BD24_MASK
, PPCVLE
, PPCNONE
, {B24
}},
6349 {"e_bdnz", EBD15(30,8,BO32DNZ
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6350 {"e_bdnzl", EBD15(30,8,BO32DNZ
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6351 {"e_bdz", EBD15(30,8,BO32DZ
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6352 {"e_bdzl", EBD15(30,8,BO32DZ
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6353 {"e_bge", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6354 {"e_bgel", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6355 {"e_bnl", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6356 {"e_bnll", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6357 {"e_blt", EBD15BI(30,8,BO32T
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6358 {"e_bltl", EBD15BI(30,8,BO32T
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6359 {"e_bgt", EBD15BI(30,8,BO32T
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6360 {"e_bgtl", EBD15BI(30,8,BO32T
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6361 {"e_ble", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6362 {"e_blel", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6363 {"e_bng", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6364 {"e_bngl", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6365 {"e_bne", EBD15BI(30,8,BO32F
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6366 {"e_bnel", EBD15BI(30,8,BO32F
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6367 {"e_beq", EBD15BI(30,8,BO32T
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6368 {"e_beql", EBD15BI(30,8,BO32T
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6369 {"e_bso", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6370 {"e_bsol", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6371 {"e_bun", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6372 {"e_bunl", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6373 {"e_bns", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6374 {"e_bnsl", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6375 {"e_bnu", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6376 {"e_bnul", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6377 {"e_bc", BD15(30,8,0), BD15_MASK
, PPCVLE
, PPCNONE
, {BO32
, BI32
, B15
}},
6378 {"e_bcl", BD15(30,8,1), BD15_MASK
, PPCVLE
, PPCNONE
, {BO32
, BI32
, B15
}},
6380 {"e_bf", EBD15(30,8,BO32F
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6381 {"e_bfl", EBD15(30,8,BO32F
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6382 {"e_bt", EBD15(30,8,BO32T
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6383 {"e_btl", EBD15(30,8,BO32T
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6385 {"e_cmph", X(31,14), X_MASK
, PPCVLE
, PPCNONE
, {CRD
, RA
, RB
}},
6386 {"e_cmphl", X(31,46), X_MASK
, PPCVLE
, PPCNONE
, {CRD
, RA
, RB
}},
6387 {"e_crandc", XL(31,129), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6388 {"e_crnand", XL(31,225), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6389 {"e_crnot", XL(31,33), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BBA
}},
6390 {"e_crnor", XL(31,33), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6391 {"e_crclr", XL(31,193), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BAT
, BBA
}},
6392 {"e_crxor", XL(31,193), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6393 {"e_mcrf", XL(31,16), XL_MASK
, PPCVLE
, PPCNONE
, {CRD
, CR
}},
6394 {"e_slwi", EX(31,112), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6395 {"e_slwi.", EX(31,113), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6397 {"e_crand", XL(31,257), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6399 {"e_rlw", EX(31,560), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
6400 {"e_rlw.", EX(31,561), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
6402 {"e_crset", XL(31,289), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BAT
, BBA
}},
6403 {"e_creqv", XL(31,289), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6405 {"e_rlwi", EX(31,624), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6406 {"e_rlwi.", EX(31,625), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6408 {"e_crorc", XL(31,417), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6410 {"e_crmove", XL(31,449), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BBA
}},
6411 {"e_cror", XL(31,449), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6413 {"mtmas1", XSPR(31,467,625), XSPR_MASK
, PPCVLE
, PPCNONE
, {RS
}},
6415 {"e_srwi", EX(31,1136), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6416 {"e_srwi.", EX(31,1137), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6418 {"se_lbz", SD4(8), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SD
, RX
}},
6420 {"se_stb", SD4(9), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SD
, RX
}},
6422 {"se_lhz", SD4(10), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDH
, RX
}},
6424 {"se_sth", SD4(11), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDH
, RX
}},
6426 {"se_lwz", SD4(12), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDW
, RX
}},
6428 {"se_stw", SD4(13), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDW
, RX
}},
6430 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6431 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6432 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6433 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6434 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6435 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6436 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6437 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK
, PPCVLE
, PPCNONE
, {BI16
, B8
}},
6438 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6439 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6440 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6441 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6442 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6443 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK
, PPCVLE
, PPCNONE
, {BI16
, B8
}},
6444 {"se_bc", BD8IO(28), BD8IO_MASK
, PPCVLE
, PPCNONE
, {BO16
, BI16
, B8
}},
6445 {"se_b", BD8(58,0,0), BD8_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6446 {"se_bl", BD8(58,0,1), BD8_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6449 const int vle_num_opcodes
=
6450 sizeof (vle_opcodes
) / sizeof (vle_opcodes
[0]);
6452 /* The macro table. This is only used by the assembler. */
6454 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
6455 when x=0; 32-x when x is between 1 and 31; are negative if x is
6456 negative; and are 32 or more otherwise. This is what you want
6457 when, for instance, you are emulating a right shift by a
6458 rotate-left-and-mask, because the underlying instructions support
6459 shifts of size 0 but not shifts of size 32. By comparison, when
6460 extracting x bits from some word you want to use just 32-x, because
6461 the underlying instructions don't support extracting 0 bits but do
6462 support extracting the whole word (32 bits in this case). */
6464 const struct powerpc_macro powerpc_macros
[] = {
6465 {"extldi", 4, PPC64
, "rldicr %0,%1,%3,(%2)-1"},
6466 {"extldi.", 4, PPC64
, "rldicr. %0,%1,%3,(%2)-1"},
6467 {"extrdi", 4, PPC64
, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6468 {"extrdi.", 4, PPC64
, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6469 {"insrdi", 4, PPC64
, "rldimi %0,%1,64-((%2)+(%3)),%3"},
6470 {"insrdi.", 4, PPC64
, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
6471 {"rotrdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
6472 {"rotrdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
6473 {"sldi", 3, PPC64
, "rldicr %0,%1,%2,63-(%2)"},
6474 {"sldi.", 3, PPC64
, "rldicr. %0,%1,%2,63-(%2)"},
6475 {"srdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
6476 {"srdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
6477 {"clrrdi", 3, PPC64
, "rldicr %0,%1,0,63-(%2)"},
6478 {"clrrdi.", 3, PPC64
, "rldicr. %0,%1,0,63-(%2)"},
6479 {"clrlsldi", 4, PPC64
, "rldic %0,%1,%3,(%2)-(%3)"},
6480 {"clrlsldi.",4, PPC64
, "rldic. %0,%1,%3,(%2)-(%3)"},
6482 {"extlwi", 4, PPCCOM
, "rlwinm %0,%1,%3,0,(%2)-1"},
6483 {"extlwi.", 4, PPCCOM
, "rlwinm. %0,%1,%3,0,(%2)-1"},
6484 {"extrwi", 4, PPCCOM
, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6485 {"extrwi.", 4, PPCCOM
, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6486 {"inslwi", 4, PPCCOM
, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6487 {"inslwi.", 4, PPCCOM
, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6488 {"insrwi", 4, PPCCOM
, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6489 {"insrwi.", 4, PPCCOM
, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6490 {"rotrwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6491 {"rotrwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6492 {"slwi", 3, PPCCOM
, "rlwinm %0,%1,%2,0,31-(%2)"},
6493 {"sli", 3, PWRCOM
, "rlinm %0,%1,%2,0,31-(%2)"},
6494 {"slwi.", 3, PPCCOM
, "rlwinm. %0,%1,%2,0,31-(%2)"},
6495 {"sli.", 3, PWRCOM
, "rlinm. %0,%1,%2,0,31-(%2)"},
6496 {"srwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6497 {"sri", 3, PWRCOM
, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6498 {"srwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6499 {"sri.", 3, PWRCOM
, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6500 {"clrrwi", 3, PPCCOM
, "rlwinm %0,%1,0,0,31-(%2)"},
6501 {"clrrwi.", 3, PPCCOM
, "rlwinm. %0,%1,0,0,31-(%2)"},
6502 {"clrlslwi", 4, PPCCOM
, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6503 {"clrlslwi.",4, PPCCOM
, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
6505 {"e_extlwi", 4, PPCVLE
, "e_rlwinm %0,%1,%3,0,(%2)-1"},
6506 {"e_extrwi", 4, PPCVLE
, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6507 {"e_inslwi", 4, PPCVLE
, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6508 {"e_insrwi", 4, PPCVLE
, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6509 {"e_rotlwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31"},
6510 {"e_rotrwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6511 {"e_slwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31-(%2)"},
6512 {"e_srwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6513 {"e_clrlwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,%2,31"},
6514 {"e_clrrwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,0,31-(%2)"},
6515 {"e_clrlslwi",4, PPCVLE
, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6518 const int powerpc_num_macros
=
6519 sizeof (powerpc_macros
) / sizeof (powerpc_macros
[0]);