opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
   3    2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING.  If not, write to the
  20    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include <stdio.h>
  24 #include "sysdep.h"
  25 #include "opcode/ppc.h"
  26 #include "opintl.h"
  27
  28 /* This file holds the PowerPC opcode table.  The opcode table
  29    includes almost all of the extended instruction mnemonics.  This
  30    permits the disassembler to use them, and simplifies the assembler
  31    logic, at the cost of increasing the table size.  The table is
  32    strictly constant data, so the compiler should be able to put it in
  33    the .text section.
  34
  35    This file also holds the operand table.  All knowledge about
  36    inserting operands into instructions and vice-versa is kept in this
  37    file.  */
  38 \f
  39 /* Local insertion and extraction functions.  */
  40
  41 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
  42 static long extract_bat (unsigned long, ppc_cpu_t, int *);
  43 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
  44 static long extract_bba (unsigned long, ppc_cpu_t, int *);
  45 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
  46 static long extract_bdm (unsigned long, ppc_cpu_t, int *);
  47 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
  48 static long extract_bdp (unsigned long, ppc_cpu_t, int *);
  49 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
  50 static long extract_bo (unsigned long, ppc_cpu_t, int *);
  51 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
  52 static long extract_boe (unsigned long, ppc_cpu_t, int *);
  53 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
  54 static long extract_fxm (unsigned long, ppc_cpu_t, int *);
  55 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
  56 static long extract_mbe (unsigned long, ppc_cpu_t, int *);
  57 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
  58 static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
  59 static long extract_nb (unsigned long, ppc_cpu_t, int *);
  60 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
  61 static long extract_nsi (unsigned long, ppc_cpu_t, int *);
  62 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
  63 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
  64 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
  65 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
  66 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
  67 static long extract_rbs (unsigned long, ppc_cpu_t, int *);
  68 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
  69 static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
  70 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
  71 static long extract_spr (unsigned long, ppc_cpu_t, int *);
  72 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
  73 static long extract_sprg (unsigned long, ppc_cpu_t, int *);
  74 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
  75 static long extract_tbr (unsigned long, ppc_cpu_t, int *);
  76 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
  77 static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
  78 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
  79 static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
  80 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
  81 static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
  82 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
  83 static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
  84 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
  85 static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
  86 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
  87 static long extract_dm (unsigned long, ppc_cpu_t, int *);
  88 \f
  89 /* The operands table.
  90
  91    The fields are bitm, shift, insert, extract, flags.
  92
  93    We used to put parens around the various additions, like the one
  94    for BA just below.  However, that caused trouble with feeble
  95    compilers with a limit on depth of a parenthesized expression, like
  96    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
  97    omit the parens, since the macros are never used in a context where
  98    the addition will be ambiguous.  */
  99
 100 const struct powerpc_operand powerpc_operands[] =
 101 {
 102   /* The zero index is used to indicate the end of the list of
 103      operands.  */
 104 #define UNUSED 0
 105   { 0, 0, NULL, NULL, 0 },
 106
 107   /* The BA field in an XL form instruction.  */
 108 #define BA UNUSED + 1
 109   /* The BI field in a B form or XL form instruction.  */
 110 #define BI BA
 111 #define BI_MASK (0x1f << 16)
 112   { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
 113
 114   /* The BA field in an XL form instruction when it must be the same
 115      as the BT field in the same instruction.  */
 116 #define BAT BA + 1
 117   { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 118
 119   /* The BB field in an XL form instruction.  */
 120 #define BB BAT + 1
 121 #define BB_MASK (0x1f << 11)
 122   { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
 123
 124   /* The BB field in an XL form instruction when it must be the same
 125      as the BA field in the same instruction.  */
 126 #define BBA BB + 1
 127   { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 128
 129   /* The BD field in a B form instruction.  The lower two bits are
 130      forced to zero.  */
 131 #define BD BBA + 1
 132   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 133
 134   /* The BD field in a B form instruction when absolute addressing is
 135      used.  */
 136 #define BDA BD + 1
 137   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 138
 139   /* The BD field in a B form instruction when the - modifier is used.
 140      This sets the y bit of the BO field appropriately.  */
 141 #define BDM BDA + 1
 142   { 0xfffc, 0, insert_bdm, extract_bdm,
 143       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 144
 145   /* The BD field in a B form instruction when the - modifier is used
 146      and absolute address is used.  */
 147 #define BDMA BDM + 1
 148   { 0xfffc, 0, insert_bdm, extract_bdm,
 149       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 150
 151   /* The BD field in a B form instruction when the + modifier is used.
 152      This sets the y bit of the BO field appropriately.  */
 153 #define BDP BDMA + 1
 154   { 0xfffc, 0, insert_bdp, extract_bdp,
 155       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 156
 157   /* The BD field in a B form instruction when the + modifier is used
 158      and absolute addressing is used.  */
 159 #define BDPA BDP + 1
 160   { 0xfffc, 0, insert_bdp, extract_bdp,
 161       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 162
 163   /* The BF field in an X or XL form instruction.  */
 164 #define BF BDPA + 1
 165   /* The CRFD field in an X form instruction.  */
 166 #define CRFD BF
 167   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
 168
 169   /* The BF field in an X or XL form instruction.  */
 170 #define BFF BF + 1
 171   { 0x7, 23, NULL, NULL, 0 },
 172
 173   /* An optional BF field.  This is used for comparison instructions,
 174      in which an omitted BF field is taken as zero.  */
 175 #define OBF BFF + 1
 176   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 177
 178   /* The BFA field in an X or XL form instruction.  */
 179 #define BFA OBF + 1
 180   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
 181
 182   /* The BO field in a B form instruction.  Certain values are
 183      illegal.  */
 184 #define BO BFA + 1
 185 #define BO_MASK (0x1f << 21)
 186   { 0x1f, 21, insert_bo, extract_bo, 0 },
 187
 188   /* The BO field in a B form instruction when the + or - modifier is
 189      used.  This is like the BO field, but it must be even.  */
 190 #define BOE BO + 1
 191   { 0x1e, 21, insert_boe, extract_boe, 0 },
 192
 193 #define BH BOE + 1
 194   { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 195
 196   /* The BT field in an X or XL form instruction.  */
 197 #define BT BH + 1
 198   { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
 199
 200   /* The condition register number portion of the BI field in a B form
 201      or XL form instruction.  This is used for the extended
 202      conditional branch mnemonics, which set the lower two bits of the
 203      BI field.  This field is optional.  */
 204 #define CR BT + 1
 205   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 206
 207   /* The CRB field in an X form instruction.  */
 208 #define CRB CR + 1
 209   /* The MB field in an M form instruction.  */
 210 #define MB CRB
 211 #define MB_MASK (0x1f << 6)
 212   { 0x1f, 6, NULL, NULL, 0 },
 213
 214   /* The CRFS field in an X form instruction.  */
 215 #define CRFS CRB + 1
 216   { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
 217
 218   /* The CT field in an X form instruction.  */
 219 #define CT CRFS + 1
 220   /* The MO field in an mbar instruction.  */
 221 #define MO CT
 222   { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 223
 224   /* The D field in a D form instruction.  This is a displacement off
 225      a register, and implies that the next operand is a register in
 226      parentheses.  */
 227 #define D CT + 1
 228   { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 229
 230   /* The DQ field in a DQ form instruction.  This is like D, but the
 231      lower four bits are forced to zero. */
 232 #define DQ D + 1
 233   { 0xfff0, 0, NULL, NULL,
 234     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 235
 236   /* The DS field in a DS form instruction.  This is like D, but the
 237      lower two bits are forced to zero.  */
 238 #define DS DQ + 1
 239   { 0xfffc, 0, NULL, NULL,
 240     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 241
 242   /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
 243 #define DUIS DS + 1
 244   { 0x3ff, 11, NULL, NULL, 0 },
 245
 246   /* The E field in a wrteei instruction.  */
 247   /* And the W bit in the pair singles instructions.  */
 248 #define E DUIS + 1
 249 #define PSW E
 250   { 0x1, 15, NULL, NULL, 0 },
 251
 252   /* The FL1 field in a POWER SC form instruction.  */
 253 #define FL1 E + 1
 254   /* The U field in an X form instruction.  */
 255 #define U FL1
 256   { 0xf, 12, NULL, NULL, 0 },
 257
 258   /* The FL2 field in a POWER SC form instruction.  */
 259 #define FL2 FL1 + 1
 260   { 0x7, 2, NULL, NULL, 0 },
 261
 262   /* The FLM field in an XFL form instruction.  */
 263 #define FLM FL2 + 1
 264   { 0xff, 17, NULL, NULL, 0 },
 265
 266   /* The FRA field in an X or A form instruction.  */
 267 #define FRA FLM + 1
 268 #define FRA_MASK (0x1f << 16)
 269   { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
 270
 271   /* The FRB field in an X or A form instruction.  */
 272 #define FRB FRA + 1
 273 #define FRB_MASK (0x1f << 11)
 274   { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
 275
 276   /* The FRC field in an A form instruction.  */
 277 #define FRC FRB + 1
 278 #define FRC_MASK (0x1f << 6)
 279   { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
 280
 281   /* The FRS field in an X form instruction or the FRT field in a D, X
 282      or A form instruction.  */
 283 #define FRS FRC + 1
 284 #define FRT FRS
 285   { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
 286
 287   /* The FXM field in an XFX instruction.  */
 288 #define FXM FRS + 1
 289   { 0xff, 12, insert_fxm, extract_fxm, 0 },
 290
 291   /* Power4 version for mfcr.  */
 292 #define FXM4 FXM + 1
 293   { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
 294
 295   /* The L field in a D or X form instruction.  */
 296 #define L FXM4 + 1
 297   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 298
 299   /* The LEV field in a POWER SVC form instruction.  */
 300 #define SVC_LEV L + 1
 301   { 0x7f, 5, NULL, NULL, 0 },
 302
 303   /* The LEV field in an SC form instruction.  */
 304 #define LEV SVC_LEV + 1
 305   { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
 306
 307   /* The LI field in an I form instruction.  The lower two bits are
 308      forced to zero.  */
 309 #define LI LEV + 1
 310   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 311
 312   /* The LI field in an I form instruction when used as an absolute
 313      address.  */
 314 #define LIA LI + 1
 315   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 316
 317   /* The LS or WC field in an X (sync or wait) form instruction.  */
 318 #define LS LIA + 1
 319 #define WC LS
 320   { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 321
 322   /* The ME field in an M form instruction.  */
 323 #define ME LS + 1
 324 #define ME_MASK (0x1f << 1)
 325   { 0x1f, 1, NULL, NULL, 0 },
 326
 327   /* The MB and ME fields in an M form instruction expressed a single
 328      operand which is a bitmask indicating which bits to select.  This
 329      is a two operand form using PPC_OPERAND_NEXT.  See the
 330      description in opcode/ppc.h for what this means.  */
 331 #define MBE ME + 1
 332   { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 333   { -1, 0, insert_mbe, extract_mbe, 0 },
 334
 335   /* The MB or ME field in an MD or MDS form instruction.  The high
 336      bit is wrapped to the low end.  */
 337 #define MB6 MBE + 2
 338 #define ME6 MB6
 339 #define MB6_MASK (0x3f << 5)
 340   { 0x3f, 5, insert_mb6, extract_mb6, 0 },
 341
 342   /* The NB field in an X form instruction.  The value 32 is stored as
 343      0.  */
 344 #define NB MB6 + 1
 345   { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
 346
 347   /* The NSI field in a D form instruction.  This is the same as the
 348      SI field, only negated.  */
 349 #define NSI NB + 1
 350   { 0xffff, 0, insert_nsi, extract_nsi,
 351       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 352
 353   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 354 #define RA NSI + 1
 355 #define RA_MASK (0x1f << 16)
 356   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
 357
 358   /* As above, but 0 in the RA field means zero, not r0.  */
 359 #define RA0 RA + 1
 360   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
 361
 362   /* The RA field in the DQ form lq instruction, which has special
 363      value restrictions.  */
 364 #define RAQ RA0 + 1
 365   { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
 366
 367   /* The RA field in a D or X form instruction which is an updating
 368      load, which means that the RA field may not be zero and may not
 369      equal the RT field.  */
 370 #define RAL RAQ + 1
 371   { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
 372
 373   /* The RA field in an lmw instruction, which has special value
 374      restrictions.  */
 375 #define RAM RAL + 1
 376   { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
 377
 378   /* The RA field in a D or X form instruction which is an updating
 379      store or an updating floating point load, which means that the RA
 380      field may not be zero.  */
 381 #define RAS RAM + 1
 382   { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
 383
 384   /* The RA field of the tlbwe, dccci and iccci instructions,
 385      which are optional.  */
 386 #define RAOPT RAS + 1
 387   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 388
 389   /* The RB field in an X, XO, M, or MDS form instruction.  */
 390 #define RB RAOPT + 1
 391 #define RB_MASK (0x1f << 11)
 392   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
 393
 394   /* The RB field in an X form instruction when it must be the same as
 395      the RS field in the instruction.  This is used for extended
 396      mnemonics like mr.  */
 397 #define RBS RB + 1
 398   { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 399
 400   /* The RB field of the dccci and iccci instructions, which are optional.  */
 401 #define RBOPT RBS + 1
 402   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 403
 404   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 405      instruction or the RT field in a D, DS, X, XFX or XO form
 406      instruction.  */
 407 #define RS RBOPT + 1
 408 #define RT RS
 409 #define RT_MASK (0x1f << 21)
 410   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
 411
 412   /* The RS and RT fields of the DS form stq instruction, which have
 413      special value restrictions.  */
 414 #define RSQ RS + 1
 415 #define RTQ RSQ
 416   { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
 417
 418   /* The RS field of the tlbwe instruction, which is optional.  */
 419 #define RSO RSQ + 1
 420 #define RTO RSO
 421   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 422
 423   /* The SH field in an X or M form instruction.  */
 424 #define SH RSO + 1
 425 #define SH_MASK (0x1f << 11)
 426   /* The other UIMM field in a EVX form instruction.  */
 427 #define EVUIMM SH
 428   { 0x1f, 11, NULL, NULL, 0 },
 429
 430   /* The SH field in an MD form instruction.  This is split.  */
 431 #define SH6 SH + 1
 432 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 433   { 0x3f, -1, insert_sh6, extract_sh6, 0 },
 434
 435   /* The SH field of the tlbwe instruction, which is optional.  */
 436 #define SHO SH6 + 1
 437   { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 438
 439   /* The SI field in a D form instruction.  */
 440 #define SI SHO + 1
 441   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 442
 443   /* The SI field in a D form instruction when we accept a wide range
 444      of positive values.  */
 445 #define SISIGNOPT SI + 1
 446   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 447
 448   /* The SPR field in an XFX form instruction.  This is flipped--the
 449      lower 5 bits are stored in the upper 5 and vice- versa.  */
 450 #define SPR SISIGNOPT + 1
 451 #define PMR SPR
 452 #define SPR_MASK (0x3ff << 11)
 453   { 0x3ff, 11, insert_spr, extract_spr, 0 },
 454
 455   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 456 #define SPRBAT SPR + 1
 457 #define SPRBAT_MASK (0x3 << 17)
 458   { 0x3, 17, NULL, NULL, 0 },
 459
 460   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 461 #define SPRG SPRBAT + 1
 462   { 0x1f, 16, insert_sprg, extract_sprg, 0 },
 463
 464   /* The SR field in an X form instruction.  */
 465 #define SR SPRG + 1
 466   { 0xf, 16, NULL, NULL, 0 },
 467
 468   /* The STRM field in an X AltiVec form instruction.  */
 469 #define STRM SR + 1
 470   /* The T field in a tlbilx form instruction.  */
 471 #define T STRM
 472   { 0x3, 21, NULL, NULL, 0 },
 473
 474   /* The SV field in a POWER SC form instruction.  */
 475 #define SV STRM + 1
 476   { 0x3fff, 2, NULL, NULL, 0 },
 477
 478   /* The TBR field in an XFX form instruction.  This is like the SPR
 479      field, but it is optional.  */
 480 #define TBR SV + 1
 481   { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 482
 483   /* The TO field in a D or X form instruction.  */
 484 #define TO TBR + 1
 485 #define DUI TO
 486 #define TO_MASK (0x1f << 21)
 487   { 0x1f, 21, NULL, NULL, 0 },
 488
 489   /* The UI field in a D form instruction.  */
 490 #define UI TO + 1
 491   { 0xffff, 0, NULL, NULL, 0 },
 492
 493   /* The VA field in a VA, VX or VXR form instruction.  */
 494 #define VA UI + 1
 495   { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
 496
 497   /* The VB field in a VA, VX or VXR form instruction.  */
 498 #define VB VA + 1
 499   { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
 500
 501   /* The VC field in a VA form instruction.  */
 502 #define VC VB + 1
 503   { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
 504
 505   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 506 #define VD VC + 1
 507 #define VS VD
 508   { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
 509
 510   /* The SIMM field in a VX form instruction, and TE in Z form.  */
 511 #define SIMM VD + 1
 512 #define TE SIMM
 513   { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
 514
 515   /* The UIMM field in a VX form instruction.  */
 516 #define UIMM SIMM + 1
 517   { 0x1f, 16, NULL, NULL, 0 },
 518
 519   /* The SHB field in a VA form instruction.  */
 520 #define SHB UIMM + 1
 521   { 0xf, 6, NULL, NULL, 0 },
 522
 523   /* The other UIMM field in a half word EVX form instruction.  */
 524 #define EVUIMM_2 SHB + 1
 525   { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
 526
 527   /* The other UIMM field in a word EVX form instruction.  */
 528 #define EVUIMM_4 EVUIMM_2 + 1
 529   { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
 530
 531   /* The other UIMM field in a double EVX form instruction.  */
 532 #define EVUIMM_8 EVUIMM_4 + 1
 533   { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
 534
 535   /* The WS field.  */
 536 #define WS EVUIMM_8 + 1
 537   { 0x7, 11, NULL, NULL, 0 },
 538
 539   /* PowerPC paired singles extensions.  */
 540   /* W bit in the pair singles instructions for x type instructions.  */
 541 #define PSWM WS + 1
 542   {  0x1, 10, 0, 0, 0 },
 543
 544   /* IDX bits for quantization in the pair singles instructions.  */
 545 #define PSQ PSWM + 1
 546   {  0x7, 12, 0, 0, 0 },
 547
 548   /* IDX bits for quantization in the pair singles x-type instructions.  */
 549 #define PSQM PSQ + 1
 550   {  0x7, 7, 0, 0, 0 },
 551
 552   /* Smaller D field for quantization in the pair singles instructions.  */
 553 #define PSD PSQM + 1
 554   {  0xfff, 0, 0, 0,  PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 555
 556 #define A_L PSD + 1
 557 #define W A_L
 558 #define MTMSRD_L W
 559   { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
 560
 561 #define RMC MTMSRD_L + 1
 562   { 0x3, 9, NULL, NULL, 0 },
 563
 564 #define R RMC + 1
 565   { 0x1, 16, NULL, NULL, 0 },
 566
 567 #define SP R + 1
 568   { 0x3, 19, NULL, NULL, 0 },
 569
 570 #define S SP + 1
 571   { 0x1, 20, NULL, NULL, 0 },
 572
 573   /* SH field starting at bit position 16.  */
 574 #define SH16 S + 1
 575   /* The DCM and DGM fields in a Z form instruction.  */
 576 #define DCM SH16
 577 #define DGM DCM
 578   { 0x3f, 10, NULL, NULL, 0 },
 579
 580   /* The EH field in larx instruction.  */
 581 #define EH SH16 + 1
 582   { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
 583
 584   /* The L field in an mtfsf or XFL form instruction.  */
 585 #define XFL_L EH + 1
 586   { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
 587
 588   /* Xilinx APU related masks and macros */
 589 #define FCRT XFL_L + 1
 590 #define FCRT_MASK (0x1f << 21)
 591   { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
 592
 593   /* Xilinx FSL related masks and macros */
 594 #define FSL FCRT + 1
 595 #define FSL_MASK (0x1f << 11)
 596   { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
 597
 598   /* Xilinx UDI related masks and macros */
 599 #define URT FSL + 1
 600   { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
 601
 602 #define URA URT + 1
 603   { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
 604
 605 #define URB URA + 1
 606   { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
 607
 608 #define URC URB + 1
 609   { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
 610
 611   /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
 612 #define XS6 URC + 1
 613 #define XT6 XS6
 614   { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
 615
 616   /* The XA field in an XX3 form instruction.  This is split.  */
 617 #define XA6 XT6 + 1
 618   { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
 619
 620   /* The XB field in an XX2 or XX3 form instruction.  This is split.  */
 621 #define XB6 XA6 + 1
 622   { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
 623
 624   /* The XB field in an XX3 form instruction when it must be the same as
 625      the XA field in the instruction.  This is used in extended mnemonics
 626      like xvmovdp.  This is split.  */
 627 #define XB6S XB6 + 1
 628   { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
 629
 630   /* The XC field in an XX4 form instruction.  This is split.  */
 631 #define XC6 XB6S + 1
 632   { 0x3f, -1, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
 633
 634   /* The DM or SHW field in an XX3 form instruction.  */
 635 #define DM XC6 + 1
 636 #define SHW DM
 637   { 0x3, 8, NULL, NULL, 0 },
 638
 639   /* The DM field in an extended mnemonic XX3 form instruction.  */
 640 #define DMEX DM + 1
 641   { 0x3, 8, insert_dm, extract_dm, 0 },
 642
 643   /* The UIM field in an XX2 form instruction.  */
 644 #define UIM DMEX + 1
 645   { 0x3, 16, NULL, NULL, 0 },
 646
 647 #define ERAT_T UIM + 1
 648   { 0x7, 21, NULL, NULL, 0 },
 649 };
 650
 651 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 652                                            / sizeof (powerpc_operands[0]));
 653
 654 /* The functions used to insert and extract complicated operands.  */
 655
 656 /* The BA field in an XL form instruction when it must be the same as
 657    the BT field in the same instruction.  This operand is marked FAKE.
 658    The insertion function just copies the BT field into the BA field,
 659    and the extraction function just checks that the fields are the
 660    same.  */
 661
 662 static unsigned long
 663 insert_bat (unsigned long insn,
 664             long value ATTRIBUTE_UNUSED,
 665             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 666             const char **errmsg ATTRIBUTE_UNUSED)
 667 {
 668   return insn | (((insn >> 21) & 0x1f) << 16);
 669 }
 670
 671 static long
 672 extract_bat (unsigned long insn,
 673              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 674              int *invalid)
 675 {
 676   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 677     *invalid = 1;
 678   return 0;
 679 }
 680
 681 /* The BB field in an XL form instruction when it must be the same as
 682    the BA field in the same instruction.  This operand is marked FAKE.
 683    The insertion function just copies the BA field into the BB field,
 684    and the extraction function just checks that the fields are the
 685    same.  */
 686
 687 static unsigned long
 688 insert_bba (unsigned long insn,
 689             long value ATTRIBUTE_UNUSED,
 690             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 691             const char **errmsg ATTRIBUTE_UNUSED)
 692 {
 693   return insn | (((insn >> 16) & 0x1f) << 11);
 694 }
 695
 696 static long
 697 extract_bba (unsigned long insn,
 698              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 699              int *invalid)
 700 {
 701   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 702     *invalid = 1;
 703   return 0;
 704 }
 705
 706 /* The BD field in a B form instruction when the - modifier is used.
 707    This modifier means that the branch is not expected to be taken.
 708    For chips built to versions of the architecture prior to version 2
 709    (ie. not Power4 compatible), we set the y bit of the BO field to 1
 710    if the offset is negative.  When extracting, we require that the y
 711    bit be 1 and that the offset be positive, since if the y bit is 0
 712    we just want to print the normal form of the instruction.
 713    Power4 compatible targets use two bits, "a", and "t", instead of
 714    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
 715    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
 716    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
 717    for branch on CTR.  We only handle the taken/not-taken hint here.
 718    Note that we don't relax the conditions tested here when
 719    disassembling with -Many because insns using extract_bdm and
 720    extract_bdp always occur in pairs.  One or the other will always
 721    be valid.  */
 722
 723 static unsigned long
 724 insert_bdm (unsigned long insn,
 725             long value,
 726             ppc_cpu_t dialect,
 727             const char **errmsg ATTRIBUTE_UNUSED)
 728 {
 729   if ((dialect & PPC_OPCODE_POWER4) == 0)
 730     {
 731       if ((value & 0x8000) != 0)
 732         insn |= 1 << 21;
 733     }
 734   else
 735     {
 736       if ((insn & (0x14 << 21)) == (0x04 << 21))
 737         insn |= 0x02 << 21;
 738       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 739         insn |= 0x08 << 21;
 740     }
 741   return insn | (value & 0xfffc);
 742 }
 743
 744 static long
 745 extract_bdm (unsigned long insn,
 746              ppc_cpu_t dialect,
 747              int *invalid)
 748 {
 749   if ((dialect & PPC_OPCODE_POWER4) == 0)
 750     {
 751       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
 752         *invalid = 1;
 753     }
 754   else
 755     {
 756       if ((insn & (0x17 << 21)) != (0x06 << 21)
 757           && (insn & (0x1d << 21)) != (0x18 << 21))
 758         *invalid = 1;
 759     }
 760
 761   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 762 }
 763
 764 /* The BD field in a B form instruction when the + modifier is used.
 765    This is like BDM, above, except that the branch is expected to be
 766    taken.  */
 767
 768 static unsigned long
 769 insert_bdp (unsigned long insn,
 770             long value,
 771             ppc_cpu_t dialect,
 772             const char **errmsg ATTRIBUTE_UNUSED)
 773 {
 774   if ((dialect & PPC_OPCODE_POWER4) == 0)
 775     {
 776       if ((value & 0x8000) == 0)
 777         insn |= 1 << 21;
 778     }
 779   else
 780     {
 781       if ((insn & (0x14 << 21)) == (0x04 << 21))
 782         insn |= 0x03 << 21;
 783       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 784         insn |= 0x09 << 21;
 785     }
 786   return insn | (value & 0xfffc);
 787 }
 788
 789 static long
 790 extract_bdp (unsigned long insn,
 791              ppc_cpu_t dialect,
 792              int *invalid)
 793 {
 794   if ((dialect & PPC_OPCODE_POWER4) == 0)
 795     {
 796       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
 797         *invalid = 1;
 798     }
 799   else
 800     {
 801       if ((insn & (0x17 << 21)) != (0x07 << 21)
 802           && (insn & (0x1d << 21)) != (0x19 << 21))
 803         *invalid = 1;
 804     }
 805
 806   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 807 }
 808
 809 /* Check for legal values of a BO field.  */
 810
 811 static int
 812 valid_bo (long value, ppc_cpu_t dialect, int extract)
 813 {
 814   if ((dialect & PPC_OPCODE_POWER4) == 0)
 815     {
 816       int valid;
 817       /* Certain encodings have bits that are required to be zero.
 818          These are (z must be zero, y may be anything):
 819              001zy
 820              011zy
 821              1z00y
 822              1z01y
 823              1z1zz
 824       */
 825       switch (value & 0x14)
 826         {
 827         default:
 828         case 0:
 829           valid = 1;
 830           break;
 831         case 0x4:
 832           valid = (value & 0x2) == 0;
 833           break;
 834         case 0x10:
 835           valid = (value & 0x8) == 0;
 836           break;
 837         case 0x14:
 838           valid = value == 0x14;
 839           break;
 840         }
 841       /* When disassembling with -Many, accept power4 encodings too.  */
 842       if (valid
 843           || (dialect & PPC_OPCODE_ANY) == 0
 844           || !extract)
 845         return valid;
 846     }
 847
 848   /* Certain encodings have bits that are required to be zero.
 849      These are (z must be zero, a & t may be anything):
 850          0000z
 851          0001z
 852          0100z
 853          0101z
 854          001at
 855          011at
 856          1a00t
 857          1a01t
 858          1z1zz
 859   */
 860   if ((value & 0x14) == 0)
 861     return (value & 0x1) == 0;
 862   else if ((value & 0x14) == 0x14)
 863     return value == 0x14;
 864   else
 865     return 1;
 866 }
 867
 868 /* The BO field in a B form instruction.  Warn about attempts to set
 869    the field to an illegal value.  */
 870
 871 static unsigned long
 872 insert_bo (unsigned long insn,
 873            long value,
 874            ppc_cpu_t dialect,
 875            const char **errmsg)
 876 {
 877   if (!valid_bo (value, dialect, 0))
 878     *errmsg = _("invalid conditional option");
 879   return insn | ((value & 0x1f) << 21);
 880 }
 881
 882 static long
 883 extract_bo (unsigned long insn,
 884             ppc_cpu_t dialect,
 885             int *invalid)
 886 {
 887   long value;
 888
 889   value = (insn >> 21) & 0x1f;
 890   if (!valid_bo (value, dialect, 1))
 891     *invalid = 1;
 892   return value;
 893 }
 894
 895 /* The BO field in a B form instruction when the + or - modifier is
 896    used.  This is like the BO field, but it must be even.  When
 897    extracting it, we force it to be even.  */
 898
 899 static unsigned long
 900 insert_boe (unsigned long insn,
 901             long value,
 902             ppc_cpu_t dialect,
 903             const char **errmsg)
 904 {
 905   if (!valid_bo (value, dialect, 0))
 906     *errmsg = _("invalid conditional option");
 907   else if ((value & 1) != 0)
 908     *errmsg = _("attempt to set y bit when using + or - modifier");
 909
 910   return insn | ((value & 0x1f) << 21);
 911 }
 912
 913 static long
 914 extract_boe (unsigned long insn,
 915              ppc_cpu_t dialect,
 916              int *invalid)
 917 {
 918   long value;
 919
 920   value = (insn >> 21) & 0x1f;
 921   if (!valid_bo (value, dialect, 1))
 922     *invalid = 1;
 923   return value & 0x1e;
 924 }
 925
 926 /* FXM mask in mfcr and mtcrf instructions.  */
 927
 928 static unsigned long
 929 insert_fxm (unsigned long insn,
 930             long value,
 931             ppc_cpu_t dialect,
 932             const char **errmsg)
 933 {
 934   /* If we're handling the mfocrf and mtocrf insns ensure that exactly
 935      one bit of the mask field is set.  */
 936   if ((insn & (1 << 20)) != 0)
 937     {
 938       if (value == 0 || (value & -value) != value)
 939         {
 940           *errmsg = _("invalid mask field");
 941           value = 0;
 942         }
 943     }
 944
 945   /* If the optional field on mfcr is missing that means we want to use
 946      the old form of the instruction that moves the whole cr.  In that
 947      case we'll have VALUE zero.  There doesn't seem to be a way to
 948      distinguish this from the case where someone writes mfcr %r3,0.  */
 949   else if (value == 0)
 950     ;
 951
 952   /* If only one bit of the FXM field is set, we can use the new form
 953      of the instruction, which is faster.  Unlike the Power4 branch hint
 954      encoding, this is not backward compatible.  Do not generate the
 955      new form unless -mpower4 has been given, or -many and the two
 956      operand form of mfcr was used.  */
 957   else if ((value & -value) == value
 958            && ((dialect & PPC_OPCODE_POWER4) != 0
 959                || ((dialect & PPC_OPCODE_ANY) != 0
 960                    && (insn & (0x3ff << 1)) == 19 << 1)))
 961     insn |= 1 << 20;
 962
 963   /* Any other value on mfcr is an error.  */
 964   else if ((insn & (0x3ff << 1)) == 19 << 1)
 965     {
 966       *errmsg = _("ignoring invalid mfcr mask");
 967       value = 0;
 968     }
 969
 970   return insn | ((value & 0xff) << 12);
 971 }
 972
 973 static long
 974 extract_fxm (unsigned long insn,
 975              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 976              int *invalid)
 977 {
 978   long mask = (insn >> 12) & 0xff;
 979
 980   /* Is this a Power4 insn?  */
 981   if ((insn & (1 << 20)) != 0)
 982     {
 983       /* Exactly one bit of MASK should be set.  */
 984       if (mask == 0 || (mask & -mask) != mask)
 985         *invalid = 1;
 986     }
 987
 988   /* Check that non-power4 form of mfcr has a zero MASK.  */
 989   else if ((insn & (0x3ff << 1)) == 19 << 1)
 990     {
 991       if (mask != 0)
 992         *invalid = 1;
 993     }
 994
 995   return mask;
 996 }
 997
 998 /* The MB and ME fields in an M form instruction expressed as a single
 999    operand which is itself a bitmask.  The extraction function always
1000    marks it as invalid, since we never want to recognize an
1001    instruction which uses a field of this type.  */
1002
1003 static unsigned long
1004 insert_mbe (unsigned long insn,
1005             long value,
1006             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1007             const char **errmsg)
1008 {
1009   unsigned long uval, mask;
1010   int mb, me, mx, count, last;
1011
1012   uval = value;
1013
1014   if (uval == 0)
1015     {
1016       *errmsg = _("illegal bitmask");
1017       return insn;
1018     }
1019
1020   mb = 0;
1021   me = 32;
1022   if ((uval & 1) != 0)
1023     last = 1;
1024   else
1025     last = 0;
1026   count = 0;
1027
1028   /* mb: location of last 0->1 transition */
1029   /* me: location of last 1->0 transition */
1030   /* count: # transitions */
1031
1032   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1033     {
1034       if ((uval & mask) && !last)
1035         {
1036           ++count;
1037           mb = mx;
1038           last = 1;
1039         }
1040       else if (!(uval & mask) && last)
1041         {
1042           ++count;
1043           me = mx;
1044           last = 0;
1045         }
1046     }
1047   if (me == 0)
1048     me = 32;
1049
1050   if (count != 2 && (count != 0 || ! last))
1051     *errmsg = _("illegal bitmask");
1052
1053   return insn | (mb << 6) | ((me - 1) << 1);
1054 }
1055
1056 static long
1057 extract_mbe (unsigned long insn,
1058              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1059              int *invalid)
1060 {
1061   long ret;
1062   int mb, me;
1063   int i;
1064
1065   *invalid = 1;
1066
1067   mb = (insn >> 6) & 0x1f;
1068   me = (insn >> 1) & 0x1f;
1069   if (mb < me + 1)
1070     {
1071       ret = 0;
1072       for (i = mb; i <= me; i++)
1073         ret |= 1L << (31 - i);
1074     }
1075   else if (mb == me + 1)
1076     ret = ~0;
1077   else /* (mb > me + 1) */
1078     {
1079       ret = ~0;
1080       for (i = me + 1; i < mb; i++)
1081         ret &= ~(1L << (31 - i));
1082     }
1083   return ret;
1084 }
1085
1086 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1087    is wrapped to the low end.  */
1088
1089 static unsigned long
1090 insert_mb6 (unsigned long insn,
1091             long value,
1092             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1093             const char **errmsg ATTRIBUTE_UNUSED)
1094 {
1095   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1096 }
1097
1098 static long
1099 extract_mb6 (unsigned long insn,
1100              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1101              int *invalid ATTRIBUTE_UNUSED)
1102 {
1103   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1104 }
1105
1106 /* The NB field in an X form instruction.  The value 32 is stored as
1107    0.  */
1108
1109 static long
1110 extract_nb (unsigned long insn,
1111             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1112             int *invalid ATTRIBUTE_UNUSED)
1113 {
1114   long ret;
1115
1116   ret = (insn >> 11) & 0x1f;
1117   if (ret == 0)
1118     ret = 32;
1119   return ret;
1120 }
1121
1122 /* The NSI field in a D form instruction.  This is the same as the SI
1123    field, only negated.  The extraction function always marks it as
1124    invalid, since we never want to recognize an instruction which uses
1125    a field of this type.  */
1126
1127 static unsigned long
1128 insert_nsi (unsigned long insn,
1129             long value,
1130             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1131             const char **errmsg ATTRIBUTE_UNUSED)
1132 {
1133   return insn | (-value & 0xffff);
1134 }
1135
1136 static long
1137 extract_nsi (unsigned long insn,
1138              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1139              int *invalid)
1140 {
1141   *invalid = 1;
1142   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1143 }
1144
1145 /* The RA field in a D or X form instruction which is an updating
1146    load, which means that the RA field may not be zero and may not
1147    equal the RT field.  */
1148
1149 static unsigned long
1150 insert_ral (unsigned long insn,
1151             long value,
1152             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1153             const char **errmsg)
1154 {
1155   if (value == 0
1156       || (unsigned long) value == ((insn >> 21) & 0x1f))
1157     *errmsg = "invalid register operand when updating";
1158   return insn | ((value & 0x1f) << 16);
1159 }
1160
1161 /* The RA field in an lmw instruction, which has special value
1162    restrictions.  */
1163
1164 static unsigned long
1165 insert_ram (unsigned long insn,
1166             long value,
1167             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1168             const char **errmsg)
1169 {
1170   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1171     *errmsg = _("index register in load range");
1172   return insn | ((value & 0x1f) << 16);
1173 }
1174
1175 /* The RA field in the DQ form lq instruction, which has special
1176    value restrictions.  */
1177
1178 static unsigned long
1179 insert_raq (unsigned long insn,
1180             long value,
1181             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1182             const char **errmsg)
1183 {
1184   long rtvalue = (insn & RT_MASK) >> 21;
1185
1186   if (value == rtvalue)
1187     *errmsg = _("source and target register operands must be different");
1188   return insn | ((value & 0x1f) << 16);
1189 }
1190
1191 /* The RA field in a D or X form instruction which is an updating
1192    store or an updating floating point load, which means that the RA
1193    field may not be zero.  */
1194
1195 static unsigned long
1196 insert_ras (unsigned long insn,
1197             long value,
1198             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1199             const char **errmsg)
1200 {
1201   if (value == 0)
1202     *errmsg = _("invalid register operand when updating");
1203   return insn | ((value & 0x1f) << 16);
1204 }
1205
1206 /* The RB field in an X form instruction when it must be the same as
1207    the RS field in the instruction.  This is used for extended
1208    mnemonics like mr.  This operand is marked FAKE.  The insertion
1209    function just copies the BT field into the BA field, and the
1210    extraction function just checks that the fields are the same.  */
1211
1212 static unsigned long
1213 insert_rbs (unsigned long insn,
1214             long value ATTRIBUTE_UNUSED,
1215             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1216             const char **errmsg ATTRIBUTE_UNUSED)
1217 {
1218   return insn | (((insn >> 21) & 0x1f) << 11);
1219 }
1220
1221 static long
1222 extract_rbs (unsigned long insn,
1223              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1224              int *invalid)
1225 {
1226   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1227     *invalid = 1;
1228   return 0;
1229 }
1230
1231 /* The SH field in an MD form instruction.  This is split.  */
1232
1233 static unsigned long
1234 insert_sh6 (unsigned long insn,
1235             long value,
1236             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1237             const char **errmsg ATTRIBUTE_UNUSED)
1238 {
1239   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1240 }
1241
1242 static long
1243 extract_sh6 (unsigned long insn,
1244              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1245              int *invalid ATTRIBUTE_UNUSED)
1246 {
1247   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1248 }
1249
1250 /* The SPR field in an XFX form instruction.  This is flipped--the
1251    lower 5 bits are stored in the upper 5 and vice- versa.  */
1252
1253 static unsigned long
1254 insert_spr (unsigned long insn,
1255             long value,
1256             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1257             const char **errmsg ATTRIBUTE_UNUSED)
1258 {
1259   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1260 }
1261
1262 static long
1263 extract_spr (unsigned long insn,
1264              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1265              int *invalid ATTRIBUTE_UNUSED)
1266 {
1267   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1268 }
1269
1270 /* Some dialects have 8 SPRG registers instead of the standard 4.  */
1271
1272 static unsigned long
1273 insert_sprg (unsigned long insn,
1274              long value,
1275              ppc_cpu_t dialect,
1276              const char **errmsg)
1277 {
1278   if (value > 7
1279       || (value > 3
1280           && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0))
1281     *errmsg = _("invalid sprg number");
1282
1283   /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1284      user mode.  Anything else must use spr 272..279.  */
1285   if (value <= 3 || (insn & 0x100) != 0)
1286     value |= 0x10;
1287
1288   return insn | ((value & 0x17) << 16);
1289 }
1290
1291 static long
1292 extract_sprg (unsigned long insn,
1293               ppc_cpu_t dialect,
1294               int *invalid)
1295 {
1296   unsigned long val = (insn >> 16) & 0x1f;
1297
1298   /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
1299      If not BOOKE or 405, then both use only 272..275.  */
1300   if ((val - 0x10 > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)
1301       || (val - 0x10 > 7 && (insn & 0x100) != 0)
1302       || val <= 3
1303       || (val & 8) != 0)
1304     *invalid = 1;
1305   return val & 7;
1306 }
1307
1308 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1309    is optional.  When TBR is omitted, it must be inserted as 268 (the
1310    magic number of the TB register).  These functions treat 0
1311    (indicating an omitted optional operand) as 268.  This means that
1312    ``mftb 4,0'' is not handled correctly.  This does not matter very
1313    much, since the architecture manual does not define mftb as
1314    accepting any values other than 268 or 269.  */
1315
1316 #define TB (268)
1317
1318 static unsigned long
1319 insert_tbr (unsigned long insn,
1320             long value,
1321             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1322             const char **errmsg ATTRIBUTE_UNUSED)
1323 {
1324   if (value == 0)
1325     value = TB;
1326   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1327 }
1328
1329 static long
1330 extract_tbr (unsigned long insn,
1331              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1332              int *invalid ATTRIBUTE_UNUSED)
1333 {
1334   long ret;
1335
1336   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1337   if (ret == TB)
1338     ret = 0;
1339   return ret;
1340 }
1341
1342 /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
1343
1344 static unsigned long
1345 insert_xt6 (unsigned long insn,
1346             long value,
1347             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1348             const char **errmsg ATTRIBUTE_UNUSED)
1349 {
1350   return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
1351 }
1352
1353 static long
1354 extract_xt6 (unsigned long insn,
1355              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1356              int *invalid ATTRIBUTE_UNUSED)
1357 {
1358   return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
1359 }
1360
1361 /* The XA field in an XX3 form instruction.  This is split.  */
1362
1363 static unsigned long
1364 insert_xa6 (unsigned long insn,
1365             long value,
1366             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1367             const char **errmsg ATTRIBUTE_UNUSED)
1368 {
1369   return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
1370 }
1371
1372 static long
1373 extract_xa6 (unsigned long insn,
1374              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1375              int *invalid ATTRIBUTE_UNUSED)
1376 {
1377   return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1378 }
1379
1380 /* The XB field in an XX3 form instruction.  This is split.  */
1381
1382 static unsigned long
1383 insert_xb6 (unsigned long insn,
1384             long value,
1385             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1386             const char **errmsg ATTRIBUTE_UNUSED)
1387 {
1388   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1389 }
1390
1391 static long
1392 extract_xb6 (unsigned long insn,
1393              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1394              int *invalid ATTRIBUTE_UNUSED)
1395 {
1396   return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
1397 }
1398
1399 /* The XB field in an XX3 form instruction when it must be the same as
1400    the XA field in the instruction.  This is used for extended
1401    mnemonics like xvmovdp.  This operand is marked FAKE.  The insertion
1402    function just copies the XA field into the XB field, and the
1403    extraction function just checks that the fields are the same.  */
1404
1405 static unsigned long
1406 insert_xb6s (unsigned long insn,
1407             long value ATTRIBUTE_UNUSED,
1408             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1409             const char **errmsg ATTRIBUTE_UNUSED)
1410 {
1411   return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
1412 }
1413
1414 static long
1415 extract_xb6s (unsigned long insn,
1416              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1417              int *invalid)
1418 {
1419   if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1420       || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
1421     *invalid = 1;
1422   return 0;
1423 }
1424
1425 /* The XC field in an XX4 form instruction.  This is split.  */
1426
1427 static unsigned long
1428 insert_xc6 (unsigned long insn,
1429             long value,
1430             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1431             const char **errmsg ATTRIBUTE_UNUSED)
1432 {
1433   return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
1434 }
1435
1436 static long
1437 extract_xc6 (unsigned long insn,
1438              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1439              int *invalid ATTRIBUTE_UNUSED)
1440 {
1441   return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
1442 }
1443
1444 static unsigned long
1445 insert_dm (unsigned long insn,
1446            long value,
1447            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1448            const char **errmsg)
1449 {
1450   if (value != 0 && value != 1)
1451     *errmsg = _("invalid constant");
1452   return insn | (((value) ? 3 : 0) << 8);
1453 }
1454
1455 static long
1456 extract_dm (unsigned long insn,
1457             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1458             int *invalid)
1459 {
1460   long value;
1461
1462   value = (insn >> 8) & 3;
1463   if (value != 0 && value != 3)
1464     *invalid = 1;
1465   return (value) ? 1 : 0;
1466 }
1467 \f
1468 /* Macros used to form opcodes.  */
1469
1470 /* The main opcode.  */
1471 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1472 #define OP_MASK OP (0x3f)
1473
1474 /* The main opcode combined with a trap code in the TO field of a D
1475    form instruction.  Used for extended mnemonics for the trap
1476    instructions.  */
1477 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1478 #define OPTO_MASK (OP_MASK | TO_MASK)
1479
1480 /* The main opcode combined with a comparison size bit in the L field
1481    of a D form or X form instruction.  Used for extended mnemonics for
1482    the comparison instructions.  */
1483 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1484 #define OPL_MASK OPL (0x3f,1)
1485
1486 /* An A form instruction.  */
1487 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1488 #define A_MASK A (0x3f, 0x1f, 1)
1489
1490 /* An A_MASK with the FRB field fixed.  */
1491 #define AFRB_MASK (A_MASK | FRB_MASK)
1492
1493 /* An A_MASK with the FRC field fixed.  */
1494 #define AFRC_MASK (A_MASK | FRC_MASK)
1495
1496 /* An A_MASK with the FRA and FRC fields fixed.  */
1497 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1498
1499 /* An AFRAFRC_MASK, but with L bit clear.  */
1500 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1501
1502 /* A B form instruction.  */
1503 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1504 #define B_MASK B (0x3f, 1, 1)
1505
1506 /* A B form instruction setting the BO field.  */
1507 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1508 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1509
1510 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1511    matching a conditional branch regardless of the setting of the y
1512    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1513 #define Y_MASK   (((unsigned long) 1) << 21)
1514 #define AT1_MASK (((unsigned long) 3) << 21)
1515 #define AT2_MASK (((unsigned long) 9) << 21)
1516 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1517 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1518
1519 /* A B form instruction setting the BO field and the condition bits of
1520    the BI field.  */
1521 #define BBOCB(op, bo, cb, aa, lk) \
1522   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1523 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1524
1525 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1526 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1527 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1528 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1529
1530 /* A BBOYCB_MASK in which the BI field is fixed.  */
1531 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1532 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1533
1534 /* An Context form instruction.  */
1535 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1536 #define CTX_MASK CTX(0x3f, 0x7)
1537
1538 /* An User Context form instruction.  */
1539 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1540 #define UCTX_MASK UCTX(0x3f, 0x1f)
1541
1542 /* The main opcode mask with the RA field clear.  */
1543 #define DRA_MASK (OP_MASK | RA_MASK)
1544
1545 /* A DS form instruction.  */
1546 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1547 #define DS_MASK DSO (0x3f, 3)
1548
1549 /* An EVSEL form instruction.  */
1550 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1551 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1552
1553 /* An M form instruction.  */
1554 #define M(op, rc) (OP (op) | ((rc) & 1))
1555 #define M_MASK M (0x3f, 1)
1556
1557 /* An M form instruction with the ME field specified.  */
1558 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1559
1560 /* An M_MASK with the MB and ME fields fixed.  */
1561 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1562
1563 /* An M_MASK with the SH and ME fields fixed.  */
1564 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1565
1566 /* An MD form instruction.  */
1567 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1568 #define MD_MASK MD (0x3f, 0x7, 1)
1569
1570 /* An MD_MASK with the MB field fixed.  */
1571 #define MDMB_MASK (MD_MASK | MB6_MASK)
1572
1573 /* An MD_MASK with the SH field fixed.  */
1574 #define MDSH_MASK (MD_MASK | SH6_MASK)
1575
1576 /* An MDS form instruction.  */
1577 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1578 #define MDS_MASK MDS (0x3f, 0xf, 1)
1579
1580 /* An MDS_MASK with the MB field fixed.  */
1581 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1582
1583 /* An SC form instruction.  */
1584 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1585 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1586
1587 /* An VX form instruction.  */
1588 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1589
1590 /* The mask for an VX form instruction.  */
1591 #define VX_MASK VX(0x3f, 0x7ff)
1592
1593 /* An VA form instruction.  */
1594 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1595
1596 /* The mask for an VA form instruction.  */
1597 #define VXA_MASK VXA(0x3f, 0x3f)
1598
1599 /* An VXR form instruction.  */
1600 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1601
1602 /* The mask for a VXR form instruction.  */
1603 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1604
1605 /* An X form instruction.  */
1606 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1607
1608 /* An XX2 form instruction.  */
1609 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
1610
1611 /* An XX3 form instruction.  */
1612 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
1613
1614 /* An XX3 form instruction with the RC bit specified.  */
1615 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
1616
1617 /* An XX4 form instruction.  */
1618 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
1619
1620 /* A Z form instruction.  */
1621 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1622
1623 /* An X form instruction with the RC bit specified.  */
1624 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1625
1626 /* A Z form instruction with the RC bit specified.  */
1627 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1628
1629 /* The mask for an X form instruction.  */
1630 #define X_MASK XRC (0x3f, 0x3ff, 1)
1631
1632 /* An X form wait instruction with everything filled in except the WC field.  */
1633 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
1634
1635 /* The mask for an XX1 form instruction.  */
1636 #define XX1_MASK X (0x3f, 0x3ff)
1637
1638 /* The mask for an XX2 form instruction.  */
1639 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
1640
1641 /* The mask for an XX2 form instruction with the UIM bits specified.  */
1642 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
1643
1644 /* The mask for an XX2 form instruction with the BF bits specified.  */
1645 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
1646
1647 /* The mask for an XX3 form instruction.  */
1648 #define XX3_MASK XX3 (0x3f, 0xff)
1649
1650 /* The mask for an XX3 form instruction with the BF bits specified.  */
1651 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
1652
1653 /* The mask for an XX3 form instruction with the DM or SHW bits specified.  */
1654 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
1655 #define XX3SHW_MASK XX3DM_MASK
1656
1657 /* The mask for an XX4 form instruction.  */
1658 #define XX4_MASK XX4 (0x3f, 0x3)
1659
1660 /* An X form wait instruction with everything filled in except the WC field.  */
1661 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
1662
1663 /* The mask for a Z form instruction.  */
1664 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1665 #define Z2_MASK ZRC (0x3f, 0xff, 1)
1666
1667 /* An X_MASK with the RA field fixed.  */
1668 #define XRA_MASK (X_MASK | RA_MASK)
1669
1670 /* An XRA_MASK with the W field clear.  */
1671 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1672
1673 /* An X_MASK with the RB field fixed.  */
1674 #define XRB_MASK (X_MASK | RB_MASK)
1675
1676 /* An X_MASK with the RT field fixed.  */
1677 #define XRT_MASK (X_MASK | RT_MASK)
1678
1679 /* An XRT_MASK mask with the L bits clear.  */
1680 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1681
1682 /* An X_MASK with the RA and RB fields fixed.  */
1683 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1684
1685 /* An XRARB_MASK, but with the L bit clear.  */
1686 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1687
1688 /* An X_MASK with the RT and RA fields fixed.  */
1689 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1690
1691 /* An XRTRA_MASK, but with L bit clear.  */
1692 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1693
1694 /* An X form instruction with the L bit specified.  */
1695 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1696
1697 /* An X form instruction with the L bits specified.  */
1698 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1699
1700 /* An X form instruction with RT fields specified */
1701 #define XRT(op, xop, rt) (X ((op), (xop)) \
1702         | ((((unsigned long)(rt)) & 0x1f) << 21))
1703
1704 /* An X form instruction with RT and RA fields specified */
1705 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
1706         | ((((unsigned long)(rt)) & 0x1f) << 21) \
1707         | ((((unsigned long)(ra)) & 0x1f) << 16))
1708
1709 /* The mask for an X form comparison instruction.  */
1710 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1711
1712 /* The mask for an X form comparison instruction with the L field
1713    fixed.  */
1714 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1715
1716 /* An X form trap instruction with the TO field specified.  */
1717 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1718 #define XTO_MASK (X_MASK | TO_MASK)
1719
1720 /* An X form tlb instruction with the SH field specified.  */
1721 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1722 #define XTLB_MASK (X_MASK | SH_MASK)
1723
1724 /* An X form sync instruction.  */
1725 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1726
1727 /* An X form sync instruction with everything filled in except the LS field.  */
1728 #define XSYNC_MASK (0xff9fffff)
1729
1730 /* An X_MASK, but with the EH bit clear.  */
1731 #define XEH_MASK (X_MASK & ~((unsigned long )1))
1732
1733 /* An X form AltiVec dss instruction.  */
1734 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1735 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1736
1737 /* An XFL form instruction.  */
1738 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1739 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
1740
1741 /* An X form isel instruction.  */
1742 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1743 #define XISEL_MASK      XISEL(0x3f, 0x1f)
1744
1745 /* An XL form instruction with the LK field set to 0.  */
1746 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1747
1748 /* An XL form instruction which uses the LK field.  */
1749 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1750
1751 /* The mask for an XL form instruction.  */
1752 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1753
1754 /* An XL form instruction which explicitly sets the BO field.  */
1755 #define XLO(op, bo, xop, lk) \
1756   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1757 #define XLO_MASK (XL_MASK | BO_MASK)
1758
1759 /* An XL form instruction which explicitly sets the y bit of the BO
1760    field.  */
1761 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1762 #define XLYLK_MASK (XL_MASK | Y_MASK)
1763
1764 /* An XL form instruction which sets the BO field and the condition
1765    bits of the BI field.  */
1766 #define XLOCB(op, bo, cb, xop, lk) \
1767   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1768 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1769
1770 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1771 #define XLBB_MASK (XL_MASK | BB_MASK)
1772 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1773 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1774
1775 /* A mask for branch instructions using the BH field.  */
1776 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1777
1778 /* An XL_MASK with the BO and BB fields fixed.  */
1779 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1780
1781 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1782 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1783
1784 /* An X form mbar instruction with MO field.  */
1785 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
1786
1787 /* An XO form instruction.  */
1788 #define XO(op, xop, oe, rc) \
1789   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1790 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1791
1792 /* An XO_MASK with the RB field fixed.  */
1793 #define XORB_MASK (XO_MASK | RB_MASK)
1794
1795 /* An XOPS form instruction for paired singles.  */
1796 #define XOPS(op, xop, rc) \
1797   (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1798 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
1799
1800
1801 /* An XS form instruction.  */
1802 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1803 #define XS_MASK XS (0x3f, 0x1ff, 1)
1804
1805 /* A mask for the FXM version of an XFX form instruction.  */
1806 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1807
1808 /* An XFX form instruction with the FXM field filled in.  */
1809 #define XFXM(op, xop, fxm, p4) \
1810   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1811    | ((unsigned long)(p4) << 20))
1812
1813 /* An XFX form instruction with the SPR field filled in.  */
1814 #define XSPR(op, xop, spr) \
1815   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1816 #define XSPR_MASK (X_MASK | SPR_MASK)
1817
1818 /* An XFX form instruction with the SPR field filled in except for the
1819    SPRBAT field.  */
1820 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1821
1822 /* An XFX form instruction with the SPR field filled in except for the
1823    SPRG field.  */
1824 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1825
1826 /* An X form instruction with everything filled in except the E field.  */
1827 #define XE_MASK (0xffff7fff)
1828
1829 /* An X form user context instruction.  */
1830 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1831 #define XUC_MASK      XUC(0x3f, 0x1f)
1832
1833 /* An XW form instruction.  */
1834 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
1835 /* The mask for a G form instruction. rc not supported at present.  */
1836 #define XW_MASK XW (0x3f, 0x3f, 0)
1837
1838 /* An APU form instruction.  */
1839 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
1840
1841 /* The mask for an APU form instruction.  */
1842 #define APU_MASK APU (0x3f, 0x3ff, 1)
1843 #define APU_RT_MASK (APU_MASK | RT_MASK)
1844 #define APU_RA_MASK (APU_MASK | RA_MASK)
1845
1846 /* The BO encodings used in extended conditional branch mnemonics.  */
1847 #define BODNZF  (0x0)
1848 #define BODNZFP (0x1)
1849 #define BODZF   (0x2)
1850 #define BODZFP  (0x3)
1851 #define BODNZT  (0x8)
1852 #define BODNZTP (0x9)
1853 #define BODZT   (0xa)
1854 #define BODZTP  (0xb)
1855
1856 #define BOF     (0x4)
1857 #define BOFP    (0x5)
1858 #define BOFM4   (0x6)
1859 #define BOFP4   (0x7)
1860 #define BOT     (0xc)
1861 #define BOTP    (0xd)
1862 #define BOTM4   (0xe)
1863 #define BOTP4   (0xf)
1864
1865 #define BODNZ   (0x10)
1866 #define BODNZP  (0x11)
1867 #define BODZ    (0x12)
1868 #define BODZP   (0x13)
1869 #define BODNZM4 (0x18)
1870 #define BODNZP4 (0x19)
1871 #define BODZM4  (0x1a)
1872 #define BODZP4  (0x1b)
1873
1874 #define BOU     (0x14)
1875
1876 /* The BI condition bit encodings used in extended conditional branch
1877    mnemonics.  */
1878 #define CBLT    (0)
1879 #define CBGT    (1)
1880 #define CBEQ    (2)
1881 #define CBSO    (3)
1882
1883 /* The TO encodings used in extended trap mnemonics.  */
1884 #define TOLGT   (0x1)
1885 #define TOLLT   (0x2)
1886 #define TOEQ    (0x4)
1887 #define TOLGE   (0x5)
1888 #define TOLNL   (0x5)
1889 #define TOLLE   (0x6)
1890 #define TOLNG   (0x6)
1891 #define TOGT    (0x8)
1892 #define TOGE    (0xc)
1893 #define TONL    (0xc)
1894 #define TOLT    (0x10)
1895 #define TOLE    (0x14)
1896 #define TONG    (0x14)
1897 #define TONE    (0x18)
1898 #define TOU     (0x1f)
1899 \f
1900 /* Smaller names for the flags so each entry in the opcodes table will
1901    fit on a single line.  */
1902 #define PPCNONE 0
1903 #undef  PPC
1904 #define PPC     PPC_OPCODE_PPC
1905 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1906 #define POWER4  PPC_OPCODE_POWER4
1907 #define POWER5  PPC_OPCODE_POWER5
1908 #define POWER6  PPC_OPCODE_POWER6
1909 #define POWER7  PPC_OPCODE_POWER7
1910 #define CELL    PPC_OPCODE_CELL
1911 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
1912 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
1913 #define PPC403  PPC_OPCODE_403
1914 #define PPC405  PPC_OPCODE_405
1915 #define PPC440  PPC_OPCODE_440
1916 #define PPC464  PPC440
1917 #define PPC476  PPC_OPCODE_476
1918 #define PPC750  PPC
1919 #define PPC7450 PPC
1920 #define PPC860  PPC
1921 #define PPCPS   PPC_OPCODE_PPCPS
1922 #define PPCVEC  PPC_OPCODE_ALTIVEC
1923 #define PPCVSX  PPC_OPCODE_VSX
1924 #define POWER   PPC_OPCODE_POWER
1925 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1926 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
1927 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
1928 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1929 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1930 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1931 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
1932 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1933 #define MFDEC1  PPC_OPCODE_POWER
1934 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1935 #define BOOKE   PPC_OPCODE_BOOKE
1936 #define CLASSIC PPC_OPCODE_CLASSIC
1937 #define PPCE300 PPC_OPCODE_E300
1938 #define PPCSPE  PPC_OPCODE_SPE
1939 #define PPCISEL PPC_OPCODE_ISEL
1940 #define PPCEFS  PPC_OPCODE_EFS
1941 #define PPCBRLK PPC_OPCODE_BRLOCK
1942 #define PPCPMR  PPC_OPCODE_PMR
1943 #define PPCCHLK PPC_OPCODE_CACHELCK
1944 #define PPCRFMCI        PPC_OPCODE_RFMCI
1945 #define E500MC  PPC_OPCODE_E500MC
1946 #define PPCA2   PPC_OPCODE_A2
1947 #define TITAN   PPC_OPCODE_TITAN
1948 #define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
1949 #define E500    PPC_OPCODE_E500
1950 \f
1951 /* The opcode table.
1952
1953    The format of the opcode table is:
1954
1955    NAME         OPCODE          MASK         FLAGS      {OPERANDS}
1956
1957    NAME is the name of the instruction.
1958    OPCODE is the instruction opcode.
1959    MASK is the opcode mask; this is used to tell the disassembler
1960      which bits in the actual opcode must match OPCODE.
1961    FLAGS are flags indicated what processors support the instruction.
1962    OPERANDS is the list of operands.
1963
1964    The disassembler reads the table in order and prints the first
1965    instruction which matches, so this table is sorted to put more
1966    specific instructions before more general instructions.
1967
1968    This table must be sorted by major opcode.  Please try to keep it
1969    vaguely sorted within major opcode too, except of course where
1970    constrained otherwise by disassembler operation.  */
1971
1972 const struct powerpc_opcode powerpc_opcodes[] = {
1973 {"attn",        X(0,256),       X_MASK,   POWER4|PPCA2, PPC476,         {0}},
1974 {"tdlgti",      OPTO(2,TOLGT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1975 {"tdllti",      OPTO(2,TOLLT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1976 {"tdeqi",       OPTO(2,TOEQ),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1977 {"tdlgei",      OPTO(2,TOLGE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1978 {"tdlnli",      OPTO(2,TOLNL),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1979 {"tdllei",      OPTO(2,TOLLE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1980 {"tdlngi",      OPTO(2,TOLNG),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1981 {"tdgti",       OPTO(2,TOGT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1982 {"tdgei",       OPTO(2,TOGE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1983 {"tdnli",       OPTO(2,TONL),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1984 {"tdlti",       OPTO(2,TOLT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1985 {"tdlei",       OPTO(2,TOLE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1986 {"tdngi",       OPTO(2,TONG),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1987 {"tdnei",       OPTO(2,TONE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1988 {"tdi",         OP(2),          OP_MASK,     PPC64,     PPCNONE,        {TO, RA, SI}},
1989
1990 {"twlgti",      OPTO(3,TOLGT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1991 {"tlgti",       OPTO(3,TOLGT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1992 {"twllti",      OPTO(3,TOLLT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1993 {"tllti",       OPTO(3,TOLLT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1994 {"tweqi",       OPTO(3,TOEQ),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1995 {"teqi",        OPTO(3,TOEQ),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1996 {"twlgei",      OPTO(3,TOLGE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1997 {"tlgei",       OPTO(3,TOLGE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1998 {"twlnli",      OPTO(3,TOLNL),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1999 {"tlnli",       OPTO(3,TOLNL),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2000 {"twllei",      OPTO(3,TOLLE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2001 {"tllei",       OPTO(3,TOLLE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2002 {"twlngi",      OPTO(3,TOLNG),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2003 {"tlngi",       OPTO(3,TOLNG),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2004 {"twgti",       OPTO(3,TOGT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2005 {"tgti",        OPTO(3,TOGT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2006 {"twgei",       OPTO(3,TOGE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2007 {"tgei",        OPTO(3,TOGE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2008 {"twnli",       OPTO(3,TONL),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2009 {"tnli",        OPTO(3,TONL),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2010 {"twlti",       OPTO(3,TOLT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2011 {"tlti",        OPTO(3,TOLT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2012 {"twlei",       OPTO(3,TOLE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2013 {"tlei",        OPTO(3,TOLE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2014 {"twngi",       OPTO(3,TONG),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2015 {"tngi",        OPTO(3,TONG),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2016 {"twnei",       OPTO(3,TONE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2017 {"tnei",        OPTO(3,TONE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2018 {"twi",         OP(3),          OP_MASK,     PPCCOM,    PPCNONE,        {TO, RA, SI}},
2019 {"ti",          OP(3),          OP_MASK,     PWRCOM,    PPCNONE,        {TO, RA, SI}},
2020
2021 {"ps_cmpu0",    X  (4,   0), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2022 {"vaddubm",     VX (4,   0),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2023 {"vmaxub",      VX (4,   2),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2024 {"vrlb",        VX (4,   4),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2025 {"vcmpequb",    VXR(4,   6,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2026 {"vmuloub",     VX (4,   8),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2027 {"vaddfp",      VX (4,  10),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2028 {"psq_lx",      XW (4,   6,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
2029 {"vmrghb",      VX (4,  12),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2030 {"psq_stx",     XW (4,   7,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
2031 {"vpkuhum",     VX (4,  14),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2032 {"mulhhwu",     XRC(4,   8,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2033 {"mulhhwu.",    XRC(4,   8,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2034 {"ps_sum0",     A  (4,  10,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2035 {"ps_sum0.",    A  (4,  10,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2036 {"ps_sum1",     A  (4,  11,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2037 {"ps_sum1.",    A  (4,  11,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2038 {"ps_muls0",    A  (4,  12,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2039 {"machhwu",     XO (4,  12,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2040 {"ps_muls0.",   A  (4,  12,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2041 {"machhwu.",    XO (4,  12,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2042 {"ps_muls1",    A  (4,  13,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2043 {"ps_muls1.",   A  (4,  13,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2044 {"ps_madds0",   A  (4,  14,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2045 {"ps_madds0.",  A  (4,  14,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2046 {"ps_madds1",   A  (4,  15,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2047 {"ps_madds1.",  A  (4,  15,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2048 {"vmhaddshs",   VXA(4,  32),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2049 {"vmhraddshs",  VXA(4,  33),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2050 {"vmladduhm",   VXA(4,  34),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2051 {"ps_div",      A  (4,  18,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2052 {"vmsumubm",    VXA(4,  36),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2053 {"ps_div.",     A  (4,  18,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2054 {"vmsummbm",    VXA(4,  37),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2055 {"vmsumuhm",    VXA(4,  38),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2056 {"vmsumuhs",    VXA(4,  39),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2057 {"ps_sub",      A  (4,  20,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2058 {"vmsumshm",    VXA(4,  40),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2059 {"ps_sub.",     A  (4,  20,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2060 {"vmsumshs",    VXA(4,  41),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2061 {"ps_add",      A  (4,  21,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2062 {"vsel",        VXA(4,  42),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2063 {"ps_add.",     A  (4,  21,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2064 {"vperm",       VXA(4,  43),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2065 {"vsldoi",      VXA(4,  44),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, SHB}},
2066 {"ps_sel",      A  (4,  23,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2067 {"vmaddfp",     VXA(4,  46),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VC, VB}},
2068 {"ps_sel.",     A  (4,  23,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2069 {"vnmsubfp",    VXA(4,  47),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VC, VB}},
2070 {"ps_res",      A  (4,  24,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2071 {"ps_res.",     A  (4,  24,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2072 {"ps_mul",      A  (4,  25,0), AFRB_MASK,    PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2073 {"ps_mul.",     A  (4,  25,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2074 {"ps_rsqrte",   A  (4,  26,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2075 {"ps_rsqrte.",  A  (4,  26,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2076 {"ps_msub",     A  (4,  28,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2077 {"ps_msub.",    A  (4,  28,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2078 {"ps_madd",     A  (4,  29,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2079 {"ps_madd.",    A  (4,  29,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2080 {"ps_nmsub",    A  (4,  30,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2081 {"ps_nmsub.",   A  (4,  30,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2082 {"ps_nmadd",    A  (4,  31,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2083 {"ps_nmadd.",   A  (4,  31,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2084 {"ps_cmpo0",    X  (4,  32), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2085 {"vadduhm",     VX (4,  64),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2086 {"vmaxuh",      VX (4,  66),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2087 {"vrlh",        VX (4,  68),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2088 {"vcmpequh",    VXR(4,  70,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2089 {"vmulouh",     VX (4,  72),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2090 {"vsubfp",      VX (4,  74),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2091 {"psq_lux",     XW (4,  38,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
2092 {"vmrghh",      VX (4,  76),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2093 {"psq_stux",    XW (4,  39,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
2094 {"vpkuwum",     VX (4,  78),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2095 {"ps_neg",      XRC(4,  40,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2096 {"mulhhw",      XRC(4,  40,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2097 {"ps_neg.",     XRC(4,  40,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2098 {"mulhhw.",     XRC(4,  40,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2099 {"machhw",      XO (4,  44,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2100 {"machhw.",     XO (4,  44,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2101 {"nmachhw",     XO (4,  46,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2102 {"nmachhw.",    XO (4,  46,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2103 {"ps_cmpu1",    X  (4,  64), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2104 {"vadduwm",     VX (4,  128),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2105 {"vmaxuw",      VX (4,  130),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2106 {"vrlw",        VX (4,  132),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2107 {"vcmpequw",    VXR(4,  134,0), VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2108 {"vmrghw",      VX (4,  140),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2109 {"vpkuhus",     VX (4,  142),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2110 {"ps_mr",       XRC(4,  72,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2111 {"ps_mr.",      XRC(4,  72,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2112 {"machhwsu",    XO (4,  76,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2113 {"machhwsu.",   XO (4,  76,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2114 {"ps_cmpo1",    X  (4,  96), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2115 {"vcmpeqfp",    VXR(4, 198,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2116 {"vpkuwus",     VX (4, 206),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2117 {"machhws",     XO (4, 108,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2118 {"machhws.",    XO (4, 108,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2119 {"nmachhws",    XO (4, 110,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2120 {"nmachhws.",   XO (4, 110,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2121 {"vmaxsb",      VX (4, 258),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2122 {"vslb",        VX (4, 260),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2123 {"vmulosb",     VX (4, 264),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2124 {"vrefp",       VX (4, 266),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2125 {"vmrglb",      VX (4, 268),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2126 {"vpkshus",     VX (4, 270),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2127 {"ps_nabs",     XRC(4, 136,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2128 {"mulchwu",     XRC(4, 136,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2129 {"ps_nabs.",    XRC(4, 136,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2130 {"mulchwu.",    XRC(4, 136,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2131 {"macchwu",     XO (4, 140,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2132 {"macchwu.",    XO (4, 140,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2133 {"vmaxsh",      VX (4, 322),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2134 {"vslh",        VX (4, 324),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2135 {"vmulosh",     VX (4, 328),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2136 {"vrsqrtefp",   VX (4, 330),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2137 {"vmrglh",      VX (4, 332),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2138 {"vpkswus",     VX (4, 334),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2139 {"mulchw",      XRC(4, 168,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2140 {"mulchw.",     XRC(4, 168,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2141 {"macchw",      XO (4, 172,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2142 {"macchw.",     XO (4, 172,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2143 {"nmacchw",     XO (4, 174,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2144 {"nmacchw.",    XO (4, 174,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2145 {"vaddcuw",     VX (4, 384),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2146 {"vmaxsw",      VX (4, 386),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2147 {"vslw",        VX (4, 388),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2148 {"vexptefp",    VX (4, 394),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2149 {"vmrglw",      VX (4, 396),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2150 {"vpkshss",     VX (4, 398),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2151 {"macchwsu",    XO (4, 204,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2152 {"macchwsu.",   XO (4, 204,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2153 {"vsl",         VX (4, 452),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2154 {"vcmpgefp",    VXR(4, 454,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2155 {"vlogefp",     VX (4, 458),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2156 {"vpkswss",     VX (4, 462),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2157 {"macchws",     XO (4, 236,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2158 {"macchws.",    XO (4, 236,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2159 {"nmacchws",    XO (4, 238,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2160 {"nmacchws.",   XO (4, 238,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2161 {"evaddw",      VX (4, 512),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2162 {"vaddubs",     VX (4, 512),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2163 {"evaddiw",     VX (4, 514),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, UIMM}},
2164 {"vminub",      VX (4, 514),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2165 {"evsubfw",     VX (4, 516),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2166 {"evsubw",      VX (4, 516),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, RA}},
2167 {"vsrb",        VX (4, 516),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2168 {"evsubifw",    VX (4, 518),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, UIMM, RB}},
2169 {"evsubiw",     VX (4, 518),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, UIMM}},
2170 {"vcmpgtub",    VXR(4, 518,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2171 {"evabs",       VX (4, 520),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2172 {"vmuleub",     VX (4, 520),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2173 {"evneg",       VX (4, 521),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2174 {"evextsb",     VX (4, 522),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2175 {"vrfin",       VX (4, 522),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2176 {"evextsh",     VX (4, 523),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2177 {"evrndw",      VX (4, 524),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2178 {"vspltb",      VX (4, 524),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2179 {"evcntlzw",    VX (4, 525),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2180 {"evcntlsw",    VX (4, 526),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2181 {"vupkhsb",     VX (4, 526),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2182 {"brinc",       VX (4, 527),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2183 {"ps_abs",      XRC(4, 264,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2184 {"ps_abs.",     XRC(4, 264,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2185 {"evand",       VX (4, 529),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2186 {"evandc",      VX (4, 530),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2187 {"evxor",       VX (4, 534),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2188 {"evmr",        VX (4, 535),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, BBA}},
2189 {"evor",        VX (4, 535),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2190 {"evnor",       VX (4, 536),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2191 {"evnot",       VX (4, 536),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, BBA}},
2192 {"get",         APU(4, 268,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2193 {"eveqv",       VX (4, 537),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2194 {"evorc",       VX (4, 539),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2195 {"evnand",      VX (4, 542),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2196 {"evsrwu",      VX (4, 544),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2197 {"evsrws",      VX (4, 545),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2198 {"evsrwiu",     VX (4, 546),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2199 {"evsrwis",     VX (4, 547),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2200 {"evslw",       VX (4, 548),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2201 {"evslwi",      VX (4, 550),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2202 {"evrlw",       VX (4, 552),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2203 {"evsplati",    VX (4, 553),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, SIMM}},
2204 {"evrlwi",      VX (4, 554),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2205 {"evsplatfi",   VX (4, 555),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, SIMM}},
2206 {"evmergehi",   VX (4, 556),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2207 {"evmergelo",   VX (4, 557),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2208 {"evmergehilo", VX (4, 558),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2209 {"evmergelohi", VX (4, 559),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2210 {"evcmpgtu",    VX (4, 560),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2211 {"evcmpgts",    VX (4, 561),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2212 {"evcmpltu",    VX (4, 562),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2213 {"evcmplts",    VX (4, 563),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2214 {"evcmpeq",     VX (4, 564),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2215 {"cget",        APU(4, 284,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2216 {"vadduhs",     VX (4, 576),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2217 {"vminuh",      VX (4, 578),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2218 {"vsrh",        VX (4, 580),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2219 {"vcmpgtuh",    VXR(4, 582,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2220 {"vmuleuh",     VX (4, 584),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2221 {"vrfiz",       VX (4, 586),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2222 {"vsplth",      VX (4, 588),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2223 {"vupkhsh",     VX (4, 590),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2224 {"nget",        APU(4, 300,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2225 {"evsel",       EVSEL(4,79),    EVSEL_MASK,  PPCSPE,    PPCNONE,        {RS, RA, RB, CRFS}},
2226 {"ncget",       APU(4, 316,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2227 {"evfsadd",     VX (4, 640),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2228 {"vadduws",     VX (4, 640),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2229 {"evfssub",     VX (4, 641),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2230 {"vminuw",      VX (4, 642),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2231 {"evfsabs",     VX (4, 644),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2232 {"vsrw",        VX (4, 644),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2233 {"evfsnabs",    VX (4, 645),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2234 {"evfsneg",     VX (4, 646),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2235 {"vcmpgtuw",    VXR(4, 646,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2236 {"evfsmul",     VX (4, 648),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2237 {"evfsdiv",     VX (4, 649),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2238 {"vrfip",       VX (4, 650),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2239 {"evfscmpgt",   VX (4, 652),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2240 {"vspltw",      VX (4, 652),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2241 {"evfscmplt",   VX (4, 653),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2242 {"evfscmpeq",   VX (4, 654),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2243 {"vupklsb",     VX (4, 654),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2244 {"evfscfui",    VX (4, 656),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2245 {"evfscfsi",    VX (4, 657),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2246 {"evfscfuf",    VX (4, 658),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2247 {"evfscfsf",    VX (4, 659),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2248 {"evfsctui",    VX (4, 660),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2249 {"evfsctsi",    VX (4, 661),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2250 {"evfsctuf",    VX (4, 662),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2251 {"evfsctsf",    VX (4, 663),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2252 {"evfsctuiz",   VX (4, 664),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2253 {"put",         APU(4, 332,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2254 {"evfsctsiz",   VX (4, 666),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2255 {"evfststgt",   VX (4, 668),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2256 {"evfststlt",   VX (4, 669),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2257 {"evfststeq",   VX (4, 670),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2258 {"cput",        APU(4, 348,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2259 {"efsadd",      VX (4, 704),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2260 {"efssub",      VX (4, 705),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2261 {"efsabs",      VX (4, 708),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2262 {"vsr",         VX (4, 708),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2263 {"efsnabs",     VX (4, 709),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2264 {"efsneg",      VX (4, 710),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2265 {"vcmpgtfp",    VXR(4, 710,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2266 {"efsmul",      VX (4, 712),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2267 {"efsdiv",      VX (4, 713),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2268 {"vrfim",       VX (4, 714),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2269 {"efscmpgt",    VX (4, 716),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2270 {"efscmplt",    VX (4, 717),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2271 {"efscmpeq",    VX (4, 718),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2272 {"vupklsh",     VX (4, 718),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2273 {"efscfd",      VX (4, 719),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2274 {"efscfui",     VX (4, 720),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2275 {"efscfsi",     VX (4, 721),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2276 {"efscfuf",     VX (4, 722),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2277 {"efscfsf",     VX (4, 723),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2278 {"efsctui",     VX (4, 724),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2279 {"efsctsi",     VX (4, 725),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2280 {"efsctuf",     VX (4, 726),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2281 {"efsctsf",     VX (4, 727),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2282 {"efsctuiz",    VX (4, 728),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2283 {"nput",        APU(4, 364,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2284 {"efsctsiz",    VX (4, 730),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2285 {"efststgt",    VX (4, 732),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2286 {"efststlt",    VX (4, 733),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2287 {"efststeq",    VX (4, 734),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2288 {"efdadd",      VX (4, 736),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2289 {"efdsub",      VX (4, 737),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2290 {"efdcfuid",    VX (4, 738),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2291 {"efdcfsid",    VX (4, 739),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2292 {"efdabs",      VX (4, 740),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2293 {"efdnabs",     VX (4, 741),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2294 {"efdneg",      VX (4, 742),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2295 {"efdmul",      VX (4, 744),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2296 {"efddiv",      VX (4, 745),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2297 {"efdctuidz",   VX (4, 746),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2298 {"efdctsidz",   VX (4, 747),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2299 {"efdcmpgt",    VX (4, 748),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2300 {"efdcmplt",    VX (4, 749),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2301 {"efdcmpeq",    VX (4, 750),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2302 {"efdcfs",      VX (4, 751),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2303 {"efdcfui",     VX (4, 752),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2304 {"efdcfsi",     VX (4, 753),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2305 {"efdcfuf",     VX (4, 754),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2306 {"efdcfsf",     VX (4, 755),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2307 {"efdctui",     VX (4, 756),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2308 {"efdctsi",     VX (4, 757),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2309 {"efdctuf",     VX (4, 758),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2310 {"efdctsf",     VX (4, 759),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2311 {"efdctuiz",    VX (4, 760),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2312 {"ncput",       APU(4, 380,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2313 {"efdctsiz",    VX (4, 762),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2314 {"efdtstgt",    VX (4, 764),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2315 {"efdtstlt",    VX (4, 765),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2316 {"efdtsteq",    VX (4, 766),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2317 {"evlddx",      VX (4, 768),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2318 {"vaddsbs",     VX (4, 768),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2319 {"evldd",       VX (4, 769),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2320 {"evldwx",      VX (4, 770),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2321 {"vminsb",      VX (4, 770),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2322 {"evldw",       VX (4, 771),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2323 {"evldhx",      VX (4, 772),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2324 {"vsrab",       VX (4, 772),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2325 {"evldh",       VX (4, 773),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2326 {"vcmpgtsb",    VXR(4, 774,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2327 {"evlhhesplatx",VX (4, 776),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2328 {"vmulesb",     VX (4, 776),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2329 {"evlhhesplat", VX (4, 777),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_2, RA}},
2330 {"vcfux",       VX (4, 778),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2331 {"evlhhousplatx",VX(4, 780),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2332 {"vspltisb",    VX (4, 780),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, SIMM}},
2333 {"evlhhousplat",VX (4, 781),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_2, RA}},
2334 {"evlhhossplatx",VX(4, 782),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2335 {"vpkpx",       VX (4, 782),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2336 {"evlhhossplat",VX (4, 783),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_2, RA}},
2337 {"mullhwu",     XRC(4, 392,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2338 {"evlwhex",     VX (4, 784),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2339 {"mullhwu.",    XRC(4, 392,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2340 {"evlwhe",      VX (4, 785),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2341 {"evlwhoux",    VX (4, 788),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2342 {"evlwhou",     VX (4, 789),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2343 {"evlwhosx",    VX (4, 790),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2344 {"evlwhos",     VX (4, 791),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2345 {"maclhwu",     XO (4, 396,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2346 {"evlwwsplatx", VX (4, 792),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2347 {"maclhwu.",    XO (4, 396,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2348 {"evlwwsplat",  VX (4, 793),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2349 {"evlwhsplatx", VX (4, 796),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2350 {"evlwhsplat",  VX (4, 797),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2351 {"evstddx",     VX (4, 800),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2352 {"evstdd",      VX (4, 801),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2353 {"evstdwx",     VX (4, 802),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2354 {"evstdw",      VX (4, 803),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2355 {"evstdhx",     VX (4, 804),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2356 {"evstdh",      VX (4, 805),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2357 {"evstwhex",    VX (4, 816),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2358 {"evstwhe",     VX (4, 817),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2359 {"evstwhox",    VX (4, 820),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2360 {"evstwho",     VX (4, 821),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2361 {"evstwwex",    VX (4, 824),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2362 {"evstwwe",     VX (4, 825),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2363 {"evstwwox",    VX (4, 828),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2364 {"evstwwo",     VX (4, 829),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2365 {"vaddshs",     VX (4, 832),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2366 {"vminsh",      VX (4, 834),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2367 {"vsrah",       VX (4, 836),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2368 {"vcmpgtsh",    VXR(4, 838,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2369 {"vmulesh",     VX (4, 840),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2370 {"vcfsx",       VX (4, 842),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2371 {"vspltish",    VX (4, 844),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, SIMM}},
2372 {"vupkhpx",     VX (4, 846),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2373 {"mullhw",      XRC(4, 424,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2374 {"mullhw.",     XRC(4, 424,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2375 {"maclhw",      XO (4, 428,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2376 {"maclhw.",     XO (4, 428,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2377 {"nmaclhw",     XO (4, 430,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2378 {"nmaclhw.",    XO (4, 430,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2379 {"vaddsws",     VX (4, 896),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2380 {"vminsw",      VX (4, 898),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2381 {"vsraw",       VX (4, 900),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2382 {"vcmpgtsw",    VXR(4, 902,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2383 {"vctuxs",      VX (4, 906),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2384 {"vspltisw",    VX (4, 908),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, SIMM}},
2385 {"maclhwsu",    XO (4, 460,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2386 {"maclhwsu.",   XO (4, 460,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2387 {"vcmpbfp",     VXR(4, 966,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2388 {"vctsxs",      VX (4, 970),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2389 {"vupklpx",     VX (4, 974),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2390 {"maclhws",     XO (4, 492,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2391 {"maclhws.",    XO (4, 492,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2392 {"nmaclhws",    XO (4, 494,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2393 {"nmaclhws.",   XO (4, 494,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2394 {"vsububm",     VX (4,1024),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2395 {"vavgub",      VX (4,1026),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2396 {"evmhessf",    VX (4,1027),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2397 {"vand",        VX (4,1028),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2398 {"vcmpequb.",   VXR(4,   6,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2399 {"udi0fcm.",    APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2400 {"udi0fcm",     APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2401 {"evmhossf",    VX (4,1031),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2402 {"evmheumi",    VX (4,1032),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2403 {"evmhesmi",    VX (4,1033),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2404 {"vmaxfp",      VX (4,1034),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2405 {"evmhesmf",    VX (4,1035),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2406 {"evmhoumi",    VX (4,1036),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2407 {"vslo",        VX (4,1036),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2408 {"evmhosmi",    VX (4,1037),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2409 {"evmhosmf",    VX (4,1039),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2410 {"machhwuo",    XO (4,  12,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2411 {"machhwuo.",   XO (4,  12,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2412 {"ps_merge00",  XOPS(4,528,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2413 {"ps_merge00.", XOPS(4,528,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2414 {"evmhessfa",   VX (4,1059),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2415 {"evmhossfa",   VX (4,1063),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2416 {"evmheumia",   VX (4,1064),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2417 {"evmhesmia",   VX (4,1065),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2418 {"evmhesmfa",   VX (4,1067),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2419 {"evmhoumia",   VX (4,1068),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2420 {"evmhosmia",   VX (4,1069),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2421 {"evmhosmfa",   VX (4,1071),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2422 {"vsubuhm",     VX (4,1088),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2423 {"vavguh",      VX (4,1090),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2424 {"vandc",       VX (4,1092),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2425 {"vcmpequh.",   VXR(4,  70,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2426 {"udi1fcm.",    APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2427 {"udi1fcm",     APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2428 {"evmwhssf",    VX (4,1095),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2429 {"evmwlumi",    VX (4,1096),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2430 {"vminfp",      VX (4,1098),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2431 {"evmwhumi",    VX (4,1100),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2432 {"vsro",        VX (4,1100),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2433 {"evmwhsmi",    VX (4,1101),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2434 {"evmwhsmf",    VX (4,1103),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2435 {"evmwssf",     VX (4,1107),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2436 {"machhwo",     XO (4,  44,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2437 {"evmwumi",     VX (4,1112),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2438 {"machhwo.",    XO (4,  44,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2439 {"evmwsmi",     VX (4,1113),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2440 {"evmwsmf",     VX (4,1115),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2441 {"nmachhwo",    XO (4,  46,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2442 {"nmachhwo.",   XO (4,  46,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2443 {"ps_merge01",  XOPS(4,560,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2444 {"ps_merge01.", XOPS(4,560,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2445 {"evmwhssfa",   VX (4,1127),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2446 {"evmwlumia",   VX (4,1128),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2447 {"evmwhumia",   VX (4,1132),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2448 {"evmwhsmia",   VX (4,1133),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2449 {"evmwhsmfa",   VX (4,1135),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2450 {"evmwssfa",    VX (4,1139),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2451 {"evmwumia",    VX (4,1144),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2452 {"evmwsmia",    VX (4,1145),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2453 {"evmwsmfa",    VX (4,1147),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2454 {"vsubuwm",     VX (4,1152),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2455 {"vavguw",      VX (4,1154),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2456 {"vor",         VX (4,1156),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2457 {"vcmpequw.",   VXR(4, 134,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2458 {"udi2fcm.",    APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2459 {"udi2fcm",     APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2460 {"machhwsuo",   XO (4,  76,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2461 {"machhwsuo.",  XO (4,  76,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2462 {"ps_merge10",  XOPS(4,592,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2463 {"ps_merge10.", XOPS(4,592,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2464 {"evaddusiaaw", VX (4,1216),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2465 {"evaddssiaaw", VX (4,1217),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2466 {"evsubfusiaaw",VX (4,1218),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2467 {"evsubfssiaaw",VX (4,1219),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2468 {"evmra",       VX (4,1220),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2469 {"vxor",        VX (4,1220),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2470 {"evdivws",     VX (4,1222),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2471 {"vcmpeqfp.",   VXR(4, 198,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2472 {"udi3fcm.",    APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2473 {"udi3fcm",     APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2474 {"evdivwu",     VX (4,1223),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2475 {"evaddumiaaw", VX (4,1224),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2476 {"evaddsmiaaw", VX (4,1225),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2477 {"evsubfumiaaw",VX (4,1226),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2478 {"evsubfsmiaaw",VX (4,1227),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2479 {"machhwso",    XO (4, 108,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2480 {"machhwso.",   XO (4, 108,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2481 {"nmachhwso",   XO (4, 110,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2482 {"nmachhwso.",  XO (4, 110,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2483 {"ps_merge11",  XOPS(4,624,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2484 {"ps_merge11.", XOPS(4,624,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2485 {"evmheusiaaw", VX (4,1280),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2486 {"evmhessiaaw", VX (4,1281),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2487 {"vavgsb",      VX (4,1282),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2488 {"evmhessfaaw", VX (4,1283),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2489 {"evmhousiaaw", VX (4,1284),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2490 {"vnor",        VX (4,1284),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2491 {"evmhossiaaw", VX (4,1285),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2492 {"udi4fcm.",    APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2493 {"udi4fcm",     APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2494 {"evmhossfaaw", VX (4,1287),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2495 {"evmheumiaaw", VX (4,1288),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2496 {"evmhesmiaaw", VX (4,1289),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2497 {"evmhesmfaaw", VX (4,1291),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2498 {"evmhoumiaaw", VX (4,1292),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2499 {"evmhosmiaaw", VX (4,1293),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2500 {"evmhosmfaaw", VX (4,1295),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2501 {"macchwuo",    XO (4, 140,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2502 {"macchwuo.",   XO (4, 140,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2503 {"evmhegumiaa", VX (4,1320),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2504 {"evmhegsmiaa", VX (4,1321),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2505 {"evmhegsmfaa", VX (4,1323),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2506 {"evmhogumiaa", VX (4,1324),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2507 {"evmhogsmiaa", VX (4,1325),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2508 {"evmhogsmfaa", VX (4,1327),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2509 {"evmwlusiaaw", VX (4,1344),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2510 {"evmwlssiaaw", VX (4,1345),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2511 {"vavgsh",      VX (4,1346),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2512 {"udi5fcm.",    APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2513 {"udi5fcm",     APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2514 {"evmwlumiaaw", VX (4,1352),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2515 {"evmwlsmiaaw", VX (4,1353),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2516 {"evmwssfaa",   VX (4,1363),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2517 {"macchwo",     XO (4, 172,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2518 {"evmwumiaa",   VX (4,1368),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2519 {"macchwo.",    XO (4, 172,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2520 {"evmwsmiaa",   VX (4,1369),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2521 {"evmwsmfaa",   VX (4,1371),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2522 {"nmacchwo",    XO (4, 174,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2523 {"nmacchwo.",   XO (4, 174,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2524 {"evmheusianw", VX (4,1408),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2525 {"vsubcuw",     VX (4,1408),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2526 {"evmhessianw", VX (4,1409),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2527 {"vavgsw",      VX (4,1410),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2528 {"evmhessfanw", VX (4,1411),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2529 {"evmhousianw", VX (4,1412),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2530 {"evmhossianw", VX (4,1413),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2531 {"udi6fcm.",    APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2532 {"udi6fcm",     APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2533 {"evmhossfanw", VX (4,1415),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2534 {"evmheumianw", VX (4,1416),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2535 {"evmhesmianw", VX (4,1417),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2536 {"evmhesmfanw", VX (4,1419),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2537 {"evmhoumianw", VX (4,1420),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2538 {"evmhosmianw", VX (4,1421),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2539 {"evmhosmfanw", VX (4,1423),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2540 {"macchwsuo",   XO (4, 204,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2541 {"macchwsuo.",  XO (4, 204,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2542 {"evmhegumian", VX (4,1448),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2543 {"evmhegsmian", VX (4,1449),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2544 {"evmhegsmfan", VX (4,1451),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2545 {"evmhogumian", VX (4,1452),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2546 {"evmhogsmian", VX (4,1453),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2547 {"evmhogsmfan", VX (4,1455),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2548 {"evmwlusianw", VX (4,1472),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2549 {"evmwlssianw", VX (4,1473),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2550 {"vcmpgefp.",   VXR(4, 454,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2551 {"udi7fcm.",    APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2552 {"udi7fcm",     APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2553 {"evmwlumianw", VX (4,1480),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2554 {"evmwlsmianw", VX (4,1481),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2555 {"evmwssfan",   VX (4,1491),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2556 {"macchwso",    XO (4, 236,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2557 {"evmwumian",   VX (4,1496),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2558 {"macchwso.",   XO (4, 236,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2559 {"evmwsmian",   VX (4,1497),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2560 {"evmwsmfan",   VX (4,1499),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2561 {"nmacchwso",   XO (4, 238,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2562 {"nmacchwso.",  XO (4, 238,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2563 {"vsububs",     VX (4,1536),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2564 {"mfvscr",      VX (4,1540),    VX_MASK,     PPCVEC,    PPCNONE,        {VD}},
2565 {"vcmpgtub.",   VXR(4, 518,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2566 {"udi8fcm.",    APU(4, 771,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2567 {"udi8fcm",     APU(4, 771,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2568 {"vsum4ubs",    VX (4,1544),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2569 {"vsubuhs",     VX (4,1600),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2570 {"mtvscr",      VX (4,1604),    VX_MASK,     PPCVEC,    PPCNONE,        {VB}},
2571 {"vcmpgtuh.",   VXR(4, 582,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2572 {"vsum4shs",    VX (4,1608),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2573 {"udi9fcm.",    APU(4, 804,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2574 {"udi9fcm",     APU(4, 804,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2575 {"vsubuws",     VX (4,1664),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2576 {"vcmpgtuw.",   VXR(4, 646,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2577 {"udi10fcm.",   APU(4, 835,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2578 {"udi10fcm",    APU(4, 835,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2579 {"vsum2sws",    VX (4,1672),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2580 {"vcmpgtfp.",   VXR(4, 710,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2581 {"udi11fcm.",   APU(4, 867,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2582 {"udi11fcm",    APU(4, 867,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2583 {"vsubsbs",     VX (4,1792),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2584 {"vcmpgtsb.",   VXR(4, 774,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2585 {"udi12fcm.",   APU(4, 899,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2586 {"udi12fcm",    APU(4, 899,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2587 {"vsum4sbs",    VX (4,1800),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2588 {"maclhwuo",    XO (4, 396,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2589 {"maclhwuo.",   XO (4, 396,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2590 {"vsubshs",     VX (4,1856),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2591 {"vcmpgtsh.",   VXR(4, 838,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2592 {"udi13fcm.",   APU(4, 931,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2593 {"udi13fcm",    APU(4, 931,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2594 {"maclhwo",     XO (4, 428,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2595 {"maclhwo.",    XO (4, 428,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2596 {"nmaclhwo",    XO (4, 430,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2597 {"nmaclhwo.",   XO (4, 430,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2598 {"vsubsws",     VX (4,1920),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2599 {"vcmpgtsw.",   VXR(4, 902,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2600 {"udi14fcm.",   APU(4, 963,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2601 {"udi14fcm",    APU(4, 963,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2602 {"vsumsws",     VX (4,1928),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2603 {"maclhwsuo",   XO (4, 460,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2604 {"maclhwsuo.",  XO (4, 460,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2605 {"vcmpbfp.",    VXR(4, 966,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2606 {"udi15fcm.",   APU(4, 995,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2607 {"udi15fcm",    APU(4, 995,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2608 {"maclhwso",    XO (4, 492,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2609 {"maclhwso.",   XO (4, 492,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2610 {"nmaclhwso",   XO (4, 494,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2611 {"nmaclhwso.",  XO (4, 494,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2612 {"dcbz_l",      X  (4,1014),    XRT_MASK,    PPCPS,     PPCNONE,        {RA, RB}},
2613
2614 {"mulli",       OP(7),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2615 {"muli",        OP(7),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2616
2617 {"subfic",      OP(8),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2618 {"sfi",         OP(8),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2619
2620 {"dozi",        OP(9),          OP_MASK,     M601,      PPCNONE,        {RT, RA, SI}},
2621
2622 {"cmplwi",      OPL(10,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, UI}},
2623 {"cmpldi",      OPL(10,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, UI}},
2624 {"cmpli",       OP(10),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, UI}},
2625 {"cmpli",       OP(10),         OP_MASK,     PWRCOM,    PPCNONE,        {BF, RA, UI}},
2626
2627 {"cmpwi",       OPL(11,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, SI}},
2628 {"cmpdi",       OPL(11,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, SI}},
2629 {"cmpi",        OP(11),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, SI}},
2630 {"cmpi",        OP(11),         OP_MASK,     PWRCOM,    PPCNONE,        {BF, RA, SI}},
2631
2632 {"addic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2633 {"ai",          OP(12),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2634 {"subic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
2635
2636 {"addic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2637 {"ai.",         OP(13),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2638 {"subic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
2639
2640 {"li",          OP(14),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SI}},
2641 {"lil",         OP(14),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SI}},
2642 {"addi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SI}},
2643 {"cal",         OP(14),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
2644 {"subi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
2645 {"la",          OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
2646
2647 {"lis",         OP(15),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SISIGNOPT}},
2648 {"liu",         OP(15),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SISIGNOPT}},
2649 {"addis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
2650 {"cau",         OP(15),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
2651 {"subis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
2652
2653 {"bdnz-",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2654 {"bdnz+",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2655 {"bdnz",     BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
2656 {"bdn",      BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
2657 {"bdnzl-",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2658 {"bdnzl+",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2659 {"bdnzl",    BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
2660 {"bdnl",     BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
2661 {"bdnza-",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2662 {"bdnza+",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2663 {"bdnza",    BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
2664 {"bdna",     BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
2665 {"bdnzla-",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2666 {"bdnzla+",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2667 {"bdnzla",   BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
2668 {"bdnla",    BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
2669 {"bdz-",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2670 {"bdz+",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2671 {"bdz",      BBO(16,BODZ,0,0),          BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
2672 {"bdzl-",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2673 {"bdzl+",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2674 {"bdzl",     BBO(16,BODZ,0,1),          BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
2675 {"bdza-",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2676 {"bdza+",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2677 {"bdza",     BBO(16,BODZ,1,0),          BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
2678 {"bdzla-",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2679 {"bdzla+",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2680 {"bdzla",    BBO(16,BODZ,1,1),          BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
2681
2682 {"bge-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2683 {"bge+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2684 {"bge",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2685 {"bnl-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2686 {"bnl+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2687 {"bnl",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2688 {"bgel-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2689 {"bgel+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2690 {"bgel",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2691 {"bnll-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2692 {"bnll+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2693 {"bnll",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2694 {"bgea-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2695 {"bgea+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2696 {"bgea",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2697 {"bnla-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2698 {"bnla+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2699 {"bnla",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2700 {"bgela-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2701 {"bgela+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2702 {"bgela",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2703 {"bnlla-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2704 {"bnlla+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2705 {"bnlla",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2706 {"ble-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2707 {"ble+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2708 {"ble",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2709 {"bng-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2710 {"bng+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2711 {"bng",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2712 {"blel-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2713 {"blel+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2714 {"blel",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2715 {"bngl-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2716 {"bngl+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2717 {"bngl",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2718 {"blea-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2719 {"blea+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2720 {"blea",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2721 {"bnga-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2722 {"bnga+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2723 {"bnga",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2724 {"blela-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2725 {"blela+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2726 {"blela",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2727 {"bngla-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2728 {"bngla+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2729 {"bngla",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2730 {"bne-",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2731 {"bne+",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2732 {"bne",      BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2733 {"bnel-",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2734 {"bnel+",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2735 {"bnel",     BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2736 {"bnea-",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2737 {"bnea+",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2738 {"bnea",     BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2739 {"bnela-",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2740 {"bnela+",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2741 {"bnela",    BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2742 {"bns-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2743 {"bns+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2744 {"bns",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2745 {"bnu-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2746 {"bnu+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2747 {"bnu",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2748 {"bnsl-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2749 {"bnsl+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2750 {"bnsl",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2751 {"bnul-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2752 {"bnul+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2753 {"bnul",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2754 {"bnsa-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2755 {"bnsa+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2756 {"bnsa",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2757 {"bnua-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2758 {"bnua+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2759 {"bnua",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2760 {"bnsla-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2761 {"bnsla+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2762 {"bnsla",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2763 {"bnula-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2764 {"bnula+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2765 {"bnula",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2766
2767 {"blt-",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2768 {"blt+",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2769 {"blt",      BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2770 {"bltl-",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2771 {"bltl+",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2772 {"bltl",     BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2773 {"blta-",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2774 {"blta+",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2775 {"blta",     BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2776 {"bltla-",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2777 {"bltla+",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2778 {"bltla",    BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2779 {"bgt-",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2780 {"bgt+",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2781 {"bgt",      BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2782 {"bgtl-",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2783 {"bgtl+",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2784 {"bgtl",     BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2785 {"bgta-",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2786 {"bgta+",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2787 {"bgta",     BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2788 {"bgtla-",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2789 {"bgtla+",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2790 {"bgtla",    BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2791 {"beq-",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2792 {"beq+",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2793 {"beq",      BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2794 {"beql-",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2795 {"beql+",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2796 {"beql",     BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2797 {"beqa-",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2798 {"beqa+",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2799 {"beqa",     BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2800 {"beqla-",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2801 {"beqla+",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2802 {"beqla",    BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2803 {"bso-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2804 {"bso+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2805 {"bso",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2806 {"bun-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2807 {"bun+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2808 {"bun",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2809 {"bsol-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2810 {"bsol+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2811 {"bsol",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2812 {"bunl-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2813 {"bunl+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2814 {"bunl",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2815 {"bsoa-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2816 {"bsoa+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2817 {"bsoa",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2818 {"buna-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2819 {"buna+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2820 {"buna",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2821 {"bsola-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2822 {"bsola+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2823 {"bsola",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2824 {"bunla-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2825 {"bunla+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2826 {"bunla",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2827
2828 {"bdnzf-",   BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2829 {"bdnzf+",   BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2830 {"bdnzf",    BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2831 {"bdnzfl-",  BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2832 {"bdnzfl+",  BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2833 {"bdnzfl",   BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2834 {"bdnzfa-",  BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2835 {"bdnzfa+",  BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2836 {"bdnzfa",   BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2837 {"bdnzfla-", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2838 {"bdnzfla+", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2839 {"bdnzfla",  BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2840 {"bdzf-",    BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2841 {"bdzf+",    BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2842 {"bdzf",     BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2843 {"bdzfl-",   BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2844 {"bdzfl+",   BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2845 {"bdzfl",    BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2846 {"bdzfa-",   BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2847 {"bdzfa+",   BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2848 {"bdzfa",    BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2849 {"bdzfla-",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2850 {"bdzfla+",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2851 {"bdzfla",   BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2852
2853 {"bf-",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2854 {"bf+",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2855 {"bf",       BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2856 {"bbf",      BBO(16,BOF,0,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2857 {"bfl-",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2858 {"bfl+",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2859 {"bfl",      BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2860 {"bbfl",     BBO(16,BOF,0,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2861 {"bfa-",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2862 {"bfa+",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2863 {"bfa",      BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2864 {"bbfa",     BBO(16,BOF,1,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2865 {"bfla-",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2866 {"bfla+",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2867 {"bfla",     BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2868 {"bbfla",    BBO(16,BOF,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2869
2870 {"bdnzt-",   BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2871 {"bdnzt+",   BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2872 {"bdnzt",    BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2873 {"bdnztl-",  BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2874 {"bdnztl+",  BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2875 {"bdnztl",   BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2876 {"bdnzta-",  BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2877 {"bdnzta+",  BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2878 {"bdnzta",   BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2879 {"bdnztla-", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2880 {"bdnztla+", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2881 {"bdnztla",  BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2882 {"bdzt-",    BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2883 {"bdzt+",    BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2884 {"bdzt",     BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2885 {"bdztl-",   BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2886 {"bdztl+",   BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2887 {"bdztl",    BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2888 {"bdzta-",   BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2889 {"bdzta+",   BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2890 {"bdzta",    BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2891 {"bdztla-",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2892 {"bdztla+",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2893 {"bdztla",   BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2894
2895 {"bt-",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2896 {"bt+",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2897 {"bt",       BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2898 {"bbt",      BBO(16,BOT,0,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2899 {"btl-",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2900 {"btl+",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2901 {"btl",      BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2902 {"bbtl",     BBO(16,BOT,0,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2903 {"bta-",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2904 {"bta+",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2905 {"bta",      BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2906 {"bbta",     BBO(16,BOT,1,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2907 {"btla-",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2908 {"btla+",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2909 {"btla",     BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2910 {"bbtla",    BBO(16,BOT,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2911
2912 {"bc-",         B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
2913 {"bc+",         B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
2914 {"bc",          B(16,0,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
2915 {"bcl-",        B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
2916 {"bcl+",        B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
2917 {"bcl",         B(16,0,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
2918 {"bca-",        B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
2919 {"bca+",        B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
2920 {"bca",         B(16,1,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
2921 {"bcla-",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
2922 {"bcla+",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
2923 {"bcla",        B(16,1,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
2924
2925 {"svc",         SC(17,0,0),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
2926 {"svcl",        SC(17,0,1),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
2927 {"sc",          SC(17,1,0),     SC_MASK,     PPC,       PPCNONE,        {LEV}},
2928 {"svca",        SC(17,1,0),     SC_MASK,     PWRCOM,    PPCNONE,        {SV}},
2929 {"svcla",       SC(17,1,1),     SC_MASK,     POWER,     PPCNONE,        {SV}},
2930
2931 {"b",           B(18,0,0),      B_MASK,      COM,       PPCNONE,        {LI}},
2932 {"bl",          B(18,0,1),      B_MASK,      COM,       PPCNONE,        {LI}},
2933 {"ba",          B(18,1,0),      B_MASK,      COM,       PPCNONE,        {LIA}},
2934 {"bla",         B(18,1,1),      B_MASK,      COM,       PPCNONE,        {LIA}},
2935
2936 {"mcrf",      XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE,        {BF, BFA}},
2937
2938 {"bdnzlr",   XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2939 {"bdnzlr-",  XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2940 {"bdnzlrl",  XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2941 {"bdnzlrl-", XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2942 {"bdnzlr+",  XLO(19,BODNZP,16,0),       XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2943 {"bdnzlrl+", XLO(19,BODNZP,16,1),       XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2944 {"bdzlr",    XLO(19,BODZ,16,0),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2945 {"bdzlr-",   XLO(19,BODZ,16,0),         XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2946 {"bdzlrl",   XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2947 {"bdzlrl-",  XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2948 {"bdzlr+",   XLO(19,BODZP,16,0),        XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2949 {"bdzlrl+",  XLO(19,BODZP,16,1),        XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2950 {"blr",      XLO(19,BOU,16,0),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2951 {"br",       XLO(19,BOU,16,0),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
2952 {"blrl",     XLO(19,BOU,16,1),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2953 {"brl",      XLO(19,BOU,16,1),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
2954 {"bdnzlr-",  XLO(19,BODNZM4,16,0),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2955 {"bdnzlrl-", XLO(19,BODNZM4,16,1),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2956 {"bdnzlr+",  XLO(19,BODNZP4,16,0),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2957 {"bdnzlrl+", XLO(19,BODNZP4,16,1),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2958 {"bdzlr-",   XLO(19,BODZM4,16,0),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2959 {"bdzlrl-",  XLO(19,BODZM4,16,1),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2960 {"bdzlr+",   XLO(19,BODZP4,16,0),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2961 {"bdzlrl+",  XLO(19,BODZP4,16,1),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2962
2963 {"bgelr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2964 {"bgelr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2965 {"bger",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2966 {"bnllr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2967 {"bnllr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2968 {"bnlr",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2969 {"bgelrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2970 {"bgelrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2971 {"bgerl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2972 {"bnllrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2973 {"bnllrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2974 {"bnlrl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2975 {"blelr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2976 {"blelr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2977 {"bler",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2978 {"bnglr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2979 {"bnglr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2980 {"bngr",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2981 {"blelrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2982 {"blelrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2983 {"blerl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2984 {"bnglrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2985 {"bnglrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2986 {"bngrl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2987 {"bnelr",    XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2988 {"bnelr-",   XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2989 {"bner",     XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2990 {"bnelrl",   XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2991 {"bnelrl-",  XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2992 {"bnerl",    XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2993 {"bnslr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2994 {"bnslr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2995 {"bnsr",     XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2996 {"bnulr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2997 {"bnulr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2998 {"bnslrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2999 {"bnslrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3000 {"bnsrl",    XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3001 {"bnulrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3002 {"bnulrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3003 {"bgelr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3004 {"bnllr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3005 {"bgelrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3006 {"bnllrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3007 {"blelr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3008 {"bnglr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3009 {"blelrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3010 {"bnglrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3011 {"bnelr+",   XLOCB(19,BOFP,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3012 {"bnelrl+",  XLOCB(19,BOFP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3013 {"bnslr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3014 {"bnulr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3015 {"bnslrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3016 {"bnulrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3017 {"bgelr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3018 {"bnllr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3019 {"bgelrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3020 {"bnllrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3021 {"blelr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3022 {"bnglr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3023 {"blelrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3024 {"bnglrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3025 {"bnelr-",   XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3026 {"bnelrl-",  XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3027 {"bnslr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3028 {"bnulr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3029 {"bnslrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3030 {"bnulrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3031 {"bgelr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3032 {"bnllr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3033 {"bgelrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3034 {"bnllrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3035 {"blelr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3036 {"bnglr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3037 {"blelrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3038 {"bnglrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3039 {"bnelr+",   XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3040 {"bnelrl+",  XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3041 {"bnslr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3042 {"bnulr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3043 {"bnslrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3044 {"bnulrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3045 {"bltlr",    XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3046 {"bltlr-",   XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3047 {"bltr",     XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3048 {"bltlrl",   XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3049 {"bltlrl-",  XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3050 {"bltrl",    XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3051 {"bgtlr",    XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3052 {"bgtlr-",   XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3053 {"bgtr",     XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3054 {"bgtlrl",   XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3055 {"bgtlrl-",  XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3056 {"bgtrl",    XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3057 {"beqlr",    XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3058 {"beqlr-",   XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3059 {"beqr",     XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3060 {"beqlrl",   XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3061 {"beqlrl-",  XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3062 {"beqrl",    XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3063 {"bsolr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3064 {"bsolr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3065 {"bsor",     XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3066 {"bunlr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3067 {"bunlr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3068 {"bsolrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3069 {"bsolrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3070 {"bsorl",    XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3071 {"bunlrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3072 {"bunlrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3073 {"bltlr+",   XLOCB(19,BOTP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3074 {"bltlrl+",  XLOCB(19,BOTP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3075 {"bgtlr+",   XLOCB(19,BOTP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3076 {"bgtlrl+",  XLOCB(19,BOTP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3077 {"beqlr+",   XLOCB(19,BOTP,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3078 {"beqlrl+",  XLOCB(19,BOTP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3079 {"bsolr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3080 {"bunlr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3081 {"bsolrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3082 {"bunlrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3083 {"bltlr-",   XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3084 {"bltlrl-",  XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3085 {"bgtlr-",   XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3086 {"bgtlrl-",  XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3087 {"beqlr-",   XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3088 {"beqlrl-",  XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3089 {"bsolr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3090 {"bunlr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3091 {"bsolrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3092 {"bunlrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3093 {"bltlr+",   XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3094 {"bltlrl+",  XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3095 {"bgtlr+",   XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3096 {"bgtlrl+",  XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3097 {"beqlr+",   XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3098 {"beqlrl+",  XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3099 {"bsolr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3100 {"bunlr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3101 {"bsolrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3102 {"bunlrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3103
3104 {"bdnzflr",  XLO(19,BODNZF,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3105 {"bdnzflr-", XLO(19,BODNZF,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3106 {"bdnzflrl", XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3107 {"bdnzflrl-",XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3108 {"bdnzflr+", XLO(19,BODNZFP,16,0),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3109 {"bdnzflrl+",XLO(19,BODNZFP,16,1),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3110 {"bdzflr",   XLO(19,BODZF,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3111 {"bdzflr-",  XLO(19,BODZF,16,0),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3112 {"bdzflrl",  XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3113 {"bdzflrl-", XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3114 {"bdzflr+",  XLO(19,BODZFP,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3115 {"bdzflrl+", XLO(19,BODZFP,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3116 {"bflr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3117 {"bflr-",    XLO(19,BOF,16,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3118 {"bbfr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3119 {"bflrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3120 {"bflrl-",   XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3121 {"bbfrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3122 {"bflr+",    XLO(19,BOFP,16,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3123 {"bflrl+",   XLO(19,BOFP,16,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3124 {"bflr-",    XLO(19,BOFM4,16,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3125 {"bflrl-",   XLO(19,BOFM4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3126 {"bflr+",    XLO(19,BOFP4,16,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3127 {"bflrl+",   XLO(19,BOFP4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3128 {"bdnztlr",  XLO(19,BODNZT,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3129 {"bdnztlr-", XLO(19,BODNZT,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3130 {"bdnztlrl", XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3131 {"bdnztlrl-",XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3132 {"bdnztlr+", XLO(19,BODNZTP,16,0),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3133 {"bdnztlrl+",XLO(19,BODNZTP,16,1),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3134 {"bdztlr",   XLO(19,BODZT,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3135 {"bdztlr-",  XLO(19,BODZT,16,0),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3136 {"bdztlrl",  XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3137 {"bdztlrl-", XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3138 {"bdztlr+",  XLO(19,BODZTP,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3139 {"bdztlrl+", XLO(19,BODZTP,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3140 {"btlr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3141 {"btlr-",    XLO(19,BOT,16,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3142 {"bbtr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3143 {"btlrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3144 {"btlrl-",   XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3145 {"bbtrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3146 {"btlr+",    XLO(19,BOTP,16,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3147 {"btlrl+",   XLO(19,BOTP,16,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3148 {"btlr-",    XLO(19,BOTM4,16,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3149 {"btlrl-",   XLO(19,BOTM4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3150 {"btlr+",    XLO(19,BOTP4,16,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3151 {"btlrl+",   XLO(19,BOTP4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3152
3153 {"bclr-",    XLYLK(19,16,0,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3154 {"bclrl-",   XLYLK(19,16,0,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3155 {"bclr+",    XLYLK(19,16,1,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3156 {"bclrl+",   XLYLK(19,16,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3157 {"bclr",     XLLK(19,16,0),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3158 {"bcr",      XLLK(19,16,0),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3159 {"bclrl",    XLLK(19,16,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3160 {"bcrl",     XLLK(19,16,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3161
3162 {"rfid",        XL(19,18),      0xffffffff,  PPC64,     PPCNONE,        {0}},
3163
3164 {"crnot",       XL(19,33),      XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
3165 {"crnor",       XL(19,33),      XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3166 {"rfmci",       X(19,38),   0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}},
3167
3168 {"rfdi",        XL(19,39),      0xffffffff,  E500MC,    PPCNONE,        {0}},
3169 {"rfi",         XL(19,50),      0xffffffff,  COM,       PPCNONE,        {0}},
3170 {"rfci",        XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
3171
3172 {"rfsvc",       XL(19,82),      0xffffffff,  POWER,     PPCNONE,        {0}},
3173
3174 {"rfgi",        XL(19,102),   0xffffffff, E500MC|PPCA2, PPCNONE,        {0}},
3175
3176 {"crandc",      XL(19,129),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3177
3178 {"isync",       XL(19,150),     0xffffffff,  PPCCOM,    PPCNONE,        {0}},
3179 {"ics",         XL(19,150),     0xffffffff,  PWRCOM,    PPCNONE,        {0}},
3180
3181 {"crclr",       XL(19,193),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
3182 {"crxor",       XL(19,193),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3183
3184 {"dnh",         X(19,198),      X_MASK,      E500MC,    PPCNONE,        {DUI, DUIS}},
3185
3186 {"crnand",      XL(19,225),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3187
3188 {"crand",       XL(19,257),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3189
3190 {"hrfid",       XL(19,274),     0xffffffff, POWER5|CELL, PPC476,        {0}},
3191
3192 {"crset",       XL(19,289),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
3193 {"creqv",       XL(19,289),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3194
3195 {"doze",        XL(19,402),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3196
3197 {"crorc",       XL(19,417),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3198
3199 {"nap",         XL(19,434),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3200
3201 {"crmove",      XL(19,449),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
3202 {"cror",        XL(19,449),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3203
3204 {"sleep",       XL(19,466),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3205 {"rvwinkle",    XL(19,498),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3206
3207 {"bctr",    XLO(19,BOU,528,0),          XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
3208 {"bctrl",   XLO(19,BOU,528,1),          XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
3209
3210 {"bgectr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3211 {"bgectr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3212 {"bnlctr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3213 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3214 {"bgectrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3215 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3216 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3217 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3218 {"blectr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3219 {"blectr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3220 {"bngctr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3221 {"bngctr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3222 {"blectrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3223 {"blectrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3224 {"bngctrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3225 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3226 {"bnectr",  XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3227 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3228 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3229 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3230 {"bnsctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3231 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3232 {"bnuctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3233 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3234 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3235 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3236 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3237 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3238 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3239 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3240 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3241 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3242 {"blectr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3243 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3244 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3245 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3246 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3247 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3248 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3249 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3250 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3251 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3252 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3253 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3254 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3255 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3256 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3257 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3258 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3259 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3260 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3261 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3262 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3263 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3264 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3265 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3266 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3267 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3268 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3269 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3270 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3271 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3272 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3273 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3274 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3275 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3276 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3277 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3278 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3279 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3280 {"bltctr",  XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3281 {"bltctr-", XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3282 {"bltctrl", XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3283 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3284 {"bgtctr",  XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3285 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3286 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3287 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3288 {"beqctr",  XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3289 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3290 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3291 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3292 {"bsoctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3293 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3294 {"bunctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3295 {"bunctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3296 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3297 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3298 {"bunctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3299 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3300 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3301 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3302 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3303 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3304 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3305 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3306 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3307 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3308 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3309 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3310 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3311 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3312 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3313 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3314 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3315 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3316 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3317 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3318 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3319 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3320 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3321 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3322 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3323 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3324 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3325 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3326 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3327 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3328 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3329 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3330
3331 {"bfctr",   XLO(19,BOF,528,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3332 {"bfctr-",  XLO(19,BOF,528,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3333 {"bfctrl",  XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3334 {"bfctrl-", XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3335 {"bfctr+",  XLO(19,BOFP,528,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3336 {"bfctrl+", XLO(19,BOFP,528,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3337 {"bfctr-",  XLO(19,BOFM4,528,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3338 {"bfctrl-", XLO(19,BOFM4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3339 {"bfctr+",  XLO(19,BOFP4,528,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3340 {"bfctrl+", XLO(19,BOFP4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3341 {"btctr",   XLO(19,BOT,528,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3342 {"btctr-",  XLO(19,BOT,528,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3343 {"btctrl",  XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3344 {"btctrl-", XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3345 {"btctr+",  XLO(19,BOTP,528,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3346 {"btctrl+", XLO(19,BOTP,528,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3347 {"btctr-",  XLO(19,BOTM4,528,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3348 {"btctrl-", XLO(19,BOTM4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3349 {"btctr+",  XLO(19,BOTP4,528,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3350 {"btctrl+", XLO(19,BOTP4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3351
3352 {"bcctr-",  XLYLK(19,528,0,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3353 {"bcctrl-", XLYLK(19,528,0,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3354 {"bcctr+",  XLYLK(19,528,1,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3355 {"bcctrl+", XLYLK(19,528,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3356 {"bcctr",   XLLK(19,528,0),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3357 {"bcc",     XLLK(19,528,0),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3358 {"bcctrl",  XLLK(19,528,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3359 {"bccl",    XLLK(19,528,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3360
3361 {"rlwimi",      M(20,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3362 {"rlimi",       M(20,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3363
3364 {"rlwimi.",     M(20,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3365 {"rlimi.",      M(20,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3366
3367 {"rotlwi",      MME(21,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
3368 {"clrlwi",      MME(21,31,0),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
3369 {"rlwinm",      M(21,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3370 {"rlinm",       M(21,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3371 {"rotlwi.",     MME(21,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
3372 {"clrlwi.",     MME(21,31,1),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
3373 {"rlwinm.",     M(21,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3374 {"rlinm.",      M(21,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3375
3376 {"rlmi",        M(22,0),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
3377 {"rlmi.",       M(22,1),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
3378
3379 {"rotlw",       MME(23,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
3380 {"rlwnm",       M(23,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3381 {"rlnm",        M(23,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3382 {"rotlw.",      MME(23,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
3383 {"rlwnm.",      M(23,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3384 {"rlnm.",       M(23,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3385
3386 {"nop",         OP(24),         0xffffffff,  PPCCOM,    PPCNONE,        {0}},
3387 {"ori",         OP(24),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3388 {"oril",        OP(24),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3389
3390 {"oris",        OP(25),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3391 {"oriu",        OP(25),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3392
3393 {"xori",        OP(26),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3394 {"xoril",       OP(26),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3395
3396 {"xoris",       OP(27),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3397 {"xoriu",       OP(27),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3398
3399 {"andi.",       OP(28),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3400 {"andil.",      OP(28),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3401
3402 {"andis.",      OP(29),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3403 {"andiu.",      OP(29),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3404
3405 {"rotldi",      MD(30,0,0),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
3406 {"clrldi",      MD(30,0,0),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
3407 {"rldicl",      MD(30,0,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3408 {"rotldi.",     MD(30,0,1),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
3409 {"clrldi.",     MD(30,0,1),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
3410 {"rldicl.",     MD(30,0,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3411
3412 {"rldicr",      MD(30,1,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
3413 {"rldicr.",     MD(30,1,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
3414
3415 {"rldic",       MD(30,2,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3416 {"rldic.",      MD(30,2,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3417
3418 {"rldimi",      MD(30,3,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3419 {"rldimi.",     MD(30,3,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3420
3421 {"rotld",       MDS(30,8,0),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
3422 {"rldcl",       MDS(30,8,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
3423 {"rotld.",      MDS(30,8,1),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
3424 {"rldcl.",      MDS(30,8,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
3425
3426 {"rldcr",       MDS(30,9,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
3427 {"rldcr.",      MDS(30,9,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
3428
3429 {"cmpw",        XOPL(31,0,0),   XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
3430 {"cmpd",        XOPL(31,0,1),   XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
3431 {"cmp",         X(31,0),        XCMP_MASK,   PPC,       PPCNONE,        {BF, L, RA, RB}},
3432 {"cmp",         X(31,0),        XCMPL_MASK,  PWRCOM,    PPCNONE,        {BF, RA, RB}},
3433
3434 {"twlgt",       XTO(31,4,TOLGT), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3435 {"tlgt",        XTO(31,4,TOLGT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3436 {"twllt",       XTO(31,4,TOLLT), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3437 {"tllt",        XTO(31,4,TOLLT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3438 {"tweq",        XTO(31,4,TOEQ),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3439 {"teq",         XTO(31,4,TOEQ),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3440 {"twlge",       XTO(31,4,TOLGE), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3441 {"tlge",        XTO(31,4,TOLGE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3442 {"twlnl",       XTO(31,4,TOLNL), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3443 {"tlnl",        XTO(31,4,TOLNL), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3444 {"twlle",       XTO(31,4,TOLLE), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3445 {"tlle",        XTO(31,4,TOLLE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3446 {"twlng",       XTO(31,4,TOLNG), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3447 {"tlng",        XTO(31,4,TOLNG), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3448 {"twgt",        XTO(31,4,TOGT),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3449 {"tgt",         XTO(31,4,TOGT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3450 {"twge",        XTO(31,4,TOGE),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3451 {"tge",         XTO(31,4,TOGE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3452 {"twnl",        XTO(31,4,TONL),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3453 {"tnl",         XTO(31,4,TONL),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3454 {"twlt",        XTO(31,4,TOLT),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3455 {"tlt",         XTO(31,4,TOLT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3456 {"twle",        XTO(31,4,TOLE),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3457 {"tle",         XTO(31,4,TOLE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3458 {"twng",        XTO(31,4,TONG),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3459 {"tng",         XTO(31,4,TONG),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3460 {"twne",        XTO(31,4,TONE),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3461 {"tne",         XTO(31,4,TONE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3462 {"trap",        XTO(31,4,TOU),   0xffffffff, PPCCOM,    PPCNONE,        {0}},
3463 {"tw",          X(31,4),         X_MASK,     PPCCOM,    PPCNONE,        {TO, RA, RB}},
3464 {"t",           X(31,4),         X_MASK,     PWRCOM,    PPCNONE,        {TO, RA, RB}},
3465
3466 {"lvsl",        X(31,6),        X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3467 {"lvebx",       X(31,7),        X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3468 {"lbfcmx",      APU(31,7,0),    APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3469
3470 {"subfc",       XO(31,8,0,0),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3471 {"sf",          XO(31,8,0,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3472 {"subc",        XO(31,8,0,0),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RB, RA}},
3473 {"subfc.",      XO(31,8,0,1),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3474 {"sf.",         XO(31,8,0,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3475 {"subc.",       XO(31,8,0,1),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RB, RA}},
3476
3477 {"mulhdu",      XO(31,9,0,0),   XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3478 {"mulhdu.",     XO(31,9,0,1),   XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3479
3480 {"addc",        XO(31,10,0,0),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3481 {"a",           XO(31,10,0,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3482 {"addc.",       XO(31,10,0,1),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3483 {"a.",          XO(31,10,0,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3484
3485 {"mulhwu",      XO(31,11,0,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3486 {"mulhwu.",     XO(31,11,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3487
3488 {"isellt",      X(31,15),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA, RB}},
3489
3490 {"tlbilxlpid",  XTO(31,18,0),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
3491 {"tlbilxpid",   XTO(31,18,1),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
3492 {"tlbilxva",    XTO(31,18,3),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {RA0, RB}},
3493 {"tlbilx",      X(31,18),       X_MASK,   E500MC|PPCA2, PPCNONE,        {T, RA0, RB}},
3494
3495 {"mfcr",        XFXM(31,19,0,0), XFXFXM_MASK, POWER4,   PPCNONE,        {RT, FXM4}},
3496 {"mfcr",        XFXM(31,19,0,0), XRARB_MASK, COM,       POWER4,         {RT}},
3497 {"mfocrf",      XFXM(31,19,0,1), XFXFXM_MASK, COM,      PPCNONE,        {RT, FXM}},
3498
3499 {"lwarx",       X(31,20),       XEH_MASK,    PPC,       PPCNONE,        {RT, RA0, RB, EH}},
3500
3501 {"ldx",         X(31,21),       X_MASK,      PPC64,     PPCNONE,        {RT, RA0, RB}},
3502
3503 {"icbt",        X(31,22),       X_MASK, BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {CT, RA, RB}},
3504
3505 {"lwzx",        X(31,23),       X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
3506 {"lx",          X(31,23),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
3507
3508 {"slw",         XRC(31,24,0),   X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
3509 {"sl",          XRC(31,24,0),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
3510 {"slw.",        XRC(31,24,1),   X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
3511 {"sl.",         XRC(31,24,1),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
3512
3513 {"cntlzw",      XRC(31,26,0),   XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
3514 {"cntlz",       XRC(31,26,0),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
3515 {"cntlzw.",     XRC(31,26,1),   XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
3516 {"cntlz.",      XRC(31,26,1),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
3517
3518 {"sld",         XRC(31,27,0),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
3519 {"sld.",        XRC(31,27,1),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
3520
3521 {"and",         XRC(31,28,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3522 {"and.",        XRC(31,28,1),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3523
3524 {"maskg",       XRC(31,29,0),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
3525 {"maskg.",      XRC(31,29,1),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
3526
3527 {"ldepx",       X(31,29),       X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3528 {"lwepx",       X(31,31),       X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3529
3530 {"cmplw",       XOPL(31,32,0),  XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
3531 {"cmpld",       XOPL(31,32,1),  XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
3532 {"cmpl",        X(31,32),       XCMP_MASK,   PPC,       PPCNONE,        {BF, L, RA, RB}},
3533 {"cmpl",        X(31,32),       XCMPL_MASK,  PWRCOM,    PPCNONE,        {BF, RA, RB}},
3534
3535 {"lvsr",        X(31,38),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3536 {"lvehx",       X(31,39),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3537 {"lhfcmx",      APU(31,39,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3538
3539 {"iselgt",      X(31,47),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA, RB}},
3540
3541 {"lvewx",       X(31,71),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3542
3543 {"addg6s",      XO(31,74,0,0),  XO_MASK,     POWER6,    PPCNONE,        {RT, RA, RB}},
3544
3545 {"iseleq",      X(31,79),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA, RB}},
3546
3547 {"isel",        XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, PPCNONE,       {RT, RA, RB, CRB}},
3548
3549 {"subf",        XO(31,40,0,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3550 {"sub",         XO(31,40,0,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
3551 {"subf.",       XO(31,40,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3552 {"sub.",        XO(31,40,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
3553
3554 {"eratilx",     X(31,51),       X_MASK,      PPCA2,     PPCNONE,        {ERAT_T, RA, RB}},
3555
3556 {"lbarx",       X(31,52),       XEH_MASK,    POWER7,    PPCNONE,        {RT, RA0, RB, EH}},
3557
3558 {"ldux",        X(31,53),       X_MASK,      PPC64,     PPCNONE,        {RT, RAL, RB}},
3559
3560 {"dcbst",       X(31,54),       XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
3561
3562 {"lwzux",       X(31,55),       X_MASK,      PPCCOM,    PPCNONE,        {RT, RAL, RB}},
3563 {"lux",         X(31,55),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
3564
3565 {"cntlzd",      XRC(31,58,0),   XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
3566 {"cntlzd.",     XRC(31,58,1),   XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
3567
3568 {"andc",        XRC(31,60,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3569 {"andc.",       XRC(31,60,1),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3570
3571 {"waitrsv",     X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
3572 {"waitimpl",    X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
3573 {"wait",        X(31,62),         XWC_MASK,   POWER7|E500MC|PPCA2, PPCNONE, {WC}},
3574
3575 {"dcbstep",     XRT(31,63,0),   XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
3576
3577 {"tdlgt",       XTO(31,68,TOLGT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3578 {"tdllt",       XTO(31,68,TOLLT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3579 {"tdeq",        XTO(31,68,TOEQ),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3580 {"tdlge",       XTO(31,68,TOLGE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3581 {"tdlnl",       XTO(31,68,TOLNL), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3582 {"tdlle",       XTO(31,68,TOLLE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3583 {"tdlng",       XTO(31,68,TOLNG), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3584 {"tdgt",        XTO(31,68,TOGT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3585 {"tdge",        XTO(31,68,TOGE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3586 {"tdnl",        XTO(31,68,TONL),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3587 {"tdlt",        XTO(31,68,TOLT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3588 {"tdle",        XTO(31,68,TOLE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3589 {"tdng",        XTO(31,68,TONG),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3590 {"tdne",        XTO(31,68,TONE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3591 {"td",          X(31,68),       X_MASK,      PPC64,     PPCNONE,        {TO, RA, RB}},
3592
3593 {"lwfcmx",      APU(31,71,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3594 {"mulhd",       XO(31,73,0,0),  XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3595 {"mulhd.",      XO(31,73,0,1),  XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3596
3597 {"mulhw",       XO(31,75,0,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3598 {"mulhw.",      XO(31,75,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3599
3600 {"dlmzb",       XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, PPCNONE,     {RA, RS, RB}},
3601 {"dlmzb.",      XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, PPCNONE,     {RA, RS, RB}},
3602
3603 {"mtsrd",       X(31,82),  XRB_MASK|(1<<20), PPC64,     PPCNONE,        {SR, RS}},
3604
3605 {"mfmsr",       X(31,83),       XRARB_MASK,  COM,       PPCNONE,        {RT}},
3606
3607 {"ldarx",       X(31,84),       XEH_MASK,    PPC64,     PPCNONE,        {RT, RA0, RB, EH}},
3608
3609 {"dcbfl",       XOPL(31,86,1),  XRT_MASK,    POWER5,    PPC476,         {RA, RB}},
3610 {"dcbf",        X(31,86),       XLRT_MASK,   PPC,       PPCNONE,        {RA, RB, L}},
3611
3612 {"lbzx",        X(31,87),       X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
3613
3614 {"lbepx",       X(31,95),       X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3615
3616 {"lvx",         X(31,103),      X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3617 {"lqfcmx",      APU(31,103,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3618
3619 {"neg",         XO(31,104,0,0), XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
3620 {"neg.",        XO(31,104,0,1), XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
3621
3622 {"mul",         XO(31,107,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3623 {"mul.",        XO(31,107,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3624
3625 {"mtsrdin",     X(31,114),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
3626
3627 {"lharx",       X(31,116),      XEH_MASK,    POWER7,    PPCNONE,        {RT, RA0, RB, EH}},
3628
3629 {"clf",         X(31,118),      XTO_MASK,    POWER,     PPCNONE,        {RA, RB}},
3630
3631 {"lbzux",       X(31,119),      X_MASK,      COM,       PPCNONE,        {RT, RAL, RB}},
3632
3633 {"popcntb",     X(31,122),      XRB_MASK,    POWER5,    PPCNONE,        {RA, RS}},
3634
3635 {"not",         XRC(31,124,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
3636 {"nor",         XRC(31,124,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3637 {"not.",        XRC(31,124,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
3638 {"nor.",        XRC(31,124,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3639
3640 {"dcbfep",      XRT(31,127,0),  XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
3641
3642 {"wrtee",       X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RS}},
3643
3644 {"dcbtstls",    X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,       {CT, RA, RB}},
3645
3646 {"stvebx",      X(31,135),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3647 {"stbfcmx",     APU(31,135,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3648
3649 {"subfe",       XO(31,136,0,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3650 {"sfe",         XO(31,136,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3651 {"subfe.",      XO(31,136,0,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3652 {"sfe.",        XO(31,136,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3653
3654 {"adde",        XO(31,138,0,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3655 {"ae",          XO(31,138,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3656 {"adde.",       XO(31,138,0,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3657 {"ae.",         XO(31,138,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3658
3659 {"dcbtstlse",   X(31,142),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
3660
3661 {"mtcr",        XFXM(31,144,0xff,0), XRARB_MASK, COM,   PPCNONE,        {RS}},
3662 {"mtcrf",       XFXM(31,144,0,0), XFXFXM_MASK, COM,     PPCNONE,        {FXM, RS}},
3663 {"mtocrf",      XFXM(31,144,0,1), XFXFXM_MASK, COM,     PPCNONE,        {FXM, RS}},
3664
3665 {"mtmsr",       X(31,146),      XRLARB_MASK, COM,       PPCNONE,        {RS, A_L}},
3666
3667 {"eratsx",      XRC(31,147,0),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
3668 {"eratsx.",     XRC(31,147,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
3669
3670 {"stdx",        X(31,149),      X_MASK,      PPC64,     PPCNONE,        {RS, RA0, RB}},
3671
3672 {"stwcx.",      XRC(31,150,1),  X_MASK,      PPC,       PPCNONE,        {RS, RA0, RB}},
3673
3674 {"stwx",        X(31,151),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, RB}},
3675 {"stx",         X(31,151),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA, RB}},
3676
3677 {"slq",         XRC(31,152,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3678 {"slq.",        XRC(31,152,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3679
3680 {"sle",         XRC(31,153,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3681 {"sle.",        XRC(31,153,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3682
3683 {"prtyw",       X(31,154),      XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
3684
3685 {"stdepx",      X(31,157),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
3686
3687 {"stwepx",      X(31,159),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
3688
3689 {"wrteei",      X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {E}},
3690
3691 {"dcbtls",      X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,       {CT, RA, RB}},
3692
3693 {"stvehx",      X(31,167),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3694 {"sthfcmx",     APU(31,167,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3695
3696 {"dcbtlse",     X(31,174),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
3697
3698 {"mtmsrd",      X(31,178),      XRLARB_MASK, PPC64,     PPCNONE,        {RS, A_L}},
3699
3700 {"eratre",      X(31,179),      X_MASK,      PPCA2,     PPCNONE,        {RT, RA, WS}},
3701
3702 {"stdux",       X(31,181),      X_MASK,      PPC64,     PPCNONE,        {RS, RAS, RB}},
3703
3704 {"wchkall",     X(31,182),      X_MASK,      PPCA2,     PPCNONE,        {OBF}},
3705
3706 {"stwux",       X(31,183),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RAS, RB}},
3707 {"stux",        X(31,183),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
3708
3709 {"sliq",        XRC(31,184,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3710 {"sliq.",       XRC(31,184,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3711
3712 {"prtyd",       X(31,186),      XRB_MASK, POWER6|PPCA2, PPCNONE,        {RA, RS}},
3713
3714 {"stvewx",      X(31,199),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3715 {"stwfcmx",     APU(31,199,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3716
3717 {"subfze",      XO(31,200,0,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3718 {"sfze",        XO(31,200,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3719 {"subfze.",     XO(31,200,0,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3720 {"sfze.",       XO(31,200,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3721
3722 {"addze",       XO(31,202,0,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3723 {"aze",         XO(31,202,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3724 {"addze.",      XO(31,202,0,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3725 {"aze.",        XO(31,202,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3726
3727 {"msgsnd",      XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE,   {RB}},
3728
3729 {"mtsr",        X(31,210), XRB_MASK|(1<<20), COM32,     TITAN,          {SR, RS}},
3730
3731 {"eratwe",      X(31,211),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA, WS}},
3732
3733 {"ldawx.",      XRC(31,212,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
3734
3735 {"stdcx.",      XRC(31,214,1),  X_MASK,      PPC64,     PPCNONE,        {RS, RA0, RB}},
3736
3737 {"stbx",        X(31,215),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
3738
3739 {"sllq",        XRC(31,216,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3740 {"sllq.",       XRC(31,216,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3741
3742 {"sleq",        XRC(31,217,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3743 {"sleq.",       XRC(31,217,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3744
3745 {"stbepx",      X(31,223),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
3746
3747 {"icblc",       X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,       {CT, RA, RB}},
3748
3749 {"stvx",        X(31,231),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3750 {"stqfcmx",     APU(31,231,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3751
3752 {"subfme",      XO(31,232,0,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3753 {"sfme",        XO(31,232,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3754 {"subfme.",     XO(31,232,0,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3755 {"sfme.",       XO(31,232,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3756
3757 {"mulld",       XO(31,233,0,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3758 {"mulld.",      XO(31,233,0,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3759
3760 {"addme",       XO(31,234,0,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3761 {"ame",         XO(31,234,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3762 {"addme.",      XO(31,234,0,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3763 {"ame.",        XO(31,234,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3764
3765 {"mullw",       XO(31,235,0,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3766 {"muls",        XO(31,235,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3767 {"mullw.",      XO(31,235,0,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3768 {"muls.",       XO(31,235,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3769
3770 {"icblce",      X(31,238),      X_MASK,      PPCCHLK,   E500MC|PPCA2,   {CT, RA, RB}},
3771 {"msgclr",      XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE,     {RB}},
3772 {"mtsrin",      X(31,242),      XRA_MASK,    PPC32,     TITAN,          {RS, RB}},
3773 {"mtsri",       X(31,242),      XRA_MASK,    POWER32,   PPCNONE,        {RS, RB}},
3774
3775 {"dcbtstt",     XRT(31,246,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA, RB}},
3776 {"dcbtst",      X(31,246),      X_MASK,      POWER4,    PPCNONE,        {RA, RB, CT}},
3777 {"dcbtst",      X(31,246),      X_MASK,      PPC,       POWER4,         {CT, RA, RB}},
3778
3779 {"stbux",       X(31,247),      X_MASK,      COM,       PPCNONE,        {RS, RAS, RB}},
3780
3781 {"slliq",       XRC(31,248,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3782 {"slliq.",      XRC(31,248,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3783
3784 {"bpermd",      X(31,252),      X_MASK,   POWER7|PPCA2, PPCNONE,        {RA, RS, RB}},
3785
3786 {"dcbtstep",    XRT(31,255,0),  X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3787
3788 {"mfdcrx",      X(31,259),      X_MASK, BOOKE|PPCA2|PPC476, TITAN,      {RS, RA}},
3789 {"mfdcrx.",     XRC(31,259,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA}},
3790
3791 {"icbt",        X(31,262),      XRT_MASK,    PPC403,    PPCNONE,        {RA, RB}},
3792
3793 {"ldfcmx",      APU(31,263,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3794 {"doz",         XO(31,264,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3795 {"doz.",        XO(31,264,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3796
3797 {"add",         XO(31,266,0,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3798 {"cax",         XO(31,266,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3799 {"add.",        XO(31,266,0,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3800 {"cax.",        XO(31,266,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3801
3802 {"ehpriv",      X(31,270),      0xffffffff, E500MC|PPCA2, PPCNONE,      {0}},
3803
3804 {"tlbiel",      X(31,274),      XRTLRA_MASK, POWER4,    PPC476,         {RB, L}},
3805
3806 {"mfapidi",     X(31,275),      X_MASK,      BOOKE,     TITAN,          {RT, RA}},
3807
3808 {"lscbx",       XRC(31,277,0),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
3809 {"lscbx.",      XRC(31,277,1),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
3810
3811 {"dcbtt",       XRT(31,278,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA, RB}},
3812 {"dcbt",        X(31,278),      X_MASK,      POWER4,    PPCNONE,        {RA, RB, CT}},
3813 {"dcbt",        X(31,278),      X_MASK,      PPC,       POWER4,         {CT, RA, RB}},
3814
3815 {"lhzx",        X(31,279),      X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
3816
3817 {"cdtbcd",      X(31,282),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
3818
3819 {"eqv",         XRC(31,284,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3820 {"eqv.",        XRC(31,284,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3821
3822 {"lhepx",       X(31,287),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3823
3824 {"mfdcrux",     X(31,291),      X_MASK,      PPC464,    PPCNONE,        {RS, RA}},
3825
3826 {"tlbie",       X(31,306),      XRTLRA_MASK, PPC,       TITAN,          {RB, L}},
3827 {"tlbi",        X(31,306),      XRT_MASK,    POWER,     PPCNONE,        {RA0, RB}},
3828
3829 {"eciwx",       X(31,310),      X_MASK,      PPC,       TITAN,          {RT, RA, RB}},
3830
3831 {"lhzux",       X(31,311),      X_MASK,      COM,       PPCNONE,        {RT, RAL, RB}},
3832
3833 {"cbcdtd",      X(31,314),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
3834
3835 {"xor",         XRC(31,316,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3836 {"xor.",        XRC(31,316,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3837
3838 {"dcbtep",      XRT(31,319,0),  X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3839
3840 {"mfexisr",     XSPR(31,323, 64), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3841 {"mfexier",     XSPR(31,323, 66), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3842 {"mfbr0",       XSPR(31,323,128), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3843 {"mfbr1",       XSPR(31,323,129), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3844 {"mfbr2",       XSPR(31,323,130), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3845 {"mfbr3",       XSPR(31,323,131), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3846 {"mfbr4",       XSPR(31,323,132), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3847 {"mfbr5",       XSPR(31,323,133), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3848 {"mfbr6",       XSPR(31,323,134), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3849 {"mfbr7",       XSPR(31,323,135), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3850 {"mfbear",      XSPR(31,323,144), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3851 {"mfbesr",      XSPR(31,323,145), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3852 {"mfiocr",      XSPR(31,323,160), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3853 {"mfdmacr0",    XSPR(31,323,192), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3854 {"mfdmact0",    XSPR(31,323,193), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3855 {"mfdmada0",    XSPR(31,323,194), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3856 {"mfdmasa0",    XSPR(31,323,195), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3857 {"mfdmacc0",    XSPR(31,323,196), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3858 {"mfdmacr1",    XSPR(31,323,200), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3859 {"mfdmact1",    XSPR(31,323,201), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3860 {"mfdmada1",    XSPR(31,323,202), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3861 {"mfdmasa1",    XSPR(31,323,203), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3862 {"mfdmacc1",    XSPR(31,323,204), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3863 {"mfdmacr2",    XSPR(31,323,208), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3864 {"mfdmact2",    XSPR(31,323,209), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3865 {"mfdmada2",    XSPR(31,323,210), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3866 {"mfdmasa2",    XSPR(31,323,211), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3867 {"mfdmacc2",    XSPR(31,323,212), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3868 {"mfdmacr3",    XSPR(31,323,216), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3869 {"mfdmact3",    XSPR(31,323,217), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3870 {"mfdmada3",    XSPR(31,323,218), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3871 {"mfdmasa3",    XSPR(31,323,219), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3872 {"mfdmacc3",    XSPR(31,323,220), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3873 {"mfdmasr",     XSPR(31,323,224), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3874 {"mfdcr",       X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN,    {RT, SPR}},
3875 {"mfdcr.",      XRC(31,323,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, SPR}},
3876
3877 {"dcread",      X(31,326),      X_MASK,  PPC476|TITAN,  PPCNONE,        {RT, RA, RB}},
3878
3879 {"div",         XO(31,331,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3880 {"div.",        XO(31,331,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3881
3882 {"lxvdsx",      X(31,332),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
3883
3884 {"mfpmr",       X(31,334),      X_MASK, PPCPMR|PPCE300, PPCNONE,        {RT, PMR}},
3885
3886 {"mfmq",        XSPR(31,339,  0), XSPR_MASK, M601,      PPCNONE,        {RT}},
3887 {"mfxer",       XSPR(31,339,  1), XSPR_MASK, COM,       PPCNONE,        {RT}},
3888 {"mfrtcu",      XSPR(31,339,  4), XSPR_MASK, COM,       TITAN,          {RT}},
3889 {"mfrtcl",      XSPR(31,339,  5), XSPR_MASK, COM,       TITAN,          {RT}},
3890 {"mfdec",       XSPR(31,339,  6), XSPR_MASK, MFDEC1,    PPCNONE,        {RT}},
3891 {"mflr",        XSPR(31,339,  8), XSPR_MASK, COM,       PPCNONE,        {RT}},
3892 {"mfctr",       XSPR(31,339,  9), XSPR_MASK, COM,       PPCNONE,        {RT}},
3893 {"mftid",       XSPR(31,339, 17), XSPR_MASK, POWER,     PPCNONE,        {RT}},
3894 {"mfdsisr",     XSPR(31,339, 18), XSPR_MASK, COM,       TITAN,          {RT}},
3895 {"mfdar",       XSPR(31,339, 19), XSPR_MASK, COM,       TITAN,          {RT}},
3896 {"mfdec",       XSPR(31,339, 22), XSPR_MASK, MFDEC2|TITAN, PPCNONE,     {RT}},
3897 {"mfsdr0",      XSPR(31,339, 24), XSPR_MASK, POWER,     PPCNONE,        {RT}},
3898 {"mfsdr1",      XSPR(31,339, 25), XSPR_MASK, COM,       TITAN,          {RT}},
3899 {"mfsrr0",      XSPR(31,339, 26), XSPR_MASK, COM,       PPCNONE,        {RT}},
3900 {"mfsrr1",      XSPR(31,339, 27), XSPR_MASK, COM,       PPCNONE,        {RT}},
3901 {"mfcfar",      XSPR(31,339, 28), XSPR_MASK, POWER6,    PPCNONE,        {RT}},
3902 {"mfpid",       XSPR(31,339, 48), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3903 {"mfcsrr0",     XSPR(31,339, 58), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3904 {"mfcsrr1",     XSPR(31,339, 59), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3905 {"mfdear",      XSPR(31,339, 61), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3906 {"mfesr",       XSPR(31,339, 62), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3907 {"mfivpr",      XSPR(31,339, 63), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3908 {"mfcmpa",      XSPR(31,339,144), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3909 {"mfcmpb",      XSPR(31,339,145), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3910 {"mfcmpc",      XSPR(31,339,146), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3911 {"mfcmpd",      XSPR(31,339,147), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3912 {"mficr",       XSPR(31,339,148), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3913 {"mfder",       XSPR(31,339,149), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3914 {"mfcounta",    XSPR(31,339,150), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3915 {"mfcountb",    XSPR(31,339,151), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3916 {"mfcmpe",      XSPR(31,339,152), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3917 {"mfcmpf",      XSPR(31,339,153), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3918 {"mfcmpg",      XSPR(31,339,154), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3919 {"mfcmph",      XSPR(31,339,155), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3920 {"mflctrl1",    XSPR(31,339,156), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3921 {"mflctrl2",    XSPR(31,339,157), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3922 {"mfictrl",     XSPR(31,339,158), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3923 {"mfbar",       XSPR(31,339,159), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3924 {"mfvrsave",    XSPR(31,339,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RT}},
3925 {"mfusprg0",    XSPR(31,339,256), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3926 {"mfsprg",      XSPR(31,339,256), XSPRG_MASK, PPC,      PPCNONE,        {RT, SPRG}},
3927 {"mfsprg4",     XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3928 {"mfsprg5",     XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3929 {"mfsprg6",     XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3930 {"mfsprg7",     XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3931 {"mftb",        XSPR(31,339,268), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3932 {"mftbl",       XSPR(31,339,268), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3933 {"mftbu",       XSPR(31,339,269), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3934 {"mfsprg0",     XSPR(31,339,272), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3935 {"mfsprg1",     XSPR(31,339,273), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3936 {"mfsprg2",     XSPR(31,339,274), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3937 {"mfsprg3",     XSPR(31,339,275), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3938 {"mfasr",       XSPR(31,339,280), XSPR_MASK, PPC64,     PPCNONE,        {RT}},
3939 {"mfear",       XSPR(31,339,282), XSPR_MASK, PPC,       TITAN,          {RT}},
3940 {"mfpir",       XSPR(31,339,286), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3941 {"mfpvr",       XSPR(31,339,287), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3942 {"mfdbsr",      XSPR(31,339,304), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3943 {"mfdbcr0",     XSPR(31,339,308), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3944 {"mfdbcr1",     XSPR(31,339,309), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3945 {"mfdbcr2",     XSPR(31,339,310), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3946 {"mfiac1",      XSPR(31,339,312), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3947 {"mfiac2",      XSPR(31,339,313), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3948 {"mfiac3",      XSPR(31,339,314), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3949 {"mfiac4",      XSPR(31,339,315), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3950 {"mfdac1",      XSPR(31,339,316), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3951 {"mfdac2",      XSPR(31,339,317), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3952 {"mfdvc1",      XSPR(31,339,318), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3953 {"mfdvc2",      XSPR(31,339,319), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3954 {"mftsr",       XSPR(31,339,336), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3955 {"mftcr",       XSPR(31,339,340), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3956 {"mfivor0",     XSPR(31,339,400), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3957 {"mfivor1",     XSPR(31,339,401), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3958 {"mfivor2",     XSPR(31,339,402), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3959 {"mfivor3",     XSPR(31,339,403), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3960 {"mfivor4",     XSPR(31,339,404), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3961 {"mfivor5",     XSPR(31,339,405), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3962 {"mfivor6",     XSPR(31,339,406), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3963 {"mfivor7",     XSPR(31,339,407), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3964 {"mfivor8",     XSPR(31,339,408), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3965 {"mfivor9",     XSPR(31,339,409), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3966 {"mfivor10",    XSPR(31,339,410), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3967 {"mfivor11",    XSPR(31,339,411), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3968 {"mfivor12",    XSPR(31,339,412), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3969 {"mfivor13",    XSPR(31,339,413), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3970 {"mfivor14",    XSPR(31,339,414), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3971 {"mfivor15",    XSPR(31,339,415), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3972 {"mfspefscr",   XSPR(31,339,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
3973 {"mfbbear",     XSPR(31,339,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
3974 {"mfbbtar",     XSPR(31,339,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
3975 {"mfivor32",    XSPR(31,339,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
3976 {"mfibatu",     XSPR(31,339,528), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
3977 {"mfivor33",    XSPR(31,339,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
3978 {"mfibatl",     XSPR(31,339,529), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
3979 {"mfivor34",    XSPR(31,339,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
3980 {"mfivor35",    XSPR(31,339,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RT}},
3981 {"mfdbatu",     XSPR(31,339,536), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
3982 {"mfdbatl",     XSPR(31,339,537), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
3983 {"mfic_cst",    XSPR(31,339,560), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3984 {"mfic_adr",    XSPR(31,339,561), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3985 {"mfic_dat",    XSPR(31,339,562), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3986 {"mfdc_cst",    XSPR(31,339,568), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3987 {"mfdc_adr",    XSPR(31,339,569), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3988 {"mfdc_dat",    XSPR(31,339,570), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3989 {"mfmcsrr0",    XSPR(31,339,570), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
3990 {"mfmcsrr1",    XSPR(31,339,571), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
3991 {"mfmcsr",      XSPR(31,339,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
3992 {"mfmcar",      XSPR(31,339,573), XSPR_MASK, PPCRFMCI,  TITAN,          {RT}},
3993 {"mfdpdr",      XSPR(31,339,630), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3994 {"mfdpir",      XSPR(31,339,631), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3995 {"mfimmr",      XSPR(31,339,638), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3996 {"mfmi_ctr",    XSPR(31,339,784), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3997 {"mfmi_ap",     XSPR(31,339,786), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3998 {"mfmi_epn",    XSPR(31,339,787), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3999 {"mfmi_twc",    XSPR(31,339,789), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4000 {"mfmi_rpn",    XSPR(31,339,790), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4001 {"mfmd_ctr",    XSPR(31,339,792), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4002 {"mfm_casid",   XSPR(31,339,793), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4003 {"mfmd_ap",     XSPR(31,339,794), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4004 {"mfmd_epn",    XSPR(31,339,795), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4005 {"mfmd_twb",    XSPR(31,339,796), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4006 {"mfmd_twc",    XSPR(31,339,797), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4007 {"mfmd_rpn",    XSPR(31,339,798), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4008 {"mfm_tw",      XSPR(31,339,799), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4009 {"mfmi_dbcam",  XSPR(31,339,816), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4010 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4011 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4012 {"mfmd_dbcam",  XSPR(31,339,824), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4013 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4014 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4015 {"mfivndx",     XSPR(31,339,880), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4016 {"mfdvndx",     XSPR(31,339,881), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4017 {"mfivlim",     XSPR(31,339,882), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4018 {"mfdvlim",     XSPR(31,339,883), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4019 {"mfclcsr",     XSPR(31,339,884), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4020 {"mfccr1",      XSPR(31,339,888), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4021 {"mfrstcfg",    XSPR(31,339,923), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4022 {"mfdcdbtrl",   XSPR(31,339,924), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4023 {"mfdcdbtrh",   XSPR(31,339,925), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4024 {"mficdbtr",    XSPR(31,339,927), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4025 {"mfummcr0",    XSPR(31,339,936), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4026 {"mfupmc1",     XSPR(31,339,937), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4027 {"mfupmc2",     XSPR(31,339,938), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4028 {"mfusia",      XSPR(31,339,939), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4029 {"mfummcr1",    XSPR(31,339,940), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4030 {"mfupmc3",     XSPR(31,339,941), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4031 {"mfupmc4",     XSPR(31,339,942), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4032 {"mfzpr",       XSPR(31,339,944), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4033 {"mfpid",       XSPR(31,339,945), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4034 {"mfmmucr",     XSPR(31,339,946), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4035 {"mfccr0",      XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RT}},
4036 {"mfiac3",      XSPR(31,339,948), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4037 {"mfiac4",      XSPR(31,339,949), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4038 {"mfdvc1",      XSPR(31,339,950), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4039 {"mfdvc2",      XSPR(31,339,951), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4040 {"mfmmcr0",     XSPR(31,339,952), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4041 {"mfpmc1",      XSPR(31,339,953), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4042 {"mfsgr",       XSPR(31,339,953), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4043 {"mfdcwr",      XSPR(31,339,954), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4044 {"mfpmc2",      XSPR(31,339,954), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4045 {"mfsia",       XSPR(31,339,955), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4046 {"mfsler",      XSPR(31,339,955), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4047 {"mfmmcr1",     XSPR(31,339,956), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4048 {"mfsu0r",      XSPR(31,339,956), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4049 {"mfdbcr1",     XSPR(31,339,957), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4050 {"mfpmc3",      XSPR(31,339,957), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4051 {"mfpmc4",      XSPR(31,339,958), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4052 {"mficdbdr",    XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, PPCNONE,     {RT}},
4053 {"mfesr",       XSPR(31,339,980), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4054 {"mfdear",      XSPR(31,339,981), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4055 {"mfevpr",      XSPR(31,339,982), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4056 {"mfcdbcr",     XSPR(31,339,983), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4057 {"mftsr",       XSPR(31,339,984), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4058 {"mftcr",       XSPR(31,339,986), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4059 {"mfpit",       XSPR(31,339,987), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4060 {"mftbhi",      XSPR(31,339,988), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4061 {"mftblo",      XSPR(31,339,989), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4062 {"mfsrr2",      XSPR(31,339,990), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4063 {"mfsrr3",      XSPR(31,339,991), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4064 {"mfdbsr",      XSPR(31,339,1008), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4065 {"mfdbcr0",     XSPR(31,339,1010), XSPR_MASK, PPC405,   PPCNONE,        {RT}},
4066 {"mfdbdr",      XSPR(31,339,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
4067 {"mfiac1",      XSPR(31,339,1012), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4068 {"mfiac2",      XSPR(31,339,1013), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4069 {"mfdac1",      XSPR(31,339,1014), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4070 {"mfdac2",      XSPR(31,339,1015), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4071 {"mfl2cr",      XSPR(31,339,1017), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4072 {"mfdccr",      XSPR(31,339,1018), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4073 {"mficcr",      XSPR(31,339,1019), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4074 {"mfictc",      XSPR(31,339,1019), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4075 {"mfpbl1",      XSPR(31,339,1020), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4076 {"mfthrm1",     XSPR(31,339,1020), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4077 {"mfpbu1",      XSPR(31,339,1021), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4078 {"mfthrm2",     XSPR(31,339,1021), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4079 {"mfpbl2",      XSPR(31,339,1022), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4080 {"mfthrm3",     XSPR(31,339,1022), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4081 {"mfpbu2",      XSPR(31,339,1023), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4082 {"mfspr",       X(31,339),      X_MASK,      COM,       PPCNONE,        {RT, SPR}},
4083
4084 {"lwax",        X(31,341),      X_MASK,      PPC64,     PPCNONE,        {RT, RA0, RB}},
4085
4086 {"dst",         XDSS(31,342,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4087
4088 {"lhax",        X(31,343),      X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
4089
4090 {"lvxl",        X(31,359),      X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
4091
4092 {"abs",         XO(31,360,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4093 {"abs.",        XO(31,360,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4094
4095 {"divs",        XO(31,363,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4096 {"divs.",       XO(31,363,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4097
4098 {"tlbia",       X(31,370),      0xffffffff,  PPC,       TITAN,          {0}},
4099
4100 {"mftbl",       XSPR(31,371,268), XSPR_MASK, CLASSIC,   PPCNONE,        {RT}},
4101 {"mftbu",       XSPR(31,371,269), XSPR_MASK, CLASSIC,   PPCNONE,        {RT}},
4102 {"mftb",        X(31,371),      X_MASK,  CLASSIC|PPCA2, POWER7,         {RT, TBR}},
4103
4104 {"lwaux",       X(31,373),      X_MASK,      PPC64,     PPCNONE,        {RT, RAL, RB}},
4105
4106 {"dstst",       XDSS(31,374,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4107
4108 {"lhaux",       X(31,375),      X_MASK,      COM,       PPCNONE,        {RT, RAL, RB}},
4109
4110 {"popcntw",     X(31,378),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
4111
4112 {"mtdcrx",      X(31,387),      X_MASK, BOOKE|PPCA2|PPC476, TITAN,      {RA, RS}},
4113 {"mtdcrx.",     XRC(31,387,1),  X_MASK,      PPCA2,     PPCNONE,        {RA, RS}},
4114
4115 {"dcblc",       X(31,390),      X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,  {CT, RA, RB}},
4116 {"stdfcmx",     APU(31,391,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4117
4118 {"divdeu",      XO(31,393,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4119 {"divdeu.",     XO(31,393,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4120 {"divweu",      XO(31,395,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4121 {"divweu.",     XO(31,395,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4122
4123 {"dcblce",      X(31,398),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
4124
4125 {"slbmte",      X(31,402),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
4126
4127 {"icswx",       XRC(31,406,0),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
4128 {"icswx.",      XRC(31,406,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
4129
4130 {"sthx",        X(31,407),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
4131
4132 {"orc",         XRC(31,412,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4133 {"orc.",        XRC(31,412,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4134
4135 {"sthepx",      X(31,415),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
4136
4137 {"mtdcrux",     X(31,419),      X_MASK,      PPC464,    PPCNONE,        {RA, RS}},
4138
4139 {"divde",       XO(31,425,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4140 {"divde.",      XO(31,425,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4141 {"divwe",       XO(31,427,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4142 {"divwe.",      XO(31,427,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4143
4144 {"slbie",       X(31,434),      XRTRA_MASK,  PPC64,     PPCNONE,        {RB}},
4145
4146 {"ecowx",       X(31,438),      X_MASK,      PPC,       TITAN,          {RT, RA, RB}},
4147
4148 {"sthux",       X(31,439),      X_MASK,      COM,       PPCNONE,        {RS, RAS, RB}},
4149
4150 {"mdors",       0x7f9ce378,     0xffffffff,  E500MC,    PPCNONE,        {0}},
4151
4152 {"mr",          XRC(31,444,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4153 {"or",          XRC(31,444,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4154 {"mr.",         XRC(31,444,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4155 {"or.",         XRC(31,444,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4156
4157 {"mtexisr",     XSPR(31,451, 64), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4158 {"mtexier",     XSPR(31,451, 66), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4159 {"mtbr0",       XSPR(31,451,128), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4160 {"mtbr1",       XSPR(31,451,129), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4161 {"mtbr2",       XSPR(31,451,130), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4162 {"mtbr3",       XSPR(31,451,131), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4163 {"mtbr4",       XSPR(31,451,132), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4164 {"mtbr5",       XSPR(31,451,133), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4165 {"mtbr6",       XSPR(31,451,134), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4166 {"mtbr7",       XSPR(31,451,135), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4167 {"mtbear",      XSPR(31,451,144), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4168 {"mtbesr",      XSPR(31,451,145), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4169 {"mtiocr",      XSPR(31,451,160), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4170 {"mtdmacr0",    XSPR(31,451,192), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4171 {"mtdmact0",    XSPR(31,451,193), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4172 {"mtdmada0",    XSPR(31,451,194), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4173 {"mtdmasa0",    XSPR(31,451,195), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4174 {"mtdmacc0",    XSPR(31,451,196), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4175 {"mtdmacr1",    XSPR(31,451,200), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4176 {"mtdmact1",    XSPR(31,451,201), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4177 {"mtdmada1",    XSPR(31,451,202), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4178 {"mtdmasa1",    XSPR(31,451,203), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4179 {"mtdmacc1",    XSPR(31,451,204), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4180 {"mtdmacr2",    XSPR(31,451,208), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4181 {"mtdmact2",    XSPR(31,451,209), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4182 {"mtdmada2",    XSPR(31,451,210), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4183 {"mtdmasa2",    XSPR(31,451,211), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4184 {"mtdmacc2",    XSPR(31,451,212), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4185 {"mtdmacr3",    XSPR(31,451,216), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4186 {"mtdmact3",    XSPR(31,451,217), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4187 {"mtdmada3",    XSPR(31,451,218), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4188 {"mtdmasa3",    XSPR(31,451,219), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4189 {"mtdmacc3",    XSPR(31,451,220), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4190 {"mtdmasr",     XSPR(31,451,224), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4191 {"mtdcr",       X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN,    {SPR, RS}},
4192 {"mtdcr.",      XRC(31,451,1), X_MASK,       PPCA2,     PPCNONE,        {SPR, RS}},
4193
4194 {"dccci",       X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
4195 {"dci",         X(31,454),      XRARB_MASK, PPCA2|PPC476, PPCNONE,      {CT}},
4196
4197 {"divdu",       XO(31,457,0,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4198 {"divdu.",      XO(31,457,0,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4199
4200 {"divwu",       XO(31,459,0,0), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4201 {"divwu.",      XO(31,459,0,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4202
4203 {"mtpmr",       X(31,462),      X_MASK, PPCPMR|PPCE300, PPCNONE,        {PMR, RS}},
4204
4205 {"mtmq",        XSPR(31,467,  0), XSPR_MASK, M601,      PPCNONE,        {RS}},
4206 {"mtxer",       XSPR(31,467,  1), XSPR_MASK, COM,       PPCNONE,        {RS}},
4207 {"mtlr",        XSPR(31,467,  8), XSPR_MASK, COM,       PPCNONE,        {RS}},
4208 {"mtctr",       XSPR(31,467,  9), XSPR_MASK, COM,       PPCNONE,        {RS}},
4209 {"mttid",       XSPR(31,467, 17), XSPR_MASK, POWER,     PPCNONE,        {RS}},
4210 {"mtdsisr",     XSPR(31,467, 18), XSPR_MASK, COM,       TITAN,          {RS}},
4211 {"mtdar",       XSPR(31,467, 19), XSPR_MASK, COM,       TITAN,          {RS}},
4212 {"mtrtcu",      XSPR(31,467, 20), XSPR_MASK, COM,       TITAN,          {RS}},
4213 {"mtrtcl",      XSPR(31,467, 21), XSPR_MASK, COM,       TITAN,          {RS}},
4214 {"mtdec",       XSPR(31,467, 22), XSPR_MASK, COM,       PPCNONE,        {RS}},
4215 {"mtsdr0",      XSPR(31,467, 24), XSPR_MASK, POWER,     PPCNONE,        {RS}},
4216 {"mtsdr1",      XSPR(31,467, 25), XSPR_MASK, COM,       TITAN,          {RS}},
4217 {"mtsrr0",      XSPR(31,467, 26), XSPR_MASK, COM,       PPCNONE,        {RS}},
4218 {"mtsrr1",      XSPR(31,467, 27), XSPR_MASK, COM,       PPCNONE,        {RS}},
4219 {"mtcfar",      XSPR(31,467, 28), XSPR_MASK, POWER6,    PPCNONE,        {RS}},
4220 {"mtpid",       XSPR(31,467, 48), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4221 {"mtdecar",     XSPR(31,467, 54), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4222 {"mtcsrr0",     XSPR(31,467, 58), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4223 {"mtcsrr1",     XSPR(31,467, 59), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4224 {"mtdear",      XSPR(31,467, 61), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4225 {"mtesr",       XSPR(31,467, 62), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4226 {"mtivpr",      XSPR(31,467, 63), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4227 {"mtcmpa",      XSPR(31,467,144), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4228 {"mtcmpb",      XSPR(31,467,145), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4229 {"mtcmpc",      XSPR(31,467,146), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4230 {"mtcmpd",      XSPR(31,467,147), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4231 {"mticr",       XSPR(31,467,148), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4232 {"mtder",       XSPR(31,467,149), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4233 {"mtcounta",    XSPR(31,467,150), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4234 {"mtcountb",    XSPR(31,467,151), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4235 {"mtcmpe",      XSPR(31,467,152), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4236 {"mtcmpf",      XSPR(31,467,153), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4237 {"mtcmpg",      XSPR(31,467,154), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4238 {"mtcmph",      XSPR(31,467,155), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4239 {"mtlctrl1",    XSPR(31,467,156), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4240 {"mtlctrl2",    XSPR(31,467,157), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4241 {"mtictrl",     XSPR(31,467,158), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4242 {"mtbar",       XSPR(31,467,159), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4243 {"mtvrsave",    XSPR(31,467,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RS}},
4244 {"mtusprg0",    XSPR(31,467,256), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4245 {"mtsprg",      XSPR(31,467,256), XSPRG_MASK,PPC,       PPCNONE,        {SPRG, RS}},
4246 {"mtsprg0",     XSPR(31,467,272), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4247 {"mtsprg1",     XSPR(31,467,273), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4248 {"mtsprg2",     XSPR(31,467,274), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4249 {"mtsprg3",     XSPR(31,467,275), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4250 {"mtsprg4",     XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4251 {"mtsprg5",     XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4252 {"mtsprg6",     XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4253 {"mtsprg7",     XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4254 {"mtasr",       XSPR(31,467,280), XSPR_MASK, PPC64,     PPCNONE,        {RS}},
4255 {"mtear",       XSPR(31,467,282), XSPR_MASK, PPC,       TITAN,          {RS}},
4256 {"mttbl",       XSPR(31,467,284), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4257 {"mttbu",       XSPR(31,467,285), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4258 {"mtdbsr",      XSPR(31,467,304), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4259 {"mtdbcr0",     XSPR(31,467,308), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4260 {"mtdbcr1",     XSPR(31,467,309), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4261 {"mtdbcr2",     XSPR(31,467,310), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4262 {"mtiac1",      XSPR(31,467,312), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4263 {"mtiac2",      XSPR(31,467,313), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4264 {"mtiac3",      XSPR(31,467,314), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4265 {"mtiac4",      XSPR(31,467,315), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4266 {"mtdac1",      XSPR(31,467,316), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4267 {"mtdac2",      XSPR(31,467,317), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4268 {"mtdvc1",      XSPR(31,467,318), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4269 {"mtdvc2",      XSPR(31,467,319), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4270 {"mttsr",       XSPR(31,467,336), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4271 {"mttcr",       XSPR(31,467,340), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4272 {"mtivor0",     XSPR(31,467,400), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4273 {"mtivor1",     XSPR(31,467,401), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4274 {"mtivor2",     XSPR(31,467,402), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4275 {"mtivor3",     XSPR(31,467,403), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4276 {"mtivor4",     XSPR(31,467,404), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4277 {"mtivor5",     XSPR(31,467,405), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4278 {"mtivor6",     XSPR(31,467,406), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4279 {"mtivor7",     XSPR(31,467,407), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4280 {"mtivor8",     XSPR(31,467,408), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4281 {"mtivor9",     XSPR(31,467,409), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4282 {"mtivor10",    XSPR(31,467,410), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4283 {"mtivor11",    XSPR(31,467,411), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4284 {"mtivor12",    XSPR(31,467,412), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4285 {"mtivor13",    XSPR(31,467,413), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4286 {"mtivor14",    XSPR(31,467,414), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4287 {"mtivor15",    XSPR(31,467,415), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4288 {"mtspefscr",   XSPR(31,467,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4289 {"mtbbear",     XSPR(31,467,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
4290 {"mtbbtar",     XSPR(31,467,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
4291 {"mtivor32",    XSPR(31,467,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4292 {"mtibatu",     XSPR(31,467,528), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
4293 {"mtivor33",    XSPR(31,467,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4294 {"mtibatl",     XSPR(31,467,529), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
4295 {"mtivor34",    XSPR(31,467,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4296 {"mtivor35",    XSPR(31,467,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RS}},
4297 {"mtdbatu",     XSPR(31,467,536), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
4298 {"mtdbatl",     XSPR(31,467,537), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
4299 {"mtmcsrr0",    XSPR(31,467,570), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
4300 {"mtmcsrr1",    XSPR(31,467,571), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
4301 {"mtmcsr",      XSPR(31,467,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
4302 {"mtivndx",     XSPR(31,467,880), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4303 {"mtdvndx",     XSPR(31,467,881), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4304 {"mtivlim",     XSPR(31,467,882), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4305 {"mtdvlim",     XSPR(31,467,883), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4306 {"mtclcsr",     XSPR(31,467,884), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4307 {"mtccr1",      XSPR(31,467,888), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4308 {"mtummcr0",    XSPR(31,467,936), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4309 {"mtupmc1",     XSPR(31,467,937), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4310 {"mtupmc2",     XSPR(31,467,938), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4311 {"mtusia",      XSPR(31,467,939), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4312 {"mtummcr1",    XSPR(31,467,940), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4313 {"mtupmc3",     XSPR(31,467,941), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4314 {"mtupmc4",     XSPR(31,467,942), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4315 {"mtzpr",       XSPR(31,467,944), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4316 {"mtpid",       XSPR(31,467,945), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4317 {"mtrmmucr",    XSPR(31,467,946), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4318 {"mtccr0",      XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RS}},
4319 {"mtiac3",      XSPR(31,467,948), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4320 {"mtiac4",      XSPR(31,467,949), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4321 {"mtdvc1",      XSPR(31,467,950), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4322 {"mtdvc2",      XSPR(31,467,951), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4323 {"mtmmcr0",     XSPR(31,467,952), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4324 {"mtpmc1",      XSPR(31,467,953), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4325 {"mtsgr",       XSPR(31,467,953), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4326 {"mtdcwr",      XSPR(31,467,954), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4327 {"mtpmc2",      XSPR(31,467,954), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4328 {"mtsia",       XSPR(31,467,955), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4329 {"mtsler",      XSPR(31,467,955), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4330 {"mtmmcr1",     XSPR(31,467,956), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4331 {"mtsu0r",      XSPR(31,467,956), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4332 {"mtdbcr1",     XSPR(31,467,957), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4333 {"mtpmc3",      XSPR(31,467,957), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4334 {"mtpmc4",      XSPR(31,467,958), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4335 {"mticdbdr",    XSPR(31,467,979), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4336 {"mtesr",       XSPR(31,467,980), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4337 {"mtdear",      XSPR(31,467,981), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4338 {"mtevpr",      XSPR(31,467,982), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4339 {"mtcdbcr",     XSPR(31,467,983), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4340 {"mttsr",       XSPR(31,467,984), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4341 {"mttcr",       XSPR(31,467,986), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4342 {"mtpit",       XSPR(31,467,987), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4343 {"mttbhi",      XSPR(31,467,988), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4344 {"mttblo",      XSPR(31,467,989), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4345 {"mtsrr2",      XSPR(31,467,990), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4346 {"mtsrr3",      XSPR(31,467,991), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4347 {"mtdbsr",      XSPR(31,467,1008), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4348 {"mtdbdr",      XSPR(31,467,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
4349 {"mtdbcr0",     XSPR(31,467,1010), XSPR_MASK, PPC405,   PPCNONE,        {RS}},
4350 {"mtiac1",      XSPR(31,467,1012), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4351 {"mtiac2",      XSPR(31,467,1013), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4352 {"mtdac1",      XSPR(31,467,1014), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4353 {"mtdac2",      XSPR(31,467,1015), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4354 {"mtl2cr",      XSPR(31,467,1017), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4355 {"mtdccr",      XSPR(31,467,1018), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4356 {"mticcr",      XSPR(31,467,1019), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4357 {"mtictc",      XSPR(31,467,1019), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4358 {"mtpbl1",      XSPR(31,467,1020), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4359 {"mtthrm1",     XSPR(31,467,1020), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4360 {"mtpbu1",      XSPR(31,467,1021), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4361 {"mtthrm2",     XSPR(31,467,1021), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4362 {"mtpbl2",      XSPR(31,467,1022), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4363 {"mtthrm3",     XSPR(31,467,1022), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4364 {"mtpbu2",      XSPR(31,467,1023), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4365 {"mtspr",       X(31,467),        X_MASK,    COM,       PPCNONE,        {SPR, RS}},
4366
4367 {"dcbi",        X(31,470),      XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4368
4369 {"nand",        XRC(31,476,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4370 {"nand.",       XRC(31,476,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4371
4372 {"dsn",         X(31,483),      XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
4373
4374 {"dcread",      X(31,486),      X_MASK,  PPC403|PPC440, PPCA2|PPC476,   {RT, RA, RB}},
4375
4376 {"icbtls",      X(31,486),      X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,  {CT, RA, RB}},
4377
4378 {"stvxl",       X(31,487),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
4379
4380 {"nabs",        XO(31,488,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4381 {"nabs.",       XO(31,488,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4382
4383 {"divd",        XO(31,489,0,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4384 {"divd.",       XO(31,489,0,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4385
4386 {"divw",        XO(31,491,0,0), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4387 {"divw.",       XO(31,491,0,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4388
4389 {"icbtlse",     X(31,494),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
4390
4391 {"slbia",       X(31,498),      0xffffffff,  PPC64,     PPCNONE,        {0}},
4392
4393 {"cli",         X(31,502),      XRB_MASK,    POWER,     PPCNONE,        {RT, RA}},
4394
4395 {"popcntd",     X(31,506),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
4396
4397 {"cmpb",        X(31,508),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {RA, RS, RB}},
4398
4399 {"mcrxr",       X(31,512), XRARB_MASK|(3<<21), COM,     POWER7,         {BF}},
4400
4401 {"lbdx",        X(31,515),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4402
4403 {"bblels",      X(31,518),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
4404
4405 {"lvlx",        X(31,519),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4406 {"lbfcmux",     APU(31,519,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4407
4408 {"subfco",      XO(31,8,1,0),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4409 {"sfo",         XO(31,8,1,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4410 {"subco",       XO(31,8,1,0),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RB, RA}},
4411 {"subfco.",     XO(31,8,1,1),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4412 {"sfo.",        XO(31,8,1,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4413 {"subco.",      XO(31,8,1,1),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RB, RA}},
4414
4415 {"addco",       XO(31,10,1,0),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4416 {"ao",          XO(31,10,1,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4417 {"addco.",      XO(31,10,1,1),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4418 {"ao.",         XO(31,10,1,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4419
4420 {"clcs",        X(31,531),      XRB_MASK,    M601,      PPCNONE,        {RT, RA}},
4421
4422 {"ldbrx",       X(31,532),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RT, RA0, RB}},
4423
4424 {"lswx",        X(31,533),      X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
4425 {"lsx",         X(31,533),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4426
4427 {"lwbrx",       X(31,534),      X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
4428 {"lbrx",        X(31,534),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4429
4430 {"lfsx",        X(31,535),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
4431
4432 {"srw",         XRC(31,536,0),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4433 {"sr",          XRC(31,536,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4434 {"srw.",        XRC(31,536,1),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4435 {"sr.",         XRC(31,536,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4436
4437 {"rrib",        XRC(31,537,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4438 {"rrib.",       XRC(31,537,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4439
4440 {"srd",         XRC(31,539,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4441 {"srd.",        XRC(31,539,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4442
4443 {"maskir",      XRC(31,541,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4444 {"maskir.",     XRC(31,541,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4445
4446 {"lhdx",        X(31,547),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4447
4448 {"bbelr",       X(31,550),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
4449
4450 {"lvrx",        X(31,551),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4451 {"lhfcmux",     APU(31,551,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4452
4453 {"subfo",       XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4454 {"subo",        XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
4455 {"subfo.",      XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4456 {"subo.",       XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
4457
4458 {"tlbsync",     X(31,566),      0xffffffff,  PPC,       PPCNONE,        {0}},
4459
4460 {"lfsux",       X(31,567),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
4461
4462 {"lwdx",        X(31,579),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4463
4464 {"lwfcmux",     APU(31,583,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4465
4466 {"lxsdx",       X(31,588),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
4467
4468 {"mfsr",        X(31,595), XRB_MASK|(1<<20), COM32,     TITAN,          {RT, SR}},
4469
4470 {"lswi",        X(31,597),      X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, NB}},
4471 {"lsi",         X(31,597),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA0, NB}},
4472
4473 {"lwsync",      XSYNC(31,598,1), 0xffffffff, PPC,       E500,           {0}},
4474 {"ptesync",     XSYNC(31,598,2), 0xffffffff, PPC64,     PPCNONE,        {0}},
4475 {"sync",        X(31,598),      XSYNC_MASK,  PPCCOM,    BOOKE|PPC476,   {LS}},
4476 {"msync",       X(31,598),      0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
4477 {"sync",        X(31,598),      0xffffffff, BOOKE|PPC476, PPCNONE, {0}},
4478 {"lwsync",      X(31,598),      0xffffffff, E500,       PPCNONE,        {0}},
4479 {"dcs",         X(31,598),      0xffffffff,  PWRCOM,    PPCNONE,        {0}},
4480
4481 {"lfdx",        X(31,599),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
4482
4483 {"mffgpr",      XRC(31,607,0),  XRA_MASK,    POWER6,    POWER7,         {FRT, RB}},
4484 {"lfdepx",      X(31,607),      X_MASK,   E500MC|PPCA2, PPCNONE,        {FRT, RA, RB}},
4485
4486 {"lddx",        X(31,611),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4487
4488 {"lqfcmux",     APU(31,615,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4489
4490 {"nego",        XO(31,104,1,0), XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
4491 {"nego.",       XO(31,104,1,1), XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
4492
4493 {"mulo",        XO(31,107,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4494 {"mulo.",       XO(31,107,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4495
4496 {"mfsri",       X(31,627),      X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
4497
4498 {"dclst",       X(31,630),      XRB_MASK,    M601,      PPCNONE,        {RS, RA}},
4499
4500 {"lfdux",       X(31,631),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
4501
4502 {"stbdx",       X(31,643),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4503
4504 {"stvlx",       X(31,647),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4505 {"stbfcmux",    APU(31,647,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4506
4507 {"subfeo",      XO(31,136,1,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4508 {"sfeo",        XO(31,136,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4509 {"subfeo.",     XO(31,136,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4510 {"sfeo.",       XO(31,136,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4511
4512 {"addeo",       XO(31,138,1,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4513 {"aeo",         XO(31,138,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4514 {"addeo.",      XO(31,138,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4515 {"aeo.",        XO(31,138,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4516
4517 {"mfsrin",      X(31,659),      XRA_MASK,    PPC32,     TITAN,          {RT, RB}},
4518
4519 {"stdbrx",      X(31,660),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RS, RA0, RB}},
4520
4521 {"stswx",       X(31,661),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, RB}},
4522 {"stsx",        X(31,661),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
4523
4524 {"stwbrx",      X(31,662),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, RB}},
4525 {"stbrx",       X(31,662),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
4526
4527 {"stfsx",       X(31,663),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
4528
4529 {"srq",         XRC(31,664,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4530 {"srq.",        XRC(31,664,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4531
4532 {"sre",         XRC(31,665,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4533 {"sre.",        XRC(31,665,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4534
4535 {"sthdx",       X(31,675),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4536
4537 {"stvrx",       X(31,679),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4538 {"sthfcmux",    APU(31,679,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4539
4540 {"stbcx.",      XRC(31,694,1),  X_MASK,      POWER7,    PPCNONE,        {RS, RA0, RB}},
4541
4542 {"stfsux",      X(31,695),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
4543
4544 {"sriq",        XRC(31,696,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4545 {"sriq.",       XRC(31,696,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4546
4547 {"stwdx",       X(31,707),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4548
4549 {"stwfcmux",    APU(31,711,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4550
4551 {"stxsdx",      X(31,716),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
4552
4553 {"subfzeo",     XO(31,200,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4554 {"sfzeo",       XO(31,200,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4555 {"subfzeo.",    XO(31,200,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4556 {"sfzeo.",      XO(31,200,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4557
4558 {"addzeo",      XO(31,202,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4559 {"azeo",        XO(31,202,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4560 {"addzeo.",     XO(31,202,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4561 {"azeo.",       XO(31,202,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4562
4563 {"stswi",       X(31,725),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, NB}},
4564 {"stsi",        X(31,725),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, NB}},
4565
4566 {"sthcx.",      XRC(31,726,1),  X_MASK,      POWER7,    PPCNONE,        {RS, RA0, RB}},
4567
4568 {"stfdx",       X(31,727),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
4569
4570 {"srlq",        XRC(31,728,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4571 {"srlq.",       XRC(31,728,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4572
4573 {"sreq",        XRC(31,729,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4574 {"sreq.",       XRC(31,729,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4575
4576 {"mftgpr",      XRC(31,735,0),  XRA_MASK,    POWER6,    POWER7,         {RT, FRB}},
4577 {"stfdepx",     X(31,735),      X_MASK,   E500MC|PPCA2, PPCNONE,        {FRS, RA, RB}},
4578
4579 {"stddx",       X(31,739),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4580
4581 {"stqfcmux",    APU(31,743,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4582
4583 {"subfmeo",     XO(31,232,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4584 {"sfmeo",       XO(31,232,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4585 {"subfmeo.",    XO(31,232,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4586 {"sfmeo.",      XO(31,232,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4587
4588 {"mulldo",      XO(31,233,1,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4589 {"mulldo.",     XO(31,233,1,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4590
4591 {"addmeo",      XO(31,234,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4592 {"ameo",        XO(31,234,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4593 {"addmeo.",     XO(31,234,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4594 {"ameo.",       XO(31,234,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4595
4596 {"mullwo",      XO(31,235,1,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4597 {"mulso",       XO(31,235,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4598 {"mullwo.",     XO(31,235,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4599 {"mulso.",      XO(31,235,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4600
4601 {"dcba",        X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
4602 {"dcbal",       XOPL(31,758,1), XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
4603
4604 {"stfdux",      X(31,759),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
4605
4606 {"srliq",       XRC(31,760,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4607 {"srliq.",      XRC(31,760,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4608
4609 {"lvlxl",       X(31,775),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4610 {"ldfcmux",     APU(31,775,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4611
4612 {"dozo",        XO(31,264,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4613 {"dozo.",       XO(31,264,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4614
4615 {"addo",        XO(31,266,1,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4616 {"caxo",        XO(31,266,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4617 {"addo.",       XO(31,266,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4618 {"caxo.",       XO(31,266,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4619
4620 {"lxvw4x",      X(31,780),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
4621
4622 {"tlbivax",     X(31,786),      XRT_MASK,  BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
4623
4624 {"lwzcix",      X(31,789),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4625
4626 {"lhbrx",       X(31,790),      X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
4627
4628 {"lfdpx",       X(31,791),      X_MASK,      POWER6,    POWER7,         {FRT, RA, RB}},
4629 {"lfqx",        X(31,791),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
4630
4631 {"sraw",        XRC(31,792,0),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4632 {"sra",         XRC(31,792,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4633 {"sraw.",       XRC(31,792,1),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4634 {"sra.",        XRC(31,792,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4635
4636 {"srad",        XRC(31,794,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4637 {"srad.",       XRC(31,794,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4638
4639 {"lfddx",       X(31,803),      X_MASK,      E500MC,    PPCNONE,        {FRT, RA, RB}},
4640
4641 {"lvrxl",       X(31,807),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4642
4643 {"rac",         X(31,818),      X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
4644
4645 {"erativax",    X(31,819),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA0, RB}},
4646
4647 {"lhzcix",      X(31,821),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4648
4649 {"dss",         XDSS(31,822,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {STRM}},
4650
4651 {"lfqux",       X(31,823),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
4652
4653 {"srawi",       XRC(31,824,0),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH}},
4654 {"srai",        XRC(31,824,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
4655 {"srawi.",      XRC(31,824,1),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH}},
4656 {"srai.",       XRC(31,824,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
4657
4658 {"sradi",       XS(31,413,0),   XS_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6}},
4659 {"sradi.",      XS(31,413,1),   XS_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6}},
4660
4661 {"divo",        XO(31,331,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4662 {"divo.",       XO(31,331,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4663
4664 {"lxvd2x",      X(31,844),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
4665
4666 {"tlbsrx.",     XRC(31,850,1),  XRT_MASK,    PPCA2,     PPCNONE,        {RA, RB}},
4667
4668 {"slbmfev",     X(31,851),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
4669
4670 {"lbzcix",      X(31,853),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4671
4672 {"eieio",       X(31,854),      0xffffffff,  PPC,   BOOKE|PPCA2|PPC476, {0}},
4673 {"mbar",        X(31,854),      X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,    {MO}},
4674 {"eieio",       XMBAR(31,854,1),0xffffffff,  E500,   PPCNONE,   {0}},
4675 {"eieio",       X(31,854),      0xffffffff, PPCA2|PPC476, PPCNONE,      {0}},
4676
4677 {"lfiwax",      X(31,855),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, RA0, RB}},
4678
4679 {"abso",        XO(31,360,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4680 {"abso.",       XO(31,360,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4681
4682 {"divso",       XO(31,363,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4683 {"divso.",      XO(31,363,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4684
4685 {"ldcix",       X(31,885),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4686
4687 {"lfiwzx",      X(31,887),      X_MASK,   POWER7|PPCA2, PPCNONE,        {FRT, RA0, RB}},
4688
4689 {"stvlxl",      X(31,903),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4690 {"stdfcmux",    APU(31,903,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4691
4692 {"divdeuo",     XO(31,393,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4693 {"divdeuo.",    XO(31,393,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4694 {"divweuo",     XO(31,395,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4695 {"divweuo.",    XO(31,395,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4696
4697 {"stxvw4x",     X(31,908),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
4698
4699 {"tlbsx",       XRC(31,914,0),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
4700 {"tlbsx.",      XRC(31,914,1),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
4701
4702 {"slbmfee",     X(31,915),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
4703
4704 {"stwcix",      X(31,917),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4705
4706 {"sthbrx",      X(31,918),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
4707
4708 {"stfdpx",      X(31,919),      X_MASK,      POWER6,    PPCNONE,        {FRS, RA, RB}},
4709 {"stfqx",       X(31,919),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA, RB}},
4710
4711 {"sraq",        XRC(31,920,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4712 {"sraq.",       XRC(31,920,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4713
4714 {"srea",        XRC(31,921,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4715 {"srea.",       XRC(31,921,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4716
4717 {"extsh",       XRC(31,922,0),  XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
4718 {"exts",        XRC(31,922,0),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4719 {"extsh.",      XRC(31,922,1),  XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
4720 {"exts.",       XRC(31,922,1),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4721
4722 {"stfddx",      X(31,931),      X_MASK,      E500MC,    PPCNONE,        {FRS, RA, RB}},
4723
4724 {"wclrone",     XOPL2(31,934,2),XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
4725 {"wclrall",     X(31,934),      XRARB_MASK,  PPCA2,     PPCNONE,        {L}},
4726 {"wclr",        X(31,934),      X_MASK,      PPCA2,     PPCNONE,        {L, RA0, RB}},
4727
4728 {"stvrxl",      X(31,935),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4729
4730 {"divdeo",      XO(31,425,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4731 {"divdeo.",     XO(31,425,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4732 {"divweo",      XO(31,427,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4733 {"divweo.",     XO(31,427,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4734
4735 {"tlbrehi",     XTLB(31,946,0), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
4736 {"tlbrelo",     XTLB(31,946,1), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
4737 {"tlbre",       X(31,946),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
4738
4739 {"sthcix",      X(31,949),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4740
4741 {"icswepx",     XRC(31,950,0),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
4742 {"icswepx.",    XRC(31,950,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
4743
4744 {"stfqux",      X(31,951),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA, RB}},
4745
4746 {"sraiq",       XRC(31,952,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4747 {"sraiq.",      XRC(31,952,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4748
4749 {"extsb",       XRC(31,954,0),  XRB_MASK,    PPC,       PPCNONE,        {RA, RS}},
4750 {"extsb.",      XRC(31,954,1),  XRB_MASK,    PPC,       PPCNONE,        {RA, RS}},
4751
4752 {"iccci",       X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
4753 {"ici",         X(31,966),      XRARB_MASK,  PPCA2|PPC476, PPCNONE,     {CT}},
4754
4755 {"divduo",      XO(31,457,1,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4756 {"divduo.",     XO(31,457,1,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4757
4758 {"divwuo",      XO(31,459,1,0), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4759 {"divwuo.",     XO(31,459,1,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4760
4761 {"stxvd2x",     X(31,972),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
4762
4763 {"tlbld",       X(31,978),      XRTRA_MASK,  PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
4764 {"tlbwehi",     XTLB(31,978,0), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
4765 {"tlbwelo",     XTLB(31,978,1), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
4766 {"tlbwe",       X(31,978),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
4767
4768 {"stbcix",      X(31,981),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4769
4770 {"icbi",        X(31,982),      XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4771
4772 {"stfiwx",      X(31,983),      X_MASK,      PPC,       PPCEFS,         {FRS, RA0, RB}},
4773
4774 {"extsw",       XRC(31,986,0),  XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
4775 {"extsw.",      XRC(31,986,1),  XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
4776
4777 {"icbiep",      XRT(31,991,0),  XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
4778
4779 {"icread",      X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, PPCNONE, {RA, RB}},
4780
4781 {"nabso",       XO(31,488,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4782 {"nabso.",      XO(31,488,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4783
4784 {"divdo",       XO(31,489,1,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4785 {"divdo.",      XO(31,489,1,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4786
4787 {"divwo",       XO(31,491,1,0), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4788 {"divwo.",      XO(31,491,1,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4789
4790 {"tlbli",       X(31,1010),     XRTRA_MASK,  PPC,       TITAN,          {RB}},
4791
4792 {"stdcix",      X(31,1013),     X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4793
4794 {"dcbz",        X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4795 {"dclz",        X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4796
4797 {"dcbzep",      XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
4798
4799 {"dcbzl",       XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476,       {RA, RB}},
4800
4801 {"cctpl",       0x7c210b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4802 {"cctpm",       0x7c421378,     0xffffffff,  CELL,      PPCNONE,        {0}},
4803 {"cctph",       0x7c631b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4804
4805 {"dstt",        XDSS(31,342,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4806 {"dststt",      XDSS(31,374,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4807 {"dssall",      XDSS(31,822,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {0}},
4808
4809 {"db8cyc",      0x7f9ce378,     0xffffffff,  CELL,      PPCNONE,        {0}},
4810 {"db10cyc",     0x7fbdeb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4811 {"db12cyc",     0x7fdef378,     0xffffffff,  CELL,      PPCNONE,        {0}},
4812 {"db16cyc",     0x7ffffb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4813
4814 {"lwz",         OP(32),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
4815 {"l",           OP(32),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
4816
4817 {"lwzu",        OP(33),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAL}},
4818 {"lu",          OP(33),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
4819
4820 {"lbz",         OP(34),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
4821
4822 {"lbzu",        OP(35),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
4823
4824 {"stw",         OP(36),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
4825 {"st",          OP(36),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
4826
4827 {"stwu",        OP(37),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RAS}},
4828 {"stu",         OP(37),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
4829
4830 {"stb",         OP(38),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
4831
4832 {"stbu",        OP(39),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
4833
4834 {"lhz",         OP(40),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
4835
4836 {"lhzu",        OP(41),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
4837
4838 {"lha",         OP(42),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
4839
4840 {"lhau",        OP(43),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
4841
4842 {"sth",         OP(44),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
4843
4844 {"sthu",        OP(45),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
4845
4846 {"lmw",         OP(46),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAM}},
4847 {"lm",          OP(46),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
4848
4849 {"stmw",        OP(47),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
4850 {"stm",         OP(47),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
4851
4852 {"lfs",         OP(48),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RA0}},
4853
4854 {"lfsu",        OP(49),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RAS}},
4855
4856 {"lfd",         OP(50),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RA0}},
4857
4858 {"lfdu",        OP(51),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RAS}},
4859
4860 {"stfs",        OP(52),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RA0}},
4861
4862 {"stfsu",       OP(53),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RAS}},
4863
4864 {"stfd",        OP(54),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RA0}},
4865
4866 {"stfdu",       OP(55),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RAS}},
4867
4868 {"lq",          OP(56),         OP_MASK,     POWER4,    PPC476,         {RTQ, DQ, RAQ}},
4869 {"psq_l",       OP(56),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
4870 {"lfq",         OP(56),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
4871
4872 {"lfdp",        OP(57),         OP_MASK,     POWER6,    POWER7,         {FRT, D, RA0}},
4873 {"psq_lu",      OP(57),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
4874 {"lfqu",        OP(57),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
4875
4876 {"ld",          DSO(58,0),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
4877 {"ldu",         DSO(58,1),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RAL}},
4878 {"lwa",         DSO(58,2),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
4879
4880 {"dadd",        XRC(59,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4881 {"dadd.",       XRC(59,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4882
4883 {"dqua",        ZRC(59,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
4884 {"dqua.",       ZRC(59,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
4885
4886 {"fdivs",       A(59,18,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
4887 {"fdivs.",      A(59,18,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
4888
4889 {"fsubs",       A(59,20,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
4890 {"fsubs.",      A(59,20,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
4891
4892 {"fadds",       A(59,21,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
4893 {"fadds.",      A(59,21,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
4894
4895 {"fsqrts",      A(59,22,0),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
4896 {"fsqrts.",     A(59,22,1),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
4897
4898 {"fres",        A(59,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
4899 {"fres",        A(59,24,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
4900 {"fres.",       A(59,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
4901 {"fres.",       A(59,24,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
4902
4903 {"fmuls",       A(59,25,0),     AFRB_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRC}},
4904 {"fmuls.",      A(59,25,1),     AFRB_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRC}},
4905
4906 {"frsqrtes",    A(59,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
4907 {"frsqrtes",    A(59,26,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
4908 {"frsqrtes.",   A(59,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
4909 {"frsqrtes.",   A(59,26,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
4910
4911 {"fmsubs",      A(59,28,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4912 {"fmsubs.",     A(59,28,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4913
4914 {"fmadds",      A(59,29,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4915 {"fmadds.",     A(59,29,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4916
4917 {"fnmsubs",     A(59,30,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4918 {"fnmsubs.",    A(59,30,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4919
4920 {"fnmadds",     A(59,31,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4921 {"fnmadds.",    A(59,31,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
4922
4923 {"dmul",        XRC(59,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4924 {"dmul.",       XRC(59,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4925
4926 {"drrnd",       ZRC(59,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
4927 {"drrnd.",      ZRC(59,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
4928
4929 {"dscli",       ZRC(59,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
4930 {"dscli.",      ZRC(59,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
4931
4932 {"dquai",       ZRC(59,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
4933 {"dquai.",      ZRC(59,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
4934
4935 {"dscri",       ZRC(59,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
4936 {"dscri.",      ZRC(59,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
4937
4938 {"drintx",      ZRC(59,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
4939 {"drintx.",     ZRC(59,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
4940
4941 {"dcmpo",       X(59,130),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
4942
4943 {"dtstex",      X(59,162),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
4944 {"dtstdc",      Z(59,194),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DCM}},
4945 {"dtstdg",      Z(59,226),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DGM}},
4946
4947 {"drintn",      ZRC(59,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
4948 {"drintn.",     ZRC(59,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
4949
4950 {"dctdp",       XRC(59,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4951 {"dctdp.",      XRC(59,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4952
4953 {"dctfix",      XRC(59,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4954 {"dctfix.",     XRC(59,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4955
4956 {"ddedpd",      XRC(59,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
4957 {"ddedpd.",     XRC(59,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
4958
4959 {"dxex",        XRC(59,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4960 {"dxex.",       XRC(59,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4961
4962 {"dsub",        XRC(59,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4963 {"dsub.",       XRC(59,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4964
4965 {"ddiv",        XRC(59,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4966 {"ddiv.",       XRC(59,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4967
4968 {"dcmpu",       X(59,642),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
4969
4970 {"dtstsf",      X(59,674),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
4971
4972 {"drsp",        XRC(59,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4973 {"drsp.",       XRC(59,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4974
4975 {"dcffix",      XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
4976 {"dcffix.",     XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
4977
4978 {"denbcd",      XRC(59,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
4979 {"denbcd.",     XRC(59,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
4980
4981 {"fcfids",      XRC(59,846,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
4982 {"fcfids.",     XRC(59,846,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
4983
4984 {"diex",        XRC(59,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4985 {"diex.",       XRC(59,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4986
4987 {"fcfidus",     XRC(59,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
4988 {"fcfidus.",    XRC(59,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
4989
4990 {"xxsldwi",     XX3(60,2),      XX3SHW_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6, SHW}},
4991 {"xxsel",       XX4(60,3),      XX4_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6, XC6}},
4992 {"xxspltd",     XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6S, DMEX}},
4993 {"xxmrghd",     XX3(60,10),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4994 {"xxswapd",     XX3(60,10)|(2<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
4995 {"xxmrgld",     XX3(60,10)|(3<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4996 {"xxpermdi",    XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6, DM}},
4997 {"xxmrghw",     XX3(60,18),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4998 {"xsadddp",     XX3(60,32),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4999 {"xsmaddadp",   XX3(60,33),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5000 {"xscmpudp",    XX3(60,35),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5001 {"xssubdp",     XX3(60,40),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5002 {"xsmaddmdp",   XX3(60,41),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5003 {"xscmpodp",    XX3(60,43),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5004 {"xsmuldp",     XX3(60,48),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5005 {"xsmsubadp",   XX3(60,49),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5006 {"xxmrglw",     XX3(60,50),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5007 {"xsdivdp",     XX3(60,56),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5008 {"xsmsubmdp",   XX3(60,57),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5009 {"xstdivdp",    XX3(60,61),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5010 {"xvaddsp",     XX3(60,64),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5011 {"xvmaddasp",   XX3(60,65),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5012 {"xvcmpeqsp",   XX3RC(60,67,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5013 {"xvcmpeqsp.",  XX3RC(60,67,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5014 {"xvsubsp",     XX3(60,72),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5015 {"xscvdpuxws",  XX2(60,72),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5016 {"xvmaddmsp",   XX3(60,73),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5017 {"xsrdpi",      XX2(60,73),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5018 {"xsrsqrtedp",  XX2(60,74),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5019 {"xssqrtdp",    XX2(60,75),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5020 {"xvcmpgtsp",   XX3RC(60,75,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5021 {"xvcmpgtsp.",  XX3RC(60,75,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5022 {"xvmulsp",     XX3(60,80),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5023 {"xvmsubasp",   XX3(60,81),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5024 {"xvcmpgesp",   XX3RC(60,83,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5025 {"xvcmpgesp.",  XX3RC(60,83,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5026 {"xvdivsp",     XX3(60,88),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5027 {"xscvdpsxws",  XX2(60,88),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5028 {"xvmsubmsp",   XX3(60,89),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5029 {"xsrdpiz",     XX2(60,89),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5030 {"xsredp",      XX2(60,90),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5031 {"xvtdivsp",    XX3(60,93),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5032 {"xvadddp",     XX3(60,96),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5033 {"xvmaddadp",   XX3(60,97),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5034 {"xvcmpeqdp",   XX3RC(60,99,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5035 {"xvcmpeqdp.",  XX3RC(60,99,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5036 {"xvsubdp",     XX3(60,104),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5037 {"xvmaddmdp",   XX3(60,105),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5038 {"xsrdpip",     XX2(60,105),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5039 {"xstsqrtdp",   XX2(60,106),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5040 {"xsrdpic",     XX2(60,107),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5041 {"xvcmpgtdp",   XX3RC(60,107,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5042 {"xvcmpgtdp.",  XX3RC(60,107,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5043 {"xvmuldp",     XX3(60,112),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5044 {"xvmsubadp",   XX3(60,113),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5045 {"xvcmpgedp",   XX3RC(60,115,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5046 {"xvcmpgedp.",  XX3RC(60,115,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5047 {"xvdivdp",     XX3(60,120),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5048 {"xvmsubmdp",   XX3(60,121),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5049 {"xsrdpim",     XX2(60,121),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5050 {"xvtdivdp",    XX3(60,125),    XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5051 {"xxland",      XX3(60,130),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5052 {"xvcvspuxws",  XX2(60,136),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5053 {"xvrspi",      XX2(60,137),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5054 {"xxlandc",     XX3(60,138),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5055 {"xvrsqrtesp",  XX2(60,138),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5056 {"xvsqrtsp",    XX2(60,139),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5057 {"xxlor",       XX3(60,146),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5058 {"xvcvspsxws",  XX2(60,152),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5059 {"xvrspiz",     XX2(60,153),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5060 {"xxlxor",      XX3(60,154),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5061 {"xvresp",      XX2(60,154),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5062 {"xsmaxdp",     XX3(60,160),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5063 {"xsnmaddadp",  XX3(60,161),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5064 {"xxlnor",      XX3(60,162),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5065 {"xxspltw",     XX2(60,164),    XX2UIM_MASK, PPCVSX,    PPCNONE,        {XT6, XB6, UIM}},
5066 {"xsmindp",     XX3(60,168),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5067 {"xvcvuxwsp",   XX2(60,168),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5068 {"xsnmaddmdp",  XX3(60,169),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5069 {"xvrspip",     XX2(60,169),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5070 {"xvtsqrtsp",   XX2(60,170),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5071 {"xvrspic",     XX2(60,171),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5072 {"xscpsgndp",   XX3(60,176),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5073 {"xsnmsubadp",  XX3(60,177),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5074 {"xvcvsxwsp",   XX2(60,184),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5075 {"xsnmsubmdp",  XX3(60,185),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5076 {"xvrspim",     XX2(60,185),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5077 {"xvmaxsp",     XX3(60,192),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5078 {"xvnmaddasp",  XX3(60,193),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5079 {"xvminsp",     XX3(60,200),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5080 {"xvcvdpuxws",  XX2(60,200),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5081 {"xvnmaddmsp",  XX3(60,201),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5082 {"xvrdpi",      XX2(60,201),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5083 {"xvrsqrtedp",  XX2(60,202),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5084 {"xvsqrtdp",    XX2(60,203),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5085 {"xvmovsp",     XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
5086 {"xvcpsgnsp",   XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5087 {"xvnmsubasp",  XX3(60,209),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5088 {"xvcvdpsxws",  XX2(60,216),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5089 {"xvnmsubmsp",  XX3(60,217),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5090 {"xvrdpiz",     XX2(60,217),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5091 {"xvredp",      XX2(60,218),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5092 {"xvmaxdp",     XX3(60,224),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5093 {"xvnmaddadp",  XX3(60,225),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5094 {"xvmindp",     XX3(60,232),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5095 {"xvnmaddmdp",  XX3(60,233),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5096 {"xvcvuxwdp",   XX2(60,232),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5097 {"xvrdpip",     XX2(60,233),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5098 {"xvtsqrtdp",   XX2(60,234),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5099 {"xvrdpic",     XX2(60,235),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5100 {"xvmovdp",     XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
5101 {"xvcpsgndp",   XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5102 {"xvnmsubadp",  XX3(60,241),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5103 {"xvcvsxwdp",   XX2(60,248),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5104 {"xvnmsubmdp",  XX3(60,249),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5105 {"xvrdpim",     XX2(60,249),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5106 {"xscvdpsp",    XX2(60,265),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5107 {"xscvdpuxds",  XX2(60,328),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5108 {"xscvspdp",    XX2(60,329),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5109 {"xscvdpsxds",  XX2(60,344),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5110 {"xsabsdp",     XX2(60,345),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5111 {"xscvuxddp",   XX2(60,360),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5112 {"xsnabsdp",    XX2(60,361),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5113 {"xscvsxddp",   XX2(60,376),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5114 {"xsnegdp",     XX2(60,377),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5115 {"xvcvspuxds",  XX2(60,392),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5116 {"xvcvdpsp",    XX2(60,393),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5117 {"xvcvspsxds",  XX2(60,408),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5118 {"xvabssp",     XX2(60,409),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5119 {"xvcvuxdsp",   XX2(60,424),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5120 {"xvnabssp",    XX2(60,425),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5121 {"xvcvsxdsp",   XX2(60,440),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5122 {"xvnegsp",     XX2(60,441),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5123 {"xvcvdpuxds",  XX2(60,456),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5124 {"xvcvspdp",    XX2(60,457),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5125 {"xvcvdpsxds",  XX2(60,472),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5126 {"xvabsdp",     XX2(60,473),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5127 {"xvcvuxddp",   XX2(60,488),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5128 {"xvnabsdp",    XX2(60,489),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5129 {"xvcvsxddp",   XX2(60,504),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5130 {"xvnegdp",     XX2(60,505),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5131
5132 {"psq_st",      OP(60),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
5133 {"stfq",        OP(60),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
5134
5135 {"stfdp",       OP(61),         OP_MASK,     POWER6,    PPCNONE,        {FRT, D, RA0}},
5136 {"psq_stu",     OP(61),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
5137 {"stfqu",       OP(61),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
5138
5139 {"std",         DSO(62,0),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RA0}},
5140 {"stdu",        DSO(62,1),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RAS}},
5141 {"stq",         DSO(62,2),      DS_MASK,     POWER4,    PPC476,         {RSQ, DS, RA0}},
5142
5143 {"fcmpu",       X(63,0),     X_MASK|(3<<21), COM,       PPCEFS,         {BF, FRA, FRB}},
5144
5145 {"daddq",       XRC(63,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5146 {"daddq.",      XRC(63,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5147
5148 {"dquaq",       ZRC(63,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5149 {"dquaq.",      ZRC(63,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5150
5151 {"fcpsgn",      XRC(63,8,0),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
5152 {"fcpsgn.",     XRC(63,8,1),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
5153
5154 {"frsp",        XRC(63,12,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5155 {"frsp.",       XRC(63,12,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5156
5157 {"fctiw",       XRC(63,14,0),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5158 {"fcir",        XRC(63,14,0),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5159 {"fctiw.",      XRC(63,14,1),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5160 {"fcir.",       XRC(63,14,1),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5161
5162 {"fctiwz",      XRC(63,15,0),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5163 {"fcirz",       XRC(63,15,0),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5164 {"fctiwz.",     XRC(63,15,1),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5165 {"fcirz.",      XRC(63,15,1),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5166
5167 {"fdiv",        A(63,18,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5168 {"fd",          A(63,18,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5169 {"fdiv.",       A(63,18,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5170 {"fd.",         A(63,18,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5171
5172 {"fsub",        A(63,20,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5173 {"fs",          A(63,20,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5174 {"fsub.",       A(63,20,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5175 {"fs.",         A(63,20,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5176
5177 {"fadd",        A(63,21,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5178 {"fa",          A(63,21,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5179 {"fadd.",       A(63,21,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
5180 {"fa.",         A(63,21,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5181
5182 {"fsqrt",       A(63,22,0),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
5183 {"fsqrt.",      A(63,22,1),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
5184
5185 {"fsel",        A(63,23,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5186 {"fsel.",       A(63,23,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5187
5188 {"fre",         A(63,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5189 {"fre",         A(63,24,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
5190 {"fre.",        A(63,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5191 {"fre.",        A(63,24,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
5192
5193 {"fmul",        A(63,25,0),     AFRB_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRC}},
5194 {"fm",          A(63,25,0),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
5195 {"fmul.",       A(63,25,1),     AFRB_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRC}},
5196 {"fm.",         A(63,25,1),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
5197
5198 {"frsqrte",     A(63,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5199 {"frsqrte",     A(63,26,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
5200 {"frsqrte.",    A(63,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5201 {"frsqrte.",    A(63,26,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
5202
5203 {"fmsub",       A(63,28,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5204 {"fms",         A(63,28,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5205 {"fmsub.",      A(63,28,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5206 {"fms.",        A(63,28,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5207
5208 {"fmadd",       A(63,29,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5209 {"fma",         A(63,29,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5210 {"fmadd.",      A(63,29,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5211 {"fma.",        A(63,29,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5212
5213 {"fnmsub",      A(63,30,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5214 {"fnms",        A(63,30,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5215 {"fnmsub.",     A(63,30,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5216 {"fnms.",       A(63,30,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5217
5218 {"fnmadd",      A(63,31,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5219 {"fnma",        A(63,31,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5220 {"fnmadd.",     A(63,31,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
5221 {"fnma.",       A(63,31,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5222
5223 {"fcmpo",       X(63,32),    X_MASK|(3<<21), COM,       PPCEFS,         {BF, FRA, FRB}},
5224
5225 {"dmulq",       XRC(63,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5226 {"dmulq.",      XRC(63,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5227
5228 {"drrndq",      ZRC(63,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5229 {"drrndq.",     ZRC(63,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5230
5231 {"mtfsb1",      XRC(63,38,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
5232 {"mtfsb1.",     XRC(63,38,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
5233
5234 {"fneg",        XRC(63,40,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5235 {"fneg.",       XRC(63,40,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5236
5237 {"mcrfs",      X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE,        {BF, BFA}},
5238
5239 {"dscliq",      ZRC(63,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5240 {"dscliq.",     ZRC(63,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5241
5242 {"dquaiq",      ZRC(63,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT, FRB, RMC}},
5243 {"dquaiq.",     ZRC(63,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT, FRB, RMC}},
5244
5245 {"mtfsb0",      XRC(63,70,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
5246 {"mtfsb0.",     XRC(63,70,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
5247
5248 {"fmr",         XRC(63,72,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5249 {"fmr.",        XRC(63,72,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5250
5251 {"dscriq",      ZRC(63,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5252 {"dscriq.",     ZRC(63,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5253
5254 {"drintxq",     ZRC(63,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5255 {"drintxq.",    ZRC(63,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5256
5257 {"ftdiv",       X(63,128),   X_MASK|(3<<21), POWER7,    PPCNONE,        {BF, FRA, FRB}},
5258
5259 {"dcmpoq",      X(63,130),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
5260
5261 {"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
5262 {"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
5263 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
5264 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
5265
5266 {"fnabs",       XRC(63,136,0),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5267 {"fnabs.",      XRC(63,136,1),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5268
5269 {"fctiwu",      XRC(63,142,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5270 {"fctiwu.",     XRC(63,142,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5271 {"fctiwuz",     XRC(63,143,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5272 {"fctiwuz.",    XRC(63,143,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5273
5274 {"ftsqrt",      X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE,    {BF, FRB}},
5275
5276 {"dtstexq",     X(63,162),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
5277 {"dtstdcq",     Z(63,194),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRA, DCM}},
5278 {"dtstdgq",     Z(63,226),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRA, DGM}},
5279
5280 {"drintnq",     ZRC(63,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5281 {"drintnq.",    ZRC(63,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5282
5283 {"dctqpq",      XRC(63,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5284 {"dctqpq.",     XRC(63,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5285
5286 {"fabs",        XRC(63,264,0),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5287 {"fabs.",       XRC(63,264,1),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5288
5289 {"dctfixq",     XRC(63,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5290 {"dctfixq.",    XRC(63,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5291
5292 {"ddedpdq",     XRC(63,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
5293 {"ddedpdq.",    XRC(63,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
5294
5295 {"dxexq",       XRC(63,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5296 {"dxexq.",      XRC(63,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5297
5298 {"frin",        XRC(63,392,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5299 {"frin.",       XRC(63,392,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5300 {"friz",        XRC(63,424,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5301 {"friz.",       XRC(63,424,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5302 {"frip",        XRC(63,456,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5303 {"frip.",       XRC(63,456,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5304 {"frim",        XRC(63,488,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5305 {"frim.",       XRC(63,488,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5306
5307 {"dsubq",       XRC(63,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5308 {"dsubq.",      XRC(63,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5309
5310 {"ddivq",       XRC(63,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5311 {"ddivq.",      XRC(63,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5312
5313 {"mffs",        XRC(63,583,0),  XRARB_MASK,  COM,       PPCEFS,         {FRT}},
5314 {"mffs.",       XRC(63,583,1),  XRARB_MASK,  COM,       PPCEFS,         {FRT}},
5315
5316 {"dcmpuq",      X(63,642),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
5317
5318 {"dtstsfq",     X(63,674),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
5319
5320 {"mtfsf",       XFL(63,711,0),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
5321 {"mtfsf",       XFL(63,711,0),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS,   {FLM, FRB}},
5322 {"mtfsf.",      XFL(63,711,1),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
5323 {"mtfsf.",      XFL(63,711,1),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS,   {FLM, FRB}},
5324
5325 {"drdpq",       XRC(63,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5326 {"drdpq.",      XRC(63,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5327
5328 {"dcffixq",     XRC(63,802,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5329 {"dcffixq.",    XRC(63,802,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5330
5331 {"fctid",       XRC(63,814,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5332 {"fctid",       XRC(63,814,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5333 {"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5334 {"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5335
5336 {"fctidz",      XRC(63,815,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5337 {"fctidz",      XRC(63,815,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5338 {"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5339 {"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5340
5341 {"denbcdq",     XRC(63,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
5342 {"denbcdq.",    XRC(63,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
5343
5344 {"fcfid",       XRC(63,846,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5345 {"fcfid",       XRC(63,846,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5346 {"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5347 {"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5348
5349 {"diexq",       XRC(63,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5350 {"diexq.",      XRC(63,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5351
5352 {"fctidu",      XRC(63,942,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5353 {"fctidu.",     XRC(63,942,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5354
5355 {"fctiduz",     XRC(63,943,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5356 {"fctiduz.",    XRC(63,943,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5357
5358 {"fcfidu",      XRC(63,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5359 {"fcfidu.",     XRC(63,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5360 };
5361
5362 const int powerpc_num_opcodes =
5363   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
5364 \f
5365 /* The macro table.  This is only used by the assembler.  */
5366
5367 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
5368    when x=0; 32-x when x is between 1 and 31; are negative if x is
5369    negative; and are 32 or more otherwise.  This is what you want
5370    when, for instance, you are emulating a right shift by a
5371    rotate-left-and-mask, because the underlying instructions support
5372    shifts of size 0 but not shifts of size 32.  By comparison, when
5373    extracting x bits from some word you want to use just 32-x, because
5374    the underlying instructions don't support extracting 0 bits but do
5375    support extracting the whole word (32 bits in this case).  */
5376
5377 const struct powerpc_macro powerpc_macros[] = {
5378 {"extldi",   4, PPC64,  "rldicr %0,%1,%3,(%2)-1"},
5379 {"extldi.",  4, PPC64,  "rldicr. %0,%1,%3,(%2)-1"},
5380 {"extrdi",   4, PPC64,  "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
5381 {"extrdi.",  4, PPC64,  "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
5382 {"insrdi",   4, PPC64,  "rldimi %0,%1,64-((%2)+(%3)),%3"},
5383 {"insrdi.",  4, PPC64,  "rldimi. %0,%1,64-((%2)+(%3)),%3"},
5384 {"rotrdi",   3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
5385 {"rotrdi.",  3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
5386 {"sldi",     3, PPC64,  "rldicr %0,%1,%2,63-(%2)"},
5387 {"sldi.",    3, PPC64,  "rldicr. %0,%1,%2,63-(%2)"},
5388 {"srdi",     3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
5389 {"srdi.",    3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
5390 {"clrrdi",   3, PPC64,  "rldicr %0,%1,0,63-(%2)"},
5391 {"clrrdi.",  3, PPC64,  "rldicr. %0,%1,0,63-(%2)"},
5392 {"clrlsldi", 4, PPC64,  "rldic %0,%1,%3,(%2)-(%3)"},
5393 {"clrlsldi.",4, PPC64,  "rldic. %0,%1,%3,(%2)-(%3)"},
5394
5395 {"extlwi",   4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
5396 {"extlwi.",  4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
5397 {"extrwi",   4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5398 {"extrwi.",  4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5399 {"inslwi",   4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5400 {"inslwi.",  4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5401 {"insrwi",   4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5402 {"insrwi.",  4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5403 {"rotrwi",   3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5404 {"rotrwi.",  3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5405 {"slwi",     3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
5406 {"sli",      3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
5407 {"slwi.",    3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
5408 {"sli.",     3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
5409 {"srwi",     3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5410 {"sri",      3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5411 {"srwi.",    3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5412 {"sri.",     3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5413 {"clrrwi",   3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
5414 {"clrrwi.",  3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
5415 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
5416 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
5417 };
5418
5419 const int powerpc_num_macros =
5420   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);