opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004
   3    Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6    This file is part of GDB, GAS, and the GNU binutils.
   7
   8    GDB, GAS, and the GNU binutils are free software; you can redistribute
   9    them and/or modify them under the terms of the GNU General Public
  10    License as published by the Free Software Foundation; either version
  11    2, or (at your option) any later version.
  12
  13    GDB, GAS, and the GNU binutils are distributed in the hope that they
  14    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16    the GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21    02111-1307, USA.  */
  22
  23 #include <stdio.h>
  24 #include "sysdep.h"
  25 #include "opcode/ppc.h"
  26 #include "opintl.h"
  27
  28 /* This file holds the PowerPC opcode table.  The opcode table
  29    includes almost all of the extended instruction mnemonics.  This
  30    permits the disassembler to use them, and simplifies the assembler
  31    logic, at the cost of increasing the table size.  The table is
  32    strictly constant data, so the compiler should be able to put it in
  33    the .text section.
  34
  35    This file also holds the operand table.  All knowledge about
  36    inserting operands into instructions and vice-versa is kept in this
  37    file.  */
  38 \f
  39 /* Local insertion and extraction functions.  */
  40
  41 static unsigned long insert_bat (unsigned long, long, int, const char **);
  42 static long extract_bat (unsigned long, int, int *);
  43 static unsigned long insert_bba (unsigned long, long, int, const char **);
  44 static long extract_bba (unsigned long, int, int *);
  45 static unsigned long insert_bd (unsigned long, long, int, const char **);
  46 static long extract_bd (unsigned long, int, int *);
  47 static unsigned long insert_bdm (unsigned long, long, int, const char **);
  48 static long extract_bdm (unsigned long, int, int *);
  49 static unsigned long insert_bdp (unsigned long, long, int, const char **);
  50 static long extract_bdp (unsigned long, int, int *);
  51 static unsigned long insert_bo (unsigned long, long, int, const char **);
  52 static long extract_bo (unsigned long, int, int *);
  53 static unsigned long insert_boe (unsigned long, long, int, const char **);
  54 static long extract_boe (unsigned long, int, int *);
  55 static unsigned long insert_dq (unsigned long, long, int, const char **);
  56 static long extract_dq (unsigned long, int, int *);
  57 static unsigned long insert_ds (unsigned long, long, int, const char **);
  58 static long extract_ds (unsigned long, int, int *);
  59 static unsigned long insert_de (unsigned long, long, int, const char **);
  60 static long extract_de (unsigned long, int, int *);
  61 static unsigned long insert_des (unsigned long, long, int, const char **);
  62 static long extract_des (unsigned long, int, int *);
  63 static unsigned long insert_fxm (unsigned long, long, int, const char **);
  64 static long extract_fxm (unsigned long, int, int *);
  65 static unsigned long insert_li (unsigned long, long, int, const char **);
  66 static long extract_li (unsigned long, int, int *);
  67 static unsigned long insert_mbe (unsigned long, long, int, const char **);
  68 static long extract_mbe (unsigned long, int, int *);
  69 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
  70 static long extract_mb6 (unsigned long, int, int *);
  71 static unsigned long insert_nb (unsigned long, long, int, const char **);
  72 static long extract_nb (unsigned long, int, int *);
  73 static unsigned long insert_nsi (unsigned long, long, int, const char **);
  74 static long extract_nsi (unsigned long, int, int *);
  75 static unsigned long insert_ral (unsigned long, long, int, const char **);
  76 static unsigned long insert_ram (unsigned long, long, int, const char **);
  77 static unsigned long insert_raq (unsigned long, long, int, const char **);
  78 static unsigned long insert_ras (unsigned long, long, int, const char **);
  79 static unsigned long insert_rbs (unsigned long, long, int, const char **);
  80 static long extract_rbs (unsigned long, int, int *);
  81 static unsigned long insert_rsq (unsigned long, long, int, const char **);
  82 static unsigned long insert_rtq (unsigned long, long, int, const char **);
  83 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
  84 static long extract_sh6 (unsigned long, int, int *);
  85 static unsigned long insert_spr (unsigned long, long, int, const char **);
  86 static long extract_spr (unsigned long, int, int *);
  87 static unsigned long insert_tbr (unsigned long, long, int, const char **);
  88 static long extract_tbr (unsigned long, int, int *);
  89 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
  90 static long extract_ev2 (unsigned long, int, int *);
  91 static unsigned long insert_ev4 (unsigned long, long, int, const char **);
  92 static long extract_ev4 (unsigned long, int, int *);
  93 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
  94 static long extract_ev8 (unsigned long, int, int *);
  95 \f
  96 /* The operands table.
  97
  98    The fields are bits, shift, insert, extract, flags.
  99
 100    We used to put parens around the various additions, like the one
 101    for BA just below.  However, that caused trouble with feeble
 102    compilers with a limit on depth of a parenthesized expression, like
 103    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
 104    omit the parens, since the macros are never used in a context where
 105    the addition will be ambiguous.  */
 106
 107 const struct powerpc_operand powerpc_operands[] =
 108 {
 109   /* The zero index is used to indicate the end of the list of
 110      operands.  */
 111 #define UNUSED 0
 112   { 0, 0, 0, 0, 0 },
 113
 114   /* The BA field in an XL form instruction.  */
 115 #define BA UNUSED + 1
 116 #define BA_MASK (0x1f << 16)
 117   { 5, 16, 0, 0, PPC_OPERAND_CR },
 118
 119   /* The BA field in an XL form instruction when it must be the same
 120      as the BT field in the same instruction.  */
 121 #define BAT BA + 1
 122   { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 123
 124   /* The BB field in an XL form instruction.  */
 125 #define BB BAT + 1
 126 #define BB_MASK (0x1f << 11)
 127   { 5, 11, 0, 0, PPC_OPERAND_CR },
 128
 129   /* The BB field in an XL form instruction when it must be the same
 130      as the BA field in the same instruction.  */
 131 #define BBA BB + 1
 132   { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 133
 134   /* The BD field in a B form instruction.  The lower two bits are
 135      forced to zero.  */
 136 #define BD BBA + 1
 137   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 138
 139   /* The BD field in a B form instruction when absolute addressing is
 140      used.  */
 141 #define BDA BD + 1
 142   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 143
 144   /* The BD field in a B form instruction when the - modifier is used.
 145      This sets the y bit of the BO field appropriately.  */
 146 #define BDM BDA + 1
 147   { 16, 0, insert_bdm, extract_bdm,
 148       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 149
 150   /* The BD field in a B form instruction when the - modifier is used
 151      and absolute address is used.  */
 152 #define BDMA BDM + 1
 153   { 16, 0, insert_bdm, extract_bdm,
 154       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 155
 156   /* The BD field in a B form instruction when the + modifier is used.
 157      This sets the y bit of the BO field appropriately.  */
 158 #define BDP BDMA + 1
 159   { 16, 0, insert_bdp, extract_bdp,
 160       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 161
 162   /* The BD field in a B form instruction when the + modifier is used
 163      and absolute addressing is used.  */
 164 #define BDPA BDP + 1
 165   { 16, 0, insert_bdp, extract_bdp,
 166       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 167
 168   /* The BF field in an X or XL form instruction.  */
 169 #define BF BDPA + 1
 170   { 3, 23, 0, 0, PPC_OPERAND_CR },
 171
 172   /* An optional BF field.  This is used for comparison instructions,
 173      in which an omitted BF field is taken as zero.  */
 174 #define OBF BF + 1
 175   { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 176
 177   /* The BFA field in an X or XL form instruction.  */
 178 #define BFA OBF + 1
 179   { 3, 18, 0, 0, PPC_OPERAND_CR },
 180
 181   /* The BI field in a B form or XL form instruction.  */
 182 #define BI BFA + 1
 183 #define BI_MASK (0x1f << 16)
 184   { 5, 16, 0, 0, PPC_OPERAND_CR },
 185
 186   /* The BO field in a B form instruction.  Certain values are
 187      illegal.  */
 188 #define BO BI + 1
 189 #define BO_MASK (0x1f << 21)
 190   { 5, 21, insert_bo, extract_bo, 0 },
 191
 192   /* The BO field in a B form instruction when the + or - modifier is
 193      used.  This is like the BO field, but it must be even.  */
 194 #define BOE BO + 1
 195   { 5, 21, insert_boe, extract_boe, 0 },
 196
 197 #define BH BOE + 1
 198   { 2, 11, 0, 0, PPC_OPERAND_OPTIONAL },
 199
 200   /* The BT field in an X or XL form instruction.  */
 201 #define BT BH + 1
 202   { 5, 21, 0, 0, PPC_OPERAND_CR },
 203
 204   /* The condition register number portion of the BI field in a B form
 205      or XL form instruction.  This is used for the extended
 206      conditional branch mnemonics, which set the lower two bits of the
 207      BI field.  This field is optional.  */
 208 #define CR BT + 1
 209   { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 210
 211   /* The CRB field in an X form instruction.  */
 212 #define CRB CR + 1
 213   { 5, 6, 0, 0, 0 },
 214
 215   /* The CRFD field in an X form instruction.  */
 216 #define CRFD CRB + 1
 217   { 3, 23, 0, 0, PPC_OPERAND_CR },
 218
 219   /* The CRFS field in an X form instruction.  */
 220 #define CRFS CRFD + 1
 221   { 3, 0, 0, 0, PPC_OPERAND_CR },
 222
 223   /* The CT field in an X form instruction.  */
 224 #define CT CRFS + 1
 225   { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 226
 227   /* The D field in a D form instruction.  This is a displacement off
 228      a register, and implies that the next operand is a register in
 229      parentheses.  */
 230 #define D CT + 1
 231   { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 232
 233   /* The DE field in a DE form instruction.  This is like D, but is 12
 234      bits only.  */
 235 #define DE D + 1
 236   { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
 237
 238   /* The DES field in a DES form instruction.  This is like DS, but is 14
 239      bits only (12 stored.)  */
 240 #define DES DE + 1
 241   { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 242
 243   /* The DQ field in a DQ form instruction.  This is like D, but the
 244      lower four bits are forced to zero. */
 245 #define DQ DES + 1
 246   { 16, 0, insert_dq, extract_dq,
 247       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 248
 249   /* The DS field in a DS form instruction.  This is like D, but the
 250      lower two bits are forced to zero.  */
 251 #define DS DQ + 1
 252   { 16, 0, insert_ds, extract_ds,
 253       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 254
 255   /* The E field in a wrteei instruction.  */
 256 #define E DS + 1
 257   { 1, 15, 0, 0, 0 },
 258
 259   /* The FL1 field in a POWER SC form instruction.  */
 260 #define FL1 E + 1
 261   { 4, 12, 0, 0, 0 },
 262
 263   /* The FL2 field in a POWER SC form instruction.  */
 264 #define FL2 FL1 + 1
 265   { 3, 2, 0, 0, 0 },
 266
 267   /* The FLM field in an XFL form instruction.  */
 268 #define FLM FL2 + 1
 269   { 8, 17, 0, 0, 0 },
 270
 271   /* The FRA field in an X or A form instruction.  */
 272 #define FRA FLM + 1
 273 #define FRA_MASK (0x1f << 16)
 274   { 5, 16, 0, 0, PPC_OPERAND_FPR },
 275
 276   /* The FRB field in an X or A form instruction.  */
 277 #define FRB FRA + 1
 278 #define FRB_MASK (0x1f << 11)
 279   { 5, 11, 0, 0, PPC_OPERAND_FPR },
 280
 281   /* The FRC field in an A form instruction.  */
 282 #define FRC FRB + 1
 283 #define FRC_MASK (0x1f << 6)
 284   { 5, 6, 0, 0, PPC_OPERAND_FPR },
 285
 286   /* The FRS field in an X form instruction or the FRT field in a D, X
 287      or A form instruction.  */
 288 #define FRS FRC + 1
 289 #define FRT FRS
 290   { 5, 21, 0, 0, PPC_OPERAND_FPR },
 291
 292   /* The FXM field in an XFX instruction.  */
 293 #define FXM FRS + 1
 294 #define FXM_MASK (0xff << 12)
 295   { 8, 12, insert_fxm, extract_fxm, 0 },
 296
 297   /* Power4 version for mfcr.  */
 298 #define FXM4 FXM + 1
 299   { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
 300
 301   /* The L field in a D or X form instruction.  */
 302 #define L FXM4 + 1
 303   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 304
 305   /* The LEV field in a POWER SC form instruction.  */
 306 #define LEV L + 1
 307   { 7, 5, 0, 0, 0 },
 308
 309   /* The LI field in an I form instruction.  The lower two bits are
 310      forced to zero.  */
 311 #define LI LEV + 1
 312   { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 313
 314   /* The LI field in an I form instruction when used as an absolute
 315      address.  */
 316 #define LIA LI + 1
 317   { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 318
 319   /* The LS field in an X (sync) form instruction.  */
 320 #define LS LIA + 1
 321   { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 322
 323   /* The MB field in an M form instruction.  */
 324 #define MB LS + 1
 325 #define MB_MASK (0x1f << 6)
 326   { 5, 6, 0, 0, 0 },
 327
 328   /* The ME field in an M form instruction.  */
 329 #define ME MB + 1
 330 #define ME_MASK (0x1f << 1)
 331   { 5, 1, 0, 0, 0 },
 332
 333   /* The MB and ME fields in an M form instruction expressed a single
 334      operand which is a bitmask indicating which bits to select.  This
 335      is a two operand form using PPC_OPERAND_NEXT.  See the
 336      description in opcode/ppc.h for what this means.  */
 337 #define MBE ME + 1
 338   { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 339   { 32, 0, insert_mbe, extract_mbe, 0 },
 340
 341   /* The MB or ME field in an MD or MDS form instruction.  The high
 342      bit is wrapped to the low end.  */
 343 #define MB6 MBE + 2
 344 #define ME6 MB6
 345 #define MB6_MASK (0x3f << 5)
 346   { 6, 5, insert_mb6, extract_mb6, 0 },
 347
 348   /* The MO field in an mbar instruction.  */
 349 #define MO MB6 + 1
 350   { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 351
 352   /* The NB field in an X form instruction.  The value 32 is stored as
 353      0.  */
 354 #define NB MO + 1
 355   { 6, 11, insert_nb, extract_nb, 0 },
 356
 357   /* The NSI field in a D form instruction.  This is the same as the
 358      SI field, only negated.  */
 359 #define NSI NB + 1
 360   { 16, 0, insert_nsi, extract_nsi,
 361       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 362
 363   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 364 #define RA NSI + 1
 365 #define RA_MASK (0x1f << 16)
 366   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 367
 368   /* As above, but 0 in the RA field means zero, not r0.  */
 369 #define RA0 RA + 1
 370   { 5, 16, 0, 0, PPC_OPERAND_GPR_0 },
 371
 372   /* The RA field in the DQ form lq instruction, which has special
 373      value restrictions.  */
 374 #define RAQ RA0 + 1
 375   { 5, 16, insert_raq, 0, PPC_OPERAND_GPR_0 },
 376
 377   /* The RA field in a D or X form instruction which is an updating
 378      load, which means that the RA field may not be zero and may not
 379      equal the RT field.  */
 380 #define RAL RAQ + 1
 381   { 5, 16, insert_ral, 0, PPC_OPERAND_GPR_0 },
 382
 383   /* The RA field in an lmw instruction, which has special value
 384      restrictions.  */
 385 #define RAM RAL + 1
 386   { 5, 16, insert_ram, 0, PPC_OPERAND_GPR_0 },
 387
 388   /* The RA field in a D or X form instruction which is an updating
 389      store or an updating floating point load, which means that the RA
 390      field may not be zero.  */
 391 #define RAS RAM + 1
 392   { 5, 16, insert_ras, 0, PPC_OPERAND_GPR_0 },
 393
 394   /* The RA field of the tlbwe instruction, which is optional.  */
 395 #define RAOPT RAS + 1
 396   { 5, 16, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 397
 398   /* The RB field in an X, XO, M, or MDS form instruction.  */
 399 #define RB RAOPT + 1
 400 #define RB_MASK (0x1f << 11)
 401   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 402
 403   /* The RB field in an X form instruction when it must be the same as
 404      the RS field in the instruction.  This is used for extended
 405      mnemonics like mr.  */
 406 #define RBS RB + 1
 407   { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 408
 409   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 410      instruction or the RT field in a D, DS, X, XFX or XO form
 411      instruction.  */
 412 #define RS RBS + 1
 413 #define RT RS
 414 #define RT_MASK (0x1f << 21)
 415   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 416
 417   /* The RS field of the DS form stq instruction, which has special
 418      value restrictions.  */
 419 #define RSQ RS + 1
 420   { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR_0 },
 421
 422   /* The RT field of the DQ form lq instruction, which has special
 423      value restrictions.  */
 424 #define RTQ RSQ + 1
 425   { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR_0 },
 426
 427   /* The RS field of the tlbwe instruction, which is optional.  */
 428 #define RSO RTQ + 1
 429   { 5, 21, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 430
 431   /* The SH field in an X or M form instruction.  */
 432 #define SH RSO + 1
 433 #define SH_MASK (0x1f << 11)
 434   { 5, 11, 0, 0, 0 },
 435
 436   /* The SH field in an MD form instruction.  This is split.  */
 437 #define SH6 SH + 1
 438 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 439   { 6, 1, insert_sh6, extract_sh6, 0 },
 440
 441   /* The SH field of the tlbwe instruction, which is optional.  */
 442 #define SHO SH6 + 1
 443   { 5, 11,0, 0, PPC_OPERAND_OPTIONAL },
 444
 445   /* The SI field in a D form instruction.  */
 446 #define SI SHO + 1
 447   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 448
 449   /* The SI field in a D form instruction when we accept a wide range
 450      of positive values.  */
 451 #define SISIGNOPT SI + 1
 452   { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 453
 454   /* The SPR field in an XFX form instruction.  This is flipped--the
 455      lower 5 bits are stored in the upper 5 and vice- versa.  */
 456 #define SPR SISIGNOPT + 1
 457 #define PMR SPR
 458 #define SPR_MASK (0x3ff << 11)
 459   { 10, 11, insert_spr, extract_spr, 0 },
 460
 461   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 462 #define SPRBAT SPR + 1
 463 #define SPRBAT_MASK (0x3 << 17)
 464   { 2, 17, 0, 0, 0 },
 465
 466   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 467 #define SPRG SPRBAT + 1
 468 #define SPRG_MASK (0x3 << 16)
 469   { 2, 16, 0, 0, 0 },
 470
 471   /* The SR field in an X form instruction.  */
 472 #define SR SPRG + 1
 473   { 4, 16, 0, 0, 0 },
 474
 475   /* The STRM field in an X AltiVec form instruction.  */
 476 #define STRM SR + 1
 477 #define STRM_MASK (0x3 << 21)
 478   { 2, 21, 0, 0, 0 },
 479
 480   /* The SV field in a POWER SC form instruction.  */
 481 #define SV STRM + 1
 482   { 14, 2, 0, 0, 0 },
 483
 484   /* The TBR field in an XFX form instruction.  This is like the SPR
 485      field, but it is optional.  */
 486 #define TBR SV + 1
 487   { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 488
 489   /* The TO field in a D or X form instruction.  */
 490 #define TO TBR + 1
 491 #define TO_MASK (0x1f << 21)
 492   { 5, 21, 0, 0, 0 },
 493
 494   /* The U field in an X form instruction.  */
 495 #define U TO + 1
 496   { 4, 12, 0, 0, 0 },
 497
 498   /* The UI field in a D form instruction.  */
 499 #define UI U + 1
 500   { 16, 0, 0, 0, 0 },
 501
 502   /* The VA field in a VA, VX or VXR form instruction.  */
 503 #define VA UI + 1
 504 #define VA_MASK (0x1f << 16)
 505   { 5, 16, 0, 0, PPC_OPERAND_VR },
 506
 507   /* The VB field in a VA, VX or VXR form instruction.  */
 508 #define VB VA + 1
 509 #define VB_MASK (0x1f << 11)
 510   { 5, 11, 0, 0, PPC_OPERAND_VR },
 511
 512   /* The VC field in a VA form instruction.  */
 513 #define VC VB + 1
 514 #define VC_MASK (0x1f << 6)
 515   { 5, 6, 0, 0, PPC_OPERAND_VR },
 516
 517   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 518 #define VD VC + 1
 519 #define VS VD
 520 #define VD_MASK (0x1f << 21)
 521   { 5, 21, 0, 0, PPC_OPERAND_VR },
 522
 523   /* The SIMM field in a VX form instruction.  */
 524 #define SIMM VD + 1
 525   { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
 526
 527   /* The UIMM field in a VX form instruction.  */
 528 #define UIMM SIMM + 1
 529   { 5, 16, 0, 0, 0 },
 530
 531   /* The SHB field in a VA form instruction.  */
 532 #define SHB UIMM + 1
 533   { 4, 6, 0, 0, 0 },
 534
 535   /* The other UIMM field in a EVX form instruction.  */
 536 #define EVUIMM SHB + 1
 537   { 5, 11, 0, 0, 0 },
 538
 539   /* The other UIMM field in a half word EVX form instruction.  */
 540 #define EVUIMM_2 EVUIMM + 1
 541   { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
 542
 543   /* The other UIMM field in a word EVX form instruction.  */
 544 #define EVUIMM_4 EVUIMM_2 + 1
 545   { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
 546
 547   /* The other UIMM field in a double EVX form instruction.  */
 548 #define EVUIMM_8 EVUIMM_4 + 1
 549   { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
 550
 551   /* The WS field.  */
 552 #define WS EVUIMM_8 + 1
 553 #define WS_MASK (0x7 << 11)
 554   { 3, 11, 0, 0, 0 },
 555
 556   /* The L field in an mtmsrd instruction */
 557 #define MTMSRD_L WS + 1
 558   { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
 559
 560 };
 561
 562 /* The functions used to insert and extract complicated operands.  */
 563
 564 /* The BA field in an XL form instruction when it must be the same as
 565    the BT field in the same instruction.  This operand is marked FAKE.
 566    The insertion function just copies the BT field into the BA field,
 567    and the extraction function just checks that the fields are the
 568    same.  */
 569
 570 static unsigned long
 571 insert_bat (unsigned long insn,
 572             long value ATTRIBUTE_UNUSED,
 573             int dialect ATTRIBUTE_UNUSED,
 574             const char **errmsg ATTRIBUTE_UNUSED)
 575 {
 576   return insn | (((insn >> 21) & 0x1f) << 16);
 577 }
 578
 579 static long
 580 extract_bat (unsigned long insn,
 581              int dialect ATTRIBUTE_UNUSED,
 582              int *invalid)
 583 {
 584   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 585     *invalid = 1;
 586   return 0;
 587 }
 588
 589 /* The BB field in an XL form instruction when it must be the same as
 590    the BA field in the same instruction.  This operand is marked FAKE.
 591    The insertion function just copies the BA field into the BB field,
 592    and the extraction function just checks that the fields are the
 593    same.  */
 594
 595 static unsigned long
 596 insert_bba (unsigned long insn,
 597             long value ATTRIBUTE_UNUSED,
 598             int dialect ATTRIBUTE_UNUSED,
 599             const char **errmsg ATTRIBUTE_UNUSED)
 600 {
 601   return insn | (((insn >> 16) & 0x1f) << 11);
 602 }
 603
 604 static long
 605 extract_bba (unsigned long insn,
 606              int dialect ATTRIBUTE_UNUSED,
 607              int *invalid)
 608 {
 609   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 610     *invalid = 1;
 611   return 0;
 612 }
 613
 614 /* The BD field in a B form instruction.  The lower two bits are
 615    forced to zero.  */
 616
 617 static unsigned long
 618 insert_bd (unsigned long insn,
 619            long value,
 620            int dialect ATTRIBUTE_UNUSED,
 621            const char **errmsg ATTRIBUTE_UNUSED)
 622 {
 623   return insn | (value & 0xfffc);
 624 }
 625
 626 static long
 627 extract_bd (unsigned long insn,
 628             int dialect ATTRIBUTE_UNUSED,
 629             int *invalid ATTRIBUTE_UNUSED)
 630 {
 631   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 632 }
 633
 634 /* The BD field in a B form instruction when the - modifier is used.
 635    This modifier means that the branch is not expected to be taken.
 636    For chips built to versions of the architecture prior to version 2
 637    (ie. not Power4 compatible), we set the y bit of the BO field to 1
 638    if the offset is negative.  When extracting, we require that the y
 639    bit be 1 and that the offset be positive, since if the y bit is 0
 640    we just want to print the normal form of the instruction.
 641    Power4 compatible targets use two bits, "a", and "t", instead of
 642    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
 643    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
 644    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
 645    for branch on CTR.  We only handle the taken/not-taken hint here.  */
 646
 647 static unsigned long
 648 insert_bdm (unsigned long insn,
 649             long value,
 650             int dialect,
 651             const char **errmsg ATTRIBUTE_UNUSED)
 652 {
 653   if ((dialect & PPC_OPCODE_POWER4) == 0)
 654     {
 655       if ((value & 0x8000) != 0)
 656         insn |= 1 << 21;
 657     }
 658   else
 659     {
 660       if ((insn & (0x14 << 21)) == (0x04 << 21))
 661         insn |= 0x02 << 21;
 662       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 663         insn |= 0x08 << 21;
 664     }
 665   return insn | (value & 0xfffc);
 666 }
 667
 668 static long
 669 extract_bdm (unsigned long insn,
 670              int dialect,
 671              int *invalid)
 672 {
 673   if ((dialect & PPC_OPCODE_POWER4) == 0)
 674     {
 675       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
 676         *invalid = 1;
 677     }
 678   else
 679     {
 680       if ((insn & (0x17 << 21)) != (0x06 << 21)
 681           && (insn & (0x1d << 21)) != (0x18 << 21))
 682         *invalid = 1;
 683     }
 684
 685   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 686 }
 687
 688 /* The BD field in a B form instruction when the + modifier is used.
 689    This is like BDM, above, except that the branch is expected to be
 690    taken.  */
 691
 692 static unsigned long
 693 insert_bdp (unsigned long insn,
 694             long value,
 695             int dialect,
 696             const char **errmsg ATTRIBUTE_UNUSED)
 697 {
 698   if ((dialect & PPC_OPCODE_POWER4) == 0)
 699     {
 700       if ((value & 0x8000) == 0)
 701         insn |= 1 << 21;
 702     }
 703   else
 704     {
 705       if ((insn & (0x14 << 21)) == (0x04 << 21))
 706         insn |= 0x03 << 21;
 707       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 708         insn |= 0x09 << 21;
 709     }
 710   return insn | (value & 0xfffc);
 711 }
 712
 713 static long
 714 extract_bdp (unsigned long insn,
 715              int dialect,
 716              int *invalid)
 717 {
 718   if ((dialect & PPC_OPCODE_POWER4) == 0)
 719     {
 720       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
 721         *invalid = 1;
 722     }
 723   else
 724     {
 725       if ((insn & (0x17 << 21)) != (0x07 << 21)
 726           && (insn & (0x1d << 21)) != (0x19 << 21))
 727         *invalid = 1;
 728     }
 729
 730   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 731 }
 732
 733 /* Check for legal values of a BO field.  */
 734
 735 static int
 736 valid_bo (long value, int dialect)
 737 {
 738   if ((dialect & PPC_OPCODE_POWER4) == 0)
 739     {
 740       /* Certain encodings have bits that are required to be zero.
 741          These are (z must be zero, y may be anything):
 742              001zy
 743              011zy
 744              1z00y
 745              1z01y
 746              1z1zz
 747       */
 748       switch (value & 0x14)
 749         {
 750         default:
 751         case 0:
 752           return 1;
 753         case 0x4:
 754           return (value & 0x2) == 0;
 755         case 0x10:
 756           return (value & 0x8) == 0;
 757         case 0x14:
 758           return value == 0x14;
 759         }
 760     }
 761   else
 762     {
 763       /* Certain encodings have bits that are required to be zero.
 764          These are (z must be zero, a & t may be anything):
 765              0000z
 766              0001z
 767              0100z
 768              0101z
 769              001at
 770              011at
 771              1a00t
 772              1a01t
 773              1z1zz
 774       */
 775       if ((value & 0x14) == 0)
 776         return (value & 0x1) == 0;
 777       else if ((value & 0x14) == 0x14)
 778         return value == 0x14;
 779       else
 780         return 1;
 781     }
 782 }
 783
 784 /* The BO field in a B form instruction.  Warn about attempts to set
 785    the field to an illegal value.  */
 786
 787 static unsigned long
 788 insert_bo (unsigned long insn,
 789            long value,
 790            int dialect,
 791            const char **errmsg)
 792 {
 793   if (!valid_bo (value, dialect))
 794     *errmsg = _("invalid conditional option");
 795   return insn | ((value & 0x1f) << 21);
 796 }
 797
 798 static long
 799 extract_bo (unsigned long insn,
 800             int dialect,
 801             int *invalid)
 802 {
 803   long value;
 804
 805   value = (insn >> 21) & 0x1f;
 806   if (!valid_bo (value, dialect))
 807     *invalid = 1;
 808   return value;
 809 }
 810
 811 /* The BO field in a B form instruction when the + or - modifier is
 812    used.  This is like the BO field, but it must be even.  When
 813    extracting it, we force it to be even.  */
 814
 815 static unsigned long
 816 insert_boe (unsigned long insn,
 817             long value,
 818             int dialect,
 819             const char **errmsg)
 820 {
 821   if (!valid_bo (value, dialect))
 822     *errmsg = _("invalid conditional option");
 823   else if ((value & 1) != 0)
 824     *errmsg = _("attempt to set y bit when using + or - modifier");
 825
 826   return insn | ((value & 0x1f) << 21);
 827 }
 828
 829 static long
 830 extract_boe (unsigned long insn,
 831              int dialect,
 832              int *invalid)
 833 {
 834   long value;
 835
 836   value = (insn >> 21) & 0x1f;
 837   if (!valid_bo (value, dialect))
 838     *invalid = 1;
 839   return value & 0x1e;
 840 }
 841
 842 /* The DQ field in a DQ form instruction.  This is like D, but the
 843    lower four bits are forced to zero. */
 844
 845 static unsigned long
 846 insert_dq (unsigned long insn,
 847            long value,
 848            int dialect ATTRIBUTE_UNUSED,
 849            const char **errmsg)
 850 {
 851   if ((value & 0xf) != 0)
 852     *errmsg = _("offset not a multiple of 16");
 853   return insn | (value & 0xfff0);
 854 }
 855
 856 static long
 857 extract_dq (unsigned long insn,
 858             int dialect ATTRIBUTE_UNUSED,
 859             int *invalid ATTRIBUTE_UNUSED)
 860 {
 861   return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
 862 }
 863
 864 static unsigned long
 865 insert_ev2 (unsigned long insn,
 866             long value,
 867             int dialect ATTRIBUTE_UNUSED,
 868             const char **errmsg)
 869 {
 870   if ((value & 1) != 0)
 871     *errmsg = _("offset not a multiple of 2");
 872   if ((value > 62) != 0)
 873     *errmsg = _("offset greater than 62");
 874   return insn | ((value & 0x3e) << 10);
 875 }
 876
 877 static long
 878 extract_ev2 (unsigned long insn,
 879              int dialect ATTRIBUTE_UNUSED,
 880              int *invalid ATTRIBUTE_UNUSED)
 881 {
 882   return (insn >> 10) & 0x3e;
 883 }
 884
 885 static unsigned long
 886 insert_ev4 (unsigned long insn,
 887             long value,
 888             int dialect ATTRIBUTE_UNUSED,
 889             const char **errmsg)
 890 {
 891   if ((value & 3) != 0)
 892     *errmsg = _("offset not a multiple of 4");
 893   if ((value > 124) != 0)
 894     *errmsg = _("offset greater than 124");
 895   return insn | ((value & 0x7c) << 9);
 896 }
 897
 898 static long
 899 extract_ev4 (unsigned long insn,
 900              int dialect ATTRIBUTE_UNUSED,
 901              int *invalid ATTRIBUTE_UNUSED)
 902 {
 903   return (insn >> 9) & 0x7c;
 904 }
 905
 906 static unsigned long
 907 insert_ev8 (unsigned long insn,
 908             long value,
 909             int dialect ATTRIBUTE_UNUSED,
 910             const char **errmsg)
 911 {
 912   if ((value & 7) != 0)
 913     *errmsg = _("offset not a multiple of 8");
 914   if ((value > 248) != 0)
 915     *errmsg = _("offset greater than 248");
 916   return insn | ((value & 0xf8) << 8);
 917 }
 918
 919 static long
 920 extract_ev8 (unsigned long insn,
 921              int dialect ATTRIBUTE_UNUSED,
 922              int *invalid ATTRIBUTE_UNUSED)
 923 {
 924   return (insn >> 8) & 0xf8;
 925 }
 926
 927 /* The DS field in a DS form instruction.  This is like D, but the
 928    lower two bits are forced to zero.  */
 929
 930 static unsigned long
 931 insert_ds (unsigned long insn,
 932            long value,
 933            int dialect ATTRIBUTE_UNUSED,
 934            const char **errmsg)
 935 {
 936   if ((value & 3) != 0)
 937     *errmsg = _("offset not a multiple of 4");
 938   return insn | (value & 0xfffc);
 939 }
 940
 941 static long
 942 extract_ds (unsigned long insn,
 943             int dialect ATTRIBUTE_UNUSED,
 944             int *invalid ATTRIBUTE_UNUSED)
 945 {
 946   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 947 }
 948
 949 /* The DE field in a DE form instruction.  */
 950
 951 static unsigned long
 952 insert_de (unsigned long insn,
 953            long value,
 954            int dialect ATTRIBUTE_UNUSED,
 955            const char **errmsg)
 956 {
 957   if (value > 2047 || value < -2048)
 958     *errmsg = _("offset not between -2048 and 2047");
 959   return insn | ((value << 4) & 0xfff0);
 960 }
 961
 962 static long
 963 extract_de (unsigned long insn,
 964             int dialect ATTRIBUTE_UNUSED,
 965             int *invalid ATTRIBUTE_UNUSED)
 966 {
 967   return (insn & 0xfff0) >> 4;
 968 }
 969
 970 /* The DES field in a DES form instruction.  */
 971
 972 static unsigned long
 973 insert_des (unsigned long insn,
 974             long value,
 975             int dialect ATTRIBUTE_UNUSED,
 976             const char **errmsg)
 977 {
 978   if (value > 8191 || value < -8192)
 979     *errmsg = _("offset not between -8192 and 8191");
 980   else if ((value & 3) != 0)
 981     *errmsg = _("offset not a multiple of 4");
 982   return insn | ((value << 2) & 0xfff0);
 983 }
 984
 985 static long
 986 extract_des (unsigned long insn,
 987              int dialect ATTRIBUTE_UNUSED,
 988              int *invalid ATTRIBUTE_UNUSED)
 989 {
 990   return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
 991 }
 992
 993 /* FXM mask in mfcr and mtcrf instructions.  */
 994
 995 static unsigned long
 996 insert_fxm (unsigned long insn,
 997             long value,
 998             int dialect,
 999             const char **errmsg)
1000 {
1001   /* If the optional field on mfcr is missing that means we want to use
1002      the old form of the instruction that moves the whole cr.  In that
1003      case we'll have VALUE zero.  There doesn't seem to be a way to
1004      distinguish this from the case where someone writes mfcr %r3,0.  */
1005   if (value == 0)
1006     ;
1007
1008   /* If only one bit of the FXM field is set, we can use the new form
1009      of the instruction, which is faster.  Unlike the Power4 branch hint
1010      encoding, this is not backward compatible.  Do not generate the
1011      new form unless -mpower4 has been given, or -many and the two
1012      operand form of mfcr was used.  */
1013   else if ((value & -value) == value
1014            && ((dialect & PPC_OPCODE_POWER4) != 0
1015                || ((dialect & PPC_OPCODE_ANY) != 0
1016                    && (insn & (0x3ff << 1)) == 19 << 1)))
1017     insn |= 1 << 20;
1018
1019   /* Any other value on mfcr is an error.  */
1020   else if ((insn & (0x3ff << 1)) == 19 << 1)
1021     {
1022       *errmsg = _("ignoring invalid mfcr mask");
1023       value = 0;
1024     }
1025
1026   return insn | ((value & 0xff) << 12);
1027 }
1028
1029 static long
1030 extract_fxm (unsigned long insn,
1031              int dialect,
1032              int *invalid)
1033 {
1034   long mask = (insn >> 12) & 0xff;
1035
1036   /* Is this a Power4 insn?  */
1037   if ((insn & (1 << 20)) != 0)
1038     {
1039       if ((dialect & PPC_OPCODE_POWER4) == 0)
1040         *invalid = 1;
1041       else
1042         {
1043           /* Exactly one bit of MASK should be set.  */
1044           if (mask == 0 || (mask & -mask) != mask)
1045             *invalid = 1;
1046         }
1047     }
1048
1049   /* Check that non-power4 form of mfcr has a zero MASK.  */
1050   else if ((insn & (0x3ff << 1)) == 19 << 1)
1051     {
1052       if (mask != 0)
1053         *invalid = 1;
1054     }
1055
1056   return mask;
1057 }
1058
1059 /* The LI field in an I form instruction.  The lower two bits are
1060    forced to zero.  */
1061
1062 static unsigned long
1063 insert_li (unsigned long insn,
1064            long value,
1065            int dialect ATTRIBUTE_UNUSED,
1066            const char **errmsg)
1067 {
1068   if ((value & 3) != 0)
1069     *errmsg = _("ignoring least significant bits in branch offset");
1070   return insn | (value & 0x3fffffc);
1071 }
1072
1073 static long
1074 extract_li (unsigned long insn,
1075             int dialect ATTRIBUTE_UNUSED,
1076             int *invalid ATTRIBUTE_UNUSED)
1077 {
1078   return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1079 }
1080
1081 /* The MB and ME fields in an M form instruction expressed as a single
1082    operand which is itself a bitmask.  The extraction function always
1083    marks it as invalid, since we never want to recognize an
1084    instruction which uses a field of this type.  */
1085
1086 static unsigned long
1087 insert_mbe (unsigned long insn,
1088             long value,
1089             int dialect ATTRIBUTE_UNUSED,
1090             const char **errmsg)
1091 {
1092   unsigned long uval, mask;
1093   int mb, me, mx, count, last;
1094
1095   uval = value;
1096
1097   if (uval == 0)
1098     {
1099       *errmsg = _("illegal bitmask");
1100       return insn;
1101     }
1102
1103   mb = 0;
1104   me = 32;
1105   if ((uval & 1) != 0)
1106     last = 1;
1107   else
1108     last = 0;
1109   count = 0;
1110
1111   /* mb: location of last 0->1 transition */
1112   /* me: location of last 1->0 transition */
1113   /* count: # transitions */
1114
1115   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1116     {
1117       if ((uval & mask) && !last)
1118         {
1119           ++count;
1120           mb = mx;
1121           last = 1;
1122         }
1123       else if (!(uval & mask) && last)
1124         {
1125           ++count;
1126           me = mx;
1127           last = 0;
1128         }
1129     }
1130   if (me == 0)
1131     me = 32;
1132
1133   if (count != 2 && (count != 0 || ! last))
1134     *errmsg = _("illegal bitmask");
1135
1136   return insn | (mb << 6) | ((me - 1) << 1);
1137 }
1138
1139 static long
1140 extract_mbe (unsigned long insn,
1141              int dialect ATTRIBUTE_UNUSED,
1142              int *invalid)
1143 {
1144   long ret;
1145   int mb, me;
1146   int i;
1147
1148   *invalid = 1;
1149
1150   mb = (insn >> 6) & 0x1f;
1151   me = (insn >> 1) & 0x1f;
1152   if (mb < me + 1)
1153     {
1154       ret = 0;
1155       for (i = mb; i <= me; i++)
1156         ret |= 1L << (31 - i);
1157     }
1158   else if (mb == me + 1)
1159     ret = ~0;
1160   else /* (mb > me + 1) */
1161     {
1162       ret = ~0;
1163       for (i = me + 1; i < mb; i++)
1164         ret &= ~(1L << (31 - i));
1165     }
1166   return ret;
1167 }
1168
1169 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1170    is wrapped to the low end.  */
1171
1172 static unsigned long
1173 insert_mb6 (unsigned long insn,
1174             long value,
1175             int dialect ATTRIBUTE_UNUSED,
1176             const char **errmsg ATTRIBUTE_UNUSED)
1177 {
1178   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1179 }
1180
1181 static long
1182 extract_mb6 (unsigned long insn,
1183              int dialect ATTRIBUTE_UNUSED,
1184              int *invalid ATTRIBUTE_UNUSED)
1185 {
1186   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1187 }
1188
1189 /* The NB field in an X form instruction.  The value 32 is stored as
1190    0.  */
1191
1192 static unsigned long
1193 insert_nb (unsigned long insn,
1194            long value,
1195            int dialect ATTRIBUTE_UNUSED,
1196            const char **errmsg)
1197 {
1198   if (value < 0 || value > 32)
1199     *errmsg = _("value out of range");
1200   if (value == 32)
1201     value = 0;
1202   return insn | ((value & 0x1f) << 11);
1203 }
1204
1205 static long
1206 extract_nb (unsigned long insn,
1207             int dialect ATTRIBUTE_UNUSED,
1208             int *invalid ATTRIBUTE_UNUSED)
1209 {
1210   long ret;
1211
1212   ret = (insn >> 11) & 0x1f;
1213   if (ret == 0)
1214     ret = 32;
1215   return ret;
1216 }
1217
1218 /* The NSI field in a D form instruction.  This is the same as the SI
1219    field, only negated.  The extraction function always marks it as
1220    invalid, since we never want to recognize an instruction which uses
1221    a field of this type.  */
1222
1223 static unsigned long
1224 insert_nsi (unsigned long insn,
1225             long value,
1226             int dialect ATTRIBUTE_UNUSED,
1227             const char **errmsg ATTRIBUTE_UNUSED)
1228 {
1229   return insn | (-value & 0xffff);
1230 }
1231
1232 static long
1233 extract_nsi (unsigned long insn,
1234              int dialect ATTRIBUTE_UNUSED,
1235              int *invalid)
1236 {
1237   *invalid = 1;
1238   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1239 }
1240
1241 /* The RA field in a D or X form instruction which is an updating
1242    load, which means that the RA field may not be zero and may not
1243    equal the RT field.  */
1244
1245 static unsigned long
1246 insert_ral (unsigned long insn,
1247             long value,
1248             int dialect ATTRIBUTE_UNUSED,
1249             const char **errmsg)
1250 {
1251   if (value == 0
1252       || (unsigned long) value == ((insn >> 21) & 0x1f))
1253     *errmsg = "invalid register operand when updating";
1254   return insn | ((value & 0x1f) << 16);
1255 }
1256
1257 /* The RA field in an lmw instruction, which has special value
1258    restrictions.  */
1259
1260 static unsigned long
1261 insert_ram (unsigned long insn,
1262             long value,
1263             int dialect ATTRIBUTE_UNUSED,
1264             const char **errmsg)
1265 {
1266   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1267     *errmsg = _("index register in load range");
1268   return insn | ((value & 0x1f) << 16);
1269 }
1270
1271 /* The RA field in the DQ form lq instruction, which has special
1272    value restrictions.  */
1273
1274 static unsigned long
1275 insert_raq (unsigned long insn,
1276             long value,
1277             int dialect ATTRIBUTE_UNUSED,
1278             const char **errmsg)
1279 {
1280   long rtvalue = (insn & RT_MASK) >> 21;
1281
1282   if (value == rtvalue)
1283     *errmsg = _("source and target register operands must be different");
1284   return insn | ((value & 0x1f) << 16);
1285 }
1286
1287 /* The RA field in a D or X form instruction which is an updating
1288    store or an updating floating point load, which means that the RA
1289    field may not be zero.  */
1290
1291 static unsigned long
1292 insert_ras (unsigned long insn,
1293             long value,
1294             int dialect ATTRIBUTE_UNUSED,
1295             const char **errmsg)
1296 {
1297   if (value == 0)
1298     *errmsg = _("invalid register operand when updating");
1299   return insn | ((value & 0x1f) << 16);
1300 }
1301
1302 /* The RB field in an X form instruction when it must be the same as
1303    the RS field in the instruction.  This is used for extended
1304    mnemonics like mr.  This operand is marked FAKE.  The insertion
1305    function just copies the BT field into the BA field, and the
1306    extraction function just checks that the fields are the same.  */
1307
1308 static unsigned long
1309 insert_rbs (unsigned long insn,
1310             long value ATTRIBUTE_UNUSED,
1311             int dialect ATTRIBUTE_UNUSED,
1312             const char **errmsg ATTRIBUTE_UNUSED)
1313 {
1314   return insn | (((insn >> 21) & 0x1f) << 11);
1315 }
1316
1317 static long
1318 extract_rbs (unsigned long insn,
1319              int dialect ATTRIBUTE_UNUSED,
1320              int *invalid)
1321 {
1322   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1323     *invalid = 1;
1324   return 0;
1325 }
1326
1327 /* The RT field of the DQ form lq instruction, which has special
1328    value restrictions.  */
1329
1330 static unsigned long
1331 insert_rtq (unsigned long insn,
1332             long value,
1333             int dialect ATTRIBUTE_UNUSED,
1334             const char **errmsg)
1335 {
1336   if ((value & 1) != 0)
1337     *errmsg = _("target register operand must be even");
1338   return insn | ((value & 0x1f) << 21);
1339 }
1340
1341 /* The RS field of the DS form stq instruction, which has special
1342    value restrictions.  */
1343
1344 static unsigned long
1345 insert_rsq (unsigned long insn,
1346             long value ATTRIBUTE_UNUSED,
1347             int dialect ATTRIBUTE_UNUSED,
1348             const char **errmsg)
1349 {
1350   if ((value & 1) != 0)
1351     *errmsg = _("source register operand must be even");
1352   return insn | ((value & 0x1f) << 21);
1353 }
1354
1355 /* The SH field in an MD form instruction.  This is split.  */
1356
1357 static unsigned long
1358 insert_sh6 (unsigned long insn,
1359             long value,
1360             int dialect ATTRIBUTE_UNUSED,
1361             const char **errmsg ATTRIBUTE_UNUSED)
1362 {
1363   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1364 }
1365
1366 static long
1367 extract_sh6 (unsigned long insn,
1368              int dialect ATTRIBUTE_UNUSED,
1369              int *invalid ATTRIBUTE_UNUSED)
1370 {
1371   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1372 }
1373
1374 /* The SPR field in an XFX form instruction.  This is flipped--the
1375    lower 5 bits are stored in the upper 5 and vice- versa.  */
1376
1377 static unsigned long
1378 insert_spr (unsigned long insn,
1379             long value,
1380             int dialect ATTRIBUTE_UNUSED,
1381             const char **errmsg ATTRIBUTE_UNUSED)
1382 {
1383   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1384 }
1385
1386 static long
1387 extract_spr (unsigned long insn,
1388              int dialect ATTRIBUTE_UNUSED,
1389              int *invalid ATTRIBUTE_UNUSED)
1390 {
1391   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1392 }
1393
1394 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1395    is optional.  When TBR is omitted, it must be inserted as 268 (the
1396    magic number of the TB register).  These functions treat 0
1397    (indicating an omitted optional operand) as 268.  This means that
1398    ``mftb 4,0'' is not handled correctly.  This does not matter very
1399    much, since the architecture manual does not define mftb as
1400    accepting any values other than 268 or 269.  */
1401
1402 #define TB (268)
1403
1404 static unsigned long
1405 insert_tbr (unsigned long insn,
1406             long value,
1407             int dialect ATTRIBUTE_UNUSED,
1408             const char **errmsg ATTRIBUTE_UNUSED)
1409 {
1410   if (value == 0)
1411     value = TB;
1412   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1413 }
1414
1415 static long
1416 extract_tbr (unsigned long insn,
1417              int dialect ATTRIBUTE_UNUSED,
1418              int *invalid ATTRIBUTE_UNUSED)
1419 {
1420   long ret;
1421
1422   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1423   if (ret == TB)
1424     ret = 0;
1425   return ret;
1426 }
1427 \f
1428 /* Macros used to form opcodes.  */
1429
1430 /* The main opcode.  */
1431 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1432 #define OP_MASK OP (0x3f)
1433
1434 /* The main opcode combined with a trap code in the TO field of a D
1435    form instruction.  Used for extended mnemonics for the trap
1436    instructions.  */
1437 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1438 #define OPTO_MASK (OP_MASK | TO_MASK)
1439
1440 /* The main opcode combined with a comparison size bit in the L field
1441    of a D form or X form instruction.  Used for extended mnemonics for
1442    the comparison instructions.  */
1443 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1444 #define OPL_MASK OPL (0x3f,1)
1445
1446 /* An A form instruction.  */
1447 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1448 #define A_MASK A (0x3f, 0x1f, 1)
1449
1450 /* An A_MASK with the FRB field fixed.  */
1451 #define AFRB_MASK (A_MASK | FRB_MASK)
1452
1453 /* An A_MASK with the FRC field fixed.  */
1454 #define AFRC_MASK (A_MASK | FRC_MASK)
1455
1456 /* An A_MASK with the FRA and FRC fields fixed.  */
1457 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1458
1459 /* A B form instruction.  */
1460 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1461 #define B_MASK B (0x3f, 1, 1)
1462
1463 /* A B form instruction setting the BO field.  */
1464 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1465 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1466
1467 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1468    matching a conditional branch regardless of the setting of the y
1469    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1470 #define Y_MASK   (((unsigned long) 1) << 21)
1471 #define AT1_MASK (((unsigned long) 3) << 21)
1472 #define AT2_MASK (((unsigned long) 9) << 21)
1473 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1474 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1475
1476 /* A B form instruction setting the BO field and the condition bits of
1477    the BI field.  */
1478 #define BBOCB(op, bo, cb, aa, lk) \
1479   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1480 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1481
1482 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1483 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1484 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1485 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1486
1487 /* A BBOYCB_MASK in which the BI field is fixed.  */
1488 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1489 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1490
1491 /* An Context form instruction.  */
1492 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1493 #define CTX_MASK CTX(0x3f, 0x7)
1494
1495 /* An User Context form instruction.  */
1496 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1497 #define UCTX_MASK UCTX(0x3f, 0x1f)
1498
1499 /* The main opcode mask with the RA field clear.  */
1500 #define DRA_MASK (OP_MASK | RA_MASK)
1501
1502 /* A DS form instruction.  */
1503 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1504 #define DS_MASK DSO (0x3f, 3)
1505
1506 /* A DE form instruction.  */
1507 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1508 #define DE_MASK DEO (0x3e, 0xf)
1509
1510 /* An EVSEL form instruction.  */
1511 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1512 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1513
1514 /* An M form instruction.  */
1515 #define M(op, rc) (OP (op) | ((rc) & 1))
1516 #define M_MASK M (0x3f, 1)
1517
1518 /* An M form instruction with the ME field specified.  */
1519 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1520
1521 /* An M_MASK with the MB and ME fields fixed.  */
1522 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1523
1524 /* An M_MASK with the SH and ME fields fixed.  */
1525 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1526
1527 /* An MD form instruction.  */
1528 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1529 #define MD_MASK MD (0x3f, 0x7, 1)
1530
1531 /* An MD_MASK with the MB field fixed.  */
1532 #define MDMB_MASK (MD_MASK | MB6_MASK)
1533
1534 /* An MD_MASK with the SH field fixed.  */
1535 #define MDSH_MASK (MD_MASK | SH6_MASK)
1536
1537 /* An MDS form instruction.  */
1538 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1539 #define MDS_MASK MDS (0x3f, 0xf, 1)
1540
1541 /* An MDS_MASK with the MB field fixed.  */
1542 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1543
1544 /* An SC form instruction.  */
1545 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1546 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1547
1548 /* An VX form instruction.  */
1549 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1550
1551 /* The mask for an VX form instruction.  */
1552 #define VX_MASK VX(0x3f, 0x7ff)
1553
1554 /* An VA form instruction.  */
1555 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1556
1557 /* The mask for an VA form instruction.  */
1558 #define VXA_MASK VXA(0x3f, 0x3f)
1559
1560 /* An VXR form instruction.  */
1561 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1562
1563 /* The mask for a VXR form instruction.  */
1564 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1565
1566 /* An X form instruction.  */
1567 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1568
1569 /* An X form instruction with the RC bit specified.  */
1570 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1571
1572 /* The mask for an X form instruction.  */
1573 #define X_MASK XRC (0x3f, 0x3ff, 1)
1574
1575 /* An X_MASK with the RA field fixed.  */
1576 #define XRA_MASK (X_MASK | RA_MASK)
1577
1578 /* An X_MASK with the RB field fixed.  */
1579 #define XRB_MASK (X_MASK | RB_MASK)
1580
1581 /* An X_MASK with the RT field fixed.  */
1582 #define XRT_MASK (X_MASK | RT_MASK)
1583
1584 /* An X_MASK with the RA and RB fields fixed.  */
1585 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1586
1587 /* An XRARB_MASK, but with the L bit clear.  */
1588 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1589
1590 /* An X_MASK with the RT and RA fields fixed.  */
1591 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1592
1593 /* An XRTRA_MASK, but with L bit clear.  */
1594 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1595
1596 /* An X form instruction with the L bit specified.  */
1597 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1598
1599 /* The mask for an X form comparison instruction.  */
1600 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1601
1602 /* The mask for an X form comparison instruction with the L field
1603    fixed.  */
1604 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1605
1606 /* An X form trap instruction with the TO field specified.  */
1607 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1608 #define XTO_MASK (X_MASK | TO_MASK)
1609
1610 /* An X form tlb instruction with the SH field specified.  */
1611 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1612 #define XTLB_MASK (X_MASK | SH_MASK)
1613
1614 /* An X form sync instruction.  */
1615 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1616
1617 /* An X form sync instruction with everything filled in except the LS field.  */
1618 #define XSYNC_MASK (0xff9fffff)
1619
1620 /* An X form AltiVec dss instruction.  */
1621 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1622 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1623
1624 /* An XFL form instruction.  */
1625 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1626 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1627
1628 /* An X form isel instruction.  */
1629 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1630 #define XISEL_MASK      XISEL(0x3f, 0x1f)
1631
1632 /* An XL form instruction with the LK field set to 0.  */
1633 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1634
1635 /* An XL form instruction which uses the LK field.  */
1636 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1637
1638 /* The mask for an XL form instruction.  */
1639 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1640
1641 /* An XL form instruction which explicitly sets the BO field.  */
1642 #define XLO(op, bo, xop, lk) \
1643   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1644 #define XLO_MASK (XL_MASK | BO_MASK)
1645
1646 /* An XL form instruction which explicitly sets the y bit of the BO
1647    field.  */
1648 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1649 #define XLYLK_MASK (XL_MASK | Y_MASK)
1650
1651 /* An XL form instruction which sets the BO field and the condition
1652    bits of the BI field.  */
1653 #define XLOCB(op, bo, cb, xop, lk) \
1654   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1655 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1656
1657 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1658 #define XLBB_MASK (XL_MASK | BB_MASK)
1659 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1660 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1661
1662 /* A mask for branch instructions using the BH field.  */
1663 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1664
1665 /* An XL_MASK with the BO and BB fields fixed.  */
1666 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1667
1668 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1669 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1670
1671 /* An XO form instruction.  */
1672 #define XO(op, xop, oe, rc) \
1673   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1674 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1675
1676 /* An XO_MASK with the RB field fixed.  */
1677 #define XORB_MASK (XO_MASK | RB_MASK)
1678
1679 /* An XS form instruction.  */
1680 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1681 #define XS_MASK XS (0x3f, 0x1ff, 1)
1682
1683 /* A mask for the FXM version of an XFX form instruction.  */
1684 #define XFXFXM_MASK (X_MASK | (1 << 11))
1685
1686 /* An XFX form instruction with the FXM field filled in.  */
1687 #define XFXM(op, xop, fxm) \
1688   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1689
1690 /* An XFX form instruction with the SPR field filled in.  */
1691 #define XSPR(op, xop, spr) \
1692   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1693 #define XSPR_MASK (X_MASK | SPR_MASK)
1694
1695 /* An XFX form instruction with the SPR field filled in except for the
1696    SPRBAT field.  */
1697 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1698
1699 /* An XFX form instruction with the SPR field filled in except for the
1700    SPRG field.  */
1701 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1702
1703 /* An X form instruction with everything filled in except the E field.  */
1704 #define XE_MASK (0xffff7fff)
1705
1706 /* An X form user context instruction.  */
1707 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1708 #define XUC_MASK      XUC(0x3f, 0x1f)
1709
1710 /* The BO encodings used in extended conditional branch mnemonics.  */
1711 #define BODNZF  (0x0)
1712 #define BODNZFP (0x1)
1713 #define BODZF   (0x2)
1714 #define BODZFP  (0x3)
1715 #define BODNZT  (0x8)
1716 #define BODNZTP (0x9)
1717 #define BODZT   (0xa)
1718 #define BODZTP  (0xb)
1719
1720 #define BOF     (0x4)
1721 #define BOFP    (0x5)
1722 #define BOFM4   (0x6)
1723 #define BOFP4   (0x7)
1724 #define BOT     (0xc)
1725 #define BOTP    (0xd)
1726 #define BOTM4   (0xe)
1727 #define BOTP4   (0xf)
1728
1729 #define BODNZ   (0x10)
1730 #define BODNZP  (0x11)
1731 #define BODZ    (0x12)
1732 #define BODZP   (0x13)
1733 #define BODNZM4 (0x18)
1734 #define BODNZP4 (0x19)
1735 #define BODZM4  (0x1a)
1736 #define BODZP4  (0x1b)
1737
1738 #define BOU     (0x14)
1739
1740 /* The BI condition bit encodings used in extended conditional branch
1741    mnemonics.  */
1742 #define CBLT    (0)
1743 #define CBGT    (1)
1744 #define CBEQ    (2)
1745 #define CBSO    (3)
1746
1747 /* The TO encodings used in extended trap mnemonics.  */
1748 #define TOLGT   (0x1)
1749 #define TOLLT   (0x2)
1750 #define TOEQ    (0x4)
1751 #define TOLGE   (0x5)
1752 #define TOLNL   (0x5)
1753 #define TOLLE   (0x6)
1754 #define TOLNG   (0x6)
1755 #define TOGT    (0x8)
1756 #define TOGE    (0xc)
1757 #define TONL    (0xc)
1758 #define TOLT    (0x10)
1759 #define TOLE    (0x14)
1760 #define TONG    (0x14)
1761 #define TONE    (0x18)
1762 #define TOU     (0x1f)
1763 \f
1764 /* Smaller names for the flags so each entry in the opcodes table will
1765    fit on a single line.  */
1766 #undef  PPC
1767 #define PPC     PPC_OPCODE_PPC
1768 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1769 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1770 #define POWER4  PPC_OPCODE_POWER4
1771 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
1772 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
1773 #define PPC403  PPC_OPCODE_403
1774 #define PPC405  PPC403
1775 #define PPC440  PPC_OPCODE_440
1776 #define PPC750  PPC
1777 #define PPC860  PPC
1778 #define PPCVEC  PPC_OPCODE_ALTIVEC
1779 #define POWER   PPC_OPCODE_POWER
1780 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1781 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1782 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1783 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1784 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1785 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
1786 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1787 #define MFDEC1  PPC_OPCODE_POWER
1788 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1789 #define BOOKE   PPC_OPCODE_BOOKE
1790 #define BOOKE64 PPC_OPCODE_BOOKE64
1791 #define CLASSIC PPC_OPCODE_CLASSIC
1792 #define PPCSPE  PPC_OPCODE_SPE
1793 #define PPCISEL PPC_OPCODE_ISEL
1794 #define PPCEFS  PPC_OPCODE_EFS
1795 #define PPCBRLK PPC_OPCODE_BRLOCK
1796 #define PPCPMR  PPC_OPCODE_PMR
1797 #define PPCCHLK PPC_OPCODE_CACHELCK
1798 #define PPCCHLK64       PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1799 #define PPCRFMCI        PPC_OPCODE_RFMCI
1800 \f
1801 /* The opcode table.
1802
1803    The format of the opcode table is:
1804
1805    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
1806
1807    NAME is the name of the instruction.
1808    OPCODE is the instruction opcode.
1809    MASK is the opcode mask; this is used to tell the disassembler
1810      which bits in the actual opcode must match OPCODE.
1811    FLAGS are flags indicated what processors support the instruction.
1812    OPERANDS is the list of operands.
1813
1814    The disassembler reads the table in order and prints the first
1815    instruction which matches, so this table is sorted to put more
1816    specific instructions before more general instructions.  It is also
1817    sorted by major opcode.  */
1818
1819 const struct powerpc_opcode powerpc_opcodes[] = {
1820 { "attn",    X(0,256), X_MASK,          POWER4,         { 0 } },
1821 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
1822 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
1823 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
1824 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
1825 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
1826 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
1827 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
1828 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
1829 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
1830 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
1831 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
1832 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
1833 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
1834 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
1835 { "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },
1836
1837 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1838 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1839 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1840 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1841 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
1842 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
1843 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1844 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1845 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
1846 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
1847 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1848 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1849 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
1850 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
1851 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1852 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1853 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1854 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1855 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
1856 { "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
1857 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1858 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1859 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1860 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1861 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
1862 { "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
1863 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1864 { "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1865 { "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
1866 { "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },
1867
1868 { "macchw",     XO(4,172,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1869 { "macchw.",    XO(4,172,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1870 { "macchwo",    XO(4,172,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1871 { "macchwo.",   XO(4,172,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1872 { "macchws",    XO(4,236,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1873 { "macchws.",   XO(4,236,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1874 { "macchwso",   XO(4,236,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1875 { "macchwso.",  XO(4,236,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1876 { "macchwsu",   XO(4,204,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1877 { "macchwsu.",  XO(4,204,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1878 { "macchwsuo",  XO(4,204,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1879 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1880 { "macchwu",    XO(4,140,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1881 { "macchwu.",   XO(4,140,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1882 { "macchwuo",   XO(4,140,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1883 { "macchwuo.",  XO(4,140,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1884 { "machhw",     XO(4,44,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1885 { "machhw.",    XO(4,44,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1886 { "machhwo",    XO(4,44,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1887 { "machhwo.",   XO(4,44,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1888 { "machhws",    XO(4,108,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1889 { "machhws.",   XO(4,108,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1890 { "machhwso",   XO(4,108,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1891 { "machhwso.",  XO(4,108,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1892 { "machhwsu",   XO(4,76,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1893 { "machhwsu.",  XO(4,76,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1894 { "machhwsuo",  XO(4,76,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1895 { "machhwsuo.", XO(4,76,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1896 { "machhwu",    XO(4,12,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1897 { "machhwu.",   XO(4,12,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1898 { "machhwuo",   XO(4,12,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1899 { "machhwuo.",  XO(4,12,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1900 { "maclhw",     XO(4,428,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1901 { "maclhw.",    XO(4,428,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1902 { "maclhwo",    XO(4,428,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1903 { "maclhwo.",   XO(4,428,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1904 { "maclhws",    XO(4,492,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1905 { "maclhws.",   XO(4,492,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1906 { "maclhwso",   XO(4,492,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1907 { "maclhwso.",  XO(4,492,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1908 { "maclhwsu",   XO(4,460,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1909 { "maclhwsu.",  XO(4,460,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1910 { "maclhwsuo",  XO(4,460,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1911 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1912 { "maclhwu",    XO(4,396,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1913 { "maclhwu.",   XO(4,396,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1914 { "maclhwuo",   XO(4,396,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1915 { "maclhwuo.",  XO(4,396,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1916 { "mulchw",     XRC(4,168,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1917 { "mulchw.",    XRC(4,168,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1918 { "mulchwu",    XRC(4,136,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1919 { "mulchwu.",   XRC(4,136,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1920 { "mulhhw",     XRC(4,40,0),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1921 { "mulhhw.",    XRC(4,40,1),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1922 { "mulhhwu",    XRC(4,8,0),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1923 { "mulhhwu.",   XRC(4,8,1),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1924 { "mullhw",     XRC(4,424,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1925 { "mullhw.",    XRC(4,424,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1926 { "mullhwu",    XRC(4,392,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1927 { "mullhwu.",   XRC(4,392,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1928 { "nmacchw",    XO(4,174,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1929 { "nmacchw.",   XO(4,174,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1930 { "nmacchwo",   XO(4,174,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1931 { "nmacchwo.",  XO(4,174,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1932 { "nmacchws",   XO(4,238,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1933 { "nmacchws.",  XO(4,238,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1934 { "nmacchwso",  XO(4,238,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1935 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1936 { "nmachhw",    XO(4,46,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1937 { "nmachhw.",   XO(4,46,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1938 { "nmachhwo",   XO(4,46,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1939 { "nmachhwo.",  XO(4,46,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1940 { "nmachhws",   XO(4,110,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1941 { "nmachhws.",  XO(4,110,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1942 { "nmachhwso",  XO(4,110,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1943 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1944 { "nmaclhw",    XO(4,430,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1945 { "nmaclhw.",   XO(4,430,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1946 { "nmaclhwo",   XO(4,430,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1947 { "nmaclhwo.",  XO(4,430,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1948 { "nmaclhws",   XO(4,494,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1949 { "nmaclhws.",  XO(4,494,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1950 { "nmaclhwso",  XO(4,494,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1951 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1952 { "mfvscr",  VX(4, 1540), VX_MASK,      PPCVEC,         { VD } },
1953 { "mtvscr",  VX(4, 1604), VX_MASK,      PPCVEC,         { VB } },
1954 { "vaddcuw", VX(4,  384), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1955 { "vaddfp",  VX(4,   10), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1956 { "vaddsbs", VX(4,  768), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1957 { "vaddshs", VX(4,  832), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1958 { "vaddsws", VX(4,  896), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1959 { "vaddubm", VX(4,    0), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1960 { "vaddubs", VX(4,  512), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1961 { "vadduhm", VX(4,   64), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1962 { "vadduhs", VX(4,  576), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1963 { "vadduwm", VX(4,  128), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1964 { "vadduws", VX(4,  640), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1965 { "vand",    VX(4, 1028), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1966 { "vandc",   VX(4, 1092), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1967 { "vavgsb",  VX(4, 1282), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1968 { "vavgsh",  VX(4, 1346), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1969 { "vavgsw",  VX(4, 1410), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1970 { "vavgub",  VX(4, 1026), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1971 { "vavguh",  VX(4, 1090), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1972 { "vavguw",  VX(4, 1154), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1973 { "vcfsx",   VX(4,  842), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1974 { "vcfux",   VX(4,  778), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1975 { "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1976 { "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1977 { "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1978 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1979 { "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1980 { "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1981 { "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1982 { "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1983 { "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1984 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1985 { "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1986 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1987 { "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1988 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1989 { "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1990 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1991 { "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1992 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1993 { "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1994 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1995 { "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1996 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1997 { "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1998 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1999 { "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2000 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
2001 { "vctsxs",    VX(4,  970), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2002 { "vctuxs",    VX(4,  906), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2003 { "vexptefp",  VX(4,  394), VX_MASK,    PPCVEC,         { VD, VB } },
2004 { "vlogefp",   VX(4,  458), VX_MASK,    PPCVEC,         { VD, VB } },
2005 { "vmaddfp",   VXA(4,  46), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
2006 { "vmaxfp",    VX(4, 1034), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2007 { "vmaxsb",    VX(4,  258), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2008 { "vmaxsh",    VX(4,  322), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2009 { "vmaxsw",    VX(4,  386), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2010 { "vmaxub",    VX(4,    2), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2011 { "vmaxuh",    VX(4,   66), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2012 { "vmaxuw",    VX(4,  130), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2013 { "vmhaddshs", VXA(4,  32), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2014 { "vmhraddshs", VXA(4, 33), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2015 { "vminfp",    VX(4, 1098), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2016 { "vminsb",    VX(4,  770), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2017 { "vminsh",    VX(4,  834), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2018 { "vminsw",    VX(4,  898), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2019 { "vminub",    VX(4,  514), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2020 { "vminuh",    VX(4,  578), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2021 { "vminuw",    VX(4,  642), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2022 { "vmladduhm", VXA(4,  34), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2023 { "vmrghb",    VX(4,   12), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2024 { "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2025 { "vmrghw",    VX(4,  140), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2026 { "vmrglb",    VX(4,  268), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2027 { "vmrglh",    VX(4,  332), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2028 { "vmrglw",    VX(4,  396), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2029 { "vmsummbm",  VXA(4,  37), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2030 { "vmsumshm",  VXA(4,  40), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2031 { "vmsumshs",  VXA(4,  41), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2032 { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2033 { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2034 { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2035 { "vmulesb",   VX(4,  776), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2036 { "vmulesh",   VX(4,  840), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2037 { "vmuleub",   VX(4,  520), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2038 { "vmuleuh",   VX(4,  584), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2039 { "vmulosb",   VX(4,  264), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2040 { "vmulosh",   VX(4,  328), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2041 { "vmuloub",   VX(4,    8), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2042 { "vmulouh",   VX(4,   72), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2043 { "vnmsubfp",  VXA(4,  47), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
2044 { "vnor",      VX(4, 1284), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2045 { "vor",       VX(4, 1156), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2046 { "vperm",     VXA(4,  43), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2047 { "vpkpx",     VX(4,  782), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2048 { "vpkshss",   VX(4,  398), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2049 { "vpkshus",   VX(4,  270), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2050 { "vpkswss",   VX(4,  462), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2051 { "vpkswus",   VX(4,  334), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2052 { "vpkuhum",   VX(4,   14), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2053 { "vpkuhus",   VX(4,  142), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2054 { "vpkuwum",   VX(4,   78), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2055 { "vpkuwus",   VX(4,  206), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2056 { "vrefp",     VX(4,  266), VX_MASK,    PPCVEC,         { VD, VB } },
2057 { "vrfim",     VX(4,  714), VX_MASK,    PPCVEC,         { VD, VB } },
2058 { "vrfin",     VX(4,  522), VX_MASK,    PPCVEC,         { VD, VB } },
2059 { "vrfip",     VX(4,  650), VX_MASK,    PPCVEC,         { VD, VB } },
2060 { "vrfiz",     VX(4,  586), VX_MASK,    PPCVEC,         { VD, VB } },
2061 { "vrlb",      VX(4,    4), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2062 { "vrlh",      VX(4,   68), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2063 { "vrlw",      VX(4,  132), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2064 { "vrsqrtefp", VX(4,  330), VX_MASK,    PPCVEC,         { VD, VB } },
2065 { "vsel",      VXA(4,  42), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
2066 { "vsl",       VX(4,  452), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2067 { "vslb",      VX(4,  260), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2068 { "vsldoi",    VXA(4,  44), VXA_MASK,   PPCVEC,         { VD, VA, VB, SHB } },
2069 { "vslh",      VX(4,  324), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2070 { "vslo",      VX(4, 1036), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2071 { "vslw",      VX(4,  388), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2072 { "vspltb",    VX(4,  524), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2073 { "vsplth",    VX(4,  588), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2074 { "vspltisb",  VX(4,  780), VX_MASK,    PPCVEC,         { VD, SIMM } },
2075 { "vspltish",  VX(4,  844), VX_MASK,    PPCVEC,         { VD, SIMM } },
2076 { "vspltisw",  VX(4,  908), VX_MASK,    PPCVEC,         { VD, SIMM } },
2077 { "vspltw",    VX(4,  652), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
2078 { "vsr",       VX(4,  708), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2079 { "vsrab",     VX(4,  772), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2080 { "vsrah",     VX(4,  836), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2081 { "vsraw",     VX(4,  900), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2082 { "vsrb",      VX(4,  516), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2083 { "vsrh",      VX(4,  580), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2084 { "vsro",      VX(4, 1100), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2085 { "vsrw",      VX(4,  644), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2086 { "vsubcuw",   VX(4, 1408), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2087 { "vsubfp",    VX(4,   74), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2088 { "vsubsbs",   VX(4, 1792), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2089 { "vsubshs",   VX(4, 1856), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2090 { "vsubsws",   VX(4, 1920), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2091 { "vsububm",   VX(4, 1024), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2092 { "vsububs",   VX(4, 1536), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2093 { "vsubuhm",   VX(4, 1088), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2094 { "vsubuhs",   VX(4, 1600), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2095 { "vsubuwm",   VX(4, 1152), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2096 { "vsubuws",   VX(4, 1664), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2097 { "vsumsws",   VX(4, 1928), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2098 { "vsum2sws",  VX(4, 1672), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2099 { "vsum4sbs",  VX(4, 1800), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2100 { "vsum4shs",  VX(4, 1608), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2101 { "vsum4ubs",  VX(4, 1544), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2102 { "vupkhpx",   VX(4,  846), VX_MASK,    PPCVEC,         { VD, VB } },
2103 { "vupkhsb",   VX(4,  526), VX_MASK,    PPCVEC,         { VD, VB } },
2104 { "vupkhsh",   VX(4,  590), VX_MASK,    PPCVEC,         { VD, VB } },
2105 { "vupklpx",   VX(4,  974), VX_MASK,    PPCVEC,         { VD, VB } },
2106 { "vupklsb",   VX(4,  654), VX_MASK,    PPCVEC,         { VD, VB } },
2107 { "vupklsh",   VX(4,  718), VX_MASK,    PPCVEC,         { VD, VB } },
2108 { "vxor",      VX(4, 1220), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2109
2110 { "evaddw",    VX(4, 512), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2111 { "evaddiw",   VX(4, 514), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
2112 { "evsubfw",   VX(4, 516), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2113 { "evsubw",    VX(4, 516), VX_MASK,     PPCSPE,         { RS, RB, RA } },
2114 { "evsubifw",  VX(4, 518), VX_MASK,     PPCSPE,         { RS, UIMM, RB } },
2115 { "evsubiw",   VX(4, 518), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
2116 { "evabs",     VX(4, 520), VX_MASK,     PPCSPE,         { RS, RA } },
2117 { "evneg",     VX(4, 521), VX_MASK,     PPCSPE,         { RS, RA } },
2118 { "evextsb",   VX(4, 522), VX_MASK,     PPCSPE,         { RS, RA } },
2119 { "evextsh",   VX(4, 523), VX_MASK,     PPCSPE,         { RS, RA } },
2120 { "evrndw",    VX(4, 524), VX_MASK,     PPCSPE,         { RS, RA } },
2121 { "evcntlzw",  VX(4, 525), VX_MASK,     PPCSPE,         { RS, RA } },
2122 { "evcntlsw",  VX(4, 526), VX_MASK,     PPCSPE,         { RS, RA } },
2123
2124 { "brinc",     VX(4, 527), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2125
2126 { "evand",     VX(4, 529), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2127 { "evandc",    VX(4, 530), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2128 { "evmr",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2129 { "evor",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2130 { "evorc",     VX(4, 539), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2131 { "evxor",     VX(4, 534), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2132 { "eveqv",     VX(4, 537), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2133 { "evnand",    VX(4, 542), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2134 { "evnot",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2135 { "evnor",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2136
2137 { "evrlw",     VX(4, 552), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2138 { "evrlwi",    VX(4, 554), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2139 { "evslw",     VX(4, 548), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2140 { "evslwi",    VX(4, 550), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2141 { "evsrws",    VX(4, 545), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2142 { "evsrwu",    VX(4, 544), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2143 { "evsrwis",   VX(4, 547), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2144 { "evsrwiu",   VX(4, 546), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2145 { "evsplati",  VX(4, 553), VX_MASK,     PPCSPE,         { RS, SIMM } },
2146 { "evsplatfi", VX(4, 555), VX_MASK,     PPCSPE,         { RS, SIMM } },
2147 { "evmergehi", VX(4, 556), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2148 { "evmergelo", VX(4, 557), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2149 { "evmergehilo",VX(4,558), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2150 { "evmergelohi",VX(4,559), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2151
2152 { "evcmpgts",  VX(4, 561), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2153 { "evcmpgtu",  VX(4, 560), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2154 { "evcmplts",  VX(4, 563), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2155 { "evcmpltu",  VX(4, 562), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2156 { "evcmpeq",   VX(4, 564), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2157 { "evsel",     EVSEL(4,79),EVSEL_MASK,  PPCSPE,         { RS, RA, RB, CRFS } },
2158
2159 { "evldd",     VX(4, 769), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2160 { "evlddx",    VX(4, 768), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2161 { "evldw",     VX(4, 771), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2162 { "evldwx",    VX(4, 770), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2163 { "evldh",     VX(4, 773), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2164 { "evldhx",    VX(4, 772), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2165 { "evlwhe",    VX(4, 785), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2166 { "evlwhex",   VX(4, 784), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2167 { "evlwhou",   VX(4, 789), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2168 { "evlwhoux",  VX(4, 788), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2169 { "evlwhos",   VX(4, 791), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2170 { "evlwhosx",  VX(4, 790), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2171 { "evlwwsplat",VX(4, 793), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2172 { "evlwwsplatx",VX(4, 792), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2173 { "evlwhsplat",VX(4, 797), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2174 { "evlwhsplatx",VX(4, 796), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2175 { "evlhhesplat",VX(4, 777), VX_MASK,    PPCSPE,         { RS, EVUIMM_2, RA } },
2176 { "evlhhesplatx",VX(4, 776), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2177 { "evlhhousplat",VX(4, 781), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2178 { "evlhhousplatx",VX(4, 780), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2179 { "evlhhossplat",VX(4, 783), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2180 { "evlhhossplatx",VX(4, 782), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2181
2182 { "evstdd",    VX(4, 801), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2183 { "evstddx",   VX(4, 800), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2184 { "evstdw",    VX(4, 803), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2185 { "evstdwx",   VX(4, 802), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2186 { "evstdh",    VX(4, 805), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2187 { "evstdhx",   VX(4, 804), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2188 { "evstwwe",   VX(4, 825), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2189 { "evstwwex",  VX(4, 824), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2190 { "evstwwo",   VX(4, 829), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2191 { "evstwwox",  VX(4, 828), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2192 { "evstwhe",   VX(4, 817), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2193 { "evstwhex",  VX(4, 816), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2194 { "evstwho",   VX(4, 821), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2195 { "evstwhox",  VX(4, 820), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2196
2197 { "evfsabs",   VX(4, 644), VX_MASK,     PPCSPE,         { RS, RA } },
2198 { "evfsnabs",  VX(4, 645), VX_MASK,     PPCSPE,         { RS, RA } },
2199 { "evfsneg",   VX(4, 646), VX_MASK,     PPCSPE,         { RS, RA } },
2200 { "evfsadd",   VX(4, 640), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2201 { "evfssub",   VX(4, 641), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2202 { "evfsmul",   VX(4, 648), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2203 { "evfsdiv",   VX(4, 649), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2204 { "evfscmpgt", VX(4, 652), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2205 { "evfscmplt", VX(4, 653), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2206 { "evfscmpeq", VX(4, 654), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2207 { "evfststgt", VX(4, 668), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2208 { "evfststlt", VX(4, 669), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2209 { "evfststeq", VX(4, 670), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2210 { "evfscfui",  VX(4, 656), VX_MASK,     PPCSPE,         { RS, RB } },
2211 { "evfsctuiz", VX(4, 664), VX_MASK,     PPCSPE,         { RS, RB } },
2212 { "evfscfsi",  VX(4, 657), VX_MASK,     PPCSPE,         { RS, RB } },
2213 { "evfscfuf",  VX(4, 658), VX_MASK,     PPCSPE,         { RS, RB } },
2214 { "evfscfsf",  VX(4, 659), VX_MASK,     PPCSPE,         { RS, RB } },
2215 { "evfsctui",  VX(4, 660), VX_MASK,     PPCSPE,         { RS, RB } },
2216 { "evfsctsi",  VX(4, 661), VX_MASK,     PPCSPE,         { RS, RB } },
2217 { "evfsctsiz", VX(4, 666), VX_MASK,     PPCSPE,         { RS, RB } },
2218 { "evfsctuf",  VX(4, 662), VX_MASK,     PPCSPE,         { RS, RB } },
2219 { "evfsctsf",  VX(4, 663), VX_MASK,     PPCSPE,         { RS, RB } },
2220
2221 { "efsabs",   VX(4, 708), VX_MASK,      PPCEFS,         { RS, RA } },
2222 { "efsnabs",  VX(4, 709), VX_MASK,      PPCEFS,         { RS, RA } },
2223 { "efsneg",   VX(4, 710), VX_MASK,      PPCEFS,         { RS, RA } },
2224 { "efsadd",   VX(4, 704), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2225 { "efssub",   VX(4, 705), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2226 { "efsmul",   VX(4, 712), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2227 { "efsdiv",   VX(4, 713), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2228 { "efscmpgt", VX(4, 716), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2229 { "efscmplt", VX(4, 717), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2230 { "efscmpeq", VX(4, 718), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2231 { "efststgt", VX(4, 732), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2232 { "efststlt", VX(4, 733), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2233 { "efststeq", VX(4, 734), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2234 { "efscfui",  VX(4, 720), VX_MASK,      PPCEFS,         { RS, RB } },
2235 { "efsctuiz", VX(4, 728), VX_MASK,      PPCEFS,         { RS, RB } },
2236 { "efscfsi",  VX(4, 721), VX_MASK,      PPCEFS,         { RS, RB } },
2237 { "efscfuf",  VX(4, 722), VX_MASK,      PPCEFS,         { RS, RB } },
2238 { "efscfsf",  VX(4, 723), VX_MASK,      PPCEFS,         { RS, RB } },
2239 { "efsctui",  VX(4, 724), VX_MASK,      PPCEFS,         { RS, RB } },
2240 { "efsctsi",  VX(4, 725), VX_MASK,      PPCEFS,         { RS, RB } },
2241 { "efsctsiz", VX(4, 730), VX_MASK,      PPCEFS,         { RS, RB } },
2242 { "efsctuf",  VX(4, 726), VX_MASK,      PPCEFS,         { RS, RB } },
2243 { "efsctsf",  VX(4, 727), VX_MASK,      PPCEFS,         { RS, RB } },
2244
2245 { "evmhossf",  VX(4, 1031), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2246 { "evmhossfa", VX(4, 1063), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2247 { "evmhosmf",  VX(4, 1039), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2248 { "evmhosmfa", VX(4, 1071), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2249 { "evmhosmi",  VX(4, 1037), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2250 { "evmhosmia", VX(4, 1069), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2251 { "evmhoumi",  VX(4, 1036), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2252 { "evmhoumia", VX(4, 1068), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2253 { "evmhessf",  VX(4, 1027), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2254 { "evmhessfa", VX(4, 1059), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2255 { "evmhesmf",  VX(4, 1035), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2256 { "evmhesmfa", VX(4, 1067), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2257 { "evmhesmi",  VX(4, 1033), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2258 { "evmhesmia", VX(4, 1065), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2259 { "evmheumi",  VX(4, 1032), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2260 { "evmheumia", VX(4, 1064), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2261
2262 { "evmhossfaaw",VX(4, 1287), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2263 { "evmhossiaaw",VX(4, 1285), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2264 { "evmhosmfaaw",VX(4, 1295), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2265 { "evmhosmiaaw",VX(4, 1293), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2266 { "evmhousiaaw",VX(4, 1284), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2267 { "evmhoumiaaw",VX(4, 1292), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2268 { "evmhessfaaw",VX(4, 1283), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2269 { "evmhessiaaw",VX(4, 1281), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2270 { "evmhesmfaaw",VX(4, 1291), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2271 { "evmhesmiaaw",VX(4, 1289), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2272 { "evmheusiaaw",VX(4, 1280), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2273 { "evmheumiaaw",VX(4, 1288), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2274
2275 { "evmhossfanw",VX(4, 1415), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2276 { "evmhossianw",VX(4, 1413), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2277 { "evmhosmfanw",VX(4, 1423), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2278 { "evmhosmianw",VX(4, 1421), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2279 { "evmhousianw",VX(4, 1412), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2280 { "evmhoumianw",VX(4, 1420), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2281 { "evmhessfanw",VX(4, 1411), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2282 { "evmhessianw",VX(4, 1409), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2283 { "evmhesmfanw",VX(4, 1419), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2284 { "evmhesmianw",VX(4, 1417), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2285 { "evmheusianw",VX(4, 1408), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2286 { "evmheumianw",VX(4, 1416), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2287
2288 { "evmhogsmfaa",VX(4, 1327), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2289 { "evmhogsmiaa",VX(4, 1325), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2290 { "evmhogumiaa",VX(4, 1324), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2291 { "evmhegsmfaa",VX(4, 1323), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2292 { "evmhegsmiaa",VX(4, 1321), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2293 { "evmhegumiaa",VX(4, 1320), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2294
2295 { "evmhogsmfan",VX(4, 1455), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2296 { "evmhogsmian",VX(4, 1453), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2297 { "evmhogumian",VX(4, 1452), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2298 { "evmhegsmfan",VX(4, 1451), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2299 { "evmhegsmian",VX(4, 1449), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2300 { "evmhegumian",VX(4, 1448), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2301
2302 { "evmwhssf",  VX(4, 1095), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2303 { "evmwhssfa", VX(4, 1127), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2304 { "evmwhsmf",  VX(4, 1103), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2305 { "evmwhsmfa", VX(4, 1135), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2306 { "evmwhsmi",  VX(4, 1101), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2307 { "evmwhsmia", VX(4, 1133), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2308 { "evmwhumi",  VX(4, 1100), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2309 { "evmwhumia", VX(4, 1132), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2310
2311 { "evmwlumi",  VX(4, 1096), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2312 { "evmwlumia", VX(4, 1128), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2313
2314 { "evmwlssiaaw",VX(4, 1345), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2315 { "evmwlsmiaaw",VX(4, 1353), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2316 { "evmwlusiaaw",VX(4, 1344), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2317 { "evmwlumiaaw",VX(4, 1352), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2318
2319 { "evmwlssianw",VX(4, 1473), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2320 { "evmwlsmianw",VX(4, 1481), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2321 { "evmwlusianw",VX(4, 1472), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2322 { "evmwlumianw",VX(4, 1480), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2323
2324 { "evmwssf",   VX(4, 1107), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2325 { "evmwssfa",  VX(4, 1139), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2326 { "evmwsmf",   VX(4, 1115), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2327 { "evmwsmfa",  VX(4, 1147), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2328 { "evmwsmi",   VX(4, 1113), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2329 { "evmwsmia",  VX(4, 1145), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2330 { "evmwumi",   VX(4, 1112), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2331 { "evmwumia",  VX(4, 1144), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2332
2333 { "evmwssfaa", VX(4, 1363), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2334 { "evmwsmfaa", VX(4, 1371), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2335 { "evmwsmiaa", VX(4, 1369), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2336 { "evmwumiaa", VX(4, 1368), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2337
2338 { "evmwssfan", VX(4, 1491), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2339 { "evmwsmfan", VX(4, 1499), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2340 { "evmwsmian", VX(4, 1497), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2341 { "evmwumian", VX(4, 1496), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2342
2343 { "evaddssiaaw",VX(4, 1217), VX_MASK,   PPCSPE,         { RS, RA } },
2344 { "evaddsmiaaw",VX(4, 1225), VX_MASK,   PPCSPE,         { RS, RA } },
2345 { "evaddusiaaw",VX(4, 1216), VX_MASK,   PPCSPE,         { RS, RA } },
2346 { "evaddumiaaw",VX(4, 1224), VX_MASK,   PPCSPE,         { RS, RA } },
2347
2348 { "evsubfssiaaw",VX(4, 1219), VX_MASK,  PPCSPE,         { RS, RA } },
2349 { "evsubfsmiaaw",VX(4, 1227), VX_MASK,  PPCSPE,         { RS, RA } },
2350 { "evsubfusiaaw",VX(4, 1218), VX_MASK,  PPCSPE,         { RS, RA } },
2351 { "evsubfumiaaw",VX(4, 1226), VX_MASK,  PPCSPE,         { RS, RA } },
2352
2353 { "evmra",    VX(4, 1220), VX_MASK,     PPCSPE,         { RS, RA } },
2354
2355 { "evdivws",  VX(4, 1222), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2356 { "evdivwu",  VX(4, 1223), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2357
2358 { "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2359 { "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2360
2361 { "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2362 { "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2363
2364 { "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },
2365
2366 { "bce",     B(9,0,0),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2367 { "bcel",    B(9,0,1),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2368 { "bcea",    B(9,1,0),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2369 { "bcela",   B(9,1,1),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2370
2371 { "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
2372 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
2373 { "cmpli",   OP(10),    OP_MASK,        PPC,            { BF, L, RA, UI } },
2374 { "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },
2375
2376 { "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
2377 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
2378 { "cmpi",    OP(11),    OP_MASK,        PPC,            { BF, L, RA, SI } },
2379 { "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },
2380
2381 { "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2382 { "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2383 { "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2384
2385 { "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2386 { "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2387 { "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2388
2389 { "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
2390 { "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
2391 { "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA0, SI } },
2392 { "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
2393 { "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA0, NSI } },
2394 { "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA0 } },
2395
2396 { "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
2397 { "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
2398 { "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA0,SISIGNOPT } },
2399 { "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA0,SISIGNOPT } },
2400 { "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA0, NSI } },
2401
2402 { "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDM } },
2403 { "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDP } },
2404 { "bdnz",    BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BD } },
2405 { "bdn",     BBO(16,BODNZ,0,0),      BBOATBI_MASK, PWRCOM,      { BD } },
2406 { "bdnzl-",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDM } },
2407 { "bdnzl+",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDP } },
2408 { "bdnzl",   BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BD } },
2409 { "bdnl",    BBO(16,BODNZ,0,1),      BBOATBI_MASK, PWRCOM,      { BD } },
2410 { "bdnza-",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDMA } },
2411 { "bdnza+",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDPA } },
2412 { "bdnza",   BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDA } },
2413 { "bdna",    BBO(16,BODNZ,1,0),      BBOATBI_MASK, PWRCOM,      { BDA } },
2414 { "bdnzla-", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDMA } },
2415 { "bdnzla+", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDPA } },
2416 { "bdnzla",  BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDA } },
2417 { "bdnla",   BBO(16,BODNZ,1,1),      BBOATBI_MASK, PWRCOM,      { BDA } },
2418 { "bdz-",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDM } },
2419 { "bdz+",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDP } },
2420 { "bdz",     BBO(16,BODZ,0,0),       BBOATBI_MASK, COM,         { BD } },
2421 { "bdzl-",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDM } },
2422 { "bdzl+",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDP } },
2423 { "bdzl",    BBO(16,BODZ,0,1),       BBOATBI_MASK, COM,         { BD } },
2424 { "bdza-",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDMA } },
2425 { "bdza+",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDPA } },
2426 { "bdza",    BBO(16,BODZ,1,0),       BBOATBI_MASK, COM,         { BDA } },
2427 { "bdzla-",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDMA } },
2428 { "bdzla+",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDPA } },
2429 { "bdzla",   BBO(16,BODZ,1,1),       BBOATBI_MASK, COM,         { BDA } },
2430 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2431 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2432 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2433 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2434 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2435 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2436 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2437 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2438 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2439 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2440 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2441 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2442 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2443 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2444 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2445 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2446 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2447 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2448 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2449 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2450 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2451 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2452 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2453 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2454 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2455 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2456 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2457 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2458 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2459 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2460 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2461 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2462 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2463 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2464 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2465 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2466 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2467 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2468 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2469 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2470 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2471 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2472 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2473 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2474 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2475 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2476 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2477 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2478 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2479 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2480 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2481 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2482 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2483 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2484 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2485 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2486 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2487 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2488 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2489 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2490 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2491 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2492 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2493 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2494 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2495 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2496 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2497 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2498 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2499 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2500 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2501 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2502 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2503 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2504 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2505 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2506 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2507 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2508 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2509 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2510 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2511 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2512 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2513 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2514 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2515 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2516 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2517 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2518 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2519 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2520 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2521 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2522 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2523 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2524 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2525 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2526 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2527 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2528 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2529 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2530 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2531 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2532 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2533 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2534 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2535 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2536 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2537 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2538 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2539 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2540 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2541 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2542 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2543 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2544 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2545 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2546 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2547 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2548 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2549 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2550 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2551 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2552 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2553 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2554 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2555 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2556 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2557 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2558 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2559 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2560 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2561 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2562 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2563 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2564 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2565 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2566 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2567 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2568 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2569 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2570 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2571 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2572 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2573 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2574 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2575 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2576 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2577 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2578 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2579 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2580 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2581 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2582 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2583 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2584 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2585 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2586 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2587 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2588 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2589 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2590 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2591 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2592 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2593 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2594 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2595 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2596 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2597 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2598 { "bt-",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2599 { "bt+",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2600 { "bt",      BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2601 { "bbt",     BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2602 { "btl-",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2603 { "btl+",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2604 { "btl",     BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2605 { "bbtl",    BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2606 { "bta-",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2607 { "bta+",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2608 { "bta",     BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2609 { "bbta",    BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2610 { "btla-",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2611 { "btla+",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2612 { "btla",    BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2613 { "bbtla",   BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2614 { "bf-",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2615 { "bf+",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2616 { "bf",      BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2617 { "bbf",     BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2618 { "bfl-",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2619 { "bfl+",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2620 { "bfl",     BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2621 { "bbfl",    BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2622 { "bfa-",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2623 { "bfa+",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2624 { "bfa",     BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2625 { "bbfa",    BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2626 { "bfla-",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2627 { "bfla+",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2628 { "bfla",    BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2629 { "bbfla",   BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2630 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2631 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2632 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2633 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2634 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2635 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2636 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2637 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2638 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2639 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2640 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2641 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2642 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2643 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2644 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2645 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2646 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2647 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2648 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2649 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2650 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2651 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2652 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2653 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2654 { "bc-",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2655 { "bc+",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2656 { "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
2657 { "bcl-",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2658 { "bcl+",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2659 { "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
2660 { "bca-",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2661 { "bca+",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2662 { "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
2663 { "bcla-",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2664 { "bcla+",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2665 { "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },
2666
2667 { "sc",      SC(17,1,0), 0xffffffff,    PPC,            { 0 } },
2668 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2669 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2670 { "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
2671 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
2672
2673 { "b",       B(18,0,0), B_MASK,         COM,            { LI } },
2674 { "bl",      B(18,0,1), B_MASK,         COM,            { LI } },
2675 { "ba",      B(18,1,0), B_MASK,         COM,            { LIA } },
2676 { "bla",     B(18,1,1), B_MASK,         COM,            { LIA } },
2677
2678 { "mcrf",    XL(19,0),  XLBB_MASK|(3 << 21)|(3 << 16), COM,     { BF, BFA } },
2679
2680 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2681 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2682 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2683 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2684 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2685 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2686 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2687 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2688 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2689 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2690 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2691 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2692 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2693 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2694 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2695 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2696 { "bdzlr-",  XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2697 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2698 { "bdzlr+",  XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2699 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2700 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2701 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2702 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2703 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2704 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2705 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2706 { "bltlr-",  XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2707 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2708 { "bltlr+",  XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2709 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2710 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2711 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2712 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2713 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2714 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2715 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2716 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2717 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2718 { "bgtlr-",  XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2719 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2720 { "bgtlr+",  XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2721 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2722 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2723 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2724 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2725 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2726 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2727 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2728 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2729 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2730 { "beqlr-",  XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2731 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2732 { "beqlr+",  XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2733 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2734 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2735 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2736 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2737 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2738 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2739 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2740 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2741 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2742 { "bsolr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2743 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2744 { "bsolr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2745 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2746 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2747 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2748 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2749 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2750 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2751 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2752 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2753 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2754 { "bunlr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2755 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2756 { "bunlr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2757 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2758 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2759 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2760 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2761 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2762 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2763 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2764 { "bgelr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2765 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2766 { "bgelr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2767 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2768 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2769 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2770 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2771 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2772 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2773 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2774 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2775 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2776 { "bnllr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2777 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2778 { "bnllr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2779 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2780 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2781 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2782 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2783 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2784 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2785 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2786 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2787 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2788 { "blelr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2789 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2790 { "blelr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2791 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2792 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2793 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2794 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2795 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2796 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2797 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2798 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2799 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2800 { "bnglr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2801 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2802 { "bnglr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2803 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2804 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2805 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2806 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2807 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2808 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2809 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2810 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2811 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2812 { "bnelr-",  XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2813 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2814 { "bnelr+",  XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2815 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2816 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2817 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2818 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2819 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2820 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2821 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2822 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2823 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2824 { "bnslr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2825 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2826 { "bnslr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2827 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2828 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2829 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2830 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2831 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2832 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2833 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2834 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2835 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2836 { "bnulr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2837 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2838 { "bnulr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2839 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2840 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2841 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2842 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2843 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2844 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2845 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2846 { "btlr-",   XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2847 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2848 { "btlr+",   XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2849 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2850 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2851 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2852 { "btlrl-",  XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2853 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2854 { "btlrl+",  XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2855 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2856 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2857 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2858 { "bflr-",   XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2859 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2860 { "bflr+",   XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2861 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2862 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2863 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2864 { "bflrl-",  XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2865 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2866 { "bflrl+",  XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2867 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2868 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2869 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2870 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2871 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2872 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2873 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2874 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2875 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2876 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2877 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2878 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2879 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2880 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2881 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2882 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2883 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2884 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2885 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2886 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2887 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2888 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2889 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2890 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2891 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2892 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2893 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2894 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2895 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2896 { "bclr",    XLLK(19,16,0), XLBH_MASK,  PPCCOM,         { BO, BI, BH } },
2897 { "bclrl",   XLLK(19,16,1), XLBH_MASK,  PPCCOM,         { BO, BI, BH } },
2898 { "bcr",     XLLK(19,16,0), XLBB_MASK,  PWRCOM,         { BO, BI } },
2899 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  PWRCOM,         { BO, BI } },
2900 { "bclre",   XLLK(19,17,0), XLBB_MASK,  BOOKE64,        { BO, BI } },
2901 { "bclrel",  XLLK(19,17,1), XLBB_MASK,  BOOKE64,        { BO, BI } },
2902
2903 { "rfid",    XL(19,18), 0xffffffff,     PPC64,          { 0 } },
2904
2905 { "crnot",   XL(19,33), XL_MASK,        PPCCOM,         { BT, BA, BBA } },
2906 { "crnor",   XL(19,33), XL_MASK,        COM,            { BT, BA, BB } },
2907 { "rfmci",    X(19,38), 0xffffffff,     PPCRFMCI,       { 0 } },
2908
2909 { "rfi",     XL(19,50), 0xffffffff,     COM,            { 0 } },
2910 { "rfci",    XL(19,51), 0xffffffff,     PPC403 | BOOKE, { 0 } },
2911
2912 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
2913
2914 { "crandc",  XL(19,129), XL_MASK,       COM,            { BT, BA, BB } },
2915
2916 { "isync",   XL(19,150), 0xffffffff,    PPCCOM,         { 0 } },
2917 { "ics",     XL(19,150), 0xffffffff,    PWRCOM,         { 0 } },
2918
2919 { "crclr",   XL(19,193), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2920 { "crxor",   XL(19,193), XL_MASK,       COM,            { BT, BA, BB } },
2921
2922 { "crnand",  XL(19,225), XL_MASK,       COM,            { BT, BA, BB } },
2923
2924 { "crand",   XL(19,257), XL_MASK,       COM,            { BT, BA, BB } },
2925
2926 { "crset",   XL(19,289), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2927 { "creqv",   XL(19,289), XL_MASK,       COM,            { BT, BA, BB } },
2928
2929 { "crorc",   XL(19,417), XL_MASK,       COM,            { BT, BA, BB } },
2930
2931 { "crmove",  XL(19,449), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
2932 { "cror",    XL(19,449), XL_MASK,       COM,            { BT, BA, BB } },
2933
2934 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
2935 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
2936 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2937 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2938 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2939 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2940 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2941 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2942 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2943 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2944 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2945 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2946 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2947 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2948 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2949 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2950 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2951 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2952 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2953 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2954 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2955 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2956 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2957 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2958 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2959 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2960 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2961 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2962 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2963 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2964 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2965 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2966 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2967 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2968 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2969 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2970 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2971 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2972 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2973 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2974 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2975 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2976 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2977 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2978 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2979 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2980 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2981 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2982 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2983 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2984 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2985 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2986 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2987 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2988 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2989 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2990 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2991 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2992 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2993 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2994 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2995 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2996 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2997 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2998 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2999 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3000 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3001 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3002 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3003 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3004 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3005 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3006 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3007 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3008 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3009 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3010 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3011 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3012 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3013 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3014 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3015 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3016 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3017 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3018 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3019 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3020 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3021 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3022 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3023 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3024 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3025 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3026 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3027 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3028 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3029 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3030 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3031 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3032 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3033 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3034 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3035 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3036 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3037 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3038 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3039 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3040 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3041 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3042 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3043 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3044 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3045 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3046 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3047 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3048 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3049 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3050 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3051 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
3052 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3053 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3054 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3055 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3056 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
3057 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
3058 { "btctr-",  XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3059 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3060 { "btctr+",  XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3061 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
3062 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
3063 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3064 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3065 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3066 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
3067 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
3068 { "bfctr-",  XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3069 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3070 { "bfctr+",  XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3071 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
3072 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
3073 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3074 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3075 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3076 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3077 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3078 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3079 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
3080 { "bcctr",   XLLK(19,528,0),     XLBH_MASK,   PPCCOM,   { BO, BI, BH } },
3081 { "bcctrl",  XLLK(19,528,1),     XLBH_MASK,   PPCCOM,   { BO, BI, BH } },
3082 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
3083 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
3084 { "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
3085 { "bcctrel", XLLK(19,529,1),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
3086
3087 { "rlwimi",  M(20,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3088 { "rlimi",   M(20,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3089
3090 { "rlwimi.", M(20,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3091 { "rlimi.",  M(20,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3092
3093 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, SH } },
3094 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
3095 { "rlwinm",  M(21,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3096 { "rlinm",   M(21,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3097 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPCCOM,         { RA,RS,SH } },
3098 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
3099 { "rlwinm.", M(21,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3100 { "rlinm.",  M(21,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3101
3102 { "rlmi",    M(22,0),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
3103 { "rlmi.",   M(22,1),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
3104
3105 { "be",      B(22,0,0), B_MASK,         BOOKE64,        { LI } },
3106 { "bel",     B(22,0,1), B_MASK,         BOOKE64,        { LI } },
3107 { "bea",     B(22,1,0), B_MASK,         BOOKE64,        { LIA } },
3108 { "bela",    B(22,1,1), B_MASK,         BOOKE64,        { LIA } },
3109
3110 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
3111 { "rlwnm",   M(23,0),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
3112 { "rlnm",    M(23,0),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
3113 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
3114 { "rlwnm.",  M(23,1),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
3115 { "rlnm.",   M(23,1),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
3116
3117 { "nop",     OP(24),    0xffffffff,     PPCCOM,         { 0 } },
3118 { "ori",     OP(24),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3119 { "oril",    OP(24),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3120
3121 { "oris",    OP(25),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3122 { "oriu",    OP(25),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3123
3124 { "xori",    OP(26),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3125 { "xoril",   OP(26),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3126
3127 { "xoris",   OP(27),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3128 { "xoriu",   OP(27),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3129
3130 { "andi.",   OP(28),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3131 { "andil.",  OP(28),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3132
3133 { "andis.",  OP(29),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3134 { "andiu.",  OP(29),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3135
3136 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3137 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3138 { "rldicl",  MD(30,0,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3139 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3140 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3141 { "rldicl.", MD(30,0,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3142
3143 { "rldicr",  MD(30,1,0), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3144 { "rldicr.", MD(30,1,1), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3145
3146 { "rldic",   MD(30,2,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3147 { "rldic.",  MD(30,2,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3148
3149 { "rldimi",  MD(30,3,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3150 { "rldimi.", MD(30,3,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3151
3152 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3153 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3154 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3155 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3156
3157 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3158 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3159
3160 { "cmpw",    XOPL(31,0,0), XCMPL_MASK, PPCCOM,          { OBF, RA, RB } },
3161 { "cmpd",    XOPL(31,0,1), XCMPL_MASK, PPC64,           { OBF, RA, RB } },
3162 { "cmp",     X(31,0),   XCMP_MASK,      PPC,            { BF, L, RA, RB } },
3163 { "cmp",     X(31,0),   XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
3164
3165 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,         { RA, RB } },
3166 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,         { RA, RB } },
3167 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,         { RA, RB } },
3168 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,         { RA, RB } },
3169 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPCCOM,         { RA, RB } },
3170 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  PWRCOM,         { RA, RB } },
3171 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,         { RA, RB } },
3172 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,         { RA, RB } },
3173 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,         { RA, RB } },
3174 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,         { RA, RB } },
3175 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,         { RA, RB } },
3176 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,         { RA, RB } },
3177 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,         { RA, RB } },
3178 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,         { RA, RB } },
3179 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPCCOM,         { RA, RB } },
3180 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  PWRCOM,         { RA, RB } },
3181 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPCCOM,         { RA, RB } },
3182 { "tge",     XTO(31,4,TOGE), XTO_MASK,  PWRCOM,         { RA, RB } },
3183 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPCCOM,         { RA, RB } },
3184 { "tnl",     XTO(31,4,TONL), XTO_MASK,  PWRCOM,         { RA, RB } },
3185 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPCCOM,         { RA, RB } },
3186 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  PWRCOM,         { RA, RB } },
3187 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPCCOM,         { RA, RB } },
3188 { "tle",     XTO(31,4,TOLE), XTO_MASK,  PWRCOM,         { RA, RB } },
3189 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPCCOM,         { RA, RB } },
3190 { "tng",     XTO(31,4,TONG), XTO_MASK,  PWRCOM,         { RA, RB } },
3191 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPCCOM,         { RA, RB } },
3192 { "tne",     XTO(31,4,TONE), XTO_MASK,  PWRCOM,         { RA, RB } },
3193 { "trap",    XTO(31,4,TOU), 0xffffffff, PPCCOM,         { 0 } },
3194 { "tw",      X(31,4),   X_MASK,         PPCCOM,         { TO, RA, RB } },
3195 { "t",       X(31,4),   X_MASK,         PWRCOM,         { TO, RA, RB } },
3196
3197 { "subfc",   XO(31,8,0,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3198 { "sf",      XO(31,8,0,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3199 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
3200 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3201 { "sf.",     XO(31,8,0,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3202 { "subc.",   XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RB, RA } },
3203 { "subfco",  XO(31,8,1,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3204 { "sfo",     XO(31,8,1,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3205 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
3206 { "subfco.", XO(31,8,1,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3207 { "sfo.",    XO(31,8,1,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3208 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
3209
3210 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC64,          { RT, RA, RB } },
3211 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC64,          { RT, RA, RB } },
3212
3213 { "addc",    XO(31,10,0,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3214 { "a",       XO(31,10,0,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3215 { "addc.",   XO(31,10,0,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3216 { "a.",      XO(31,10,0,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3217 { "addco",   XO(31,10,1,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3218 { "ao",      XO(31,10,1,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3219 { "addco.",  XO(31,10,1,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3220 { "ao.",     XO(31,10,1,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3221
3222 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3223 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3224
3225 { "isellt",  X(31,15),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3226 { "iselgt",  X(31,47),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3227 { "iseleq",  X(31,79),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3228 { "isel",    XISEL(31,15),  XISEL_MASK, PPCISEL,        { RT, RA, RB, CRB } },
3229
3230 { "mfcr",    X(31,19),  XRARB_MASK,     NOPOWER4,       { RT } },
3231 { "mfcr",    X(31,19),  XFXFXM_MASK,    POWER4,         { RT, FXM4 } },
3232
3233 { "lwarx",   X(31,20),  X_MASK,         PPC,            { RT, RA0, RB } },
3234
3235 { "ldx",     X(31,21),  X_MASK,         PPC64,          { RT, RA0, RB } },
3236
3237 { "icbt",    X(31,22),  X_MASK,         BOOKE,          { CT, RA, RB } },
3238 { "icbt",    X(31,262), XRT_MASK,       PPC403,         { RA, RB } },
3239
3240 { "lwzx",    X(31,23),  X_MASK,         PPCCOM,         { RT, RA0, RB } },
3241 { "lx",      X(31,23),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3242
3243 { "slw",     XRC(31,24,0), X_MASK,      PPCCOM,         { RA, RS, RB } },
3244 { "sl",      XRC(31,24,0), X_MASK,      PWRCOM,         { RA, RS, RB } },
3245 { "slw.",    XRC(31,24,1), X_MASK,      PPCCOM,         { RA, RS, RB } },
3246 { "sl.",     XRC(31,24,1), X_MASK,      PWRCOM,         { RA, RS, RB } },
3247
3248 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPCCOM,         { RA, RS } },
3249 { "cntlz",   XRC(31,26,0), XRB_MASK,    PWRCOM,         { RA, RS } },
3250 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPCCOM,         { RA, RS } },
3251 { "cntlz.",  XRC(31,26,1), XRB_MASK,    PWRCOM,         { RA, RS } },
3252
3253 { "sld",     XRC(31,27,0), X_MASK,      PPC64,          { RA, RS, RB } },
3254 { "sld.",    XRC(31,27,1), X_MASK,      PPC64,          { RA, RS, RB } },
3255
3256 { "and",     XRC(31,28,0), X_MASK,      COM,            { RA, RS, RB } },
3257 { "and.",    XRC(31,28,1), X_MASK,      COM,            { RA, RS, RB } },
3258
3259 { "maskg",   XRC(31,29,0), X_MASK,      M601,           { RA, RS, RB } },
3260 { "maskg.",  XRC(31,29,1), X_MASK,      M601,           { RA, RS, RB } },
3261
3262 { "icbte",   X(31,30),  X_MASK,         BOOKE64,        { CT, RA, RB } },
3263
3264 { "lwzxe",   X(31,31),  X_MASK,         BOOKE64,        { RT, RA0, RB } },
3265
3266 { "cmplw",   XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3267 { "cmpld",   XOPL(31,32,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
3268 { "cmpl",    X(31,32),  XCMP_MASK,       PPC,           { BF, L, RA, RB } },
3269 { "cmpl",    X(31,32),  XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
3270
3271 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3272 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
3273 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3274 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
3275 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
3276 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
3277 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
3278 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
3279
3280 { "ldux",    X(31,53),  X_MASK,         PPC64,          { RT, RAL, RB } },
3281
3282 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
3283
3284 { "lwzux",   X(31,55),  X_MASK,         PPCCOM,         { RT, RAL, RB } },
3285 { "lux",     X(31,55),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3286
3287 { "dcbste",  X(31,62),  XRT_MASK,       BOOKE64,        { RA, RB } },
3288
3289 { "lwzuxe",  X(31,63),  X_MASK,         BOOKE64,        { RT, RAL, RB } },
3290
3291 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC64,          { RA, RS } },
3292 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC64,          { RA, RS } },
3293
3294 { "andc",    XRC(31,60,0), X_MASK,      COM,            { RA, RS, RB } },
3295 { "andc.",   XRC(31,60,1), X_MASK,      COM,            { RA, RS, RB } },
3296
3297 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,         { RA, RB } },
3298 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,         { RA, RB } },
3299 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,         { RA, RB } },
3300 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,         { RA, RB } },
3301 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,         { RA, RB } },
3302 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,         { RA, RB } },
3303 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,         { RA, RB } },
3304 { "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,         { RA, RB } },
3305 { "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,         { RA, RB } },
3306 { "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,         { RA, RB } },
3307 { "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,         { RA, RB } },
3308 { "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,         { RA, RB } },
3309 { "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,         { RA, RB } },
3310 { "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,         { RA, RB } },
3311 { "td",      X(31,68),  X_MASK,          PPC64,         { TO, RA, RB } },
3312
3313 { "mulhd",   XO(31,73,0,0), XO_MASK,     PPC64,         { RT, RA, RB } },
3314 { "mulhd.",  XO(31,73,0,1), XO_MASK,     PPC64,         { RT, RA, RB } },
3315
3316 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3317 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3318
3319 { "dlmzb",   XRC(31,78,0),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
3320 { "dlmzb.",  XRC(31,78,1),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
3321
3322 { "mtsrd",   X(31,82),  XRB_MASK|(1<<20), PPC64,        { SR, RS } },
3323
3324 { "mfmsr",   X(31,83),  XRARB_MASK,     COM,            { RT } },
3325
3326 { "ldarx",   X(31,84),  X_MASK,         PPC64,          { RT, RA0, RB } },
3327
3328 { "dcbf",    X(31,86),  XRT_MASK,       PPC,            { RA, RB } },
3329
3330 { "lbzx",    X(31,87),  X_MASK,         COM,            { RT, RA0, RB } },
3331
3332 { "dcbfe",   X(31,94),  XRT_MASK,       BOOKE64,        { RA, RB } },
3333
3334 { "lbzxe",   X(31,95),  X_MASK,         BOOKE64,        { RT, RA0, RB } },
3335
3336 { "neg",     XO(31,104,0,0), XORB_MASK, COM,            { RT, RA } },
3337 { "neg.",    XO(31,104,0,1), XORB_MASK, COM,            { RT, RA } },
3338 { "nego",    XO(31,104,1,0), XORB_MASK, COM,            { RT, RA } },
3339 { "nego.",   XO(31,104,1,1), XORB_MASK, COM,            { RT, RA } },
3340
3341 { "mul",     XO(31,107,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3342 { "mul.",    XO(31,107,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3343 { "mulo",    XO(31,107,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3344 { "mulo.",   XO(31,107,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3345
3346 { "mtsrdin", X(31,114), XRA_MASK,       PPC64,          { RS, RB } },
3347
3348 { "clf",     X(31,118), XTO_MASK,       POWER,          { RA, RB } },
3349
3350 { "lbzux",   X(31,119), X_MASK,         COM,            { RT, RAL, RB } },
3351
3352 { "not",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RBS } },
3353 { "nor",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RB } },
3354 { "not.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RBS } },
3355 { "nor.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RB } },
3356
3357 { "lwarxe",  X(31,126), X_MASK,         BOOKE64,        { RT, RA0, RB } },
3358
3359 { "lbzuxe",  X(31,127), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3360
3361 { "wrtee",   X(31,131), XRARB_MASK,     PPC403 | BOOKE, { RS } },
3362
3363 { "dcbtstls",X(31,134), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3364
3365 { "subfe",   XO(31,136,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3366 { "sfe",     XO(31,136,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3367 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3368 { "sfe.",    XO(31,136,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3369 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3370 { "sfeo",    XO(31,136,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3371 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3372 { "sfeo.",   XO(31,136,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3373
3374 { "adde",    XO(31,138,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3375 { "ae",      XO(31,138,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3376 { "adde.",   XO(31,138,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3377 { "ae.",     XO(31,138,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3378 { "addeo",   XO(31,138,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3379 { "aeo",     XO(31,138,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3380 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3381 { "aeo.",    XO(31,138,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3382
3383 { "dcbtstlse",X(31,142),X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3384
3385 { "mtcr",    XFXM(31,144,0xff), XRARB_MASK, COM,        { RS }},
3386 { "mtcrf",   X(31,144), XFXFXM_MASK,    COM,            { FXM, RS } },
3387
3388 { "mtmsr",   X(31,146), XRARB_MASK,     COM,            { RS } },
3389
3390 { "stdx",    X(31,149), X_MASK,         PPC64,          { RS, RA0, RB } },
3391
3392 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA0, RB } },
3393
3394 { "stwx",    X(31,151), X_MASK,         PPCCOM,         { RS, RA0, RB } },
3395 { "stx",     X(31,151), X_MASK,         PWRCOM,         { RS, RA, RB } },
3396
3397 { "stwcxe.", XRC(31,158,1), X_MASK,     BOOKE64,        { RS, RA0, RB } },
3398
3399 { "stwxe",   X(31,159), X_MASK,         BOOKE64,        { RS, RA0, RB } },
3400
3401 { "slq",     XRC(31,152,0), X_MASK,     M601,           { RA, RS, RB } },
3402 { "slq.",    XRC(31,152,1), X_MASK,     M601,           { RA, RS, RB } },
3403
3404 { "sle",     XRC(31,153,0), X_MASK,     M601,           { RA, RS, RB } },
3405 { "sle.",    XRC(31,153,1), X_MASK,     M601,           { RA, RS, RB } },
3406
3407 { "wrteei",  X(31,163), XE_MASK,        PPC403 | BOOKE, { E } },
3408
3409 { "dcbtls",  X(31,166), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3410 { "dcbtlse", X(31,174), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3411
3412 { "mtmsrd",  X(31,178), XRLARB_MASK,    PPC64,          { RS, MTMSRD_L } },
3413
3414 { "stdux",   X(31,181), X_MASK,         PPC64,          { RS, RAS, RB } },
3415
3416 { "stwux",   X(31,183), X_MASK,         PPCCOM,         { RS, RAS, RB } },
3417 { "stux",    X(31,183), X_MASK,         PWRCOM,         { RS, RA0, RB } },
3418
3419 { "sliq",    XRC(31,184,0), X_MASK,     M601,           { RA, RS, SH } },
3420 { "sliq.",   XRC(31,184,1), X_MASK,     M601,           { RA, RS, SH } },
3421
3422 { "stwuxe",  X(31,191), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3423
3424 { "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3425 { "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3426 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3427 { "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3428 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3429 { "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3430 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3431 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3432
3433 { "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3434 { "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3435 { "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3436 { "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3437 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3438 { "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3439 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3440 { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3441
3442 { "mtsr",    X(31,210), XRB_MASK|(1<<20), COM32,        { SR, RS } },
3443
3444 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC64,          { RS, RA0, RB } },
3445
3446 { "stbx",    X(31,215), X_MASK,         COM,            { RS, RA0, RB } },
3447
3448 { "sllq",    XRC(31,216,0), X_MASK,     M601,           { RA, RS, RB } },
3449 { "sllq.",   XRC(31,216,1), X_MASK,     M601,           { RA, RS, RB } },
3450
3451 { "sleq",    XRC(31,217,0), X_MASK,     M601,           { RA, RS, RB } },
3452 { "sleq.",   XRC(31,217,1), X_MASK,     M601,           { RA, RS, RB } },
3453
3454 { "stbxe",   X(31,223), X_MASK,         BOOKE64,        { RS, RA0, RB } },
3455
3456 { "icblc",   X(31,230), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3457
3458 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3459 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3460 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3461 { "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3462 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3463 { "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3464 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3465 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3466
3467 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3468 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3469 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3470 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3471
3472 { "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3473 { "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3474 { "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3475 { "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3476 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3477 { "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3478 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3479 { "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3480
3481 { "mullw",   XO(31,235,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3482 { "muls",    XO(31,235,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3483 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3484 { "muls.",   XO(31,235,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3485 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3486 { "mulso",   XO(31,235,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3487 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3488 { "mulso.",  XO(31,235,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3489
3490 { "icblce",  X(31,238), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3491 { "mtsrin",  X(31,242), XRA_MASK,       PPC32,          { RS, RB } },
3492 { "mtsri",   X(31,242), XRA_MASK,       POWER32,        { RS, RB } },
3493
3494 { "dcbtst",  X(31,246), X_MASK, PPC,                    { CT, RA, RB } },
3495
3496 { "stbux",   X(31,247), X_MASK,         COM,            { RS, RAS, RB } },
3497
3498 { "slliq",   XRC(31,248,0), X_MASK,     M601,           { RA, RS, SH } },
3499 { "slliq.",  XRC(31,248,1), X_MASK,     M601,           { RA, RS, SH } },
3500
3501 { "dcbtste", X(31,253), X_MASK,         BOOKE64,        { CT, RA, RB } },
3502
3503 { "stbuxe",  X(31,255), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3504
3505 { "mfdcrx",  X(31,259), X_MASK,         BOOKE,          { RS, RA } },
3506
3507 { "doz",     XO(31,264,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3508 { "doz.",    XO(31,264,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3509 { "dozo",    XO(31,264,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3510 { "dozo.",   XO(31,264,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3511
3512 { "add",     XO(31,266,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3513 { "cax",     XO(31,266,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3514 { "add.",    XO(31,266,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3515 { "cax.",    XO(31,266,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3516 { "addo",    XO(31,266,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3517 { "caxo",    XO(31,266,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3518 { "addo.",   XO(31,266,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3519 { "caxo.",   XO(31,266,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3520
3521 { "tlbiel",  X(31,274), XRTRA_MASK,     POWER4,         { RB } },
3522
3523 { "mfapidi", X(31,275), X_MASK,         BOOKE,          { RT, RA } },
3524
3525 { "lscbx",   XRC(31,277,0), X_MASK,     M601,           { RT, RA, RB } },
3526 { "lscbx.",  XRC(31,277,1), X_MASK,     M601,           { RT, RA, RB } },
3527
3528 { "dcbt",    X(31,278), X_MASK, PPC,                    { CT, RA, RB } },
3529
3530 { "lhzx",    X(31,279), X_MASK,         COM,            { RT, RA0, RB } },
3531
3532 { "eqv",     XRC(31,284,0), X_MASK,     COM,            { RA, RS, RB } },
3533 { "eqv.",    XRC(31,284,1), X_MASK,     COM,            { RA, RS, RB } },
3534
3535 { "dcbte",   X(31,286), X_MASK,         BOOKE64,        { CT, RA, RB } },
3536
3537 { "lhzxe",   X(31,287), X_MASK,         BOOKE64,        { RT, RA0, RB } },
3538
3539 { "tlbie",   X(31,306), XRTLRA_MASK,    PPC,            { RB, L } },
3540 { "tlbi",    X(31,306), XRT_MASK,       POWER,          { RA0, RB } },
3541
3542 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
3543
3544 { "lhzux",   X(31,311), X_MASK,         COM,            { RT, RAL, RB } },
3545
3546 { "xor",     XRC(31,316,0), X_MASK,     COM,            { RA, RS, RB } },
3547 { "xor.",    XRC(31,316,1), X_MASK,     COM,            { RA, RS, RB } },
3548
3549 { "lhzuxe",  X(31,319), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3550
3551 { "mfexisr",  XSPR(31,323,64),  XSPR_MASK, PPC403,      { RT } },
3552 { "mfexier",  XSPR(31,323,66),  XSPR_MASK, PPC403,      { RT } },
3553 { "mfbr0",    XSPR(31,323,128), XSPR_MASK, PPC403,      { RT } },
3554 { "mfbr1",    XSPR(31,323,129), XSPR_MASK, PPC403,      { RT } },
3555 { "mfbr2",    XSPR(31,323,130), XSPR_MASK, PPC403,      { RT } },
3556 { "mfbr3",    XSPR(31,323,131), XSPR_MASK, PPC403,      { RT } },
3557 { "mfbr4",    XSPR(31,323,132), XSPR_MASK, PPC403,      { RT } },
3558 { "mfbr5",    XSPR(31,323,133), XSPR_MASK, PPC403,      { RT } },
3559 { "mfbr6",    XSPR(31,323,134), XSPR_MASK, PPC403,      { RT } },
3560 { "mfbr7",    XSPR(31,323,135), XSPR_MASK, PPC403,      { RT } },
3561 { "mfbear",   XSPR(31,323,144), XSPR_MASK, PPC403,      { RT } },
3562 { "mfbesr",   XSPR(31,323,145), XSPR_MASK, PPC403,      { RT } },
3563 { "mfiocr",   XSPR(31,323,160), XSPR_MASK, PPC403,      { RT } },
3564 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,      { RT } },
3565 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,      { RT } },
3566 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,      { RT } },
3567 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,      { RT } },
3568 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,      { RT } },
3569 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,      { RT } },
3570 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,      { RT } },
3571 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,      { RT } },
3572 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,      { RT } },
3573 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,      { RT } },
3574 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,      { RT } },
3575 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,      { RT } },
3576 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,      { RT } },
3577 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,      { RT } },
3578 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,      { RT } },
3579 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,      { RT } },
3580 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,      { RT } },
3581 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,      { RT } },
3582 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,      { RT } },
3583 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,      { RT } },
3584 { "mfdmasr",  XSPR(31,323,224), XSPR_MASK, PPC403,      { RT } },
3585 { "mfdcr",    X(31,323),        X_MASK, PPC403 | BOOKE, { RT, SPR } },
3586
3587 { "div",     XO(31,331,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3588 { "div.",    XO(31,331,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3589 { "divo",    XO(31,331,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3590 { "divo.",   XO(31,331,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3591
3592 { "mfpmr",   X(31,334), X_MASK,         PPCPMR,         { RT, PMR }},
3593
3594 { "mfmq",       XSPR(31,339,0),    XSPR_MASK, M601,     { RT } },
3595 { "mfxer",      XSPR(31,339,1),    XSPR_MASK, COM,      { RT } },
3596 { "mfrtcu",     XSPR(31,339,4),    XSPR_MASK, COM,      { RT } },
3597 { "mfrtcl",     XSPR(31,339,5),    XSPR_MASK, COM,      { RT } },
3598 { "mfdec",      XSPR(31,339,6),    XSPR_MASK, MFDEC1,   { RT } },
3599 { "mfdec",      XSPR(31,339,22),   XSPR_MASK, MFDEC2,   { RT } },
3600 { "mflr",       XSPR(31,339,8),    XSPR_MASK, COM,      { RT } },
3601 { "mfctr",      XSPR(31,339,9),    XSPR_MASK, COM,      { RT } },
3602 { "mftid",      XSPR(31,339,17),   XSPR_MASK, POWER,    { RT } },
3603 { "mfdsisr",    XSPR(31,339,18),   XSPR_MASK, COM,      { RT } },
3604 { "mfdar",      XSPR(31,339,19),   XSPR_MASK, COM,      { RT } },
3605 { "mfsdr0",     XSPR(31,339,24),   XSPR_MASK, POWER,    { RT } },
3606 { "mfsdr1",     XSPR(31,339,25),   XSPR_MASK, COM,      { RT } },
3607 { "mfsrr0",     XSPR(31,339,26),   XSPR_MASK, COM,      { RT } },
3608 { "mfsrr1",     XSPR(31,339,27),   XSPR_MASK, COM,      { RT } },
3609 { "mfpid",      XSPR(31,339,48),   XSPR_MASK, BOOKE,    { RT } },
3610 { "mfpid",      XSPR(31,339,945),  XSPR_MASK, PPC403,   { RT } },
3611 { "mfcsrr0",    XSPR(31,339,58),   XSPR_MASK, BOOKE,    { RT } },
3612 { "mfcsrr1",    XSPR(31,339,59),   XSPR_MASK, BOOKE,    { RT } },
3613 { "mfdear",     XSPR(31,339,61),   XSPR_MASK, BOOKE,    { RT } },
3614 { "mfdear",     XSPR(31,339,981),  XSPR_MASK, PPC403,   { RT } },
3615 { "mfesr",      XSPR(31,339,62),   XSPR_MASK, BOOKE,    { RT } },
3616 { "mfesr",      XSPR(31,339,980),  XSPR_MASK, PPC403,   { RT } },
3617 { "mfivpr",     XSPR(31,339,63),   XSPR_MASK, BOOKE,    { RT } },
3618 { "mfcmpa",     XSPR(31,339,144),  XSPR_MASK, PPC860,   { RT } },
3619 { "mfcmpb",     XSPR(31,339,145),  XSPR_MASK, PPC860,   { RT } },
3620 { "mfcmpc",     XSPR(31,339,146),  XSPR_MASK, PPC860,   { RT } },
3621 { "mfcmpd",     XSPR(31,339,147),  XSPR_MASK, PPC860,   { RT } },
3622 { "mficr",      XSPR(31,339,148),  XSPR_MASK, PPC860,   { RT } },
3623 { "mfder",      XSPR(31,339,149),  XSPR_MASK, PPC860,   { RT } },
3624 { "mfcounta",   XSPR(31,339,150),  XSPR_MASK, PPC860,   { RT } },
3625 { "mfcountb",   XSPR(31,339,151),  XSPR_MASK, PPC860,   { RT } },
3626 { "mfcmpe",     XSPR(31,339,152),  XSPR_MASK, PPC860,   { RT } },
3627 { "mfcmpf",     XSPR(31,339,153),  XSPR_MASK, PPC860,   { RT } },
3628 { "mfcmpg",     XSPR(31,339,154),  XSPR_MASK, PPC860,   { RT } },
3629 { "mfcmph",     XSPR(31,339,155),  XSPR_MASK, PPC860,   { RT } },
3630 { "mflctrl1",   XSPR(31,339,156),  XSPR_MASK, PPC860,   { RT } },
3631 { "mflctrl2",   XSPR(31,339,157),  XSPR_MASK, PPC860,   { RT } },
3632 { "mfictrl",    XSPR(31,339,158),  XSPR_MASK, PPC860,   { RT } },
3633 { "mfbar",      XSPR(31,339,159),  XSPR_MASK, PPC860,   { RT } },
3634 { "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,   { RT } },
3635 { "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
3636 { "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405,   { RT } },
3637 { "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, BOOKE,    { RT } },
3638 { "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405,   { RT } },
3639 { "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, BOOKE,    { RT } },
3640 { "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405,   { RT } },
3641 { "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, BOOKE,    { RT } },
3642 { "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405,   { RT } },
3643 { "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, BOOKE,    { RT } },
3644 { "mftb",       X(31,371),         X_MASK,    CLASSIC,  { RT, TBR } },
3645 { "mftb",       XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3646 { "mftbl",      XSPR(31,371,268),  XSPR_MASK, CLASSIC,  { RT } },
3647 { "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3648 { "mftbu",      XSPR(31,371,269),  XSPR_MASK, CLASSIC,  { RT } },
3649 { "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
3650 { "mfsprg",     XSPR(31,339,272),  XSPRG_MASK, PPC,     { RT, SPRG } },
3651 { "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,      { RT } },
3652 { "mfsprg1",    XSPR(31,339,273),  XSPR_MASK, PPC,      { RT } },
3653 { "mfsprg2",    XSPR(31,339,274),  XSPR_MASK, PPC,      { RT } },
3654 { "mfsprg3",    XSPR(31,339,275),  XSPR_MASK, PPC,      { RT } },
3655 { "mfasr",      XSPR(31,339,280),  XSPR_MASK, PPC64,    { RT } },
3656 { "mfear",      XSPR(31,339,282),  XSPR_MASK, PPC,      { RT } },
3657 { "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
3658 { "mfpvr",      XSPR(31,339,287),  XSPR_MASK, PPC,      { RT } },
3659 { "mfdbsr",     XSPR(31,339,304),  XSPR_MASK, BOOKE,    { RT } },
3660 { "mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,   { RT } },
3661 { "mfdbcr0",    XSPR(31,339,308),  XSPR_MASK, BOOKE,    { RT } },
3662 { "mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,   { RT } },
3663 { "mfdbcr1",    XSPR(31,339,309),  XSPR_MASK, BOOKE,    { RT } },
3664 { "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
3665 { "mfdbcr2",    XSPR(31,339,310),  XSPR_MASK, BOOKE,    { RT } },
3666 { "mfiac1",     XSPR(31,339,312),  XSPR_MASK, BOOKE,    { RT } },
3667 { "mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,   { RT } },
3668 { "mfiac2",     XSPR(31,339,313),  XSPR_MASK, BOOKE,    { RT } },
3669 { "mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,   { RT } },
3670 { "mfiac3",     XSPR(31,339,314),  XSPR_MASK, BOOKE,    { RT } },
3671 { "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,   { RT } },
3672 { "mfiac4",     XSPR(31,339,315),  XSPR_MASK, BOOKE,    { RT } },
3673 { "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,   { RT } },
3674 { "mfdac1",     XSPR(31,339,316),  XSPR_MASK, BOOKE,    { RT } },
3675 { "mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,   { RT } },
3676 { "mfdac2",     XSPR(31,339,317),  XSPR_MASK, BOOKE,    { RT } },
3677 { "mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,   { RT } },
3678 { "mfdvc1",     XSPR(31,339,318),  XSPR_MASK, BOOKE,    { RT } },
3679 { "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,   { RT } },
3680 { "mfdvc2",     XSPR(31,339,319),  XSPR_MASK, BOOKE,    { RT } },
3681 { "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,   { RT } },
3682 { "mftsr",      XSPR(31,339,336),  XSPR_MASK, BOOKE,    { RT } },
3683 { "mftsr",      XSPR(31,339,984),  XSPR_MASK, PPC403,   { RT } },
3684 { "mftcr",      XSPR(31,339,340),  XSPR_MASK, BOOKE,    { RT } },
3685 { "mftcr",      XSPR(31,339,986),  XSPR_MASK, PPC403,   { RT } },
3686 { "mfivor0",    XSPR(31,339,400),  XSPR_MASK, BOOKE,    { RT } },
3687 { "mfivor1",    XSPR(31,339,401),  XSPR_MASK, BOOKE,    { RT } },
3688 { "mfivor2",    XSPR(31,339,402),  XSPR_MASK, BOOKE,    { RT } },
3689 { "mfivor3",    XSPR(31,339,403),  XSPR_MASK, BOOKE,    { RT } },
3690 { "mfivor4",    XSPR(31,339,404),  XSPR_MASK, BOOKE,    { RT } },
3691 { "mfivor5",    XSPR(31,339,405),  XSPR_MASK, BOOKE,    { RT } },
3692 { "mfivor6",    XSPR(31,339,406),  XSPR_MASK, BOOKE,    { RT } },
3693 { "mfivor7",    XSPR(31,339,407),  XSPR_MASK, BOOKE,    { RT } },
3694 { "mfivor8",    XSPR(31,339,408),  XSPR_MASK, BOOKE,    { RT } },
3695 { "mfivor9",    XSPR(31,339,409),  XSPR_MASK, BOOKE,    { RT } },
3696 { "mfivor10",   XSPR(31,339,410),  XSPR_MASK, BOOKE,    { RT } },
3697 { "mfivor11",   XSPR(31,339,411),  XSPR_MASK, BOOKE,    { RT } },
3698 { "mfivor12",   XSPR(31,339,412),  XSPR_MASK, BOOKE,    { RT } },
3699 { "mfivor13",   XSPR(31,339,413),  XSPR_MASK, BOOKE,    { RT } },
3700 { "mfivor14",   XSPR(31,339,414),  XSPR_MASK, BOOKE,    { RT } },
3701 { "mfivor15",   XSPR(31,339,415),  XSPR_MASK, BOOKE,    { RT } },
3702 { "mfspefscr",  XSPR(31,339,512),  XSPR_MASK, PPCSPE,   { RT } },
3703 { "mfbbear",    XSPR(31,339,513),  XSPR_MASK, PPCBRLK,  { RT } },
3704 { "mfbbtar",    XSPR(31,339,514),  XSPR_MASK, PPCBRLK,  { RT } },
3705 { "mfivor32",   XSPR(31,339,528),  XSPR_MASK, PPCSPE,   { RT } },
3706 { "mfivor33",   XSPR(31,339,529),  XSPR_MASK, PPCSPE,   { RT } },
3707 { "mfivor34",   XSPR(31,339,530),  XSPR_MASK, PPCSPE,   { RT } },
3708 { "mfivor35",   XSPR(31,339,531),  XSPR_MASK, PPCPMR,   { RT } },
3709 { "mfibatu",    XSPR(31,339,528),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3710 { "mfibatl",    XSPR(31,339,529),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3711 { "mfdbatu",    XSPR(31,339,536),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3712 { "mfdbatl",    XSPR(31,339,537),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3713 { "mfic_cst",   XSPR(31,339,560),  XSPR_MASK, PPC860,   { RT } },
3714 { "mfic_adr",   XSPR(31,339,561),  XSPR_MASK, PPC860,   { RT } },
3715 { "mfic_dat",   XSPR(31,339,562),  XSPR_MASK, PPC860,   { RT } },
3716 { "mfdc_cst",   XSPR(31,339,568),  XSPR_MASK, PPC860,   { RT } },
3717 { "mfdc_adr",   XSPR(31,339,569),  XSPR_MASK, PPC860,   { RT } },
3718 { "mfmcsrr0",   XSPR(31,339,570),  XSPR_MASK, PPCRFMCI, { RT } },
3719 { "mfdc_dat",   XSPR(31,339,570),  XSPR_MASK, PPC860,   { RT } },
3720 { "mfmcsrr1",   XSPR(31,339,571),  XSPR_MASK, PPCRFMCI, { RT } },
3721 { "mfmcsr",     XSPR(31,339,572),  XSPR_MASK, PPCRFMCI, { RT } },
3722 { "mfmcar",     XSPR(31,339,573),  XSPR_MASK, PPCRFMCI, { RT } },
3723 { "mfdpdr",     XSPR(31,339,630),  XSPR_MASK, PPC860,   { RT } },
3724 { "mfdpir",     XSPR(31,339,631),  XSPR_MASK, PPC860,   { RT } },
3725 { "mfimmr",     XSPR(31,339,638),  XSPR_MASK, PPC860,   { RT } },
3726 { "mfmi_ctr",   XSPR(31,339,784),  XSPR_MASK, PPC860,   { RT } },
3727 { "mfmi_ap",    XSPR(31,339,786),  XSPR_MASK, PPC860,   { RT } },
3728 { "mfmi_epn",   XSPR(31,339,787),  XSPR_MASK, PPC860,   { RT } },
3729 { "mfmi_twc",   XSPR(31,339,789),  XSPR_MASK, PPC860,   { RT } },
3730 { "mfmi_rpn",   XSPR(31,339,790),  XSPR_MASK, PPC860,   { RT } },
3731 { "mfmd_ctr",   XSPR(31,339,792),  XSPR_MASK, PPC860,   { RT } },
3732 { "mfm_casid",  XSPR(31,339,793),  XSPR_MASK, PPC860,   { RT } },
3733 { "mfmd_ap",    XSPR(31,339,794),  XSPR_MASK, PPC860,   { RT } },
3734 { "mfmd_epn",   XSPR(31,339,795),  XSPR_MASK, PPC860,   { RT } },
3735 { "mfmd_twb",   XSPR(31,339,796),  XSPR_MASK, PPC860,   { RT } },
3736 { "mfmd_twc",   XSPR(31,339,797),  XSPR_MASK, PPC860,   { RT } },
3737 { "mfmd_rpn",   XSPR(31,339,798),  XSPR_MASK, PPC860,   { RT } },
3738 { "mfm_tw",     XSPR(31,339,799),  XSPR_MASK, PPC860,   { RT } },
3739 { "mfmi_dbcam", XSPR(31,339,816),  XSPR_MASK, PPC860,   { RT } },
3740 { "mfmi_dbram0",XSPR(31,339,817),  XSPR_MASK, PPC860,   { RT } },
3741 { "mfmi_dbram1",XSPR(31,339,818),  XSPR_MASK, PPC860,   { RT } },
3742 { "mfmd_dbcam", XSPR(31,339,824),  XSPR_MASK, PPC860,   { RT } },
3743 { "mfmd_dbram0",XSPR(31,339,825),  XSPR_MASK, PPC860,   { RT } },
3744 { "mfmd_dbram1",XSPR(31,339,826),  XSPR_MASK, PPC860,   { RT } },
3745 { "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
3746 { "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
3747 { "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
3748 { "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
3749 { "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
3750 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
3751 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
3752 { "mfzpr",      XSPR(31,339,944),  XSPR_MASK, PPC403,   { RT } },
3753 { "mfccr0",     XSPR(31,339,947),  XSPR_MASK, PPC405,   { RT } },
3754 { "mfmmcr0",    XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
3755 { "mfpmc1",     XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
3756 { "mfsgr",      XSPR(31,339,953),  XSPR_MASK, PPC403,   { RT } },
3757 { "mfpmc2",     XSPR(31,339,954),  XSPR_MASK, PPC750,   { RT } },
3758 { "mfdcwr",     XSPR(31,339,954),  XSPR_MASK, PPC403,   { RT } },
3759 { "mfsia",      XSPR(31,339,955),  XSPR_MASK, PPC750,   { RT } },
3760 { "mfsler",     XSPR(31,339,955),  XSPR_MASK, PPC405,   { RT } },
3761 { "mfmmcr1",    XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
3762 { "mfsu0r",     XSPR(31,339,956),  XSPR_MASK, PPC405,   { RT } },
3763 { "mfpmc3",     XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
3764 { "mfpmc4",     XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
3765 { "mficdbdr",   XSPR(31,339,979),  XSPR_MASK, PPC403,   { RT } },
3766 { "mfevpr",     XSPR(31,339,982),  XSPR_MASK, PPC403,   { RT } },
3767 { "mfcdbcr",    XSPR(31,339,983),  XSPR_MASK, PPC403,   { RT } },
3768 { "mfpit",      XSPR(31,339,987),  XSPR_MASK, PPC403,   { RT } },
3769 { "mftbhi",     XSPR(31,339,988),  XSPR_MASK, PPC403,   { RT } },
3770 { "mftblo",     XSPR(31,339,989),  XSPR_MASK, PPC403,   { RT } },
3771 { "mfsrr2",     XSPR(31,339,990),  XSPR_MASK, PPC403,   { RT } },
3772 { "mfsrr3",     XSPR(31,339,991),  XSPR_MASK, PPC403,   { RT } },
3773 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
3774 { "mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,   { RT } },
3775 { "mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,   { RT } },
3776 { "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
3777 { "mfpbl1",     XSPR(31,339,1020), XSPR_MASK, PPC403,   { RT } },
3778 { "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
3779 { "mfpbu1",     XSPR(31,339,1021), XSPR_MASK, PPC403,   { RT } },
3780 { "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
3781 { "mfpbl2",     XSPR(31,339,1022), XSPR_MASK, PPC403,   { RT } },
3782 { "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
3783 { "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,   { RT } },
3784 { "mfspr",      X(31,339),         X_MASK,    COM,      { RT, SPR } },
3785
3786 { "lwax",    X(31,341), X_MASK,         PPC64,          { RT, RA0, RB } },
3787
3788 { "dst",     XDSS(31,342,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3789 { "dstt",    XDSS(31,342,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3790
3791 { "lhax",    X(31,343), X_MASK,         COM,            { RT, RA0, RB } },
3792
3793 { "lhaxe",   X(31,351), X_MASK,         BOOKE64,        { RT, RA0, RB } },
3794
3795 { "dstst",   XDSS(31,374,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3796 { "dststt",  XDSS(31,374,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3797
3798 { "dccci",   X(31,454), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
3799
3800 { "abs",     XO(31,360,0,0), XORB_MASK, M601,           { RT, RA } },
3801 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,           { RT, RA } },
3802 { "abso",    XO(31,360,1,0), XORB_MASK, M601,           { RT, RA } },
3803 { "abso.",   XO(31,360,1,1), XORB_MASK, M601,           { RT, RA } },
3804
3805 { "divs",    XO(31,363,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3806 { "divs.",   XO(31,363,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3807 { "divso",   XO(31,363,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3808 { "divso.",  XO(31,363,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3809
3810 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
3811
3812 { "lwaux",   X(31,373), X_MASK,         PPC64,          { RT, RAL, RB } },
3813
3814 { "lhaux",   X(31,375), X_MASK,         COM,            { RT, RAL, RB } },
3815
3816 { "lhauxe",  X(31,383), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3817
3818 { "mtdcrx",  X(31,387), X_MASK,         BOOKE,          { RA, RS } },
3819
3820 { "dcblc",   X(31,390), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3821
3822 { "subfe64", XO(31,392,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3823 { "subfe64o",XO(31,392,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3824
3825 { "adde64",  XO(31,394,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3826 { "adde64o", XO(31,394,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3827
3828 { "dcblce",  X(31,398), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3829
3830 { "slbmte",  X(31,402), XRA_MASK,       PPC64,          { RS, RB } },
3831
3832 { "sthx",    X(31,407), X_MASK,         COM,            { RS, RA0, RB } },
3833
3834 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
3835
3836 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
3837
3838 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
3839
3840 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
3841
3842 { "orc",     XRC(31,412,0), X_MASK,     COM,            { RA, RS, RB } },
3843 { "orc.",    XRC(31,412,1), X_MASK,     COM,            { RA, RS, RB } },
3844
3845 { "sradi",   XS(31,413,0), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3846 { "sradi.",  XS(31,413,1), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3847
3848 { "sthxe",   X(31,415), X_MASK,         BOOKE64,        { RS, RA0, RB } },
3849
3850 { "slbie",   X(31,434), XRTRA_MASK,     PPC64,          { RB } },
3851
3852 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
3853
3854 { "sthux",   X(31,439), X_MASK,         COM,            { RS, RAS, RB } },
3855
3856 { "sthuxe",  X(31,447), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3857
3858 { "mr",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RBS } },
3859 { "or",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RB } },
3860 { "mr.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RBS } },
3861 { "or.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RB } },
3862
3863 { "mtexisr",  XSPR(31,451,64),  XSPR_MASK, PPC403,      { RS } },
3864 { "mtexier",  XSPR(31,451,66),  XSPR_MASK, PPC403,      { RS } },
3865 { "mtbr0",    XSPR(31,451,128), XSPR_MASK, PPC403,      { RS } },
3866 { "mtbr1",    XSPR(31,451,129), XSPR_MASK, PPC403,      { RS } },
3867 { "mtbr2",    XSPR(31,451,130), XSPR_MASK, PPC403,      { RS } },
3868 { "mtbr3",    XSPR(31,451,131), XSPR_MASK, PPC403,      { RS } },
3869 { "mtbr4",    XSPR(31,451,132), XSPR_MASK, PPC403,      { RS } },
3870 { "mtbr5",    XSPR(31,451,133), XSPR_MASK, PPC403,      { RS } },
3871 { "mtbr6",    XSPR(31,451,134), XSPR_MASK, PPC403,      { RS } },
3872 { "mtbr7",    XSPR(31,451,135), XSPR_MASK, PPC403,      { RS } },
3873 { "mtbear",   XSPR(31,451,144), XSPR_MASK, PPC403,      { RS } },
3874 { "mtbesr",   XSPR(31,451,145), XSPR_MASK, PPC403,      { RS } },
3875 { "mtiocr",   XSPR(31,451,160), XSPR_MASK, PPC403,      { RS } },
3876 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,      { RS } },
3877 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,      { RS } },
3878 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,      { RS } },
3879 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,      { RS } },
3880 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,      { RS } },
3881 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,      { RS } },
3882 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,      { RS } },
3883 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,      { RS } },
3884 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,      { RS } },
3885 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,      { RS } },
3886 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,      { RS } },
3887 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,      { RS } },
3888 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,      { RS } },
3889 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,      { RS } },
3890 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,      { RS } },
3891 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,      { RS } },
3892 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,      { RS } },
3893 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,      { RS } },
3894 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,      { RS } },
3895 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,      { RS } },
3896 { "mtdmasr",  XSPR(31,451,224), XSPR_MASK, PPC403,      { RS } },
3897 { "mtdcr",    X(31,451),        X_MASK, PPC403 | BOOKE, { SPR, RS } },
3898
3899 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3900 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
3901
3902 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3903 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3904 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3905 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3906
3907 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3908 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
3909
3910 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3911 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3912 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3913 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
3914
3915 { "mtmq",      XSPR(31,467,0),    XSPR_MASK, M601,      { RS } },
3916 { "mtxer",     XSPR(31,467,1),    XSPR_MASK, COM,       { RS } },
3917 { "mtlr",      XSPR(31,467,8),    XSPR_MASK, COM,       { RS } },
3918 { "mtctr",     XSPR(31,467,9),    XSPR_MASK, COM,       { RS } },
3919 { "mttid",     XSPR(31,467,17),   XSPR_MASK, POWER,     { RS } },
3920 { "mtdsisr",   XSPR(31,467,18),   XSPR_MASK, COM,       { RS } },
3921 { "mtdar",     XSPR(31,467,19),   XSPR_MASK, COM,       { RS } },
3922 { "mtrtcu",    XSPR(31,467,20),   XSPR_MASK, COM,       { RS } },
3923 { "mtrtcl",    XSPR(31,467,21),   XSPR_MASK, COM,       { RS } },
3924 { "mtdec",     XSPR(31,467,22),   XSPR_MASK, COM,       { RS } },
3925 { "mtsdr0",    XSPR(31,467,24),   XSPR_MASK, POWER,     { RS } },
3926 { "mtsdr1",    XSPR(31,467,25),   XSPR_MASK, COM,       { RS } },
3927 { "mtsrr0",    XSPR(31,467,26),   XSPR_MASK, COM,       { RS } },
3928 { "mtsrr1",    XSPR(31,467,27),   XSPR_MASK, COM,       { RS } },
3929 { "mtpid",     XSPR(31,467,48),   XSPR_MASK, BOOKE,     { RS } },
3930 { "mtpid",     XSPR(31,467,945),  XSPR_MASK, PPC403,    { RS } },
3931 { "mtdecar",   XSPR(31,467,54),   XSPR_MASK, BOOKE,     { RS } },
3932 { "mtcsrr0",   XSPR(31,467,58),   XSPR_MASK, BOOKE,     { RS } },
3933 { "mtcsrr1",   XSPR(31,467,59),   XSPR_MASK, BOOKE,     { RS } },
3934 { "mtdear",    XSPR(31,467,61),   XSPR_MASK, BOOKE,     { RS } },
3935 { "mtdear",    XSPR(31,467,981),  XSPR_MASK, PPC403,    { RS } },
3936 { "mtesr",     XSPR(31,467,62),   XSPR_MASK, BOOKE,     { RS } },
3937 { "mtesr",     XSPR(31,467,980),  XSPR_MASK, PPC403,    { RS } },
3938 { "mtivpr",    XSPR(31,467,63),   XSPR_MASK, BOOKE,     { RS } },
3939 { "mtcmpa",    XSPR(31,467,144),  XSPR_MASK, PPC860,    { RS } },
3940 { "mtcmpb",    XSPR(31,467,145),  XSPR_MASK, PPC860,    { RS } },
3941 { "mtcmpc",    XSPR(31,467,146),  XSPR_MASK, PPC860,    { RS } },
3942 { "mtcmpd",    XSPR(31,467,147),  XSPR_MASK, PPC860,    { RS } },
3943 { "mticr",     XSPR(31,467,148),  XSPR_MASK, PPC860,    { RS } },
3944 { "mtder",     XSPR(31,467,149),  XSPR_MASK, PPC860,    { RS } },
3945 { "mtcounta",  XSPR(31,467,150),  XSPR_MASK, PPC860,    { RS } },
3946 { "mtcountb",  XSPR(31,467,151),  XSPR_MASK, PPC860,    { RS } },
3947 { "mtcmpe",    XSPR(31,467,152),  XSPR_MASK, PPC860,    { RS } },
3948 { "mtcmpf",    XSPR(31,467,153),  XSPR_MASK, PPC860,    { RS } },
3949 { "mtcmpg",    XSPR(31,467,154),  XSPR_MASK, PPC860,    { RS } },
3950 { "mtcmph",    XSPR(31,467,155),  XSPR_MASK, PPC860,    { RS } },
3951 { "mtlctrl1",  XSPR(31,467,156),  XSPR_MASK, PPC860,    { RS } },
3952 { "mtlctrl2",  XSPR(31,467,157),  XSPR_MASK, PPC860,    { RS } },
3953 { "mtictrl",   XSPR(31,467,158),  XSPR_MASK, PPC860,    { RS } },
3954 { "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,    { RS } },
3955 { "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,    { RS } },
3956 { "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
3957 { "mtsprg",    XSPR(31,467,272),  XSPRG_MASK,PPC,       { SPRG, RS } },
3958 { "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,       { RS } },
3959 { "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,       { RS } },
3960 { "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,       { RS } },
3961 { "mtsprg3",   XSPR(31,467,275),  XSPR_MASK, PPC,       { RS } },
3962 { "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3963 { "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3964 { "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3965 { "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3966 { "mtasr",     XSPR(31,467,280),  XSPR_MASK, PPC64,     { RS } },
3967 { "mtear",     XSPR(31,467,282),  XSPR_MASK, PPC,       { RS } },
3968 { "mttbl",     XSPR(31,467,284),  XSPR_MASK, PPC,       { RS } },
3969 { "mttbu",     XSPR(31,467,285),  XSPR_MASK, PPC,       { RS } },
3970 { "mtdbsr",    XSPR(31,467,304),  XSPR_MASK, BOOKE,     { RS } },
3971 { "mtdbsr",    XSPR(31,467,1008), XSPR_MASK, PPC403,    { RS } },
3972 { "mtdbcr0",   XSPR(31,467,308),  XSPR_MASK, BOOKE,     { RS } },
3973 { "mtdbcr0",   XSPR(31,467,1010), XSPR_MASK, PPC405,    { RS } },
3974 { "mtdbcr1",   XSPR(31,467,309),  XSPR_MASK, BOOKE,     { RS } },
3975 { "mtdbcr1",   XSPR(31,467,957),  XSPR_MASK, PPC405,    { RS } },
3976 { "mtdbcr2",   XSPR(31,467,310),  XSPR_MASK, BOOKE,     { RS } },
3977 { "mtiac1",    XSPR(31,467,312),  XSPR_MASK, BOOKE,     { RS } },
3978 { "mtiac1",    XSPR(31,467,1012), XSPR_MASK, PPC403,    { RS } },
3979 { "mtiac2",    XSPR(31,467,313),  XSPR_MASK, BOOKE,     { RS } },
3980 { "mtiac2",    XSPR(31,467,1013), XSPR_MASK, PPC403,    { RS } },
3981 { "mtiac3",    XSPR(31,467,314),  XSPR_MASK, BOOKE,     { RS } },
3982 { "mtiac3",    XSPR(31,467,948),  XSPR_MASK, PPC405,    { RS } },
3983 { "mtiac4",    XSPR(31,467,315),  XSPR_MASK, BOOKE,     { RS } },
3984 { "mtiac4",    XSPR(31,467,949),  XSPR_MASK, PPC405,    { RS } },
3985 { "mtdac1",    XSPR(31,467,316),  XSPR_MASK, BOOKE,     { RS } },
3986 { "mtdac1",    XSPR(31,467,1014), XSPR_MASK, PPC403,    { RS } },
3987 { "mtdac2",    XSPR(31,467,317),  XSPR_MASK, BOOKE,     { RS } },
3988 { "mtdac2",    XSPR(31,467,1015), XSPR_MASK, PPC403,    { RS } },
3989 { "mtdvc1",    XSPR(31,467,318),  XSPR_MASK, BOOKE,     { RS } },
3990 { "mtdvc1",    XSPR(31,467,950),  XSPR_MASK, PPC405,    { RS } },
3991 { "mtdvc2",    XSPR(31,467,319),  XSPR_MASK, BOOKE,     { RS } },
3992 { "mtdvc2",    XSPR(31,467,951),  XSPR_MASK, PPC405,    { RS } },
3993 { "mttsr",     XSPR(31,467,336),  XSPR_MASK, BOOKE,     { RS } },
3994 { "mttsr",     XSPR(31,467,984),  XSPR_MASK, PPC403,    { RS } },
3995 { "mttcr",     XSPR(31,467,340),  XSPR_MASK, BOOKE,     { RS } },
3996 { "mttcr",     XSPR(31,467,986),  XSPR_MASK, PPC403,    { RS } },
3997 { "mtivor0",   XSPR(31,467,400),  XSPR_MASK, BOOKE,     { RS } },
3998 { "mtivor1",   XSPR(31,467,401),  XSPR_MASK, BOOKE,     { RS } },
3999 { "mtivor2",   XSPR(31,467,402),  XSPR_MASK, BOOKE,     { RS } },
4000 { "mtivor3",   XSPR(31,467,403),  XSPR_MASK, BOOKE,     { RS } },
4001 { "mtivor4",   XSPR(31,467,404),  XSPR_MASK, BOOKE,     { RS } },
4002 { "mtivor5",   XSPR(31,467,405),  XSPR_MASK, BOOKE,     { RS } },
4003 { "mtivor6",   XSPR(31,467,406),  XSPR_MASK, BOOKE,     { RS } },
4004 { "mtivor7",   XSPR(31,467,407),  XSPR_MASK, BOOKE,     { RS } },
4005 { "mtivor8",   XSPR(31,467,408),  XSPR_MASK, BOOKE,     { RS } },
4006 { "mtivor9",   XSPR(31,467,409),  XSPR_MASK, BOOKE,     { RS } },
4007 { "mtivor10",  XSPR(31,467,410),  XSPR_MASK, BOOKE,     { RS } },
4008 { "mtivor11",  XSPR(31,467,411),  XSPR_MASK, BOOKE,     { RS } },
4009 { "mtivor12",  XSPR(31,467,412),  XSPR_MASK, BOOKE,     { RS } },
4010 { "mtivor13",  XSPR(31,467,413),  XSPR_MASK, BOOKE,     { RS } },
4011 { "mtivor14",  XSPR(31,467,414),  XSPR_MASK, BOOKE,     { RS } },
4012 { "mtivor15",  XSPR(31,467,415),  XSPR_MASK, BOOKE,     { RS } },
4013 { "mtspefscr",  XSPR(31,467,512),  XSPR_MASK, PPCSPE,   { RS } },
4014 { "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
4015 { "mtbbtar",   XSPR(31,467,514),  XSPR_MASK, PPCBRLK,  { RS } },
4016 { "mtivor32",  XSPR(31,467,528),  XSPR_MASK, PPCSPE,    { RS } },
4017 { "mtivor33",  XSPR(31,467,529),  XSPR_MASK, PPCSPE,    { RS } },
4018 { "mtivor34",  XSPR(31,467,530),  XSPR_MASK, PPCSPE,    { RS } },
4019 { "mtivor35",  XSPR(31,467,531),  XSPR_MASK, PPCPMR,    { RS } },
4020 { "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4021 { "mtibatl",   XSPR(31,467,529),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4022 { "mtdbatu",   XSPR(31,467,536),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4023 { "mtdbatl",   XSPR(31,467,537),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
4024 { "mtmcsrr0",  XSPR(31,467,570),  XSPR_MASK, PPCRFMCI,  { RS } },
4025 { "mtmcsrr1",  XSPR(31,467,571),  XSPR_MASK, PPCRFMCI,  { RS } },
4026 { "mtmcsr",    XSPR(31,467,572),  XSPR_MASK, PPCRFMCI,  { RS } },
4027 { "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,    { RS } },
4028 { "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,    { RS } },
4029 { "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,    { RS } },
4030 { "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,    { RS } },
4031 { "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,    { RS } },
4032 { "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,    { RS } },
4033 { "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,    { RS } },
4034 { "mtzpr",     XSPR(31,467,944),  XSPR_MASK, PPC403,    { RS } },
4035 { "mtccr0",    XSPR(31,467,947),  XSPR_MASK, PPC405,    { RS } },
4036 { "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,    { RS } },
4037 { "mtsgr",     XSPR(31,467,953),  XSPR_MASK, PPC403,    { RS } },
4038 { "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,    { RS } },
4039 { "mtdcwr",    XSPR(31,467,954),  XSPR_MASK, PPC403,    { RS } },
4040 { "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,    { RS } },
4041 { "mtsler",    XSPR(31,467,955),  XSPR_MASK, PPC405,    { RS } },
4042 { "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,    { RS } },
4043 { "mtsu0r",    XSPR(31,467,956),  XSPR_MASK, PPC405,    { RS } },
4044 { "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,    { RS } },
4045 { "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,    { RS } },
4046 { "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,    { RS } },
4047 { "mticdbdr",  XSPR(31,467,979),  XSPR_MASK, PPC403,    { RS } },
4048 { "mtevpr",    XSPR(31,467,982),  XSPR_MASK, PPC403,    { RS } },
4049 { "mtcdbcr",   XSPR(31,467,983),  XSPR_MASK, PPC403,    { RS } },
4050 { "mtpit",     XSPR(31,467,987),  XSPR_MASK, PPC403,    { RS } },
4051 { "mttbhi",    XSPR(31,467,988),  XSPR_MASK, PPC403,    { RS } },
4052 { "mttblo",    XSPR(31,467,989),  XSPR_MASK, PPC403,    { RS } },
4053 { "mtsrr2",    XSPR(31,467,990),  XSPR_MASK, PPC403,    { RS } },
4054 { "mtsrr3",    XSPR(31,467,991),  XSPR_MASK, PPC403,    { RS } },
4055 { "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,    { RS } },
4056 { "mtdccr",    XSPR(31,467,1018), XSPR_MASK, PPC403,    { RS } },
4057 { "mticcr",    XSPR(31,467,1019), XSPR_MASK, PPC403,    { RS } },
4058 { "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,    { RS } },
4059 { "mtpbl1",    XSPR(31,467,1020), XSPR_MASK, PPC403,    { RS } },
4060 { "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,    { RS } },
4061 { "mtpbu1",    XSPR(31,467,1021), XSPR_MASK, PPC403,    { RS } },
4062 { "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,    { RS } },
4063 { "mtpbl2",    XSPR(31,467,1022), XSPR_MASK, PPC403,    { RS } },
4064 { "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,    { RS } },
4065 { "mtpbu2",    XSPR(31,467,1023), XSPR_MASK, PPC403,    { RS } },
4066 { "mtspr",     X(31,467),         X_MASK,    COM,       { SPR, RS } },
4067
4068 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
4069
4070 { "nand",    XRC(31,476,0), X_MASK,     COM,            { RA, RS, RB } },
4071 { "nand.",   XRC(31,476,1), X_MASK,     COM,            { RA, RS, RB } },
4072
4073 { "dcbie",   X(31,478), XRT_MASK,       BOOKE64,        { RA, RB } },
4074
4075 { "dcread",  X(31,486), X_MASK,         PPC403|PPC440,  { RT, RA, RB }},
4076
4077 { "mtpmr",   X(31,462), X_MASK,         PPCPMR,         { PMR, RS }},
4078
4079 { "icbtls",  X(31,486), X_MASK,         PPCCHLK,        { CT, RA, RB }},
4080
4081 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,           { RT, RA } },
4082 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
4083 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,           { RT, RA } },
4084 { "nabso",   XO(31,488,1,0), XORB_MASK, M601,           { RT, RA } },
4085 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
4086 { "nabso.",  XO(31,488,1,1), XORB_MASK, M601,           { RT, RA } },
4087
4088 { "divd",    XO(31,489,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
4089 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
4090 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
4091 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
4092
4093 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
4094 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
4095
4096 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
4097 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
4098 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
4099 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
4100
4101 { "icbtlse", X(31,494), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
4102
4103 { "slbia",   X(31,498), 0xffffffff,     PPC64,          { 0 } },
4104
4105 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
4106
4107 { "stdcxe.", XRC(31,511,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
4108
4109 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), COM,        { BF } },
4110
4111 { "bblels",  X(31,518), X_MASK,         PPCBRLK,        { 0 }},
4112 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64,    { BF } },
4113
4114 { "clcs",    X(31,531), XRB_MASK,       M601,           { RT, RA } },
4115
4116 { "lswx",    X(31,533), X_MASK,         PPCCOM,         { RT, RA0, RB } },
4117 { "lsx",     X(31,533), X_MASK,         PWRCOM,         { RT, RA, RB } },
4118
4119 { "lwbrx",   X(31,534), X_MASK,         PPCCOM,         { RT, RA0, RB } },
4120 { "lbrx",    X(31,534), X_MASK,         PWRCOM,         { RT, RA, RB } },
4121
4122 { "lfsx",    X(31,535), X_MASK,         COM,            { FRT, RA0, RB } },
4123
4124 { "srw",     XRC(31,536,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4125 { "sr",      XRC(31,536,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4126 { "srw.",    XRC(31,536,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4127 { "sr.",     XRC(31,536,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4128
4129 { "rrib",    XRC(31,537,0), X_MASK,     M601,           { RA, RS, RB } },
4130 { "rrib.",   XRC(31,537,1), X_MASK,     M601,           { RA, RS, RB } },
4131
4132 { "srd",     XRC(31,539,0), X_MASK,     PPC64,          { RA, RS, RB } },
4133 { "srd.",    XRC(31,539,1), X_MASK,     PPC64,          { RA, RS, RB } },
4134
4135 { "maskir",  XRC(31,541,0), X_MASK,     M601,           { RA, RS, RB } },
4136 { "maskir.", XRC(31,541,1), X_MASK,     M601,           { RA, RS, RB } },
4137
4138 { "lwbrxe",  X(31,542), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4139
4140 { "lfsxe",   X(31,543), X_MASK,         BOOKE64,        { FRT, RA0, RB } },
4141
4142 { "bbelr",   X(31,550), X_MASK,         PPCBRLK,        { 0 }},
4143
4144 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
4145
4146 { "lfsux",   X(31,567), X_MASK,         COM,            { FRT, RAS, RB } },
4147
4148 { "lfsuxe",  X(31,575), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4149
4150 { "mfsr",    X(31,595), XRB_MASK|(1<<20), COM32,        { RT, SR } },
4151
4152 { "lswi",    X(31,597), X_MASK,         PPCCOM,         { RT, RA0, NB } },
4153 { "lsi",     X(31,597), X_MASK,         PWRCOM,         { RT, RA0, NB } },
4154
4155 { "lwsync",  XSYNC(31,598,1), 0xffffffff, PPC,          { 0 } },
4156 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,        { 0 } },
4157 { "msync",   X(31,598), 0xffffffff,     BOOKE,          { 0 } },
4158 { "sync",    X(31,598), XSYNC_MASK,     PPCCOM,         { LS } },
4159 { "dcs",     X(31,598), 0xffffffff,     PWRCOM,         { 0 } },
4160
4161 { "lfdx",    X(31,599), X_MASK,         COM,            { FRT, RA0, RB } },
4162
4163 { "lfdxe",   X(31,607), X_MASK,         BOOKE64,        { FRT, RA0, RB } },
4164
4165 { "mfsri",   X(31,627), X_MASK,         PWRCOM,         { RT, RA, RB } },
4166
4167 { "dclst",   X(31,630), XRB_MASK,       PWRCOM,         { RS, RA } },
4168
4169 { "lfdux",   X(31,631), X_MASK,         COM,            { FRT, RAS, RB } },
4170
4171 { "lfduxe",  X(31,639), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4172
4173 { "mfsrin",  X(31,659), XRA_MASK,       PPC32,          { RT, RB } },
4174
4175 { "stswx",   X(31,661), X_MASK,         PPCCOM,         { RS, RA0, RB } },
4176 { "stsx",    X(31,661), X_MASK,         PWRCOM,         { RS, RA0, RB } },
4177
4178 { "stwbrx",  X(31,662), X_MASK,         PPCCOM,         { RS, RA0, RB } },
4179 { "stbrx",   X(31,662), X_MASK,         PWRCOM,         { RS, RA0, RB } },
4180
4181 { "stfsx",   X(31,663), X_MASK,         COM,            { FRS, RA0, RB } },
4182
4183 { "srq",     XRC(31,664,0), X_MASK,     M601,           { RA, RS, RB } },
4184 { "srq.",    XRC(31,664,1), X_MASK,     M601,           { RA, RS, RB } },
4185
4186 { "sre",     XRC(31,665,0), X_MASK,     M601,           { RA, RS, RB } },
4187 { "sre.",    XRC(31,665,1), X_MASK,     M601,           { RA, RS, RB } },
4188
4189 { "stwbrxe", X(31,670), X_MASK,         BOOKE64,        { RS, RA0, RB } },
4190
4191 { "stfsxe",  X(31,671), X_MASK,         BOOKE64,        { FRS, RA0, RB } },
4192
4193 { "stfsux",  X(31,695), X_MASK,         COM,            { FRS, RAS, RB } },
4194
4195 { "sriq",    XRC(31,696,0), X_MASK,     M601,           { RA, RS, SH } },
4196 { "sriq.",   XRC(31,696,1), X_MASK,     M601,           { RA, RS, SH } },
4197
4198 { "stfsuxe", X(31,703), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4199
4200 { "stswi",   X(31,725), X_MASK,         PPCCOM,         { RS, RA0, NB } },
4201 { "stsi",    X(31,725), X_MASK,         PWRCOM,         { RS, RA0, NB } },
4202
4203 { "stfdx",   X(31,727), X_MASK,         COM,            { FRS, RA0, RB } },
4204
4205 { "srlq",    XRC(31,728,0), X_MASK,     M601,           { RA, RS, RB } },
4206 { "srlq.",   XRC(31,728,1), X_MASK,     M601,           { RA, RS, RB } },
4207
4208 { "sreq",    XRC(31,729,0), X_MASK,     M601,           { RA, RS, RB } },
4209 { "sreq.",   XRC(31,729,1), X_MASK,     M601,           { RA, RS, RB } },
4210
4211 { "stfdxe",  X(31,735), X_MASK,         BOOKE64,        { FRS, RA0, RB } },
4212
4213 { "dcba",    X(31,758), XRT_MASK,       PPC405 | BOOKE, { RA, RB } },
4214
4215 { "stfdux",  X(31,759), X_MASK,         COM,            { FRS, RAS, RB } },
4216
4217 { "srliq",   XRC(31,760,0), X_MASK,     M601,           { RA, RS, SH } },
4218 { "srliq.",  XRC(31,760,1), X_MASK,     M601,           { RA, RS, SH } },
4219
4220 { "dcbae",   X(31,766), XRT_MASK,       BOOKE64,        { RA, RB } },
4221
4222 { "stfduxe", X(31,767), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4223
4224 { "tlbivax", X(31,786), XRT_MASK,       BOOKE,          { RA, RB } },
4225 { "tlbivaxe",X(31,787), XRT_MASK,       BOOKE64,        { RA, RB } },
4226
4227 { "lhbrx",   X(31,790), X_MASK,         COM,            { RT, RA0, RB } },
4228
4229 { "sraw",    XRC(31,792,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4230 { "sra",     XRC(31,792,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4231 { "sraw.",   XRC(31,792,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4232 { "sra.",    XRC(31,792,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4233
4234 { "srad",    XRC(31,794,0), X_MASK,     PPC64,          { RA, RS, RB } },
4235 { "srad.",   XRC(31,794,1), X_MASK,     PPC64,          { RA, RS, RB } },
4236
4237 { "lhbrxe",  X(31,798), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4238
4239 { "ldxe",    X(31,799), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4240 { "lduxe",   X(31,831), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4241
4242 { "rac",     X(31,818), X_MASK,         PWRCOM,         { RT, RA, RB } },
4243
4244 { "dss",     XDSS(31,822,0), XDSS_MASK, PPCVEC,         { STRM } },
4245 { "dssall",  XDSS(31,822,1), XDSS_MASK, PPCVEC,         { 0 } },
4246
4247 { "srawi",   XRC(31,824,0), X_MASK,     PPCCOM,         { RA, RS, SH } },
4248 { "srai",    XRC(31,824,0), X_MASK,     PWRCOM,         { RA, RS, SH } },
4249 { "srawi.",  XRC(31,824,1), X_MASK,     PPCCOM,         { RA, RS, SH } },
4250 { "srai.",   XRC(31,824,1), X_MASK,     PWRCOM,         { RA, RS, SH } },
4251
4252 { "slbmfev", X(31,851), XRA_MASK,       PPC64,          { RT, RB } },
4253
4254 { "mbar",    X(31,854), X_MASK,         BOOKE,          { MO } },
4255 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
4256
4257 { "tlbsx",   XRC(31,914,0), X_MASK,     BOOKE,          { RA, RB } },
4258 { "tlbsx",   XRC(31,914,0), X_MASK,     PPC403,         { RT, RA, RB } },
4259 { "tlbsx.",  XRC(31,914,1), X_MASK,     BOOKE,          { RA, RB } },
4260 { "tlbsx.",  XRC(31,914,1), X_MASK,     PPC403,         { RT, RA, RB } },
4261 { "tlbsxe",  XRC(31,915,0), X_MASK,     BOOKE64,        { RA, RB } },
4262 { "tlbsxe.", XRC(31,915,1), X_MASK,     BOOKE64,        { RA, RB } },
4263
4264 { "slbmfee", X(31,915), XRA_MASK,       PPC64,          { RT, RB } },
4265
4266 { "sthbrx",  X(31,918), X_MASK,         COM,            { RS, RA0, RB } },
4267
4268 { "sraq",    XRC(31,920,0), X_MASK,     M601,           { RA, RS, RB } },
4269 { "sraq.",   XRC(31,920,1), X_MASK,     M601,           { RA, RS, RB } },
4270
4271 { "srea",    XRC(31,921,0), X_MASK,     M601,           { RA, RS, RB } },
4272 { "srea.",   XRC(31,921,1), X_MASK,     M601,           { RA, RS, RB } },
4273
4274 { "extsh",   XRC(31,922,0), XRB_MASK,   PPCCOM,         { RA, RS } },
4275 { "exts",    XRC(31,922,0), XRB_MASK,   PWRCOM,         { RA, RS } },
4276 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPCCOM,         { RA, RS } },
4277 { "exts.",   XRC(31,922,1), XRB_MASK,   PWRCOM,         { RA, RS } },
4278
4279 { "sthbrxe", X(31,926), X_MASK,         BOOKE64,        { RS, RA0, RB } },
4280
4281 { "stdxe",   X(31,927), X_MASK,         BOOKE64,        { RS, RA0, RB } },
4282
4283 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403,         { RT, RA } },
4284 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403,         { RT, RA } },
4285 { "tlbre",   X(31,946), X_MASK,         BOOKE,          { 0 } },
4286 { "tlbre",   X(31,946), X_MASK,         PPC403,         { RS, RA, SH } },
4287
4288 { "sraiq",   XRC(31,952,0), X_MASK,     M601,           { RA, RS, SH } },
4289 { "sraiq.",  XRC(31,952,1), X_MASK,     M601,           { RA, RS, SH } },
4290
4291 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
4292 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
4293
4294 { "stduxe",  X(31,959), X_MASK,         BOOKE64,        { RS, RAS, RB } },
4295
4296 { "iccci",   X(31,966), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
4297
4298 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403,         { RT, RA } },
4299 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403,         { RT, RA } },
4300 { "tlbwe",   X(31,978), X_MASK,         PPC403|BOOKE,   { RSO, RAOPT, SHO } },
4301 { "tlbld",   X(31,978), XRTRA_MASK,     PPC,            { RB } },
4302
4303 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
4304
4305 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA0, RB } },
4306
4307 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC64 | BOOKE64,{ RA, RS } },
4308 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC64,          { RA, RS } },
4309
4310 { "icread",  X(31,998), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
4311
4312 { "icbie",   X(31,990), XRT_MASK,       BOOKE64,        { RA, RB } },
4313 { "stfiwxe", X(31,991), X_MASK,         BOOKE64,        { FRS, RA0, RB } },
4314
4315 { "tlbli",   X(31,1010), XRTRA_MASK,    PPC,            { RB } },
4316
4317 { "dcbzl",   XOPL(31,1014,1), XRT_MASK,POWER4,            { RA, RB } },
4318 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4319 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4320
4321 { "dcbze",   X(31,1022), XRT_MASK,      BOOKE64,        { RA, RB } },
4322
4323 { "lvebx",   X(31,   7), X_MASK,        PPCVEC,         { VD, RA, RB } },
4324 { "lvehx",   X(31,  39), X_MASK,        PPCVEC,         { VD, RA, RB } },
4325 { "lvewx",   X(31,  71), X_MASK,        PPCVEC,         { VD, RA, RB } },
4326 { "lvsl",    X(31,   6), X_MASK,        PPCVEC,         { VD, RA, RB } },
4327 { "lvsr",    X(31,  38), X_MASK,        PPCVEC,         { VD, RA, RB } },
4328 { "lvx",     X(31, 103), X_MASK,        PPCVEC,         { VD, RA, RB } },
4329 { "lvxl",    X(31, 359), X_MASK,        PPCVEC,         { VD, RA, RB } },
4330 { "stvebx",  X(31, 135), X_MASK,        PPCVEC,         { VS, RA, RB } },
4331 { "stvehx",  X(31, 167), X_MASK,        PPCVEC,         { VS, RA, RB } },
4332 { "stvewx",  X(31, 199), X_MASK,        PPCVEC,         { VS, RA, RB } },
4333 { "stvx",    X(31, 231), X_MASK,        PPCVEC,         { VS, RA, RB } },
4334 { "stvxl",   X(31, 487), X_MASK,        PPCVEC,         { VS, RA, RB } },
4335
4336 { "lwz",     OP(32),    OP_MASK,        PPCCOM,         { RT, D, RA0 } },
4337 { "l",       OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
4338
4339 { "lwzu",    OP(33),    OP_MASK,        PPCCOM,         { RT, D, RAL } },
4340 { "lu",      OP(33),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
4341
4342 { "lbz",     OP(34),    OP_MASK,        COM,            { RT, D, RA0 } },
4343
4344 { "lbzu",    OP(35),    OP_MASK,        COM,            { RT, D, RAL } },
4345
4346 { "stw",     OP(36),    OP_MASK,        PPCCOM,         { RS, D, RA0 } },
4347 { "st",      OP(36),    OP_MASK,        PWRCOM,         { RS, D, RA0 } },
4348
4349 { "stwu",    OP(37),    OP_MASK,        PPCCOM,         { RS, D, RAS } },
4350 { "stu",     OP(37),    OP_MASK,        PWRCOM,         { RS, D, RA0 } },
4351
4352 { "stb",     OP(38),    OP_MASK,        COM,            { RS, D, RA0 } },
4353
4354 { "stbu",    OP(39),    OP_MASK,        COM,            { RS, D, RAS } },
4355
4356 { "lhz",     OP(40),    OP_MASK,        COM,            { RT, D, RA0 } },
4357
4358 { "lhzu",    OP(41),    OP_MASK,        COM,            { RT, D, RAL } },
4359
4360 { "lha",     OP(42),    OP_MASK,        COM,            { RT, D, RA0 } },
4361
4362 { "lhau",    OP(43),    OP_MASK,        COM,            { RT, D, RAL } },
4363
4364 { "sth",     OP(44),    OP_MASK,        COM,            { RS, D, RA0 } },
4365
4366 { "sthu",    OP(45),    OP_MASK,        COM,            { RS, D, RAS } },
4367
4368 { "lmw",     OP(46),    OP_MASK,        PPCCOM,         { RT, D, RAM } },
4369 { "lm",      OP(46),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
4370
4371 { "stmw",    OP(47),    OP_MASK,        PPCCOM,         { RS, D, RA0 } },
4372 { "stm",     OP(47),    OP_MASK,        PWRCOM,         { RS, D, RA0 } },
4373
4374 { "lfs",     OP(48),    OP_MASK,        COM,            { FRT, D, RA0 } },
4375
4376 { "lfsu",    OP(49),    OP_MASK,        COM,            { FRT, D, RAS } },
4377
4378 { "lfd",     OP(50),    OP_MASK,        COM,            { FRT, D, RA0 } },
4379
4380 { "lfdu",    OP(51),    OP_MASK,        COM,            { FRT, D, RAS } },
4381
4382 { "stfs",    OP(52),    OP_MASK,        COM,            { FRS, D, RA0 } },
4383
4384 { "stfsu",   OP(53),    OP_MASK,        COM,            { FRS, D, RAS } },
4385
4386 { "stfd",    OP(54),    OP_MASK,        COM,            { FRS, D, RA0 } },
4387
4388 { "stfdu",   OP(55),    OP_MASK,        COM,            { FRS, D, RAS } },
4389
4390 { "lq",      OP(56),    OP_MASK,        POWER4,         { RTQ, DQ, RAQ } },
4391
4392 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA0 } },
4393
4394 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA0 } },
4395
4396 { "lbze",    DEO(58,0), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4397 { "lbzue",   DEO(58,1), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4398 { "lhze",    DEO(58,2), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4399 { "lhzue",   DEO(58,3), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4400 { "lhae",    DEO(58,4), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4401 { "lhaue",   DEO(58,5), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4402 { "lwze",    DEO(58,6), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4403 { "lwzue",   DEO(58,7), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4404 { "stbe",    DEO(58,8), DE_MASK,        BOOKE64,        { RS, DE, RA0 } },
4405 { "stbue",   DEO(58,9), DE_MASK,        BOOKE64,        { RS, DE, RAS } },
4406 { "sthe",    DEO(58,10), DE_MASK,       BOOKE64,        { RS, DE, RA0 } },
4407 { "sthue",   DEO(58,11), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4408 { "stwe",    DEO(58,14), DE_MASK,       BOOKE64,        { RS, DE, RA0 } },
4409 { "stwue",   DEO(58,15), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4410
4411 { "ld",      DSO(58,0), DS_MASK,        PPC64,          { RT, DS, RA0 } },
4412
4413 { "ldu",     DSO(58,1), DS_MASK,        PPC64,          { RT, DS, RAL } },
4414
4415 { "lwa",     DSO(58,2), DS_MASK,        PPC64,          { RT, DS, RA0 } },
4416
4417 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4418 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4419
4420 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4421 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4422
4423 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4424 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4425
4426 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4427 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4428
4429 { "fres",    A(59,24,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4430 { "fres.",   A(59,24,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4431
4432 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4433 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4434
4435 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4436 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4437
4438 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4439 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4440
4441 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4442 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4443
4444 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4445 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4446
4447 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
4448
4449 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
4450
4451 { "lde",     DEO(62,0), DE_MASK,        BOOKE64,        { RT, DES, RA0 } },
4452 { "ldue",    DEO(62,1), DE_MASK,        BOOKE64,        { RT, DES, RA0 } },
4453 { "lfse",    DEO(62,4), DE_MASK,        BOOKE64,        { FRT, DES, RA0 } },
4454 { "lfsue",   DEO(62,5), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4455 { "lfde",    DEO(62,6), DE_MASK,        BOOKE64,        { FRT, DES, RA0 } },
4456 { "lfdue",   DEO(62,7), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4457 { "stde",    DEO(62,8), DE_MASK,        BOOKE64,        { RS, DES, RA0 } },
4458 { "stdue",   DEO(62,9), DE_MASK,        BOOKE64,        { RS, DES, RAS } },
4459 { "stfse",   DEO(62,12), DE_MASK,       BOOKE64,        { FRS, DES, RA0 } },
4460 { "stfsue",  DEO(62,13), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4461 { "stfde",   DEO(62,14), DE_MASK,       BOOKE64,        { FRS, DES, RA0 } },
4462 { "stfdue",  DEO(62,15), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4463
4464 { "std",     DSO(62,0), DS_MASK,        PPC64,          { RS, DS, RA0 } },
4465
4466 { "stdu",    DSO(62,1), DS_MASK,        PPC64,          { RS, DS, RAS } },
4467
4468 { "stq",     DSO(62,2), DS_MASK,        POWER4,         { RSQ, DS, RA0 } },
4469
4470 { "fcmpu",   X(63,0),   X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4471
4472 { "frsp",    XRC(63,12,0), XRA_MASK,    COM,            { FRT, FRB } },
4473 { "frsp.",   XRC(63,12,1), XRA_MASK,    COM,            { FRT, FRB } },
4474
4475 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4476 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4477 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4478 { "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4479
4480 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4481 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4482 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4483 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4484
4485 { "fdiv",    A(63,18,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4486 { "fd",      A(63,18,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4487 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4488 { "fd.",     A(63,18,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4489
4490 { "fsub",    A(63,20,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4491 { "fs",      A(63,20,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4492 { "fsub.",   A(63,20,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4493 { "fs.",     A(63,20,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4494
4495 { "fadd",    A(63,21,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4496 { "fa",      A(63,21,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4497 { "fadd.",   A(63,21,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4498 { "fa.",     A(63,21,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4499
4500 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4501 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4502
4503 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4504 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4505
4506 { "fmul",    A(63,25,0), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4507 { "fm",      A(63,25,0), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4508 { "fmul.",   A(63,25,1), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4509 { "fm.",     A(63,25,1), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4510
4511 { "frsqrte", A(63,26,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4512 { "frsqrte.",A(63,26,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4513
4514 { "fmsub",   A(63,28,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4515 { "fms",     A(63,28,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4516 { "fmsub.",  A(63,28,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4517 { "fms.",    A(63,28,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4518
4519 { "fmadd",   A(63,29,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4520 { "fma",     A(63,29,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4521 { "fmadd.",  A(63,29,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4522 { "fma.",    A(63,29,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4523
4524 { "fnmsub",  A(63,30,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4525 { "fnms",    A(63,30,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4526 { "fnmsub.", A(63,30,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4527 { "fnms.",   A(63,30,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4528
4529 { "fnmadd",  A(63,31,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4530 { "fnma",    A(63,31,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4531 { "fnmadd.", A(63,31,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4532 { "fnma.",   A(63,31,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4533
4534 { "fcmpo",   X(63,32),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4535
4536 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  COM,            { BT } },
4537 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  COM,            { BT } },
4538
4539 { "fneg",    XRC(63,40,0), XRA_MASK,    COM,            { FRT, FRB } },
4540 { "fneg.",   XRC(63,40,1), XRA_MASK,    COM,            { FRT, FRB } },
4541
4542 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), COM,  { BF, BFA } },
4543
4544 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  COM,            { BT } },
4545 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  COM,            { BT } },
4546
4547 { "fmr",     XRC(63,72,0), XRA_MASK,    COM,            { FRT, FRB } },
4548 { "fmr.",    XRC(63,72,1), XRA_MASK,    COM,            { FRT, FRB } },
4549
4550 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4551 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4552
4553 { "fnabs",   XRC(63,136,0), XRA_MASK,   COM,            { FRT, FRB } },
4554 { "fnabs.",  XRC(63,136,1), XRA_MASK,   COM,            { FRT, FRB } },
4555
4556 { "fabs",    XRC(63,264,0), XRA_MASK,   COM,            { FRT, FRB } },
4557 { "fabs.",   XRC(63,264,1), XRA_MASK,   COM,            { FRT, FRB } },
4558
4559 { "mffs",    XRC(63,583,0), XRARB_MASK, COM,            { FRT } },
4560 { "mffs.",   XRC(63,583,1), XRARB_MASK, COM,            { FRT } },
4561
4562 { "mtfsf",   XFL(63,711,0), XFL_MASK,   COM,            { FLM, FRB } },
4563 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   COM,            { FLM, FRB } },
4564
4565 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4566 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4567
4568 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4569 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4570
4571 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4572 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4573
4574 };
4575
4576 const int powerpc_num_opcodes =
4577   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4578 \f
4579 /* The macro table.  This is only used by the assembler.  */
4580
4581 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4582    when x=0; 32-x when x is between 1 and 31; are negative if x is
4583    negative; and are 32 or more otherwise.  This is what you want
4584    when, for instance, you are emulating a right shift by a
4585    rotate-left-and-mask, because the underlying instructions support
4586    shifts of size 0 but not shifts of size 32.  By comparison, when
4587    extracting x bits from some word you want to use just 32-x, because
4588    the underlying instructions don't support extracting 0 bits but do
4589    support extracting the whole word (32 bits in this case).  */
4590
4591 const struct powerpc_macro powerpc_macros[] = {
4592 { "extldi",  4,   PPC64,        "rldicr %0,%1,%3,(%2)-1" },
4593 { "extldi.", 4,   PPC64,        "rldicr. %0,%1,%3,(%2)-1" },
4594 { "extrdi",  4,   PPC64,        "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4595 { "extrdi.", 4,   PPC64,        "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4596 { "insrdi",  4,   PPC64,        "rldimi %0,%1,64-((%2)+(%3)),%3" },
4597 { "insrdi.", 4,   PPC64,        "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4598 { "rotrdi",  3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4599 { "rotrdi.", 3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4600 { "sldi",    3,   PPC64,        "rldicr %0,%1,%2,63-(%2)" },
4601 { "sldi.",   3,   PPC64,        "rldicr. %0,%1,%2,63-(%2)" },
4602 { "srdi",    3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4603 { "srdi.",   3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4604 { "clrrdi",  3,   PPC64,        "rldicr %0,%1,0,63-(%2)" },
4605 { "clrrdi.", 3,   PPC64,        "rldicr. %0,%1,0,63-(%2)" },
4606 { "clrlsldi",4,   PPC64,        "rldic %0,%1,%3,(%2)-(%3)" },
4607 { "clrlsldi.",4,  PPC64,        "rldic. %0,%1,%3,(%2)-(%3)" },
4608
4609 { "extlwi",  4,   PPCCOM,       "rlwinm %0,%1,%3,0,(%2)-1" },
4610 { "extlwi.", 4,   PPCCOM,       "rlwinm. %0,%1,%3,0,(%2)-1" },
4611 { "extrwi",  4,   PPCCOM,       "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4612 { "extrwi.", 4,   PPCCOM,       "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4613 { "inslwi",  4,   PPCCOM,       "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4614 { "inslwi.", 4,   PPCCOM,       "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4615 { "insrwi",  4,   PPCCOM,       "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4616 { "insrwi.", 4,   PPCCOM,       "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4617 { "rotrwi",  3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4618 { "rotrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4619 { "slwi",    3,   PPCCOM,       "rlwinm %0,%1,%2,0,31-(%2)" },
4620 { "sli",     3,   PWRCOM,       "rlinm %0,%1,%2,0,31-(%2)" },
4621 { "slwi.",   3,   PPCCOM,       "rlwinm. %0,%1,%2,0,31-(%2)" },
4622 { "sli.",    3,   PWRCOM,       "rlinm. %0,%1,%2,0,31-(%2)" },
4623 { "srwi",    3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4624 { "sri",     3,   PWRCOM,       "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4625 { "srwi.",   3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4626 { "sri.",    3,   PWRCOM,       "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4627 { "clrrwi",  3,   PPCCOM,       "rlwinm %0,%1,0,0,31-(%2)" },
4628 { "clrrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,0,0,31-(%2)" },
4629 { "clrlslwi",4,   PPCCOM,       "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4630 { "clrlslwi.",4,  PPCCOM,       "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4631 };
4632
4633 const int powerpc_num_macros =
4634   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);