1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of GDB, GAS, and the GNU binutils.
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 2, or (at your option) any later version.
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
23 #include "opcode/ppc.h"
25 /* This file holds the PowerPC opcode table. The opcode table
26 includes almost all of the extended instruction mnemonics. This
27 permits the disassembler to use them, and simplifies the assembler
28 logic, at the cost of increasing the table size. The table is
29 strictly constant data, so the compiler should be able to put it in
32 This file also holds the operand table. All knowledge about
33 inserting operands into instructions and vice-versa is kept in this
36 /* Local insertion and extraction functions. */
38 static unsigned long insert_bat
PARAMS ((unsigned long, long, const char **));
39 static long extract_bat
PARAMS ((unsigned long, int *));
40 static unsigned long insert_bba
PARAMS ((unsigned long, long, const char **));
41 static long extract_bba
PARAMS ((unsigned long, int *));
42 static unsigned long insert_bd
PARAMS ((unsigned long, long, const char **));
43 static long extract_bd
PARAMS ((unsigned long, int *));
44 static unsigned long insert_bdm
PARAMS ((unsigned long, long, const char **));
45 static long extract_bdm
PARAMS ((unsigned long, int *));
46 static unsigned long insert_bdp
PARAMS ((unsigned long, long, const char **));
47 static long extract_bdp
PARAMS ((unsigned long, int *));
48 static unsigned long insert_bo
PARAMS ((unsigned long, long, const char **));
49 static long extract_bo
PARAMS ((unsigned long, int *));
50 static unsigned long insert_boe
PARAMS ((unsigned long, long, const char **));
51 static long extract_boe
PARAMS ((unsigned long, int *));
52 static unsigned long insert_cr
PARAMS ((unsigned long, long, const char **));
53 static long extract_cr
PARAMS ((unsigned long, int *));
54 static unsigned long insert_ds
PARAMS ((unsigned long, long, const char **));
55 static long extract_ds
PARAMS ((unsigned long, int *));
56 static unsigned long insert_li
PARAMS ((unsigned long, long, const char **));
57 static long extract_li
PARAMS ((unsigned long, int *));
58 static unsigned long insert_mbe
PARAMS ((unsigned long, long, const char **));
59 static long extract_mbe
PARAMS ((unsigned long, int *));
60 static unsigned long insert_mb6
PARAMS ((unsigned long, long, const char **));
61 static long extract_mb6
PARAMS ((unsigned long, int *));
62 static unsigned long insert_nb
PARAMS ((unsigned long, long, const char **));
63 static long extract_nb
PARAMS ((unsigned long, int *));
64 static unsigned long insert_nsi
PARAMS ((unsigned long, long, const char **));
65 static long extract_nsi
PARAMS ((unsigned long, int *));
66 static unsigned long insert_rbs
PARAMS ((unsigned long, long, const char **));
67 static long extract_rbs
PARAMS ((unsigned long, int *));
68 static unsigned long insert_sh6
PARAMS ((unsigned long, long, const char **));
69 static long extract_sh6
PARAMS ((unsigned long, int *));
70 static unsigned long insert_spr
PARAMS ((unsigned long, long, const char **));
71 static long extract_spr
PARAMS ((unsigned long, int *));
73 /* The operands table.
75 The fields are bits, shift, signed, insert, extract, flags. */
77 const struct powerpc_operand powerpc_operands
[] =
79 /* The zero index is used to indicate the end of the list of
84 /* The BA field in an XL form instruction. */
85 #define BA (UNUSED + 1)
86 #define BA_MASK (0x1f << 16)
87 { 5, 16, 0, 0, 0, PPC_OPERAND_CR
},
89 /* The BA field in an XL form instruction when it must be the same
90 as the BT field in the same instruction. */
92 { 5, 16, 0, insert_bat
, extract_bat
, PPC_OPERAND_FAKE
},
94 /* The BB field in an XL form instruction. */
96 #define BB_MASK (0x1f << 11)
97 { 5, 11, 0, 0, 0, PPC_OPERAND_CR
},
99 /* The BB field in an XL form instruction when it must be the same
100 as the BA field in the same instruction. */
102 { 5, 11, 0, insert_bba
, extract_bba
, PPC_OPERAND_FAKE
},
104 /* The BD field in a B form instruction. The lower two bits are
107 { 16, 0, 1, insert_bd
, extract_bd
, PPC_OPERAND_RELATIVE
},
109 /* The BD field in a B form instruction when absolute addressing is
112 { 16, 0, 1, insert_bd
, extract_bd
, PPC_OPERAND_ABSOLUTE
},
114 /* The BD field in a B form instruction when the - modifier is used.
115 This sets the y bit of the BO field appropriately. */
116 #define BDM (BDA + 1)
117 { 16, 0, 1, insert_bdm
, extract_bdm
, PPC_OPERAND_RELATIVE
},
119 /* The BD field in a B form instruction when the - modifier is used
120 and absolute address is used. */
121 #define BDMA (BDM + 1)
122 { 16, 0, 1, insert_bdm
, extract_bdm
, PPC_OPERAND_ABSOLUTE
},
124 /* The BD field in a B form instruction when the + modifier is used.
125 This sets the y bit of the BO field appropriately. */
126 #define BDP (BDMA + 1)
127 { 16, 0, 1, insert_bdp
, extract_bdp
, PPC_OPERAND_RELATIVE
},
129 /* The BD field in a B form instruction when the + modifier is used
130 and absolute addressing is used. */
131 #define BDPA (BDP + 1)
132 { 16, 0, 1, insert_bdp
, extract_bdp
, PPC_OPERAND_ABSOLUTE
},
134 /* The BF field in an X or XL form instruction. */
135 #define BF (BDPA + 1)
136 { 3, 23, 0, 0, 0, PPC_OPERAND_CR
},
138 /* An optional BF field. This is used for comparison instructions,
139 in which an omitted BF field is taken as zero. */
141 { 3, 23, 0, 0, 0, PPC_OPERAND_CR
| PPC_OPERAND_OPTIONAL
},
143 /* The BFA field in an X or XL form instruction. */
144 #define BFA (OBF + 1)
145 { 3, 18, 0, 0, 0, PPC_OPERAND_CR
},
147 /* The BI field in a B form or XL form instruction. */
149 #define BI_MASK (0x1f << 16)
150 { 5, 16, 0, 0, 0, PPC_OPERAND_CR
},
152 /* The BO field in a B form instruction. Certain values are
155 #define BO_MASK (0x1f << 21)
156 { 5, 21, 0, insert_bo
, extract_bo
, 0 },
158 /* The BO field in a B form instruction when the + or - modifier is
159 used. This is like the BO field, but it must be even. */
161 { 5, 21, 0, insert_boe
, extract_boe
, 0 },
163 /* The BT field in an X or XL form instruction. */
165 { 5, 21, 0, 0, 0, PPC_OPERAND_CR
},
167 /* The condition register number portion of the BI field in a B form
168 or XL form instruction. This is used for the extended
169 conditional branch mnemonics, which set the lower two bits of the
170 BI field. This field is optional. */
172 { 5, 16, 0, insert_cr
, extract_cr
, PPC_OPERAND_CR
| PPC_OPERAND_OPTIONAL
},
174 /* The D field in a D form instruction. This is a displacement off
175 a register, and implies that the next operand is a register in
178 { 16, 0, 1, 0, 0, PPC_OPERAND_PARENS
},
180 /* The DS field in a DS form instruction. This is like D, but the
181 lower two bits are forced to zero. */
183 { 16, 0, 1, insert_ds
, extract_ds
, PPC_OPERAND_PARENS
},
185 /* The FL1 field in a POWER SC form instruction. */
187 { 4, 12, 0, 0, 0, 0 },
189 /* The FL2 field in a POWER SC form instruction. */
190 #define FL2 (FL1 + 1)
191 { 3, 2, 0, 0, 0, 0 },
193 /* The FLM field in an XFL form instruction. */
194 #define FLM (FL2 + 1)
195 { 8, 17, 0, 0, 0, 0 },
197 /* The FRA field in an X or A form instruction. */
198 #define FRA (FLM + 1)
199 #define FRA_MASK (0x1f << 16)
200 { 5, 16, 0, 0, 0, PPC_OPERAND_FPR
},
202 /* The FRB field in an X or A form instruction. */
203 #define FRB (FRA + 1)
204 #define FRB_MASK (0x1f << 11)
205 { 5, 11, 0, 0, 0, PPC_OPERAND_FPR
},
207 /* The FRC field in an A form instruction. */
208 #define FRC (FRB + 1)
209 #define FRC_MASK (0x1f << 6)
210 { 5, 6, 0, 0, 0, PPC_OPERAND_FPR
},
212 /* The FRS field in an X form instruction or the FRT field in a D, X
213 or A form instruction. */
214 #define FRS (FRC + 1)
216 { 5, 21, 0, 0, 0, PPC_OPERAND_FPR
},
218 /* The FXM field in an XFX instruction. */
219 #define FXM (FRS + 1)
220 { 8, 12, 0, 0, 0, 0 },
222 /* The L field in a D or X form instruction. */
224 { 1, 21, 0, 0, 0, PPC_OPERAND_OPTIONAL
},
226 /* The LEV field in a POWER SC form instruction. */
228 { 7, 5, 0, 0, 0, 0 },
230 /* The LI field in an I form instruction. The lower two bits are
233 { 26, 0, 1, insert_li
, extract_li
, PPC_OPERAND_RELATIVE
},
235 /* The LI field in an I form instruction when used as an absolute
238 { 26, 0, 1, insert_li
, extract_li
, PPC_OPERAND_ABSOLUTE
},
240 /* The MB field in an M form instruction. */
242 #define MB_MASK (0x1f << 6)
243 { 5, 6, 0, 0, 0, 0 },
245 /* The ME field in an M form instruction. */
247 #define ME_MASK (0x1f << 1)
248 { 5, 1, 0, 0, 0, 0 },
250 /* The MB and ME fields in an M form instruction expressed a single
251 operand which is a bitmask indicating which bits to select. This
252 is a two operand form using PPC_OPERAND_NEXT. See the
253 description in opcode/ppc.h for what this means. */
255 { 5, 6, 0, 0, 0, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
256 { 32, 0, 0, insert_mbe
, extract_mbe
, 0 },
258 /* The MB or ME field in an MD or MDS form instruction. The high
259 bit is wrapped to the low end. */
260 #define MB6 (MBE + 2)
262 #define MB6_MASK (0x3f << 5)
263 { 6, 5, 0, insert_mb6
, extract_mb6
, 0 },
265 /* The NB field in an X form instruction. The value 32 is stored as
268 { 6, 11, 0, insert_nb
, extract_nb
, 0 },
270 /* The NSI field in a D form instruction. This is the same as the
271 SI field, only negated. */
273 { 16, 0, 1, insert_nsi
, extract_nsi
, PPC_OPERAND_NEGATIVE
},
275 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
277 #define RA_MASK (0x1f << 16)
278 { 5, 16, 0, 0, 0, PPC_OPERAND_GPR
},
280 /* The RB field in an X, XO, M, or MDS form instruction. */
282 #define RB_MASK (0x1f << 11)
283 { 5, 11, 0, 0, 0, PPC_OPERAND_GPR
},
285 /* The RB field in an X form instruction when it must be the same as
286 the RS field in the instruction. This is used for extended
287 mnemonics like mr. */
289 { 5, 1, 0, insert_rbs
, extract_rbs
, PPC_OPERAND_FAKE
},
291 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
292 instruction or the RT field in a D, DS, X, XFX or XO form
296 #define RT_MASK (0x1f << 21)
297 { 5, 21, 0, 0, 0, PPC_OPERAND_GPR
},
299 /* The SH field in an X or M form instruction. */
301 #define SH_MASK (0x1f << 11)
302 { 5, 11, 0, 0, 0, 0 },
304 /* The SH field in an MD form instruction. This is split. */
306 #define SH6_MASK ((0x1f << 11) | (1 << 1))
307 { 6, 1, 0, insert_sh6
, extract_sh6
, 0 },
309 /* The SI field in a D form instruction. */
311 { 16, 0, 1, 0, 0, 0 },
313 /* The SPR or TBR field in an XFX form instruction. This is
314 flipped--the lower 5 bits are stored in the upper 5 and vice-
318 #define SPR_MASK (0x3ff << 11)
319 { 10, 11, 0, insert_spr
, extract_spr
, 0 },
321 /* The SR field in an X form instruction. */
323 { 4, 16, 0, 0, 0, 0 },
325 /* The SV field in a POWER SC form instruction. */
327 { 14, 2, 0, 0, 0, 0 },
329 /* The TO field in a D or X form instruction. */
331 #define TO_MASK (0x1f << 21)
332 { 5, 21, 0, 0, 0, 0 },
334 /* The U field in an X form instruction. */
336 { 4, 12, 0, 0, 0, 0 },
338 /* The UI field in a D form instruction. */
340 { 16, 0, 0, 0, 0, 0 },
343 /* The functions used to insert and extract complicated operands. */
345 /* The BA field in an XL form instruction when it must be the same as
346 the BT field in the same instruction. This operand is marked FAKE.
347 The insertion function just copies the BT field into the BA field,
348 and the extraction function just checks that the fields are the
353 insert_bat (insn
, value
, errmsg
)
358 return insn
| (((insn
>> 21) & 0x1f) << 16);
362 extract_bat (insn
, invalid
)
366 if (invalid
!= (int *) NULL
367 && ((insn
>> 21) & 0x1f) != ((insn
>> 16) & 0x1f))
372 /* The BB field in an XL form instruction when it must be the same as
373 the BA field in the same instruction. This operand is marked FAKE.
374 The insertion function just copies the BA field into the BB field,
375 and the extraction function just checks that the fields are the
380 insert_bba (insn
, value
, errmsg
)
385 return insn
| (((insn
>> 16) & 0x1f) << 11);
389 extract_bba (insn
, invalid
)
393 if (invalid
!= (int *) NULL
394 && ((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
399 /* The BD field in a B form instruction. The lower two bits are
404 insert_bd (insn
, value
, errmsg
)
409 return insn
| (value
& 0xfffc);
414 extract_bd (insn
, invalid
)
418 if ((insn
& 0x8000) != 0)
419 return (insn
& 0xfffc) - 0x10000;
421 return insn
& 0xfffc;
424 /* The BD field in a B form instruction when the - modifier is used.
425 This modifier means that the branch is not expected to be taken.
426 We must set the y bit of the BO field to 1 if the offset is
427 negative. When extracting, we require that the y bit be 1 and that
428 the offset be positive, since if the y bit is 0 we just want to
429 print the normal form of the instruction. */
433 insert_bdm (insn
, value
, errmsg
)
438 if ((value
& 0x8000) != 0)
440 return insn
| (value
& 0xfffc);
444 extract_bdm (insn
, invalid
)
448 if (invalid
!= (int *) NULL
449 && ((insn
& (1 << 21)) == 0
450 || (insn
& (1 << 15) == 0)))
452 if ((insn
& 0x8000) != 0)
453 return (insn
& 0xfffc) - 0x10000;
455 return insn
& 0xfffc;
458 /* The BD field in a B form instruction when the + modifier is used.
459 This is like BDM, above, except that the branch is expected to be
464 insert_bdp (insn
, value
, errmsg
)
469 if ((value
& 0x8000) == 0)
471 return insn
| (value
& 0xfffc);
475 extract_bdp (insn
, invalid
)
479 if (invalid
!= (int *) NULL
480 && ((insn
& (1 << 21)) == 0
481 || (insn
& (1 << 15)) != 0))
483 if ((insn
& 0x8000) != 0)
484 return (insn
& 0xfffc) - 0x10000;
486 return insn
& 0xfffc;
489 /* Check for legal values of a BO field. */
495 /* Certain encodings have bits that are required to be zero. These
496 are (z must be zero, y may be anything):
503 switch (value
& 0x14)
509 return (value
& 0x2) == 0;
511 return (value
& 0x8) == 0;
513 return value
== 0x14;
517 /* The BO field in a B form instruction. Warn about attempts to set
518 the field to an illegal value. */
521 insert_bo (insn
, value
, errmsg
)
526 if (errmsg
!= (const char **) NULL
527 && ! valid_bo (value
))
528 *errmsg
= "invalid conditional option";
529 return insn
| ((value
& 0x1f) << 21);
533 extract_bo (insn
, invalid
)
539 value
= (insn
>> 21) & 0x1f;
540 if (invalid
!= (int *) NULL
541 && ! valid_bo (value
))
546 /* The BO field in a B form instruction when the + or - modifier is
547 used. This is like the BO field, but it must be even. When
548 extracting it, we force it to be even. */
551 insert_boe (insn
, value
, errmsg
)
556 if (errmsg
!= (const char **) NULL
)
558 if (! valid_bo (value
))
559 *errmsg
= "invalid conditional option";
560 else if ((value
& 1) != 0)
561 *errmsg
= "attempt to set y bit when using + or - modifier";
563 return insn
| ((value
& 0x1f) << 21);
567 extract_boe (insn
, invalid
)
573 value
= (insn
>> 21) & 0x1f;
574 if (invalid
!= (int *) NULL
575 && ! valid_bo (value
))
580 /* The condition register number portion of the BI field in a B form
581 or XL form instruction. This is used for the extended conditional
582 branch mnemonics, which set the lower two bits of the BI field. It
583 is the BI field with the lower two bits ignored. */
587 insert_cr (insn
, value
, errmsg
)
592 return insn
| ((value
& 0x1c) << 16);
597 extract_cr (insn
, invalid
)
601 return (insn
>> 16) & 0x1c;
604 /* The DS field in a DS form instruction. This is like D, but the
605 lower two bits are forced to zero. */
609 insert_ds (insn
, value
, errmsg
)
614 return insn
| (value
& 0xfffc);
619 extract_ds (insn
, invalid
)
623 if ((insn
& 0x8000) != 0)
624 return (insn
& 0xfffc) - 0x10000;
626 return insn
& 0xfffc;
629 /* The LI field in an I form instruction. The lower two bits are
634 insert_li (insn
, value
, errmsg
)
639 return insn
| (value
& 0x3fffffc);
644 extract_li (insn
, invalid
)
648 if ((insn
& 0x2000000) != 0)
649 return (insn
& 0x3fffffc) - 0x4000000;
651 return insn
& 0x3fffffc;
654 /* The MB and ME fields in an M form instruction expressed as a single
655 operand which is itself a bitmask. The extraction function always
656 marks it as invalid, since we never want to recognize an
657 instruction which uses a field of this type. */
660 insert_mbe (insn
, value
, errmsg
)
672 if (errmsg
!= (const char **) NULL
)
673 *errmsg
= "illegal bitmask";
678 while ((uval
& 1) == 0)
686 while ((uval
& 1) != 0)
694 if (errmsg
!= (const char **) NULL
)
695 *errmsg
= "illegal bitmask";
698 return insn
| (mb
<< 6) | (me
<< 1);
702 extract_mbe (insn
, invalid
)
710 if (invalid
!= (int *) NULL
)
714 mb
= (insn
>> 6) & 0x1f;
715 me
= (insn
>> 1) & 0x1f;
716 for (i
= mb
; i
< me
; i
++)
717 ret
|= 1 << (31 - i
);
721 /* The MB or ME field in an MD or MDS form instruction. The high bit
722 is wrapped to the low end. */
726 insert_mb6 (insn
, value
, errmsg
)
731 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
736 extract_mb6 (insn
, invalid
)
740 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
743 /* The NB field in an X form instruction. The value 32 is stored as
747 insert_nb (insn
, value
, errmsg
)
752 if (value
< 0 || value
> 32)
753 *errmsg
= "value out of range";
756 return insn
| ((value
& 0x1f) << 11);
761 extract_nb (insn
, invalid
)
767 ret
= (insn
>> 11) & 0x1f;
773 /* The NSI field in a D form instruction. This is the same as the SI
774 field, only negated. The extraction function always marks it as
775 invalid, since we never want to recognize an instruction which uses
776 a field of this type. */
780 insert_nsi (insn
, value
, errmsg
)
785 return insn
| ((- value
) & 0xffff);
789 extract_nsi (insn
, invalid
)
793 if (invalid
!= (int *) NULL
)
795 if ((insn
& 0x8000) != 0)
796 return - ((insn
& 0xffff) - 0x10000);
798 return - (insn
& 0xffff);
801 /* The RB field in an X form instruction when it must be the same as
802 the RS field in the instruction. This is used for extended
803 mnemonics like mr. This operand is marked FAKE. The insertion
804 function just copies the BT field into the BA field, and the
805 extraction function just checks that the fields are the same. */
809 insert_rbs (insn
, value
, errmsg
)
814 return insn
| (((insn
>> 21) & 0x1f) << 11);
818 extract_rbs (insn
, invalid
)
822 if (invalid
!= (int *) NULL
823 && ((insn
>> 21) & 0x1f) != ((insn
>> 11) & 0x1f))
828 /* The SH field in an MD form instruction. This is split. */
832 insert_sh6 (insn
, value
, errmsg
)
837 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
842 extract_sh6 (insn
, invalid
)
846 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
849 /* The SPR or TBR field in an XFX form instruction. This is
850 flipped--the lower 5 bits are stored in the upper 5 and vice-
854 insert_spr (insn
, value
, errmsg
)
859 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
863 extract_spr (insn
, invalid
)
867 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
870 /* Macros used to form opcodes. */
872 /* The main opcode. */
873 #define OP(x) (((x) & 0x3f) << 26)
874 #define OP_MASK OP (0x3f)
876 /* The main opcode combined with a trap code in the TO field of a D
877 form instruction. Used for extended mnemonics for the trap
879 #define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21))
880 #define OPTO_MASK (OP_MASK | TO_MASK)
882 /* The main opcode combined with a comparison size bit in the L field
883 of a D form or X form instruction. Used for extended mnemonics for
884 the comparison instructions. */
885 #define OPL(x,l) (OP (x) | (((l) & 1) << 21))
886 #define OPL_MASK OPL (0x3f,1)
888 /* An A form instruction. */
889 #define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1))
890 #define A_MASK A (0x3f, 0x1f, 1)
892 /* An A_MASK with the FRB field fixed. */
893 #define AFRB_MASK (A_MASK | FRB_MASK)
895 /* An A_MASK with the FRC field fixed. */
896 #define AFRC_MASK (A_MASK | FRC_MASK)
898 /* An A_MASK with the FRA and FRC fields fixed. */
899 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
901 /* A B form instruction. */
902 #define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1))
903 #define B_MASK B (0x3f, 1, 1)
905 /* A B form instruction setting the BO field. */
906 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21))
907 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
909 /* A BBO_MASK with the y bit of the BO field removed. This permits
910 matching a conditional branch regardless of the setting of the y
912 #define Y_MASK (1 << 21)
913 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
915 /* A B form instruction setting the BO field and the condition bits of
917 #define BBOCB(op, bo, cb, aa, lk) \
918 (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16))
919 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
921 /* A BBOCB_MASK with the y bit of the BO field removed. */
922 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
924 /* A BBOYCB_MASK in which the BI field is fixed. */
925 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
927 /* The main opcode mask with the RA field clear. */
928 #define DRA_MASK (OP_MASK | RA_MASK)
930 /* A DS form instruction. */
931 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
932 #define DS_MASK DSO (0x3f, 3)
934 /* An M form instruction. */
935 #define M(op, rc) (OP (op) | ((rc) & 1))
936 #define M_MASK M (0x3f, 1)
938 /* An M form instruction with the ME field specified. */
939 #define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1))
941 /* An M_MASK with the MB and ME fields fixed. */
942 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
944 /* An M_MASK with the SH and ME fields fixed. */
945 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
947 /* An MD form instruction. */
948 #define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1))
949 #define MD_MASK MD (0x3f, 0x7, 1)
951 /* An MD_MASK with the MB field fixed. */
952 #define MDMB_MASK (MD_MASK | MB6_MASK)
954 /* An MD_MASK with the SH field fixed. */
955 #define MDSH_MASK (MD_MASK | SH6_MASK)
957 /* An MDS form instruction. */
958 #define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1))
959 #define MDS_MASK MDS (0x3f, 0xf, 1)
961 /* An MDS_MASK with the MB field fixed. */
962 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
964 /* An SC form instruction. */
965 #define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1))
966 #define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1)
968 /* An X form instruction. */
969 #define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
971 /* An X form instruction with the RC bit specified. */
972 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
974 /* The mask for an X form instruction. */
975 #define X_MASK XRC (0x3f, 0x3ff, 1)
977 /* An X_MASK with the RA field fixed. */
978 #define XRA_MASK (X_MASK | RA_MASK)
980 /* An X_MASK with the RB field fixed. */
981 #define XRB_MASK (X_MASK | RB_MASK)
983 /* An X_MASK with the RT field fixed. */
984 #define XRT_MASK (X_MASK | RT_MASK)
986 /* An X_MASK with the RA and RB fields fixed. */
987 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
989 /* An X_MASK with the RT and RA fields fixed. */
990 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
992 /* An X form comparison instruction. */
993 #define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21))
995 /* The mask for an X form comparison instruction. */
996 #define XCMP_MASK (X_MASK | (1 << 22))
998 /* The mask for an X form comparison instruction with the L field
1000 #define XCMPL_MASK (XCMP_MASK | (1 << 21))
1002 /* An X form trap instruction with the TO field specified. */
1003 #define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21))
1004 #define XTO_MASK (X_MASK | TO_MASK)
1006 /* An XFL form instruction. */
1007 #define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1))
1008 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16))
1010 /* An XL form instruction with the LK field set to 0. */
1011 #define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1013 /* An XL form instruction which uses the LK field. */
1014 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1016 /* The mask for an XL form instruction. */
1017 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1019 /* An XL form instruction which explicitly sets the BO field. */
1020 #define XLO(op, bo, xop, lk) \
1021 (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21))
1022 #define XLO_MASK (XL_MASK | BO_MASK)
1024 /* An XL form instruction which explicitly sets the y bit of the BO
1026 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21))
1027 #define XLYLK_MASK (XL_MASK | Y_MASK)
1029 /* An XL form instruction which sets the BO field and the condition
1030 bits of the BI field. */
1031 #define XLOCB(op, bo, cb, xop, lk) \
1032 (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16))
1033 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1035 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1036 #define XLBB_MASK (XL_MASK | BB_MASK)
1037 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1038 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1040 /* An XL_MASK with the BO and BB fields fixed. */
1041 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1043 /* An XL_MASK with the BO, BI and BB fields fixed. */
1044 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1046 /* An XO form instruction. */
1047 #define XO(op, xop, oe, rc) \
1048 (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1))
1049 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1051 /* An XO_MASK with the RB field fixed. */
1052 #define XORB_MASK (XO_MASK | RB_MASK)
1054 /* An XS form instruction. */
1055 #define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
1056 #define XS_MASK XS (0x3f, 0x1ff, 1)
1058 /* An XFX form instruction with the SPR field filled in. */
1059 #define XSPR(op, xop, spr) \
1060 (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
1061 #define XSPR_MASK (X_MASK | SPR_MASK)
1063 /* The BO encodings used in extended conditional branch mnemonics. */
1064 #define BODNZF (0x0)
1065 #define BODNZFP (0x1)
1067 #define BODZFP (0x3)
1070 #define BODNZT (0x8)
1071 #define BODNZTP (0x9)
1073 #define BODZTP (0xb)
1076 #define BODNZ (0x10)
1077 #define BODNZP (0x11)
1079 #define BODZP (0x13)
1082 /* The BI condition bit encodings used in extended conditional branch
1089 /* The TO encodings used in extended trap mnemonics. */
1106 /* Smaller names for the flags so each entry in the opcodes table will
1107 fit on a single line. */
1108 #define PPC PPC_OPCODE_PPC
1109 #define POWER PPC_OPCODE_POWER
1110 #define B32 PPC_OPCODE_32
1111 #define B64 PPC_OPCODE_64
1113 /* The opcode table.
1115 The format of the opcode table is:
1117 NAME OPCODE MASK FLAGS { OPERANDS }
1119 NAME is the name of the instruction.
1120 OPCODE is the instruction opcode.
1121 MASK is the opcode mask; this is used to tell the disassembler
1122 which bits in the actual opcode must match OPCODE.
1123 FLAGS are flags indicated what processors support the instruction.
1124 OPERANDS is the list of operands.
1126 The disassembler reads the table in order and prints the first
1127 instruction which matches, so this table is sorted to put more
1128 specific instructions before more general instructions. It is also
1129 sorted by major opcode. */
1131 const struct powerpc_opcode powerpc_opcodes
[] = {
1132 { "tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1133 { "tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1134 { "tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1135 { "tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1136 { "tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1137 { "tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1138 { "tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1139 { "tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1140 { "tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1141 { "tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1142 { "tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1143 { "tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1144 { "tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1145 { "tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC
|B64
, { RA
, SI
} },
1146 { "tdi", OP(2), OP_MASK
, PPC
|B64
, { TO
, RA
, SI
} },
1148 { "twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPC
, { RA
, SI
} },
1149 { "tlgti", OPTO(3,TOLGT
), OPTO_MASK
, POWER
, { RA
, SI
} },
1150 { "twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPC
, { RA
, SI
} },
1151 { "tllti", OPTO(3,TOLLT
), OPTO_MASK
, POWER
, { RA
, SI
} },
1152 { "tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPC
, { RA
, SI
} },
1153 { "teqi", OPTO(3,TOEQ
), OPTO_MASK
, POWER
, { RA
, SI
} },
1154 { "twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPC
, { RA
, SI
} },
1155 { "tlgei", OPTO(3,TOLGE
), OPTO_MASK
, POWER
, { RA
, SI
} },
1156 { "twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPC
, { RA
, SI
} },
1157 { "tlnli", OPTO(3,TOLNL
), OPTO_MASK
, POWER
, { RA
, SI
} },
1158 { "twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPC
, { RA
, SI
} },
1159 { "tllei", OPTO(3,TOLLE
), OPTO_MASK
, POWER
, { RA
, SI
} },
1160 { "twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPC
, { RA
, SI
} },
1161 { "tlngi", OPTO(3,TOLNG
), OPTO_MASK
, POWER
, { RA
, SI
} },
1162 { "twgti", OPTO(3,TOGT
), OPTO_MASK
, PPC
, { RA
, SI
} },
1163 { "tgti", OPTO(3,TOGT
), OPTO_MASK
, POWER
, { RA
, SI
} },
1164 { "twgei", OPTO(3,TOGE
), OPTO_MASK
, PPC
, { RA
, SI
} },
1165 { "tgei", OPTO(3,TOGE
), OPTO_MASK
, POWER
, { RA
, SI
} },
1166 { "twnli", OPTO(3,TONL
), OPTO_MASK
, PPC
, { RA
, SI
} },
1167 { "tnli", OPTO(3,TONL
), OPTO_MASK
, POWER
, { RA
, SI
} },
1168 { "twlti", OPTO(3,TOLT
), OPTO_MASK
, PPC
, { RA
, SI
} },
1169 { "tlti", OPTO(3,TOLT
), OPTO_MASK
, POWER
, { RA
, SI
} },
1170 { "twlei", OPTO(3,TOLE
), OPTO_MASK
, PPC
, { RA
, SI
} },
1171 { "tlei", OPTO(3,TOLE
), OPTO_MASK
, POWER
, { RA
, SI
} },
1172 { "twngi", OPTO(3,TONG
), OPTO_MASK
, PPC
, { RA
, SI
} },
1173 { "tngi", OPTO(3,TONG
), OPTO_MASK
, POWER
, { RA
, SI
} },
1174 { "twnei", OPTO(3,TONE
), OPTO_MASK
, PPC
, { RA
, SI
} },
1175 { "tnei", OPTO(3,TONE
), OPTO_MASK
, POWER
, { RA
, SI
} },
1176 { "twi", OP(3), OP_MASK
, PPC
, { TO
, RA
, SI
} },
1177 { "ti", OP(3), OP_MASK
, POWER
, { TO
, RA
, SI
} },
1179 { "mulli", OP(7), OP_MASK
, PPC
, { RT
, RA
, SI
} },
1180 { "muli", OP(7), OP_MASK
, POWER
, { RT
, RA
, SI
} },
1182 { "subfic", OP(8), OP_MASK
, PPC
, { RT
, RA
, SI
} },
1183 { "sfi", OP(8), OP_MASK
, POWER
, { RT
, RA
, SI
} },
1185 { "dozi", OP(9), OP_MASK
, POWER
, { RT
, RA
, SI
} },
1187 { "cmplwi", OPL(10,0), OPL_MASK
, PPC
, { OBF
, RA
, UI
} },
1188 { "cmpldi", OPL(10,1), OPL_MASK
, PPC
|B64
, { OBF
, RA
, UI
} },
1189 { "cmpli", OP(10), OP_MASK
, PPC
, { BF
, L
, RA
, UI
} },
1190 { "cmpli", OP(10), OP_MASK
, POWER
, { BF
, RA
, UI
} },
1192 { "cmpwi", OPL(11,0), OPL_MASK
, PPC
, { OBF
, RA
, SI
} },
1193 { "cmpdi", OPL(11,1), OPL_MASK
, PPC
|B64
, { OBF
, RA
, SI
} },
1194 { "cmpi", OP(11), OP_MASK
, PPC
, { BF
, L
, RA
, SI
} },
1195 { "cmpi", OP(11), OP_MASK
, POWER
, { BF
, RA
, SI
} },
1197 { "addic", OP(12), OP_MASK
, PPC
, { RT
, RA
, SI
} },
1198 { "ai", OP(12), OP_MASK
, POWER
, { RT
, RA
, SI
} },
1199 { "subic", OP(12), OP_MASK
, PPC
, { RT
, RA
, NSI
} },
1201 { "addic.", OP(13), OP_MASK
, PPC
, { RT
, RA
, SI
} },
1202 { "ai.", OP(13), OP_MASK
, POWER
, { RT
, RA
, SI
} },
1203 { "subic.", OP(13), OP_MASK
, PPC
, { RT
, RA
, NSI
} },
1205 { "li", OP(14), DRA_MASK
, PPC
, { RT
, SI
} },
1206 { "lil", OP(14), DRA_MASK
, POWER
, { RT
, SI
} },
1207 { "addi", OP(14), OP_MASK
, PPC
, { RT
, RA
, SI
} },
1208 { "cal", OP(14), OP_MASK
, POWER
, { RT
, D
, RA
} },
1209 { "subi", OP(14), OP_MASK
, PPC
, { RT
, RA
, NSI
} },
1210 { "la", OP(14), OP_MASK
, PPC
, { RT
, D
, RA
} },
1212 { "lis", OP(15), DRA_MASK
, PPC
, { RT
, SI
} },
1213 { "liu", OP(15), DRA_MASK
, POWER
, { RT
, UI
} },
1214 { "addis", OP(15), OP_MASK
, PPC
, { RT
, RA
, SI
} },
1215 { "cau", OP(15), OP_MASK
, POWER
, { RT
, RA
, UI
} },
1216 { "subis", OP(15), OP_MASK
, PPC
, { RT
, RA
, NSI
} },
1218 { "bdnz-", BBO(16,BODNZ
,0,0), BBOYBI_MASK
, PPC
, { BDM
} },
1219 { "bdnz+", BBO(16,BODNZ
,0,0), BBOYBI_MASK
, PPC
, { BDP
} },
1220 { "bdnz", BBO(16,BODNZ
,0,0), BBOYBI_MASK
, PPC
|POWER
, { BD
} },
1221 { "bdnzl-", BBO(16,BODNZ
,0,1), BBOYBI_MASK
, PPC
, { BDM
} },
1222 { "bdnzl+", BBO(16,BODNZ
,0,1), BBOYBI_MASK
, PPC
, { BDP
} },
1223 { "bdnzl", BBO(16,BODNZ
,0,1), BBOYBI_MASK
, PPC
|POWER
, { BD
} },
1224 { "bdnza-", BBO(16,BODNZ
,1,0), BBOYBI_MASK
, PPC
, { BDMA
} },
1225 { "bdnza+", BBO(16,BODNZ
,1,0), BBOYBI_MASK
, PPC
, { BDPA
} },
1226 { "bdnza", BBO(16,BODNZ
,1,0), BBOYBI_MASK
, PPC
|POWER
, { BDA
} },
1227 { "bdnzla-", BBO(16,BODNZ
,1,1), BBOYBI_MASK
, PPC
, { BDMA
} },
1228 { "bdnzla+", BBO(16,BODNZ
,1,1), BBOYBI_MASK
, PPC
, { BDPA
} },
1229 { "bdnzla", BBO(16,BODNZ
,1,1), BBOYBI_MASK
, PPC
|POWER
, { BDA
} },
1230 { "bdz-", BBO(16,BODZ
,0,0), BBOYBI_MASK
, PPC
, { BDM
} },
1231 { "bdz+", BBO(16,BODZ
,0,0), BBOYBI_MASK
, PPC
, { BDP
} },
1232 { "bdz", BBO(16,BODZ
,0,0), BBOYBI_MASK
, PPC
|POWER
, { BD
} },
1233 { "bdzl-", BBO(16,BODZ
,0,1), BBOYBI_MASK
, PPC
, { BDM
} },
1234 { "bdzl+", BBO(16,BODZ
,0,1), BBOYBI_MASK
, PPC
, { BDP
} },
1235 { "bdzl", BBO(16,BODZ
,0,1), BBOYBI_MASK
, PPC
|POWER
, { BD
} },
1236 { "bdza-", BBO(16,BODZ
,1,0), BBOYBI_MASK
, PPC
, { BDMA
} },
1237 { "bdza+", BBO(16,BODZ
,1,0), BBOYBI_MASK
, PPC
, { BDPA
} },
1238 { "bdza", BBO(16,BODZ
,1,0), BBOYBI_MASK
, PPC
|POWER
, { BDA
} },
1239 { "bdzla-", BBO(16,BODZ
,1,1), BBOYBI_MASK
, PPC
, { BDMA
} },
1240 { "bdzla+", BBO(16,BODZ
,1,1), BBOYBI_MASK
, PPC
, { BDPA
} },
1241 { "bdzla", BBO(16,BODZ
,1,1), BBOYBI_MASK
, PPC
|POWER
, { BDA
} },
1242 { "blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1243 { "blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1244 { "blt", BBOCB(16,BOT
,CBLT
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1245 { "bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1246 { "bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1247 { "bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1248 { "blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1249 { "blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1250 { "blta", BBOCB(16,BOT
,CBLT
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1251 { "bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1252 { "bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1253 { "bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1254 { "bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1255 { "bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1256 { "bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1257 { "bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1258 { "bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1259 { "bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1260 { "bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1261 { "bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1262 { "bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1263 { "bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1264 { "bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1265 { "bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1266 { "beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1267 { "beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1268 { "beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1269 { "beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1270 { "beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1271 { "beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1272 { "beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1273 { "beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1274 { "beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1275 { "beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1276 { "beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1277 { "beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1278 { "bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1279 { "bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1280 { "bso", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1281 { "bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1282 { "bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1283 { "bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1284 { "bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1285 { "bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1286 { "bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1287 { "bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1288 { "bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1289 { "bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1290 { "bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1291 { "bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1292 { "bun", BBOCB(16,BOT
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BD
} },
1293 { "bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1294 { "bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1295 { "bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BD
} },
1296 { "buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1297 { "buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1298 { "buna", BBOCB(16,BOT
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDA
} },
1299 { "bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1300 { "bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1301 { "bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDA
} },
1302 { "bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1303 { "bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1304 { "bge", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1305 { "bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1306 { "bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1307 { "bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1308 { "bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1309 { "bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1310 { "bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1311 { "bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1312 { "bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1313 { "bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1314 { "bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1315 { "bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1316 { "bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1317 { "bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1318 { "bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1319 { "bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1320 { "bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1321 { "bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1322 { "bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1323 { "bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1324 { "bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1325 { "bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1326 { "ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1327 { "ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1328 { "ble", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1329 { "blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1330 { "blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1331 { "blel", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1332 { "blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1333 { "blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1334 { "blea", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1335 { "blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1336 { "blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1337 { "blela", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1338 { "bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1339 { "bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1340 { "bng", BBOCB(16,BOF
,CBGT
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1341 { "bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1342 { "bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1343 { "bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1344 { "bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1345 { "bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1346 { "bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1347 { "bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1348 { "bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1349 { "bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1350 { "bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1351 { "bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1352 { "bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1353 { "bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1354 { "bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1355 { "bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1356 { "bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1357 { "bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1358 { "bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1359 { "bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1360 { "bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1361 { "bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1362 { "bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1363 { "bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1364 { "bns", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1365 { "bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1366 { "bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1367 { "bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BD
} },
1368 { "bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1369 { "bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1370 { "bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1371 { "bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1372 { "bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1373 { "bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPC
|POWER
, { CR
, BDA
} },
1374 { "bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1375 { "bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1376 { "bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOYCB_MASK
, PPC
, { CR
, BD
} },
1377 { "bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDM
} },
1378 { "bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BDP
} },
1379 { "bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOYCB_MASK
, PPC
, { CR
, BD
} },
1380 { "bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1381 { "bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1382 { "bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOYCB_MASK
, PPC
, { CR
, BDA
} },
1383 { "bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDMA
} },
1384 { "bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDPA
} },
1385 { "bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOYCB_MASK
, PPC
, { CR
, BDA
} },
1386 { "bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPC
, { BI
, BDM
} },
1387 { "bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPC
, { BI
, BDP
} },
1388 { "bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPC
, { BI
, BD
} },
1389 { "bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPC
, { BI
, BDM
} },
1390 { "bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPC
, { BI
, BDP
} },
1391 { "bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPC
, { BI
, BD
} },
1392 { "bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1393 { "bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1394 { "bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPC
, { BI
, BDA
} },
1395 { "bdnztla-",BBO(16,BODNZT
,1,1), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1396 { "bdnztla+",BBO(16,BODNZT
,1,1), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1397 { "bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPC
, { BI
, BDA
} },
1398 { "bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPC
, { BI
, BDM
} },
1399 { "bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPC
, { BI
, BDP
} },
1400 { "bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPC
, { BI
, BD
} },
1401 { "bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPC
, { BI
, BDM
} },
1402 { "bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPC
, { BI
, BDP
} },
1403 { "bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPC
, { BI
, BD
} },
1404 { "bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1405 { "bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1406 { "bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPC
, { BI
, BDA
} },
1407 { "bdnzfla-",BBO(16,BODNZF
,1,1), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1408 { "bdnzfla+",BBO(16,BODNZF
,1,1), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1409 { "bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPC
, { BI
, BDA
} },
1410 { "bt-", BBO(16,BOT
,0,0), BBOY_MASK
, PPC
, { BI
, BDM
} },
1411 { "bt+", BBO(16,BOT
,0,0), BBOY_MASK
, PPC
, { BI
, BDP
} },
1412 { "bt", BBO(16,BOT
,0,0), BBOY_MASK
, PPC
, { BI
, BD
} },
1413 { "bbt", BBO(16,BOT
,0,0), BBOY_MASK
, POWER
, { BI
, BD
} },
1414 { "btl-", BBO(16,BOT
,0,1), BBOY_MASK
, PPC
, { BI
, BDM
} },
1415 { "btl+", BBO(16,BOT
,0,1), BBOY_MASK
, PPC
, { BI
, BDP
} },
1416 { "btl", BBO(16,BOT
,0,1), BBOY_MASK
, PPC
, { BI
, BD
} },
1417 { "bbtl", BBO(16,BOT
,0,1), BBOY_MASK
, POWER
, { BI
, BD
} },
1418 { "bta-", BBO(16,BOT
,1,0), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1419 { "bta+", BBO(16,BOT
,1,0), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1420 { "bta", BBO(16,BOT
,1,0), BBOY_MASK
, PPC
, { BI
, BDA
} },
1421 { "bbta", BBO(16,BOT
,1,0), BBOY_MASK
, POWER
, { BI
, BDA
} },
1422 { "btla-", BBO(16,BOT
,1,1), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1423 { "btla+", BBO(16,BOT
,1,1), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1424 { "btla", BBO(16,BOT
,1,1), BBOY_MASK
, PPC
, { BI
, BDA
} },
1425 { "bbtla", BBO(16,BOT
,1,1), BBOY_MASK
, POWER
, { BI
, BDA
} },
1426 { "bf-", BBO(16,BOF
,0,0), BBOY_MASK
, PPC
, { BI
, BDM
} },
1427 { "bf+", BBO(16,BOF
,0,0), BBOY_MASK
, PPC
, { BI
, BDP
} },
1428 { "bf", BBO(16,BOF
,0,0), BBOY_MASK
, PPC
, { BI
, BD
} },
1429 { "bbf", BBO(16,BOF
,0,0), BBOY_MASK
, POWER
, { BI
, BD
} },
1430 { "bfl-", BBO(16,BOF
,0,1), BBOY_MASK
, PPC
, { BI
, BDM
} },
1431 { "bfl+", BBO(16,BOF
,0,1), BBOY_MASK
, PPC
, { BI
, BDP
} },
1432 { "bfl", BBO(16,BOF
,0,1), BBOY_MASK
, PPC
, { BI
, BD
} },
1433 { "bbfl", BBO(16,BOF
,0,1), BBOY_MASK
, POWER
, { BI
, BD
} },
1434 { "bfa-", BBO(16,BOF
,1,0), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1435 { "bfa+", BBO(16,BOF
,1,0), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1436 { "bfa", BBO(16,BOF
,1,0), BBOY_MASK
, PPC
, { BI
, BDA
} },
1437 { "bbfa", BBO(16,BOF
,1,0), BBOY_MASK
, POWER
, { BI
, BDA
} },
1438 { "bfla-", BBO(16,BOF
,1,1), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1439 { "bfla+", BBO(16,BOF
,1,1), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1440 { "bfla", BBO(16,BOF
,1,1), BBOY_MASK
, PPC
, { BI
, BDA
} },
1441 { "bbfla", BBO(16,BOF
,1,1), BBOY_MASK
, POWER
, { BI
, BDA
} },
1442 { "bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, PPC
, { BI
, BDM
} },
1443 { "bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, PPC
, { BI
, BDP
} },
1444 { "bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPC
, { BI
, BD
} },
1445 { "bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, PPC
, { BI
, BDM
} },
1446 { "bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, PPC
, { BI
, BDP
} },
1447 { "bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPC
, { BI
, BD
} },
1448 { "bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1449 { "bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1450 { "bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPC
, { BI
, BDA
} },
1451 { "bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1452 { "bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1453 { "bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPC
, { BI
, BDA
} },
1454 { "bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, PPC
, { BI
, BDM
} },
1455 { "bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, PPC
, { BI
, BDP
} },
1456 { "bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPC
, { BI
, BD
} },
1457 { "bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, PPC
, { BI
, BDM
} },
1458 { "bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, PPC
, { BI
, BDP
} },
1459 { "bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPC
, { BI
, BD
} },
1460 { "bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1461 { "bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1462 { "bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPC
, { BI
, BDA
} },
1463 { "bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, PPC
, { BI
, BDMA
} },
1464 { "bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, PPC
, { BI
, BDPA
} },
1465 { "bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPC
, { BI
, BDA
} },
1466 { "bc-", B(16,0,0), B_MASK
, PPC
, { BOE
, BI
, BDM
} },
1467 { "bc+", B(16,0,0), B_MASK
, PPC
, { BOE
, BI
, BDP
} },
1468 { "bc", B(16,0,0), B_MASK
, PPC
|POWER
, { BO
, BI
, BD
} },
1469 { "bcl-", B(16,0,1), B_MASK
, PPC
, { BOE
, BI
, BDM
} },
1470 { "bcl+", B(16,0,1), B_MASK
, PPC
, { BOE
, BI
, BDP
} },
1471 { "bcl", B(16,0,1), B_MASK
, PPC
|POWER
, { BO
, BI
, BD
} },
1472 { "bca-", B(16,1,0), B_MASK
, PPC
, { BOE
, BI
, BDMA
} },
1473 { "bca+", B(16,1,0), B_MASK
, PPC
, { BOE
, BI
, BDPA
} },
1474 { "bca", B(16,1,0), B_MASK
, PPC
|POWER
, { BO
, BI
, BDA
} },
1475 { "bcla-", B(16,1,1), B_MASK
, PPC
, { BOE
, BI
, BDMA
} },
1476 { "bcla+", B(16,1,1), B_MASK
, PPC
, { BOE
, BI
, BDPA
} },
1477 { "bcla", B(16,1,1), B_MASK
, PPC
|POWER
, { BO
, BI
, BDA
} },
1479 { "sc", SC(17,1,0), 0xffffffff, PPC
, { 0 } },
1480 { "svc", SC(17,0,0), SC_MASK
, POWER
, { LEV
, FL1
, FL2
} },
1481 { "svcl", SC(17,0,1), SC_MASK
, POWER
, { LEV
, FL1
, FL2
} },
1482 { "svca", SC(17,1,0), SC_MASK
, POWER
, { SV
} },
1483 { "svcla", SC(17,1,1), SC_MASK
, POWER
, { SV
} },
1485 { "b", B(18,0,0), B_MASK
, PPC
|POWER
, { LI
} },
1486 { "bl", B(18,0,1), B_MASK
, PPC
|POWER
, { LI
} },
1487 { "ba", B(18,1,0), B_MASK
, PPC
|POWER
, { LIA
} },
1488 { "bla", B(18,1,1), B_MASK
, PPC
|POWER
, { LIA
} },
1490 { "mcrf", XL(19,0), XLBB_MASK
|(3<<21)|(3<<16), PPC
|POWER
, { BF
, BFA
} },
1492 { "blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPC
, { 0 } },
1493 { "br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, POWER
, { 0 } },
1494 { "blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPC
, { 0 } },
1495 { "brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, POWER
, { 0 } },
1496 { "bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPC
, { 0 } },
1497 { "bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPC
, { 0 } },
1498 { "bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, PPC
, { 0 } },
1499 { "bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPC
, { 0 } },
1500 { "bdnzlrl-",XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPC
, { 0 } },
1501 { "bdnzlrl+",XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, PPC
, { 0 } },
1502 { "bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPC
, { 0 } },
1503 { "bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPC
, { 0 } },
1504 { "bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, PPC
, { 0 } },
1505 { "bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPC
, { 0 } },
1506 { "bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPC
, { 0 } },
1507 { "bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, PPC
, { 0 } },
1508 { "bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1509 { "bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1510 { "bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1511 { "bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1512 { "bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1513 { "bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1514 { "bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1515 { "bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1516 { "bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1517 { "bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1518 { "bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1519 { "bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1520 { "bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1521 { "bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1522 { "bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1523 { "bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1524 { "beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1525 { "beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1526 { "beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1527 { "beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1528 { "beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1529 { "beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1530 { "beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1531 { "beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1532 { "bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1533 { "bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1534 { "bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1535 { "bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1536 { "bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1537 { "bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1538 { "bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1539 { "bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1540 { "bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1541 { "bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1542 { "bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1543 { "bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1544 { "bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1545 { "bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1546 { "bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1547 { "bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1548 { "bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1549 { "bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1550 { "bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1551 { "bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1552 { "bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1553 { "bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1554 { "bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1555 { "bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1556 { "bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1557 { "bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1558 { "bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1559 { "bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1560 { "bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1561 { "bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1562 { "blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1563 { "blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1564 { "blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1565 { "bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1566 { "blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1567 { "blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1568 { "blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1569 { "blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1570 { "bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1571 { "bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1572 { "bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1573 { "bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1574 { "bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1575 { "bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1576 { "bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1577 { "bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1578 { "bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1579 { "bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1580 { "bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1581 { "bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1582 { "bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1583 { "bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1584 { "bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1585 { "bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1586 { "bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1587 { "bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1588 { "bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1589 { "bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, POWER
, { CR
} },
1590 { "bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1591 { "bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1592 { "bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1593 { "bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, POWER
, { CR
} },
1594 { "bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1595 { "bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1596 { "bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1597 { "bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1598 { "bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1599 { "bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1600 { "btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1601 { "btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1602 { "btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1603 { "bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, POWER
, { BI
} },
1604 { "btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1605 { "btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1606 { "btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1607 { "bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, POWER
, { BI
} },
1608 { "bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1609 { "bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1610 { "bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1611 { "bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, POWER
, { BI
} },
1612 { "bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1613 { "bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1614 { "bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1615 { "bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, POWER
, { BI
} },
1616 { "bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1617 { "bdnztlr-",XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1618 { "bdnztlr+",XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1619 { "bdnztlrl",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1620 { "bdnztlrl-",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1621 { "bdnztlrl+",XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1622 { "bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1623 { "bdnzflr-",XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1624 { "bdnzflr+",XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1625 { "bdnzflrl",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1626 { "bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1627 { "bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1628 { "bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1629 { "bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1630 { "bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1631 { "bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1632 { "bdztlrl-",XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1633 { "bdztlrl+",XLO(19,BODZTP
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1634 { "bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1635 { "bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1636 { "bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, PPC
, { BI
} },
1637 { "bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1638 { "bdzflrl-",XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1639 { "bdzflrl+",XLO(19,BODZFP
,16,1), XLBOBB_MASK
, PPC
, { BI
} },
1640 { "bclr", XLLK(19,16,0), XLYBB_MASK
, PPC
, { BO
, BI
} },
1641 { "bclrl", XLLK(19,16,1), XLYBB_MASK
, PPC
, { BO
, BI
} },
1642 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1643 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1644 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1645 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1646 { "bcr", XLLK(19,16,0), XLBB_MASK
, POWER
, { BO
, BI
} },
1647 { "bcrl", XLLK(19,16,1), XLBB_MASK
, POWER
, { BO
, BI
} },
1649 { "crnot", XL(19,33), XL_MASK
, PPC
, { BT
, BA
, BBA
} },
1650 { "crnor", XL(19,33), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1652 { "rfi", XL(19,50), 0xffffffff, PPC
|POWER
, { 0 } },
1654 { "rfsvc", XL(19,82), 0xffffffff, POWER
, { 0 } },
1656 { "crandc", XL(19,129), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1658 { "isync", XL(19,150), 0xffffffff, PPC
, { 0 } },
1659 { "ics", XL(19,150), 0xffffffff, POWER
, { 0 } },
1661 { "crclr", XL(19,193), XL_MASK
, PPC
, { BT
, BAT
, BBA
} },
1662 { "crxor", XL(19,193), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1664 { "crnand", XL(19,225), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1666 { "crand", XL(19,257), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1668 { "crset", XL(19,289), XL_MASK
, PPC
, { BT
, BAT
, BBA
} },
1669 { "creqv", XL(19,289), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1671 { "crorc", XL(19,417), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1673 { "crmove", XL(19,449), XL_MASK
, PPC
, { BT
, BA
, BBA
} },
1674 { "cror", XL(19,449), XL_MASK
, PPC
|POWER
, { BT
, BA
, BB
} },
1676 { "bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, PPC
|POWER
, { 0 } },
1677 { "bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, PPC
|POWER
, { 0 } },
1678 { "bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1679 { "bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1680 { "bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1681 { "bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1682 { "bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1683 { "bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1684 { "bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1685 { "bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1686 { "bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1687 { "bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1688 { "bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1689 { "bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1690 { "beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1691 { "beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1692 { "beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1693 { "beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1694 { "beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1695 { "beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1696 { "bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1697 { "bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1698 { "bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1699 { "bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1700 { "bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1701 { "bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1702 { "bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1703 { "bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1704 { "bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1705 { "bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1706 { "bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1707 { "bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1708 { "bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1709 { "bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1710 { "bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1711 { "bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1712 { "bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1713 { "bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1714 { "bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1715 { "bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1716 { "bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1717 { "bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1718 { "bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1719 { "bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1720 { "blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1721 { "blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1722 { "blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1723 { "blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1724 { "blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1725 { "blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1726 { "bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1727 { "bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1728 { "bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1729 { "bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1730 { "bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1731 { "bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1732 { "bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1733 { "bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1734 { "bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1735 { "bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1736 { "bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1737 { "bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1738 { "bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1739 { "bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1740 { "bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1741 { "bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1742 { "bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1743 { "bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1744 { "bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1745 { "bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1746 { "bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPC
, { CR
} },
1747 { "bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1748 { "bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1749 { "bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPC
, { CR
} },
1750 { "btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPC
, { BI
} },
1751 { "btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPC
, { BI
} },
1752 { "btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, PPC
, { BI
} },
1753 { "btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPC
, { BI
} },
1754 { "btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPC
, { BI
} },
1755 { "btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, PPC
, { BI
} },
1756 { "bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPC
, { BI
} },
1757 { "bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPC
, { BI
} },
1758 { "bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, PPC
, { BI
} },
1759 { "bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPC
, { BI
} },
1760 { "bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPC
, { BI
} },
1761 { "bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, PPC
, { BI
} },
1762 { "bcctr", XLLK(19,528,0), XLYBB_MASK
, PPC
, { BO
, BI
} },
1763 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1764 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1765 { "bcctrl", XLLK(19,528,1), XLYBB_MASK
, PPC
, { BO
, BI
} },
1766 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1767 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK
, PPC
, { BOE
, BI
} },
1768 { "bcc", XLLK(19,528,0), XLBB_MASK
, POWER
, { BO
, BI
} },
1769 { "bccl", XLLK(19,528,1), XLBB_MASK
, POWER
, { BO
, BI
} },
1771 { "rlwimi", M(20,0), M_MASK
, PPC
, { RA
,RS
,SH
,MBE
,ME
} },
1772 { "rlimi", M(20,0), M_MASK
, POWER
, { RA
,RS
,SH
,MBE
,ME
} },
1774 { "rlwimi.", M(20,1), M_MASK
, PPC
, { RA
,RS
,SH
,MBE
,ME
} },
1775 { "rlimi.", M(20,1), M_MASK
, POWER
, { RA
,RS
,SH
,MBE
,ME
} },
1777 { "rotlwi", MME(21,31,0), MMBME_MASK
, PPC
, { RA
, RS
, SH
} },
1778 { "clrlwi", MME(21,31,0), MSHME_MASK
, PPC
, { RA
, RS
, MB
} },
1779 { "rlwinm", M(21,0), M_MASK
, PPC
, { RA
,RS
,SH
,MBE
,ME
} },
1780 { "rlinm", M(21,0), M_MASK
, POWER
, { RA
,RS
,SH
,MBE
,ME
} },
1781 { "rotlwi.", MME(21,31,1), MMBME_MASK
, PPC
, { RA
,RS
,SH
} },
1782 { "clrlwi.", MME(21,31,1), MSHME_MASK
, PPC
, { RA
, RS
, MB
} },
1783 { "rlwinm.", M(21,1), M_MASK
, PPC
, { RA
,RS
,SH
,MBE
,ME
} },
1784 { "rlinm.", M(21,1), M_MASK
, POWER
, { RA
,RS
,SH
,MBE
,ME
} },
1786 { "rlmi", M(22,0), M_MASK
, POWER
, { RA
,RS
,RB
,MBE
,ME
} },
1787 { "rlmi.", M(22,1), M_MASK
, POWER
, { RA
,RS
,RB
,MBE
,ME
} },
1789 { "rotlw", MME(23,31,0), MMBME_MASK
, PPC
, { RA
, RS
, RB
} },
1790 { "rlwnm", M(23,0), M_MASK
, PPC
, { RA
,RS
,RB
,MBE
,ME
} },
1791 { "rlnm", M(23,0), M_MASK
, POWER
, { RA
,RS
,RB
,MBE
,ME
} },
1792 { "rotlw.", MME(23,31,1), MMBME_MASK
, PPC
, { RA
, RS
, RB
} },
1793 { "rlwnm.", M(23,1), M_MASK
, PPC
, { RA
,RS
,RB
,MBE
,ME
} },
1794 { "rlnm.", M(23,1), M_MASK
, POWER
, { RA
,RS
,RB
,MBE
,ME
} },
1796 { "nop", OP(24), 0xffffffff, PPC
, { 0 } },
1797 { "ori", OP(24), OP_MASK
, PPC
, { RA
, RS
, UI
} },
1798 { "oril", OP(24), OP_MASK
, POWER
, { RA
, RS
, UI
} },
1800 { "oris", OP(25), OP_MASK
, PPC
, { RA
, RS
, UI
} },
1801 { "oriu", OP(25), OP_MASK
, POWER
, { RA
, RS
, UI
} },
1803 { "xori", OP(26), OP_MASK
, PPC
, { RA
, RS
, UI
} },
1804 { "xoril", OP(26), OP_MASK
, POWER
, { RA
, RS
, UI
} },
1806 { "xoris", OP(27), OP_MASK
, PPC
, { RA
, RS
, UI
} },
1807 { "xoriu", OP(27), OP_MASK
, POWER
, { RA
, RS
, UI
} },
1809 { "andi.", OP(28), OP_MASK
, PPC
, { RA
, RS
, UI
} },
1810 { "andil.", OP(28), OP_MASK
, POWER
, { RA
, RS
, UI
} },
1812 { "andis.", OP(29), OP_MASK
, PPC
, { RA
, RS
, UI
} },
1813 { "andiu.", OP(29), OP_MASK
, POWER
, { RA
, RS
, UI
} },
1815 { "rotldi", MD(30,0,0), MDMB_MASK
, PPC
|B64
, { RA
, RS
, SH6
} },
1816 { "clrldi", MD(30,0,0), MDSH_MASK
, PPC
|B64
, { RA
, RS
, MB6
} },
1817 { "rldicl", MD(30,0,0), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, MB6
} },
1818 { "rotldi.", MD(30,0,1), MDMB_MASK
, PPC
|B64
, { RA
, RS
, SH6
} },
1819 { "clrldi.", MD(30,0,1), MDSH_MASK
, PPC
|B64
, { RA
, RS
, MB6
} },
1820 { "rldicl.", MD(30,0,1), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, MB6
} },
1822 { "rldicr", MD(30,1,0), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, ME6
} },
1823 { "rldicr.", MD(30,1,1), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, ME6
} },
1825 { "rldic", MD(30,2,0), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, MB6
} },
1826 { "rldic.", MD(30,2,1), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, MB6
} },
1828 { "rldimi", MD(30,3,0), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, MB6
} },
1829 { "rldimi.", MD(30,3,1), MD_MASK
, PPC
|B64
, { RA
, RS
, SH6
, MB6
} },
1831 { "rotld", MDS(30,8,0), MDSMB_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
1832 { "rldcl", MDS(30,8,0), MDS_MASK
, PPC
|B64
, { RA
, RS
, RB
, MB6
} },
1833 { "rotld.", MDS(30,8,1), MDSMB_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
1834 { "rldcl.", MDS(30,8,1), MDS_MASK
, PPC
|B64
, { RA
, RS
, RB
, MB6
} },
1836 { "rldcr", MDS(30,9,0), MDS_MASK
, PPC
|B64
, { RA
, RS
, RB
, ME6
} },
1837 { "rldcr.", MDS(30,9,1), MDS_MASK
, PPC
|B64
, { RA
, RS
, RB
, ME6
} },
1839 { "cmpw", XCMPL(31,0,0), XCMPL_MASK
, PPC
, { OBF
, RA
, RB
} },
1840 { "cmpd", XCMPL(31,0,1), XCMPL_MASK
, PPC
|B64
, { OBF
, RA
, RB
} },
1841 { "cmp", X(31,0), XCMPL_MASK
, POWER
, { BF
, RA
, RB
} },
1842 { "cmp", X(31,0), XCMP_MASK
, PPC
, { BF
, L
, RA
, RB
} },
1844 { "twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPC
, { RA
, RB
} },
1845 { "tlgt", XTO(31,4,TOLGT
), XTO_MASK
, POWER
, { RA
, RB
} },
1846 { "twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPC
, { RA
, RB
} },
1847 { "tllt", XTO(31,4,TOLLT
), XTO_MASK
, POWER
, { RA
, RB
} },
1848 { "tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPC
, { RA
, RB
} },
1849 { "teq", XTO(31,4,TOEQ
), XTO_MASK
, POWER
, { RA
, RB
} },
1850 { "twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPC
, { RA
, RB
} },
1851 { "tlge", XTO(31,4,TOLGE
), XTO_MASK
, POWER
, { RA
, RB
} },
1852 { "twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPC
, { RA
, RB
} },
1853 { "tlnl", XTO(31,4,TOLNL
), XTO_MASK
, POWER
, { RA
, RB
} },
1854 { "twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPC
, { RA
, RB
} },
1855 { "tlle", XTO(31,4,TOLLE
), XTO_MASK
, POWER
, { RA
, RB
} },
1856 { "twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPC
, { RA
, RB
} },
1857 { "tlng", XTO(31,4,TOLNG
), XTO_MASK
, POWER
, { RA
, RB
} },
1858 { "twgt", XTO(31,4,TOGT
), XTO_MASK
, PPC
, { RA
, RB
} },
1859 { "tgt", XTO(31,4,TOGT
), XTO_MASK
, POWER
, { RA
, RB
} },
1860 { "twge", XTO(31,4,TOGE
), XTO_MASK
, PPC
, { RA
, RB
} },
1861 { "tge", XTO(31,4,TOGE
), XTO_MASK
, POWER
, { RA
, RB
} },
1862 { "twnl", XTO(31,4,TONL
), XTO_MASK
, PPC
, { RA
, RB
} },
1863 { "tnl", XTO(31,4,TONL
), XTO_MASK
, POWER
, { RA
, RB
} },
1864 { "twlt", XTO(31,4,TOLT
), XTO_MASK
, PPC
, { RA
, RB
} },
1865 { "tlt", XTO(31,4,TOLT
), XTO_MASK
, POWER
, { RA
, RB
} },
1866 { "twle", XTO(31,4,TOLE
), XTO_MASK
, PPC
, { RA
, RB
} },
1867 { "tle", XTO(31,4,TOLE
), XTO_MASK
, POWER
, { RA
, RB
} },
1868 { "twng", XTO(31,4,TONG
), XTO_MASK
, PPC
, { RA
, RB
} },
1869 { "tng", XTO(31,4,TONG
), XTO_MASK
, POWER
, { RA
, RB
} },
1870 { "twne", XTO(31,4,TONE
), XTO_MASK
, PPC
, { RA
, RB
} },
1871 { "tne", XTO(31,4,TONE
), XTO_MASK
, POWER
, { RA
, RB
} },
1872 { "trap", XTO(31,4,TOU
), 0xffffffff, PPC
, { 0 } },
1873 { "tw", X(31,4), X_MASK
, PPC
, { TO
, RA
, RB
} },
1874 { "t", X(31,4), X_MASK
, POWER
, { TO
, RA
, RB
} },
1876 { "subfc", XO(31,8,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1877 { "sf", XO(31,8,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1878 { "subc", XO(31,8,0,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1879 { "subfc.", XO(31,8,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1880 { "sf.", XO(31,8,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1881 { "subc.", XO(31,8,0,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1882 { "subfco", XO(31,8,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1883 { "sfo", XO(31,8,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1884 { "subco", XO(31,8,1,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1885 { "subfco.", XO(31,8,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1886 { "sfo.", XO(31,8,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1887 { "subco.", XO(31,8,1,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1889 { "mulhdu", XO(31,9,0,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
1890 { "mulhdu.", XO(31,9,0,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
1892 { "addc", XO(31,10,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1893 { "a", XO(31,10,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1894 { "addc.", XO(31,10,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1895 { "a.", XO(31,10,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1896 { "addco", XO(31,10,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1897 { "ao", XO(31,10,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1898 { "addco.", XO(31,10,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1899 { "ao.", XO(31,10,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1901 { "mulhwu", XO(31,11,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1902 { "mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1904 { "mfcr", X(31,19), XRARB_MASK
, POWER
|PPC
, { RT
} },
1906 { "lwarx", X(31,20), X_MASK
, PPC
, { RT
, RA
, RB
} },
1908 { "ldx", X(31,21), X_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
1910 { "lwzx", X(31,23), X_MASK
, PPC
, { RT
, RA
, RB
} },
1911 { "lx", X(31,23), X_MASK
, POWER
, { RT
, RA
, RB
} },
1913 { "slw", XRC(31,24,0), X_MASK
, PPC
, { RA
, RS
, RB
} },
1914 { "sl", XRC(31,24,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
1915 { "slw.", XRC(31,24,1), X_MASK
, PPC
, { RA
, RS
, RB
} },
1916 { "sl.", XRC(31,24,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
1918 { "cntlzw", XRC(31,26,0), XRB_MASK
, PPC
, { RA
, RS
} },
1919 { "cntlz", XRC(31,26,0), XRB_MASK
, POWER
, { RA
, RS
} },
1920 { "cntlzw.", XRC(31,26,1), XRB_MASK
, PPC
, { RA
, RS
} },
1921 { "cntlz.", XRC(31,26,1), XRB_MASK
, POWER
, { RA
, RS
} },
1923 { "sld", XRC(31,27,0), X_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
1924 { "sld.", XRC(31,27,1), X_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
1926 { "and", XRC(31,28,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
1927 { "and.", XRC(31,28,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
1929 { "maskg", XRC(31,29,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
1930 { "maskg.", XRC(31,29,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
1932 { "cmplw", XCMPL(31,32,0), XCMPL_MASK
, PPC
, { OBF
, RA
, RB
} },
1933 { "cmpld", XCMPL(31,32,1), XCMPL_MASK
, PPC
|B64
, { OBF
, RA
, RB
} },
1934 { "cmpl", X(31,32), XCMPL_MASK
, POWER
, { BF
, RA
, RB
} },
1935 { "cmpl", X(31,32), XCMP_MASK
, PPC
, { BF
, L
, RA
, RB
} },
1937 { "subf", XO(31,40,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1938 { "sub", XO(31,40,0,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1939 { "subf.", XO(31,40,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1940 { "sub.", XO(31,40,0,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1941 { "subfo", XO(31,40,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1942 { "subo", XO(31,40,1,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1943 { "subfo.", XO(31,40,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1944 { "subo.", XO(31,40,1,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
1946 { "ldux", X(31,53), X_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
1948 { "dcbst", X(31,54), XRT_MASK
, PPC
, { RA
, RB
} },
1950 { "lwzux", X(31,55), X_MASK
, PPC
, { RT
, RA
, RB
} },
1951 { "lux", X(31,55), X_MASK
, POWER
, { RT
, RA
, RB
} },
1953 { "cntlzd", XRC(31,58,0), XRB_MASK
, PPC
|B64
, { RA
, RS
} },
1954 { "cntlzd.", XRC(31,58,1), XRB_MASK
, PPC
|B64
, { RA
, RS
} },
1956 { "andc", XRC(31,60,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
1957 { "andc.", XRC(31,60,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
1959 { "tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1960 { "tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1961 { "tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1962 { "tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1963 { "tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1964 { "tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1965 { "tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1966 { "tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1967 { "tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1968 { "tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1969 { "tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1970 { "tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1971 { "tdng", XTO(31,68,TONG
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1972 { "tdne", XTO(31,68,TONE
), XTO_MASK
, PPC
|B64
, { RA
, RB
} },
1973 { "td", X(31,68), X_MASK
, PPC
|B64
, { TO
, RA
, RB
} },
1975 { "mulhd", XO(31,73,0,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
1976 { "mulhd.", XO(31,73,0,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
1978 { "mulhw", XO(31,75,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1979 { "mulhw.", XO(31,75,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
1981 { "mfmsr", X(31,83), XRARB_MASK
, PPC
|POWER
, { RT
} },
1983 { "ldarx", X(31,84), X_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
1985 { "dcbf", X(31,86), XRT_MASK
, PPC
, { RA
, RB
} },
1987 { "lbzx", X(31,87), X_MASK
, PPC
|POWER
, { RT
, RA
, RB
} },
1989 { "neg", XO(31,104,0,0), XORB_MASK
, PPC
|POWER
, { RT
, RA
} },
1990 { "neg.", XO(31,104,0,1), XORB_MASK
, PPC
|POWER
, { RT
, RA
} },
1991 { "nego", XO(31,104,1,0), XORB_MASK
, PPC
|POWER
, { RT
, RA
} },
1992 { "nego.", XO(31,104,1,1), XORB_MASK
, PPC
|POWER
, { RT
, RA
} },
1994 { "mul", XO(31,107,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1995 { "mul.", XO(31,107,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1996 { "mulo", XO(31,107,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1997 { "mulo.", XO(31,107,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
1999 { "clf", X(31,118), XRB_MASK
, POWER
, { RT
, RA
} },
2001 { "lbzux", X(31,119), X_MASK
, PPC
|POWER
, { RT
, RA
, RB
} },
2003 { "not", XRC(31,124,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RBS
} },
2004 { "nor", XRC(31,124,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2005 { "not.", XRC(31,124,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RBS
} },
2006 { "nor.", XRC(31,124,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2008 { "subfe", XO(31,136,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2009 { "sfe", XO(31,136,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2010 { "subfe.", XO(31,136,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2011 { "sfe.", XO(31,136,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2012 { "subfeo", XO(31,136,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2013 { "sfeo", XO(31,136,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2014 { "subfeo.", XO(31,136,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2015 { "sfeo.", XO(31,136,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2017 { "adde", XO(31,138,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2018 { "ae", XO(31,138,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2019 { "adde.", XO(31,138,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2020 { "ae.", XO(31,138,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2021 { "addeo", XO(31,138,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2022 { "aeo", XO(31,138,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2023 { "addeo.", XO(31,138,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2024 { "aeo.", XO(31,138,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2026 { "mtcrf", X(31,144), X_MASK
|(1<<20)|(1<<11), PPC
|POWER
, { FXM
, RS
} },
2028 { "mtmsr", X(31,146), XRARB_MASK
, PPC
|POWER
, { RS
} },
2030 { "stdx", X(31,149), X_MASK
, PPC
|B64
, { RS
, RA
, RB
} },
2032 { "stwcx.", XRC(31,150,1), X_MASK
, PPC
, { RS
, RA
, RB
} },
2034 { "stwx", X(31,151), X_MASK
, PPC
, { RS
, RA
, RB
} },
2035 { "stx", X(31,151), X_MASK
, POWER
, { RS
, RA
, RB
} },
2037 { "slq", XRC(31,152,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2038 { "slq.", XRC(31,152,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2040 { "sle", XRC(31,153,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2041 { "sle.", XRC(31,153,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2043 { "stdux", X(31,181), X_MASK
, PPC
|B64
, { RS
, RA
, RB
} },
2045 { "stwux", X(31,183), X_MASK
, PPC
, { RS
, RA
, RB
} },
2046 { "stux", X(31,183), X_MASK
, POWER
, { RS
, RA
, RB
} },
2048 { "sliq", XRC(31,184,0), X_MASK
, POWER
, { RA
, RS
, SH
} },
2049 { "sliq.", XRC(31,184,1), X_MASK
, POWER
, { RA
, RS
, SH
} },
2051 { "subfze", XO(31,200,0,0), XORB_MASK
, PPC
, { RT
, RA
} },
2052 { "sfze", XO(31,200,0,0), XORB_MASK
, POWER
, { RT
, RA
} },
2053 { "subfze.", XO(31,200,0,1), XORB_MASK
, PPC
, { RT
, RA
} },
2054 { "sfze.", XO(31,200,0,1), XORB_MASK
, POWER
, { RT
, RA
} },
2055 { "subfzeo", XO(31,200,1,0), XORB_MASK
, PPC
, { RT
, RA
} },
2056 { "sfzeo", XO(31,200,1,0), XORB_MASK
, POWER
, { RT
, RA
} },
2057 { "subfzeo.",XO(31,200,1,1), XORB_MASK
, PPC
, { RT
, RA
} },
2058 { "sfzeo.", XO(31,200,1,1), XORB_MASK
, POWER
, { RT
, RA
} },
2060 { "addze", XO(31,202,0,0), XORB_MASK
, PPC
, { RT
, RA
} },
2061 { "aze", XO(31,202,0,0), XORB_MASK
, POWER
, { RT
, RA
} },
2062 { "addze.", XO(31,202,0,1), XORB_MASK
, PPC
, { RT
, RA
} },
2063 { "aze.", XO(31,202,0,1), XORB_MASK
, POWER
, { RT
, RA
} },
2064 { "addzeo", XO(31,202,1,0), XORB_MASK
, PPC
, { RT
, RA
} },
2065 { "azeo", XO(31,202,1,0), XORB_MASK
, POWER
, { RT
, RA
} },
2066 { "addzeo.", XO(31,202,1,1), XORB_MASK
, PPC
, { RT
, RA
} },
2067 { "azeo.", XO(31,202,1,1), XORB_MASK
, POWER
, { RT
, RA
} },
2069 { "mtsr", X(31,210), XRB_MASK
|(1<<20), PPC
|POWER
|B32
, { SR
, RS
} },
2071 { "stdcx.", XRC(31,214,1), X_MASK
, PPC
|B64
, { RS
, RA
, RB
} },
2073 { "stbx", X(31,215), X_MASK
, PPC
|POWER
, { RS
, RA
, RB
} },
2075 { "sllq", XRC(31,216,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2076 { "sllq.", XRC(31,216,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2078 { "sleq", XRC(31,217,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2079 { "sleq.", XRC(31,217,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2081 { "subfme", XO(31,232,0,0), XORB_MASK
, PPC
, { RT
, RA
} },
2082 { "sfme", XO(31,232,0,0), XORB_MASK
, POWER
, { RT
, RA
} },
2083 { "subfme.", XO(31,232,0,1), XORB_MASK
, PPC
, { RT
, RA
} },
2084 { "sfme.", XO(31,232,0,1), XORB_MASK
, POWER
, { RT
, RA
} },
2085 { "subfmeo", XO(31,232,1,0), XORB_MASK
, PPC
, { RT
, RA
} },
2086 { "sfmeo", XO(31,232,1,0), XORB_MASK
, POWER
, { RT
, RA
} },
2087 { "subfmeo.",XO(31,232,1,1), XORB_MASK
, PPC
, { RT
, RA
} },
2088 { "sfmeo.", XO(31,232,1,1), XORB_MASK
, POWER
, { RT
, RA
} },
2090 { "mulld", XO(31,233,0,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2091 { "mulld.", XO(31,233,0,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2092 { "mulldo", XO(31,233,1,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2093 { "mulldo.", XO(31,233,1,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2095 { "addme", XO(31,234,0,0), XORB_MASK
, PPC
, { RT
, RA
} },
2096 { "ame", XO(31,234,0,0), XORB_MASK
, POWER
, { RT
, RA
} },
2097 { "addme.", XO(31,234,0,1), XORB_MASK
, PPC
, { RT
, RA
} },
2098 { "ame.", XO(31,234,0,1), XORB_MASK
, POWER
, { RT
, RA
} },
2099 { "addmeo", XO(31,234,1,0), XORB_MASK
, PPC
, { RT
, RA
} },
2100 { "ameo", XO(31,234,1,0), XORB_MASK
, POWER
, { RT
, RA
} },
2101 { "addmeo.", XO(31,234,1,1), XORB_MASK
, PPC
, { RT
, RA
} },
2102 { "ameo.", XO(31,234,1,1), XORB_MASK
, POWER
, { RT
, RA
} },
2104 { "mullw", XO(31,235,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2105 { "muls", XO(31,235,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2106 { "mullw.", XO(31,235,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2107 { "muls.", XO(31,235,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2108 { "mullwo", XO(31,235,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2109 { "mulso", XO(31,235,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2110 { "mullwo.", XO(31,235,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2111 { "mulso.", XO(31,235,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2113 { "mtsrin", X(31,242), XRA_MASK
, PPC
|B32
, { RS
, RB
} },
2114 { "mtsri", X(31,242), XRA_MASK
, POWER
|B32
, { RS
, RB
} },
2116 { "dcbtst", X(31,246), XRT_MASK
, PPC
, { RA
, RB
} },
2118 { "stbux", X(31,247), X_MASK
, PPC
|POWER
, { RS
, RA
, RB
} },
2120 { "slliq", XRC(31,248,0), X_MASK
, POWER
, { RA
, RS
, SH
} },
2121 { "slliq.", XRC(31,248,1), X_MASK
, POWER
, { RA
, RS
, SH
} },
2123 { "doz", XO(31,264,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2124 { "doz.", XO(31,264,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2125 { "dozo", XO(31,264,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2126 { "dozo.", XO(31,264,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2128 { "add", XO(31,266,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2129 { "cax", XO(31,266,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2130 { "add.", XO(31,266,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2131 { "cax.", XO(31,266,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2132 { "addo", XO(31,266,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2133 { "caxo", XO(31,266,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2134 { "addo.", XO(31,266,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2135 { "caxo.", XO(31,266,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2137 { "lscbx", XRC(31,277,0), X_MASK
, POWER
, { RT
, RA
, RB
} },
2138 { "lscbx.", XRC(31,277,1), X_MASK
, POWER
, { RT
, RA
, RB
} },
2140 { "dcbt", X(31,278), XRT_MASK
, PPC
, { RA
, RB
} },
2142 { "lhzx", X(31,279), X_MASK
, PPC
|POWER
, { RT
, RA
, RB
} },
2144 { "eqv", XRC(31,284,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2145 { "eqv.", XRC(31,284,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2147 { "tlbie", X(31,306), XRTRA_MASK
, PPC
, { RB
} },
2148 { "tlbi", X(31,306), XRTRA_MASK
, POWER
, { RB
} },
2150 { "eciwx", X(31,310), X_MASK
, PPC
, { RT
, RA
, RB
} },
2152 { "lhzux", X(31,311), X_MASK
, PPC
|POWER
, { RT
, RA
, RB
} },
2154 { "xor", XRC(31,316,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2155 { "xor.", XRC(31,316,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2157 { "div", XO(31,331,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2158 { "div.", XO(31,331,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2159 { "divo", XO(31,331,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2160 { "divo.", XO(31,331,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2162 { "mfmq", XSPR(31,339,0), XSPR_MASK
, POWER
, { RT
} },
2163 { "mfxer", XSPR(31,339,1), XSPR_MASK
, PPC
|POWER
, { RT
} },
2164 { "mflr", XSPR(31,339,8), XSPR_MASK
, PPC
|POWER
, { RT
} },
2165 { "mfctr", XSPR(31,339,9), XSPR_MASK
, PPC
|POWER
, { RT
} },
2166 { "mfspr", X(31,339), X_MASK
, PPC
|POWER
, { RT
, SPR
} },
2168 { "lwax", X(31,341), X_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2170 { "lhax", X(31,343), X_MASK
, PPC
|POWER
, { RT
, RA
, RB
} },
2172 { "abs", XO(31,360,0,0), XORB_MASK
, POWER
, { RT
, RA
} },
2173 { "abs.", XO(31,360,0,1), XORB_MASK
, POWER
, { RT
, RA
} },
2174 { "abso", XO(31,360,1,0), XORB_MASK
, POWER
, { RT
, RA
} },
2175 { "abso.", XO(31,360,1,1), XORB_MASK
, POWER
, { RT
, RA
} },
2177 { "divs", XO(31,363,0,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2178 { "divs.", XO(31,363,0,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2179 { "divso", XO(31,363,1,0), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2180 { "divso.", XO(31,363,1,1), XO_MASK
, POWER
, { RT
, RA
, RB
} },
2182 { "tlbia", X(31,370), 0xffffffff, PPC
, { 0 } },
2184 { "mftb", X(31,371), X_MASK
, PPC
, { RT
, TBR
} },
2186 { "lwaux", X(31,373), X_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2188 { "lhaux", X(31,375), X_MASK
, PPC
|POWER
, { RT
, RA
, RB
} },
2190 { "sthx", X(31,407), X_MASK
, PPC
|POWER
, { RS
, RA
, RB
} },
2192 { "orc", XRC(31,412,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2193 { "orc.", XRC(31,412,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2195 { "sradi", XS(31,413,0), XS_MASK
, PPC
|B64
, { RA
, RS
, SH6
} },
2196 { "sradi.", XS(31,413,1), XS_MASK
, PPC
|B64
, { RA
, RS
, SH6
} },
2198 { "slbie", X(31,434), XRTRA_MASK
, PPC
|B64
, { RB
} },
2200 { "ecowx", X(31,438), X_MASK
, PPC
, { RT
, RA
, RB
} },
2202 { "sthux", X(31,439), X_MASK
, PPC
|POWER
, { RS
, RA
, RB
} },
2204 { "mr", XRC(31,444,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RBS
} },
2205 { "or", XRC(31,444,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2206 { "mr.", XRC(31,444,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RBS
} },
2207 { "or.", XRC(31,444,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2209 { "divdu", XO(31,457,0,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2210 { "divdu.", XO(31,457,0,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2211 { "divduo", XO(31,457,1,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2212 { "divduo.", XO(31,457,1,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2214 { "divwu", XO(31,459,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2215 { "divwu.", XO(31,459,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2216 { "divwuo", XO(31,459,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2217 { "divwuo.", XO(31,459,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2219 { "mtmq", XSPR(31,467,0), XSPR_MASK
, POWER
, { RS
} },
2220 { "mtxer", XSPR(31,467,1), XSPR_MASK
, PPC
|POWER
, { RS
} },
2221 { "mtlr", XSPR(31,467,8), XSPR_MASK
, PPC
|POWER
, { RS
} },
2222 { "mtctr", XSPR(31,467,9), XSPR_MASK
, PPC
|POWER
, { RS
} },
2223 { "mtspr", X(31,467), X_MASK
, PPC
|POWER
, { SPR
, RS
} },
2225 { "dcbi", X(31,470), XRT_MASK
, PPC
, { RA
, RB
} },
2227 { "nand", XRC(31,476,0), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2228 { "nand.", XRC(31,476,1), X_MASK
, PPC
|POWER
, { RA
, RS
, RB
} },
2230 { "nabs", XO(31,488,0,0), XORB_MASK
, POWER
, { RT
, RA
} },
2231 { "nabs.", XO(31,488,0,1), XORB_MASK
, POWER
, { RT
, RA
} },
2232 { "nabso", XO(31,488,1,0), XORB_MASK
, POWER
, { RT
, RA
} },
2233 { "nabso.", XO(31,488,1,1), XORB_MASK
, POWER
, { RT
, RA
} },
2235 { "divd", XO(31,489,0,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2236 { "divd.", XO(31,489,0,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2237 { "divdo", XO(31,489,1,0), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2238 { "divdo.", XO(31,489,1,1), XO_MASK
, PPC
|B64
, { RT
, RA
, RB
} },
2240 { "divw", XO(31,491,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2241 { "divw.", XO(31,491,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2242 { "divwo", XO(31,491,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2243 { "divwo.", XO(31,491,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2245 { "slbia", X(31,498), 0xffffffff, PPC
|B64
, { 0 } },
2247 { "cli", X(31,502), XRB_MASK
, POWER
, { RT
, RA
} },
2249 { "mcrxr", X(31,512), XRARB_MASK
|(3<<21), PPC
|POWER
, { BF
} },
2251 { "clcs", X(31,531), XRB_MASK
, POWER
, { RT
, RA
} },
2253 { "lswx", X(31,533), X_MASK
, PPC
, { RT
, RA
, RB
} },
2254 { "lsx", X(31,533), X_MASK
, POWER
, { RT
, RA
, RB
} },
2256 { "lwbrx", X(31,534), X_MASK
, PPC
, { RT
, RA
, RB
} },
2257 { "lbrx", X(31,534), X_MASK
, POWER
, { RT
, RA
, RB
} },
2259 { "lfsx", X(31,535), X_MASK
, PPC
|POWER
, { FRT
, RA
, RB
} },
2261 { "srw", XRC(31,536,0), X_MASK
, PPC
, { RA
, RS
, RB
} },
2262 { "sr", XRC(31,536,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2263 { "srw.", XRC(31,536,1), X_MASK
, PPC
, { RA
, RS
, RB
} },
2264 { "sr.", XRC(31,536,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2266 { "rrib", XRC(31,537,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2267 { "rrib.", XRC(31,537,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2269 { "srd", XRC(31,539,0), X_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
2270 { "srd.", XRC(31,539,1), X_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
2272 { "maskir", XRC(31,541,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2273 { "maskir.", XRC(31,541,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2275 { "tlbsync", X(31,566), 0xffffffff, PPC
, { 0 } },
2277 { "lfsux", X(31,567), X_MASK
, PPC
|POWER
, { FRT
, RA
, RB
} },
2279 { "mfsr", X(31,595), XRB_MASK
|(1<<20), PPC
|POWER
|B32
, { RT
, SR
} },
2281 { "lswi", X(31,597), X_MASK
, PPC
, { RT
, RA
, NB
} },
2282 { "lsi", X(31,597), X_MASK
, POWER
, { RT
, RA
, NB
} },
2284 { "sync", X(31,598), 0xffffffff, PPC
, { 0 } },
2285 { "dcs", X(31,598), 0xffffffff, POWER
, { 0 } },
2287 { "lfdx", X(31,599), X_MASK
, PPC
|POWER
, { FRT
, RA
, RB
} },
2289 { "mfsri", X(31,627), X_MASK
, POWER
, { RT
, RA
, RB
} },
2291 { "dclst", X(31,630), XRB_MASK
, POWER
, { RS
, RA
} },
2293 { "lfdux", X(31,631), X_MASK
, PPC
|POWER
, { FRT
, RA
, RB
} },
2295 { "mfsrin", X(31,659), XRA_MASK
, PPC
|B32
, { RT
, RB
} },
2297 { "stswx", X(31,661), X_MASK
, PPC
, { RS
, RA
, RB
} },
2298 { "stsx", X(31,661), X_MASK
, POWER
, { RS
, RA
, RB
} },
2300 { "stwbrx", X(31,662), X_MASK
, PPC
, { RS
, RA
, RB
} },
2301 { "stbrx", X(31,662), X_MASK
, POWER
, { RS
, RA
, RB
} },
2303 { "stfsx", X(31,663), X_MASK
, PPC
|POWER
, { FRS
, RA
, RB
} },
2305 { "srq", XRC(31,664,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2306 { "srq.", XRC(31,664,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2308 { "sre", XRC(31,665,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2309 { "sre.", XRC(31,665,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2311 { "stfsux", X(31,695), X_MASK
, PPC
|POWER
, { FRS
, RA
, RB
} },
2313 { "sriq", XRC(31,696,0), X_MASK
, POWER
, { RA
, RS
, SH
} },
2314 { "sriq.", XRC(31,696,1), X_MASK
, POWER
, { RA
, RS
, SH
} },
2316 { "stswi", X(31,725), X_MASK
, PPC
, { RS
, RA
, NB
} },
2317 { "stsi", X(31,725), X_MASK
, POWER
, { RS
, RA
, NB
} },
2319 { "stfdx", X(31,727), X_MASK
, PPC
|POWER
, { FRS
, RA
, RB
} },
2321 { "srlq", XRC(31,728,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2322 { "srlq.", XRC(31,728,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2324 { "sreq", XRC(31,729,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2325 { "sreq.", XRC(31,729,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2327 { "stfdux", X(31,759), X_MASK
, PPC
|POWER
, { FRS
, RA
, RB
} },
2329 { "srliq", XRC(31,760,0), X_MASK
, POWER
, { RA
, RS
, SH
} },
2330 { "srliq.", XRC(31,760,1), X_MASK
, POWER
, { RA
, RS
, SH
} },
2332 { "lhbrx", X(31,790), X_MASK
, PPC
|POWER
, { RT
, RA
, RB
} },
2334 { "sraw", XRC(31,792,0), X_MASK
, PPC
, { RA
, RS
, RB
} },
2335 { "sra", XRC(31,792,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2336 { "sraw.", XRC(31,792,1), X_MASK
, PPC
, { RA
, RS
, RB
} },
2337 { "sra.", XRC(31,792,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2339 { "srad", XRC(31,794,0), X_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
2340 { "srad.", XRC(31,794,1), X_MASK
, PPC
|B64
, { RA
, RS
, RB
} },
2342 { "rac", X(31,818), X_MASK
, POWER
, { RT
, RA
, RB
} },
2344 { "srawi", XRC(31,824,0), X_MASK
, PPC
, { RA
, RS
, SH
} },
2345 { "srai", XRC(31,824,0), X_MASK
, POWER
, { RA
, RS
, SH
} },
2346 { "srawi.", XRC(31,824,1), X_MASK
, PPC
, { RA
, RS
, SH
} },
2347 { "srai.", XRC(31,824,1), X_MASK
, POWER
, { RA
, RS
, SH
} },
2349 { "eieio", X(31,854), 0xffffffff, PPC
, { 0 } },
2351 { "sthbrx", X(31,918), X_MASK
, PPC
|POWER
, { RS
, RA
, RB
} },
2353 { "sraq", XRC(31,920,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2354 { "sraq.", XRC(31,920,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2356 { "srea", XRC(31,921,0), X_MASK
, POWER
, { RA
, RS
, RB
} },
2357 { "srea.", XRC(31,921,1), X_MASK
, POWER
, { RA
, RS
, RB
} },
2359 { "extsh", XRC(31,922,0), XRB_MASK
, PPC
, { RA
, RS
} },
2360 { "exts", XRC(31,922,0), XRB_MASK
, POWER
, { RA
, RS
} },
2361 { "extsh.", XRC(31,922,1), XRB_MASK
, PPC
, { RA
, RS
} },
2362 { "exts.", XRC(31,922,1), XRB_MASK
, POWER
, { RA
, RS
} },
2364 { "sraiq", XRC(31,952,0), X_MASK
, POWER
, { RA
, RS
, SH
} },
2365 { "sraiq.", XRC(31,952,1), X_MASK
, POWER
, { RA
, RS
, SH
} },
2367 { "extsb", XRC(31,954,0), XRB_MASK
, PPC
, { RA
, RS
} },
2368 { "extsb.", XRC(31,954,1), XRB_MASK
, PPC
, { RA
, RS
} },
2370 { "icbi", X(31,982), XRT_MASK
, PPC
, { RA
, RB
} },
2372 { "stfiwx", X(31,983), X_MASK
, PPC
, { FRS
, RA
, RB
} },
2374 { "extsw", XRC(31,986,0), XRB_MASK
, PPC
, { RA
, RS
} },
2375 { "extsw.", XRC(31,986,1), XRB_MASK
, PPC
, { RA
, RS
} },
2377 { "dcbz", X(31,1014), XRT_MASK
, PPC
, { RA
, RB
} },
2378 { "dclz", X(31,1014), XRT_MASK
, PPC
, { RA
, RB
} },
2380 { "lwz", OP(32), OP_MASK
, PPC
, { RT
, D
, RA
} },
2381 { "l", OP(32), OP_MASK
, POWER
, { RT
, D
, RA
} },
2383 { "lwzu", OP(33), OP_MASK
, PPC
, { RT
, D
, RA
} },
2384 { "lu", OP(33), OP_MASK
, POWER
, { RT
, D
, RA
} },
2386 { "lbz", OP(34), OP_MASK
, PPC
|POWER
, { RT
, D
, RA
} },
2388 { "lbzu", OP(35), OP_MASK
, PPC
|POWER
, { RT
, D
, RA
} },
2390 { "stw", OP(36), OP_MASK
, PPC
, { RS
, D
, RA
} },
2391 { "st", OP(36), OP_MASK
, POWER
, { RS
, D
, RA
} },
2393 { "stwu", OP(37), OP_MASK
, PPC
, { RS
, D
, RA
} },
2394 { "stu", OP(37), OP_MASK
, POWER
, { RS
, D
, RA
} },
2396 { "stb", OP(38), OP_MASK
, PPC
|POWER
, { RS
, D
, RA
} },
2398 { "stbu", OP(39), OP_MASK
, PPC
|POWER
, { RS
, D
, RA
} },
2400 { "lhz", OP(40), OP_MASK
, PPC
|POWER
, { RT
, D
, RA
} },
2402 { "lhzu", OP(41), OP_MASK
, PPC
|POWER
, { RT
, D
, RA
} },
2404 { "lha", OP(42), OP_MASK
, PPC
|POWER
, { RT
, D
, RA
} },
2406 { "lhau", OP(43), OP_MASK
, PPC
|POWER
, { RT
, D
, RA
} },
2408 { "sth", OP(44), OP_MASK
, PPC
|POWER
, { RS
, D
, RA
} },
2410 { "sthu", OP(45), OP_MASK
, PPC
|POWER
, { RS
, D
, RA
} },
2412 { "lmw", OP(46), OP_MASK
, PPC
, { RT
, D
, RA
} },
2413 { "lm", OP(46), OP_MASK
, POWER
, { RT
, D
, RA
} },
2415 { "stmw", OP(47), OP_MASK
, PPC
, { RS
, D
, RA
} },
2416 { "stm", OP(47), OP_MASK
, POWER
, { RS
, D
, RA
} },
2418 { "lfs", OP(48), OP_MASK
, PPC
|POWER
, { FRT
, D
, RA
} },
2420 { "lfsu", OP(49), OP_MASK
, PPC
|POWER
, { FRT
, D
, RA
} },
2422 { "lfd", OP(50), OP_MASK
, PPC
|POWER
, { FRT
, D
, RA
} },
2424 { "lfdu", OP(51), OP_MASK
, PPC
|POWER
, { FRT
, D
, RA
} },
2426 { "stfs", OP(52), OP_MASK
, PPC
|POWER
, { FRS
, D
, RA
} },
2428 { "stfsu", OP(53), OP_MASK
, PPC
|POWER
, { FRS
, D
, RA
} },
2430 { "stfd", OP(54), OP_MASK
, PPC
|POWER
, { FRS
, D
, RA
} },
2432 { "stfdu", OP(55), OP_MASK
, PPC
|POWER
, { FRS
, D
, RA
} },
2434 { "ld", DSO(58,0), DS_MASK
, PPC
|B64
, { RT
, DS
, RA
} },
2436 { "ldu", DSO(58,1), DS_MASK
, PPC
|B64
, { RT
, DS
, RA
} },
2438 { "lwa", DSO(58,2), DS_MASK
, PPC
|B64
, { RT
, DS
, RA
} },
2440 { "fdivs", A(59,18,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2441 { "fdivs.", A(59,18,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2443 { "fsubs", A(59,20,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2444 { "fsubs.", A(59,20,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2446 { "fadds", A(59,21,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2447 { "fadds.", A(59,21,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2449 { "fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
2450 { "fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
2452 { "fres", A(59,24,0), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
2453 { "fres.", A(59,24,1), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
2455 { "fmuls", A(59,25,0), AFRB_MASK
, PPC
, { FRT
, FRA
, FRC
} },
2456 { "fmuls.", A(59,25,1), AFRB_MASK
, PPC
, { FRT
, FRA
, FRC
} },
2458 { "fmsubs", A(59,28,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2459 { "fmsubs.", A(59,28,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2461 { "fmadds", A(59,29,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2462 { "fmadds.", A(59,29,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2464 { "fnmsubs", A(59,30,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2465 { "fnmsubs.",A(59,30,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2467 { "fnmadds", A(59,31,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2468 { "fnmadds.",A(59,31,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2470 { "std", DSO(62,0), DS_MASK
, PPC
|B64
, { RS
, DS
, RA
} },
2472 { "stdu", DSO(62,1), DS_MASK
, PPC
|B64
, { RS
, DS
, RA
} },
2474 { "fcmpu", X(63,0), X_MASK
|(3<<21), PPC
|POWER
, { BF
, FRA
, FRB
} },
2476 { "frsp", XRC(63,12,0), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2477 { "frsp.", XRC(63,12,1), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2479 { "fctiw", XRC(63,14,0), XRA_MASK
, PPC
, { FRT
, FRB
} },
2480 { "fctiw.", XRC(63,14,1), XRA_MASK
, PPC
, { FRT
, FRB
} },
2482 { "fctiwz", XRC(63,15,0), XRA_MASK
, PPC
, { FRT
, FRB
} },
2483 { "fctiwz.", XRC(63,15,1), XRA_MASK
, PPC
, { FRT
, FRB
} },
2485 { "fdiv", A(63,18,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2486 { "fd", A(63,18,0), AFRC_MASK
, POWER
, { FRT
, FRA
, FRB
} },
2487 { "fdiv.", A(63,18,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2488 { "fd.", A(63,18,1), AFRC_MASK
, POWER
, { FRT
, FRA
, FRB
} },
2490 { "fsub", A(63,20,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2491 { "fs", A(63,20,0), AFRC_MASK
, POWER
, { FRT
, FRA
, FRB
} },
2492 { "fsub.", A(63,20,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2493 { "fs.", A(63,20,1), AFRC_MASK
, POWER
, { FRT
, FRA
, FRB
} },
2495 { "fadd", A(63,21,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2496 { "fa", A(63,21,0), AFRC_MASK
, POWER
, { FRT
, FRA
, FRB
} },
2497 { "fadd.", A(63,21,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
2498 { "fa.", A(63,21,1), AFRC_MASK
, POWER
, { FRT
, FRA
, FRB
} },
2500 { "fsqrt", A(63,22,0), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
2501 { "fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
2503 { "fsel", A(63,23,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2504 { "fsel.", A(63,23,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2506 { "fmul", A(63,25,0), AFRB_MASK
, PPC
, { FRT
, FRA
, FRC
} },
2507 { "fm", A(63,25,0), AFRB_MASK
, POWER
, { FRT
, FRA
, FRC
} },
2508 { "fmul.", A(63,25,1), AFRB_MASK
, PPC
, { FRT
, FRA
, FRC
} },
2509 { "fm.", A(63,25,1), AFRB_MASK
, POWER
, { FRT
, FRA
, FRC
} },
2511 { "frsqrte", A(63,26,0), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
2512 { "frsqrte.",A(63,26,1), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
2514 { "fmsub", A(63,28,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2515 { "fms", A(63,28,0), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2516 { "fmsub.", A(63,28,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2517 { "fms.", A(63,28,1), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2519 { "fmadd", A(63,29,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2520 { "fma", A(63,29,0), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2521 { "fmadd.", A(63,29,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2522 { "fma.", A(63,29,1), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2524 { "fnmsub", A(63,30,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2525 { "fnms", A(63,30,0), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2526 { "fnmsub.", A(63,30,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2527 { "fnms.", A(63,30,1), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2529 { "fnmadd", A(63,31,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2530 { "fnma", A(63,31,0), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2531 { "fnmadd.", A(63,31,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
2532 { "fnma.", A(63,31,1), A_MASK
, POWER
, { FRT
,FRA
,FRC
,FRB
} },
2534 { "fcmpo", X(63,30), X_MASK
|(3<<21), PPC
|POWER
, { BF
, FRA
, FRB
} },
2536 { "mtfsb1", XRC(63,38,0), XRARB_MASK
, PPC
|POWER
, { BT
} },
2537 { "mtfsb1.", XRC(63,38,1), XRARB_MASK
, PPC
|POWER
, { BT
} },
2539 { "fneg", XRC(63,40,0), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2540 { "fneg.", XRC(63,40,1), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2542 { "mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), PPC
|POWER
, { BF
, BFA
} },
2544 { "mtfsb0", XRC(63,70,0), XRARB_MASK
, PPC
|POWER
, { BT
} },
2545 { "mtfsb0.", XRC(63,70,1), XRARB_MASK
, PPC
|POWER
, { BT
} },
2547 { "fmr", XRC(63,72,0), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2548 { "fmr.", XRC(63,72,1), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2550 { "mtfsfi", XRC(63,134,0), XRA_MASK
|(3<<21)|(1<<11), PPC
|POWER
, { BF
, U
} },
2551 { "mtfsfi.", XRC(63,134,1), XRA_MASK
|(3<<21)|(1<<11), PPC
|POWER
, { BF
, U
} },
2553 { "fnabs", XRC(63,136,0), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2554 { "fnabs.", XRC(63,136,1), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2556 { "fabs", XRC(63,264,0), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2557 { "fabs.", XRC(63,264,1), XRA_MASK
, PPC
|POWER
, { FRT
, FRB
} },
2559 { "mffs", XRC(63,583,0), XRARB_MASK
, PPC
|POWER
, { FRT
} },
2560 { "mffs.", XRC(63,583,1), XRARB_MASK
, PPC
|POWER
, { FRT
} },
2562 { "mtfsf", XFL(63,711,0), XFL_MASK
, PPC
|POWER
, { FLM
, FRB
} },
2563 { "mtfsf.", XFL(63,711,1), XFL_MASK
, PPC
|POWER
, { FLM
, FRB
} },
2565 { "fctid", XRC(63,814,0), XRA_MASK
, PPC
|B64
, { FRT
, FRB
} },
2566 { "fctid.", XRC(63,814,1), XRA_MASK
, PPC
|B64
, { FRT
, FRB
} },
2568 { "fctidz", XRC(63,815,0), XRA_MASK
, PPC
|B64
, { FRT
, FRB
} },
2569 { "fctidz.", XRC(63,815,1), XRA_MASK
, PPC
|B64
, { FRT
, FRB
} },
2571 { "fcfid", XRC(63,846,0), XRA_MASK
, PPC
|B64
, { FRT
, FRB
} },
2572 { "fcfid.", XRC(63,846,1), XRA_MASK
, PPC
|B64
, { FRT
, FRB
} },
2576 const int powerpc_num_opcodes
=
2577 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
2579 /* The macro table. This is only used by the assembler. */
2581 const struct powerpc_macro powerpc_macros
[] = {
2582 { "extldi", 4, PPC
|B64
, "rldicr %0,%1,%3,(%2)-1" },
2583 { "extldi.", 4, PPC
|B64
, "rldicr. %0,%1,%3,(%2)-1" },
2584 { "extrdi", 4, PPC
|B64
, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
2585 { "extrdi.", 4, PPC
|B64
, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
2586 { "insrdi", 4, PPC
|B64
, "rldimi %0,%1,64-((%2)+(%3)),%3" },
2587 { "insrdi.", 4, PPC
|B64
, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
2588 { "rotrdi", 3, PPC
|B64
, "rldicl %0,%1,64-(%2),0" },
2589 { "rotrdi.", 3, PPC
|B64
, "rldicl. %0,%1,64-(%2),0" },
2590 { "sldi", 3, PPC
|B64
, "rldicr %0,%1,%2,63-(%2)" },
2591 { "sldi.", 3, PPC
|B64
, "rldicr. %0,%1,%2,63-(%2)" },
2592 { "srdi", 3, PPC
|B64
, "rldicl %0,%1,64-(%2),%2" },
2593 { "srdi.", 3, PPC
|B64
, "rldicl. %0,%1,64-(%2),%2" },
2594 { "clrrdi", 3, PPC
|B64
, "rldicr %0,%1,0,63-(%2)" },
2595 { "clrrdi.", 3, PPC
|B64
, "rldicr. %0,%1,0,63-(%2)" },
2596 { "clrlsldi",4, PPC
|B64
, "rldic %0,%1,%3,(%2)-(%3)" },
2597 { "clrlsldi.",4, PPC
|B64
, "rldic. %0,%1,%3,(%2)-(%3)" },
2599 { "extlwi", 4, PPC
, "rlwinm %0,%1,%3,0,(%2)-1" },
2600 { "extlwi.", 4, PPC
, "rlwinm. %0,%1,%3,0,(%2)-1" },
2601 { "extrwi", 4, PPC
, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
2602 { "extrwi.", 4, PPC
, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
2603 { "inslwi", 4, PPC
, "rlwimi %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2604 { "inslwi.", 4, PPC
, "rlwimi. %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2605 { "insrwi", 4, PPC
, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
2606 { "insrwi.", 4, PPC
, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
2607 { "rotrwi", 3, PPC
, "rlwinm %0,%1,32-(%2),0,31" },
2608 { "rotrwi.", 3, PPC
, "rlwinm. %0,%1,32-(%2),0,31" },
2609 { "slwi", 3, PPC
, "rlwinm %0,%1,%2,0,31-(%2)" },
2610 { "sli", 3, POWER
, "rlinm %0,%1,%2,0,31-(%2)" },
2611 { "slwi.", 3, PPC
, "rlwinm. %0,%1,%2,0,31-(%2)" },
2612 { "sli.", 3, POWER
, "rlinm. %0,%1,%2,0,31-(%2)" },
2613 { "srwi", 3, PPC
, "rlwinm %0,%1,32-(%2),%2,31" },
2614 { "sri", 3, POWER
, "rlinm %0,%1,32-(%2),%2,31" },
2615 { "srwi.", 3, PPC
, "rlwinm. %0,%1,32-(%2),%2,31" },
2616 { "sri.", 3, POWER
, "rlinm. %0,%1,32-(%2),%2,31" },
2617 { "clrrwi", 3, PPC
, "rlwinm %0,%1,0,0,31-(%2)" },
2618 { "clrrwi.", 3, PPC
, "rlwinm. %0,%1,0,0,31-(%2)" },
2619 { "clrlslwi",4, PPC
, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
2620 { "clrlslwi.",4, PPC
, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
2624 const int powerpc_num_macros
=
2625 sizeof (powerpc_macros
) / sizeof (powerpc_macros
[0]);