2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of the GNU opcodes library.
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
24 #include "opcode/riscv.h"
27 /* Register names used by gas and objdump. */
29 const char * const riscv_gpr_names_numeric
[NGPR
] =
31 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
32 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
33 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
34 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31"
37 const char * const riscv_gpr_names_abi
[NGPR
] =
39 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
40 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
41 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
42 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"
45 const char * const riscv_fpr_names_numeric
[NFPR
] =
47 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
48 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
49 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
50 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
53 const char * const riscv_fpr_names_abi
[NFPR
] =
55 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
56 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
57 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
58 "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
61 /* The order of overloaded instructions matters. Label arguments and
62 register arguments look the same. Instructions that can have either
63 for arguments must apear in the correct order in this table for the
64 assembler to pick the right one. In other words, entries with
65 immediate operands must apear after the same instruction with
68 Because of the lookup algorithm used, entries with the same opcode
69 name must be contiguous. */
71 #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1)
72 #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2)
73 #define MASK_RD (OP_MASK_RD << OP_SH_RD)
74 #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2)
75 #define MASK_IMM ENCODE_ITYPE_IMM (-1U)
76 #define MASK_RVC_IMM ENCODE_RVC_IMM (-1U)
77 #define MASK_UIMM ENCODE_UTYPE_IMM (-1U)
78 #define MASK_RM (OP_MASK_RM << OP_SH_RM)
79 #define MASK_PRED (OP_MASK_PRED << OP_SH_PRED)
80 #define MASK_SUCC (OP_MASK_SUCC << OP_SH_SUCC)
81 #define MASK_AQ (OP_MASK_AQ << OP_SH_AQ)
82 #define MASK_RL (OP_MASK_RL << OP_SH_RL)
83 #define MASK_AQRL (MASK_AQ | MASK_RL)
86 match_opcode (const struct riscv_opcode
*op
, insn_t insn
)
88 return ((insn
^ op
->match
) & op
->mask
) == 0;
92 match_never (const struct riscv_opcode
*op ATTRIBUTE_UNUSED
,
93 insn_t insn ATTRIBUTE_UNUSED
)
99 match_rs1_eq_rs2 (const struct riscv_opcode
*op
, insn_t insn
)
101 int rs1
= (insn
& MASK_RS1
) >> OP_SH_RS1
;
102 int rs2
= (insn
& MASK_RS2
) >> OP_SH_RS2
;
103 return match_opcode (op
, insn
) && rs1
== rs2
;
107 match_rd_nonzero (const struct riscv_opcode
*op
, insn_t insn
)
109 return match_opcode (op
, insn
) && ((insn
& MASK_RD
) != 0);
113 match_c_add (const struct riscv_opcode
*op
, insn_t insn
)
115 return match_rd_nonzero (op
, insn
) && ((insn
& MASK_CRS2
) != 0);
118 /* We don't allow mv zero,X to become a c.mv hint, so we need a separate
119 matching function for this. */
122 match_c_add_with_hint (const struct riscv_opcode
*op
, insn_t insn
)
124 return match_opcode (op
, insn
) && ((insn
& MASK_CRS2
) != 0);
128 match_c_nop (const struct riscv_opcode
*op
, insn_t insn
)
130 return (match_opcode (op
, insn
)
131 && (((insn
& MASK_RD
) >> OP_SH_RD
) == 0));
135 match_c_addi16sp (const struct riscv_opcode
*op
, insn_t insn
)
137 return (match_opcode (op
, insn
)
138 && (((insn
& MASK_RD
) >> OP_SH_RD
) == 2)
139 && EXTRACT_RVC_ADDI16SP_IMM (insn
) != 0);
143 match_c_lui (const struct riscv_opcode
*op
, insn_t insn
)
145 return (match_rd_nonzero (op
, insn
)
146 && (((insn
& MASK_RD
) >> OP_SH_RD
) != 2)
147 && EXTRACT_RVC_LUI_IMM (insn
) != 0);
150 /* We don't allow lui zero,X to become a c.lui hint, so we need a separate
151 matching function for this. */
154 match_c_lui_with_hint (const struct riscv_opcode
*op
, insn_t insn
)
156 return (match_opcode (op
, insn
)
157 && (((insn
& MASK_RD
) >> OP_SH_RD
) != 2)
158 && EXTRACT_RVC_LUI_IMM (insn
) != 0);
162 match_c_addi4spn (const struct riscv_opcode
*op
, insn_t insn
)
164 return match_opcode (op
, insn
) && EXTRACT_RVC_ADDI4SPN_IMM (insn
) != 0;
167 /* This requires a non-zero shift. A zero rd is a hint, so is allowed. */
170 match_c_slli (const struct riscv_opcode
*op
, insn_t insn
)
172 return match_opcode (op
, insn
) && EXTRACT_RVC_IMM (insn
) != 0;
175 /* This requires a non-zero rd, and a non-zero shift. */
178 match_slli_as_c_slli (const struct riscv_opcode
*op
, insn_t insn
)
180 return match_rd_nonzero (op
, insn
) && EXTRACT_RVC_IMM (insn
) != 0;
183 /* This requires a zero shift. A zero rd is a hint, so is allowed. */
186 match_c_slli64 (const struct riscv_opcode
*op
, insn_t insn
)
188 return match_opcode (op
, insn
) && EXTRACT_RVC_IMM (insn
) == 0;
191 /* This is used for both srli and srai. This requires a non-zero shift.
192 A zero rd is not possible. */
195 match_srxi_as_c_srxi (const struct riscv_opcode
*op
, insn_t insn
)
197 return match_opcode (op
, insn
) && EXTRACT_RVC_IMM (insn
) != 0;
200 const struct riscv_opcode riscv_opcodes
[] =
202 /* name, xlen, isa, operands, match, mask, match_func, pinfo. */
203 {"unimp", 0, INSN_CLASS_C
, "", 0, 0xffffU
, match_opcode
, INSN_ALIAS
},
204 {"unimp", 0, INSN_CLASS_I
, "", MATCH_CSRRW
|(CSR_CYCLE
<< OP_SH_CSR
), 0xffffffffU
, match_opcode
, 0 }, /* csrw cycle, x0 */
205 {"ebreak", 0, INSN_CLASS_C
, "", MATCH_C_EBREAK
, MASK_C_EBREAK
, match_opcode
, INSN_ALIAS
},
206 {"ebreak", 0, INSN_CLASS_I
, "", MATCH_EBREAK
, MASK_EBREAK
, match_opcode
, 0 },
207 {"sbreak", 0, INSN_CLASS_C
, "", MATCH_C_EBREAK
, MASK_C_EBREAK
, match_opcode
, INSN_ALIAS
},
208 {"sbreak", 0, INSN_CLASS_I
, "", MATCH_EBREAK
, MASK_EBREAK
, match_opcode
, INSN_ALIAS
},
209 {"ret", 0, INSN_CLASS_C
, "", MATCH_C_JR
|(X_RA
<< OP_SH_RD
), MASK_C_JR
|MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
210 {"ret", 0, INSN_CLASS_I
, "", MATCH_JALR
|(X_RA
<< OP_SH_RS1
), MASK_JALR
|MASK_RD
|MASK_RS1
|MASK_IMM
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
211 {"jr", 0, INSN_CLASS_C
, "d", MATCH_C_JR
, MASK_C_JR
, match_rd_nonzero
, INSN_ALIAS
|INSN_BRANCH
},
212 {"jr", 0, INSN_CLASS_I
, "s", MATCH_JALR
, MASK_JALR
|MASK_RD
|MASK_IMM
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
213 {"jr", 0, INSN_CLASS_I
, "o(s)", MATCH_JALR
, MASK_JALR
|MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
214 {"jr", 0, INSN_CLASS_I
, "s,j", MATCH_JALR
, MASK_JALR
|MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
215 {"jalr", 0, INSN_CLASS_C
, "d", MATCH_C_JALR
, MASK_C_JALR
, match_rd_nonzero
, INSN_ALIAS
|INSN_JSR
},
216 {"jalr", 0, INSN_CLASS_I
, "s", MATCH_JALR
|(X_RA
<< OP_SH_RD
), MASK_JALR
|MASK_RD
|MASK_IMM
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
217 {"jalr", 0, INSN_CLASS_I
, "o(s)", MATCH_JALR
|(X_RA
<< OP_SH_RD
), MASK_JALR
|MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
218 {"jalr", 0, INSN_CLASS_I
, "s,j", MATCH_JALR
|(X_RA
<< OP_SH_RD
), MASK_JALR
|MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
219 {"jalr", 0, INSN_CLASS_I
, "d,s", MATCH_JALR
, MASK_JALR
|MASK_IMM
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
220 {"jalr", 0, INSN_CLASS_I
, "d,o(s)", MATCH_JALR
, MASK_JALR
, match_opcode
, INSN_JSR
},
221 {"jalr", 0, INSN_CLASS_I
, "d,s,j", MATCH_JALR
, MASK_JALR
, match_opcode
, INSN_JSR
},
222 {"j", 0, INSN_CLASS_C
, "Ca", MATCH_C_J
, MASK_C_J
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
223 {"j", 0, INSN_CLASS_I
, "a", MATCH_JAL
, MASK_JAL
|MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
224 {"jal", 0, INSN_CLASS_I
, "d,a", MATCH_JAL
, MASK_JAL
, match_opcode
, INSN_JSR
},
225 {"jal", 32, INSN_CLASS_C
, "Ca", MATCH_C_JAL
, MASK_C_JAL
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
226 {"jal", 0, INSN_CLASS_I
, "a", MATCH_JAL
|(X_RA
<< OP_SH_RD
), MASK_JAL
|MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
227 {"call", 0, INSN_CLASS_I
, "d,c", (X_T1
<< OP_SH_RS1
), (int) M_CALL
, match_never
, INSN_MACRO
},
228 {"call", 0, INSN_CLASS_I
, "c", (X_RA
<< OP_SH_RS1
)|(X_RA
<< OP_SH_RD
), (int) M_CALL
, match_never
, INSN_MACRO
},
229 {"tail", 0, INSN_CLASS_I
, "c", (X_T1
<< OP_SH_RS1
), (int) M_CALL
, match_never
, INSN_MACRO
},
230 {"jump", 0, INSN_CLASS_I
, "c,s", 0, (int) M_CALL
, match_never
, INSN_MACRO
},
231 {"nop", 0, INSN_CLASS_C
, "", MATCH_C_ADDI
, 0xffff, match_opcode
, INSN_ALIAS
},
232 {"nop", 0, INSN_CLASS_I
, "", MATCH_ADDI
, MASK_ADDI
|MASK_RD
|MASK_RS1
|MASK_IMM
, match_opcode
, INSN_ALIAS
},
233 {"lui", 0, INSN_CLASS_C
, "d,Cu", MATCH_C_LUI
, MASK_C_LUI
, match_c_lui
, INSN_ALIAS
},
234 {"lui", 0, INSN_CLASS_I
, "d,u", MATCH_LUI
, MASK_LUI
, match_opcode
, 0 },
235 {"li", 0, INSN_CLASS_C
, "d,Cv", MATCH_C_LUI
, MASK_C_LUI
, match_c_lui
, INSN_ALIAS
},
236 {"li", 0, INSN_CLASS_C
, "d,Co", MATCH_C_LI
, MASK_C_LI
, match_rd_nonzero
, INSN_ALIAS
},
237 {"li", 0, INSN_CLASS_I
, "d,j", MATCH_ADDI
, MASK_ADDI
|MASK_RS1
, match_opcode
, INSN_ALIAS
}, /* addi */
238 {"li", 0, INSN_CLASS_I
, "d,I", 0, (int) M_LI
, match_never
, INSN_MACRO
},
239 {"mv", 0, INSN_CLASS_C
, "d,CV", MATCH_C_MV
, MASK_C_MV
, match_c_add
, INSN_ALIAS
},
240 {"mv", 0, INSN_CLASS_I
, "d,s", MATCH_ADDI
, MASK_ADDI
|MASK_IMM
, match_opcode
, INSN_ALIAS
},
241 {"move", 0, INSN_CLASS_C
, "d,CV", MATCH_C_MV
, MASK_C_MV
, match_c_add
, INSN_ALIAS
},
242 {"move", 0, INSN_CLASS_I
, "d,s", MATCH_ADDI
, MASK_ADDI
|MASK_IMM
, match_opcode
, INSN_ALIAS
},
243 {"sext.b", 0, INSN_CLASS_I
, "d,s", 0, (int) M_SEXTB
, match_never
, INSN_MACRO
},
244 {"sext.h", 0, INSN_CLASS_I
, "d,s", 0, (int) M_SEXTH
, match_never
, INSN_MACRO
},
245 {"zext.b", 0, INSN_CLASS_I
, "d,s", MATCH_ANDI
|ENCODE_ITYPE_IMM (255), MASK_ANDI
| MASK_IMM
, match_opcode
, INSN_ALIAS
},
246 {"zext.h", 0, INSN_CLASS_I
, "d,s", 0, (int) M_ZEXTH
, match_never
, INSN_MACRO
},
247 {"andi", 0, INSN_CLASS_C
, "Cs,Cw,Co", MATCH_C_ANDI
, MASK_C_ANDI
, match_opcode
, INSN_ALIAS
},
248 {"andi", 0, INSN_CLASS_I
, "d,s,j", MATCH_ANDI
, MASK_ANDI
, match_opcode
, 0 },
249 {"and", 0, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_AND
, MASK_C_AND
, match_opcode
, INSN_ALIAS
},
250 {"and", 0, INSN_CLASS_C
, "Cs,Ct,Cw", MATCH_C_AND
, MASK_C_AND
, match_opcode
, INSN_ALIAS
},
251 {"and", 0, INSN_CLASS_C
, "Cs,Cw,Co", MATCH_C_ANDI
, MASK_C_ANDI
, match_opcode
, INSN_ALIAS
},
252 {"and", 0, INSN_CLASS_I
, "d,s,t", MATCH_AND
, MASK_AND
, match_opcode
, 0 },
253 {"and", 0, INSN_CLASS_I
, "d,s,j", MATCH_ANDI
, MASK_ANDI
, match_opcode
, INSN_ALIAS
},
254 {"beqz", 0, INSN_CLASS_C
, "Cs,Cp", MATCH_C_BEQZ
, MASK_C_BEQZ
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
255 {"beqz", 0, INSN_CLASS_I
, "s,p", MATCH_BEQ
, MASK_BEQ
|MASK_RS2
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
256 {"beq", 0, INSN_CLASS_C
, "Cs,Cz,Cp", MATCH_C_BEQZ
, MASK_C_BEQZ
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
257 {"beq", 0, INSN_CLASS_I
, "s,t,p", MATCH_BEQ
, MASK_BEQ
, match_opcode
, INSN_CONDBRANCH
},
258 {"blez", 0, INSN_CLASS_I
, "t,p", MATCH_BGE
, MASK_BGE
|MASK_RS1
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
259 {"bgez", 0, INSN_CLASS_I
, "s,p", MATCH_BGE
, MASK_BGE
|MASK_RS2
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
260 {"bge", 0, INSN_CLASS_I
, "s,t,p", MATCH_BGE
, MASK_BGE
, match_opcode
, INSN_CONDBRANCH
},
261 {"bgeu", 0, INSN_CLASS_I
, "s,t,p", MATCH_BGEU
, MASK_BGEU
, match_opcode
, INSN_CONDBRANCH
},
262 {"ble", 0, INSN_CLASS_I
, "t,s,p", MATCH_BGE
, MASK_BGE
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
263 {"bleu", 0, INSN_CLASS_I
, "t,s,p", MATCH_BGEU
, MASK_BGEU
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
264 {"bltz", 0, INSN_CLASS_I
, "s,p", MATCH_BLT
, MASK_BLT
|MASK_RS2
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
265 {"bgtz", 0, INSN_CLASS_I
, "t,p", MATCH_BLT
, MASK_BLT
|MASK_RS1
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
266 {"blt", 0, INSN_CLASS_I
, "s,t,p", MATCH_BLT
, MASK_BLT
, match_opcode
, INSN_CONDBRANCH
},
267 {"bltu", 0, INSN_CLASS_I
, "s,t,p", MATCH_BLTU
, MASK_BLTU
, match_opcode
, INSN_CONDBRANCH
},
268 {"bgt", 0, INSN_CLASS_I
, "t,s,p", MATCH_BLT
, MASK_BLT
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
269 {"bgtu", 0, INSN_CLASS_I
, "t,s,p", MATCH_BLTU
, MASK_BLTU
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
270 {"bnez", 0, INSN_CLASS_C
, "Cs,Cp", MATCH_C_BNEZ
, MASK_C_BNEZ
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
271 {"bnez", 0, INSN_CLASS_I
, "s,p", MATCH_BNE
, MASK_BNE
|MASK_RS2
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
272 {"bne", 0, INSN_CLASS_C
, "Cs,Cz,Cp", MATCH_C_BNEZ
, MASK_C_BNEZ
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
273 {"bne", 0, INSN_CLASS_I
, "s,t,p", MATCH_BNE
, MASK_BNE
, match_opcode
, INSN_CONDBRANCH
},
274 {"addi", 0, INSN_CLASS_C
, "Ct,Cc,CK", MATCH_C_ADDI4SPN
, MASK_C_ADDI4SPN
, match_c_addi4spn
, INSN_ALIAS
},
275 {"addi", 0, INSN_CLASS_C
, "d,CU,Cj", MATCH_C_ADDI
, MASK_C_ADDI
, match_rd_nonzero
, INSN_ALIAS
},
276 {"addi", 0, INSN_CLASS_C
, "d,CU,z", MATCH_C_NOP
, MASK_C_ADDI
|MASK_RVC_IMM
, match_c_nop
, INSN_ALIAS
},
277 {"addi", 0, INSN_CLASS_C
, "Cc,Cc,CL", MATCH_C_ADDI16SP
, MASK_C_ADDI16SP
, match_c_addi16sp
, INSN_ALIAS
},
278 {"addi", 0, INSN_CLASS_C
, "d,Cz,Co", MATCH_C_LI
, MASK_C_LI
, match_rd_nonzero
, INSN_ALIAS
},
279 {"addi", 0, INSN_CLASS_I
, "d,s,j", MATCH_ADDI
, MASK_ADDI
, match_opcode
, 0 },
280 {"add", 0, INSN_CLASS_C
, "d,CU,CV", MATCH_C_ADD
, MASK_C_ADD
, match_c_add
, INSN_ALIAS
},
281 {"add", 0, INSN_CLASS_C
, "d,CV,CU", MATCH_C_ADD
, MASK_C_ADD
, match_c_add
, INSN_ALIAS
},
282 {"add", 0, INSN_CLASS_C
, "d,CU,Co", MATCH_C_ADDI
, MASK_C_ADDI
, match_rd_nonzero
, INSN_ALIAS
},
283 {"add", 0, INSN_CLASS_C
, "Ct,Cc,CK", MATCH_C_ADDI4SPN
, MASK_C_ADDI4SPN
, match_c_addi4spn
, INSN_ALIAS
},
284 {"add", 0, INSN_CLASS_C
, "Cc,Cc,CL", MATCH_C_ADDI16SP
, MASK_C_ADDI16SP
, match_c_addi16sp
, INSN_ALIAS
},
285 {"add", 0, INSN_CLASS_C
, "d,Cz,CV", MATCH_C_MV
, MASK_C_MV
, match_c_add
, INSN_ALIAS
},
286 {"add", 0, INSN_CLASS_I
, "d,s,t", MATCH_ADD
, MASK_ADD
, match_opcode
, 0 },
287 {"add", 0, INSN_CLASS_I
, "d,s,t,1", MATCH_ADD
, MASK_ADD
, match_opcode
, 0 },
288 {"add", 0, INSN_CLASS_I
, "d,s,j", MATCH_ADDI
, MASK_ADDI
, match_opcode
, INSN_ALIAS
},
289 {"la", 0, INSN_CLASS_I
, "d,B", 0, (int) M_LA
, match_never
, INSN_MACRO
},
290 {"lla", 0, INSN_CLASS_I
, "d,B", 0, (int) M_LLA
, match_never
, INSN_MACRO
},
291 {"la.tls.gd", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LA_TLS_GD
, match_never
, INSN_MACRO
},
292 {"la.tls.ie", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LA_TLS_IE
, match_never
, INSN_MACRO
},
293 {"neg", 0, INSN_CLASS_I
, "d,t", MATCH_SUB
, MASK_SUB
|MASK_RS1
, match_opcode
, INSN_ALIAS
}, /* sub 0 */
294 {"slli", 0, INSN_CLASS_C
, "d,CU,C>", MATCH_C_SLLI
, MASK_C_SLLI
, match_slli_as_c_slli
, INSN_ALIAS
},
295 {"slli", 0, INSN_CLASS_I
, "d,s,>", MATCH_SLLI
, MASK_SLLI
, match_opcode
, 0 },
296 {"sll", 0, INSN_CLASS_C
, "d,CU,C>", MATCH_C_SLLI
, MASK_C_SLLI
, match_slli_as_c_slli
, INSN_ALIAS
},
297 {"sll", 0, INSN_CLASS_I
, "d,s,t", MATCH_SLL
, MASK_SLL
, match_opcode
, 0 },
298 {"sll", 0, INSN_CLASS_I
, "d,s,>", MATCH_SLLI
, MASK_SLLI
, match_opcode
, INSN_ALIAS
},
299 {"srli", 0, INSN_CLASS_C
, "Cs,Cw,C>", MATCH_C_SRLI
, MASK_C_SRLI
, match_srxi_as_c_srxi
, INSN_ALIAS
},
300 {"srli", 0, INSN_CLASS_I
, "d,s,>", MATCH_SRLI
, MASK_SRLI
, match_opcode
, 0 },
301 {"srl", 0, INSN_CLASS_C
, "Cs,Cw,C>", MATCH_C_SRLI
, MASK_C_SRLI
, match_srxi_as_c_srxi
, INSN_ALIAS
},
302 {"srl", 0, INSN_CLASS_I
, "d,s,t", MATCH_SRL
, MASK_SRL
, match_opcode
, 0 },
303 {"srl", 0, INSN_CLASS_I
, "d,s,>", MATCH_SRLI
, MASK_SRLI
, match_opcode
, INSN_ALIAS
},
304 {"srai", 0, INSN_CLASS_C
, "Cs,Cw,C>", MATCH_C_SRAI
, MASK_C_SRAI
, match_srxi_as_c_srxi
, INSN_ALIAS
},
305 {"srai", 0, INSN_CLASS_I
, "d,s,>", MATCH_SRAI
, MASK_SRAI
, match_opcode
, 0 },
306 {"sra", 0, INSN_CLASS_C
, "Cs,Cw,C>", MATCH_C_SRAI
, MASK_C_SRAI
, match_srxi_as_c_srxi
, INSN_ALIAS
},
307 {"sra", 0, INSN_CLASS_I
, "d,s,t", MATCH_SRA
, MASK_SRA
, match_opcode
, 0 },
308 {"sra", 0, INSN_CLASS_I
, "d,s,>", MATCH_SRAI
, MASK_SRAI
, match_opcode
, INSN_ALIAS
},
309 {"sub", 0, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_SUB
, MASK_C_SUB
, match_opcode
, INSN_ALIAS
},
310 {"sub", 0, INSN_CLASS_I
, "d,s,t", MATCH_SUB
, MASK_SUB
, match_opcode
, 0 },
311 {"lb", 0, INSN_CLASS_I
, "d,o(s)", MATCH_LB
, MASK_LB
, match_opcode
, INSN_DREF
|INSN_1_BYTE
},
312 {"lb", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LB
, match_never
, INSN_MACRO
},
313 {"lbu", 0, INSN_CLASS_I
, "d,o(s)", MATCH_LBU
, MASK_LBU
, match_opcode
, INSN_DREF
|INSN_1_BYTE
},
314 {"lbu", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LBU
, match_never
, INSN_MACRO
},
315 {"lh", 0, INSN_CLASS_I
, "d,o(s)", MATCH_LH
, MASK_LH
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
316 {"lh", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LH
, match_never
, INSN_MACRO
},
317 {"lhu", 0, INSN_CLASS_I
, "d,o(s)", MATCH_LHU
, MASK_LHU
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
318 {"lhu", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LHU
, match_never
, INSN_MACRO
},
319 {"lw", 0, INSN_CLASS_C
, "d,Cm(Cc)", MATCH_C_LWSP
, MASK_C_LWSP
, match_rd_nonzero
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
320 {"lw", 0, INSN_CLASS_C
, "Ct,Ck(Cs)", MATCH_C_LW
, MASK_C_LW
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
321 {"lw", 0, INSN_CLASS_I
, "d,o(s)", MATCH_LW
, MASK_LW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
322 {"lw", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LW
, match_never
, INSN_MACRO
},
323 {"not", 0, INSN_CLASS_I
, "d,s", MATCH_XORI
|MASK_IMM
, MASK_XORI
|MASK_IMM
, match_opcode
, INSN_ALIAS
},
324 {"ori", 0, INSN_CLASS_I
, "d,s,j", MATCH_ORI
, MASK_ORI
, match_opcode
, 0 },
325 {"or", 0, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_OR
, MASK_C_OR
, match_opcode
, INSN_ALIAS
},
326 {"or", 0, INSN_CLASS_C
, "Cs,Ct,Cw", MATCH_C_OR
, MASK_C_OR
, match_opcode
, INSN_ALIAS
},
327 {"or", 0, INSN_CLASS_I
, "d,s,t", MATCH_OR
, MASK_OR
, match_opcode
, 0 },
328 {"or", 0, INSN_CLASS_I
, "d,s,j", MATCH_ORI
, MASK_ORI
, match_opcode
, INSN_ALIAS
},
329 {"auipc", 0, INSN_CLASS_I
, "d,u", MATCH_AUIPC
, MASK_AUIPC
, match_opcode
, 0 },
330 {"seqz", 0, INSN_CLASS_I
, "d,s", MATCH_SLTIU
|ENCODE_ITYPE_IMM (1), MASK_SLTIU
| MASK_IMM
, match_opcode
, INSN_ALIAS
},
331 {"snez", 0, INSN_CLASS_I
, "d,t", MATCH_SLTU
, MASK_SLTU
|MASK_RS1
, match_opcode
, INSN_ALIAS
},
332 {"sltz", 0, INSN_CLASS_I
, "d,s", MATCH_SLT
, MASK_SLT
|MASK_RS2
, match_opcode
, INSN_ALIAS
},
333 {"sgtz", 0, INSN_CLASS_I
, "d,t", MATCH_SLT
, MASK_SLT
|MASK_RS1
, match_opcode
, INSN_ALIAS
},
334 {"slti", 0, INSN_CLASS_I
, "d,s,j", MATCH_SLTI
, MASK_SLTI
, match_opcode
, 0 },
335 {"slt", 0, INSN_CLASS_I
, "d,s,t", MATCH_SLT
, MASK_SLT
, match_opcode
, 0 },
336 {"slt", 0, INSN_CLASS_I
, "d,s,j", MATCH_SLTI
, MASK_SLTI
, match_opcode
, INSN_ALIAS
},
337 {"sltiu", 0, INSN_CLASS_I
, "d,s,j", MATCH_SLTIU
, MASK_SLTIU
, match_opcode
, 0 },
338 {"sltu", 0, INSN_CLASS_I
, "d,s,t", MATCH_SLTU
, MASK_SLTU
, match_opcode
, 0 },
339 {"sltu", 0, INSN_CLASS_I
, "d,s,j", MATCH_SLTIU
, MASK_SLTIU
, match_opcode
, INSN_ALIAS
},
340 {"sgt", 0, INSN_CLASS_I
, "d,t,s", MATCH_SLT
, MASK_SLT
, match_opcode
, INSN_ALIAS
},
341 {"sgtu", 0, INSN_CLASS_I
, "d,t,s", MATCH_SLTU
, MASK_SLTU
, match_opcode
, INSN_ALIAS
},
342 {"sb", 0, INSN_CLASS_I
, "t,q(s)", MATCH_SB
, MASK_SB
, match_opcode
, INSN_DREF
|INSN_1_BYTE
},
343 {"sb", 0, INSN_CLASS_I
, "t,A,s", 0, (int) M_SB
, match_never
, INSN_MACRO
},
344 {"sh", 0, INSN_CLASS_I
, "t,q(s)", MATCH_SH
, MASK_SH
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
345 {"sh", 0, INSN_CLASS_I
, "t,A,s", 0, (int) M_SH
, match_never
, INSN_MACRO
},
346 {"sw", 0, INSN_CLASS_C
, "CV,CM(Cc)", MATCH_C_SWSP
, MASK_C_SWSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
347 {"sw", 0, INSN_CLASS_C
, "Ct,Ck(Cs)", MATCH_C_SW
, MASK_C_SW
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
348 {"sw", 0, INSN_CLASS_I
, "t,q(s)", MATCH_SW
, MASK_SW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
349 {"sw", 0, INSN_CLASS_I
, "t,A,s", 0, (int) M_SW
, match_never
, INSN_MACRO
},
350 {"pause", 0, INSN_CLASS_ZIHINTPAUSE
, "",MATCH_PAUSE
, MASK_PAUSE
, match_opcode
, 0 },
351 {"fence", 0, INSN_CLASS_I
, "", MATCH_FENCE
|MASK_PRED
|MASK_SUCC
, MASK_FENCE
|MASK_RD
|MASK_RS1
|MASK_IMM
, match_opcode
, INSN_ALIAS
},
352 {"fence", 0, INSN_CLASS_I
, "P,Q", MATCH_FENCE
, MASK_FENCE
|MASK_RD
|MASK_RS1
|(MASK_IMM
& ~MASK_PRED
& ~MASK_SUCC
), match_opcode
, 0 },
353 {"fence.i", 0, INSN_CLASS_ZIFENCEI
, "", MATCH_FENCE_I
, MASK_FENCE
|MASK_RD
|MASK_RS1
|MASK_IMM
, match_opcode
, 0 },
354 {"fence.tso", 0, INSN_CLASS_I
, "", MATCH_FENCE_TSO
, MASK_FENCE_TSO
|MASK_RD
|MASK_RS1
, match_opcode
, INSN_ALIAS
},
355 {"rdcycle", 0, INSN_CLASS_I
, "d", MATCH_RDCYCLE
, MASK_RDCYCLE
, match_opcode
, INSN_ALIAS
},
356 {"rdinstret", 0, INSN_CLASS_I
, "d", MATCH_RDINSTRET
, MASK_RDINSTRET
, match_opcode
, INSN_ALIAS
},
357 {"rdtime", 0, INSN_CLASS_I
, "d", MATCH_RDTIME
, MASK_RDTIME
, match_opcode
, INSN_ALIAS
},
358 {"rdcycleh", 32, INSN_CLASS_I
, "d", MATCH_RDCYCLEH
, MASK_RDCYCLEH
, match_opcode
, INSN_ALIAS
},
359 {"rdinstreth", 32, INSN_CLASS_I
, "d", MATCH_RDINSTRETH
, MASK_RDINSTRETH
, match_opcode
, INSN_ALIAS
},
360 {"rdtimeh", 32, INSN_CLASS_I
, "d", MATCH_RDTIMEH
, MASK_RDTIMEH
, match_opcode
, INSN_ALIAS
},
361 {"ecall", 0, INSN_CLASS_I
, "", MATCH_SCALL
, MASK_SCALL
, match_opcode
, 0 },
362 {"scall", 0, INSN_CLASS_I
, "", MATCH_SCALL
, MASK_SCALL
, match_opcode
, 0 },
363 {"xori", 0, INSN_CLASS_I
, "d,s,j", MATCH_XORI
, MASK_XORI
, match_opcode
, 0 },
364 {"xor", 0, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_XOR
, MASK_C_XOR
, match_opcode
, INSN_ALIAS
},
365 {"xor", 0, INSN_CLASS_C
, "Cs,Ct,Cw", MATCH_C_XOR
, MASK_C_XOR
, match_opcode
, INSN_ALIAS
},
366 {"xor", 0, INSN_CLASS_I
, "d,s,t", MATCH_XOR
, MASK_XOR
, match_opcode
, 0 },
367 {"xor", 0, INSN_CLASS_I
, "d,s,j", MATCH_XORI
, MASK_XORI
, match_opcode
, INSN_ALIAS
},
368 {"lwu", 64, INSN_CLASS_I
, "d,o(s)", MATCH_LWU
, MASK_LWU
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
369 {"lwu", 64, INSN_CLASS_I
, "d,A", 0, (int) M_LWU
, match_never
, INSN_MACRO
},
370 {"ld", 64, INSN_CLASS_C
, "d,Cn(Cc)", MATCH_C_LDSP
, MASK_C_LDSP
, match_rd_nonzero
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
371 {"ld", 64, INSN_CLASS_C
, "Ct,Cl(Cs)", MATCH_C_LD
, MASK_C_LD
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
372 {"ld", 64, INSN_CLASS_I
, "d,o(s)", MATCH_LD
, MASK_LD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
373 {"ld", 64, INSN_CLASS_I
, "d,A", 0, (int) M_LD
, match_never
, INSN_MACRO
},
374 {"sd", 64, INSN_CLASS_C
, "CV,CN(Cc)", MATCH_C_SDSP
, MASK_C_SDSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
375 {"sd", 64, INSN_CLASS_C
, "Ct,Cl(Cs)", MATCH_C_SD
, MASK_C_SD
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
376 {"sd", 64, INSN_CLASS_I
, "t,q(s)", MATCH_SD
, MASK_SD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
377 {"sd", 64, INSN_CLASS_I
, "t,A,s", 0, (int) M_SD
, match_never
, INSN_MACRO
},
378 {"zext.w", 64, INSN_CLASS_I
, "d,s", 0, (int) M_ZEXTW
, match_never
, INSN_MACRO
},
379 {"sext.w", 64, INSN_CLASS_C
, "d,CU", MATCH_C_ADDIW
, MASK_C_ADDIW
|MASK_RVC_IMM
, match_rd_nonzero
, INSN_ALIAS
},
380 {"sext.w", 64, INSN_CLASS_I
, "d,s", MATCH_ADDIW
, MASK_ADDIW
|MASK_IMM
, match_opcode
, INSN_ALIAS
},
381 {"addiw", 64, INSN_CLASS_C
, "d,CU,Co", MATCH_C_ADDIW
, MASK_C_ADDIW
, match_rd_nonzero
, INSN_ALIAS
},
382 {"addiw", 64, INSN_CLASS_I
, "d,s,j", MATCH_ADDIW
, MASK_ADDIW
, match_opcode
, 0 },
383 {"addw", 64, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_ADDW
, MASK_C_ADDW
, match_opcode
, INSN_ALIAS
},
384 {"addw", 64, INSN_CLASS_C
, "Cs,Ct,Cw", MATCH_C_ADDW
, MASK_C_ADDW
, match_opcode
, INSN_ALIAS
},
385 {"addw", 64, INSN_CLASS_C
, "d,CU,Co", MATCH_C_ADDIW
, MASK_C_ADDIW
, match_rd_nonzero
, INSN_ALIAS
},
386 {"addw", 64, INSN_CLASS_I
, "d,s,t", MATCH_ADDW
, MASK_ADDW
, match_opcode
, 0 },
387 {"addw", 64, INSN_CLASS_I
, "d,s,j", MATCH_ADDIW
, MASK_ADDIW
, match_opcode
, INSN_ALIAS
},
388 {"negw", 64, INSN_CLASS_I
, "d,t", MATCH_SUBW
, MASK_SUBW
|MASK_RS1
, match_opcode
, INSN_ALIAS
}, /* sub 0 */
389 {"slliw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SLLIW
, MASK_SLLIW
, match_opcode
, 0 },
390 {"sllw", 64, INSN_CLASS_I
, "d,s,t", MATCH_SLLW
, MASK_SLLW
, match_opcode
, 0 },
391 {"sllw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SLLIW
, MASK_SLLIW
, match_opcode
, INSN_ALIAS
},
392 {"srliw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SRLIW
, MASK_SRLIW
, match_opcode
, 0 },
393 {"srlw", 64, INSN_CLASS_I
, "d,s,t", MATCH_SRLW
, MASK_SRLW
, match_opcode
, 0 },
394 {"srlw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SRLIW
, MASK_SRLIW
, match_opcode
, INSN_ALIAS
},
395 {"sraiw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SRAIW
, MASK_SRAIW
, match_opcode
, 0 },
396 {"sraw", 64, INSN_CLASS_I
, "d,s,t", MATCH_SRAW
, MASK_SRAW
, match_opcode
, 0 },
397 {"sraw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SRAIW
, MASK_SRAIW
, match_opcode
, INSN_ALIAS
},
398 {"subw", 64, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_SUBW
, MASK_C_SUBW
, match_opcode
, INSN_ALIAS
},
399 {"subw", 64, INSN_CLASS_I
, "d,s,t", MATCH_SUBW
, MASK_SUBW
, match_opcode
, 0 },
401 /* Atomic memory operation instruction subset. */
402 {"lr.w", 0, INSN_CLASS_A
, "d,0(s)", MATCH_LR_W
, MASK_LR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
403 {"sc.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_W
, MASK_SC_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
404 {"amoadd.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_W
, MASK_AMOADD_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
405 {"amoswap.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_W
, MASK_AMOSWAP_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
406 {"amoand.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_W
, MASK_AMOAND_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
407 {"amoor.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_W
, MASK_AMOOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
408 {"amoxor.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_W
, MASK_AMOXOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
409 {"amomax.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_W
, MASK_AMOMAX_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
410 {"amomaxu.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_W
, MASK_AMOMAXU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
411 {"amomin.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_W
, MASK_AMOMIN_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
412 {"amominu.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_W
, MASK_AMOMINU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
413 {"lr.w.aq", 0, INSN_CLASS_A
, "d,0(s)", MATCH_LR_W
|MASK_AQ
, MASK_LR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
414 {"sc.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_W
|MASK_AQ
, MASK_SC_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
415 {"amoadd.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_W
|MASK_AQ
, MASK_AMOADD_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
416 {"amoswap.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_W
|MASK_AQ
, MASK_AMOSWAP_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
417 {"amoand.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_W
|MASK_AQ
, MASK_AMOAND_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
418 {"amoor.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_W
|MASK_AQ
, MASK_AMOOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
419 {"amoxor.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_W
|MASK_AQ
, MASK_AMOXOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
420 {"amomax.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_W
|MASK_AQ
, MASK_AMOMAX_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
421 {"amomaxu.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_W
|MASK_AQ
, MASK_AMOMAXU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
422 {"amomin.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_W
|MASK_AQ
, MASK_AMOMIN_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
423 {"amominu.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_W
|MASK_AQ
, MASK_AMOMINU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
424 {"lr.w.rl", 0, INSN_CLASS_A
, "d,0(s)", MATCH_LR_W
|MASK_RL
, MASK_LR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
425 {"sc.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_W
|MASK_RL
, MASK_SC_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
426 {"amoadd.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_W
|MASK_RL
, MASK_AMOADD_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
427 {"amoswap.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_W
|MASK_RL
, MASK_AMOSWAP_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
428 {"amoand.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_W
|MASK_RL
, MASK_AMOAND_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
429 {"amoor.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_W
|MASK_RL
, MASK_AMOOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
430 {"amoxor.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_W
|MASK_RL
, MASK_AMOXOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
431 {"amomax.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_W
|MASK_RL
, MASK_AMOMAX_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
432 {"amomaxu.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_W
|MASK_RL
, MASK_AMOMAXU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
433 {"amomin.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_W
|MASK_RL
, MASK_AMOMIN_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
434 {"amominu.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_W
|MASK_RL
, MASK_AMOMINU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
435 {"lr.w.aqrl", 0, INSN_CLASS_A
, "d,0(s)", MATCH_LR_W
|MASK_AQRL
, MASK_LR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
436 {"sc.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_W
|MASK_AQRL
, MASK_SC_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
437 {"amoadd.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_W
|MASK_AQRL
, MASK_AMOADD_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
438 {"amoswap.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_W
|MASK_AQRL
, MASK_AMOSWAP_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
439 {"amoand.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_W
|MASK_AQRL
, MASK_AMOAND_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
440 {"amoor.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_W
|MASK_AQRL
, MASK_AMOOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
441 {"amoxor.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_W
|MASK_AQRL
, MASK_AMOXOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
442 {"amomax.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_W
|MASK_AQRL
, MASK_AMOMAX_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
443 {"amomaxu.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_W
|MASK_AQRL
, MASK_AMOMAXU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
444 {"amomin.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_W
|MASK_AQRL
, MASK_AMOMIN_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
445 {"amominu.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_W
|MASK_AQRL
, MASK_AMOMINU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
446 {"lr.d", 64, INSN_CLASS_A
, "d,0(s)", MATCH_LR_D
, MASK_LR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
447 {"sc.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_D
, MASK_SC_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
448 {"amoadd.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_D
, MASK_AMOADD_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
449 {"amoswap.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_D
, MASK_AMOSWAP_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
450 {"amoand.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_D
, MASK_AMOAND_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
451 {"amoor.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_D
, MASK_AMOOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
452 {"amoxor.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_D
, MASK_AMOXOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
453 {"amomax.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_D
, MASK_AMOMAX_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
454 {"amomaxu.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_D
, MASK_AMOMAXU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
455 {"amomin.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_D
, MASK_AMOMIN_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
456 {"amominu.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_D
, MASK_AMOMINU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
457 {"lr.d.aq", 64, INSN_CLASS_A
, "d,0(s)", MATCH_LR_D
|MASK_AQ
, MASK_LR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
458 {"sc.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_D
|MASK_AQ
, MASK_SC_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
459 {"amoadd.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_D
|MASK_AQ
, MASK_AMOADD_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
460 {"amoswap.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_D
|MASK_AQ
, MASK_AMOSWAP_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
461 {"amoand.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_D
|MASK_AQ
, MASK_AMOAND_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
462 {"amoor.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_D
|MASK_AQ
, MASK_AMOOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
463 {"amoxor.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_D
|MASK_AQ
, MASK_AMOXOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
464 {"amomax.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_D
|MASK_AQ
, MASK_AMOMAX_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
465 {"amomaxu.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_D
|MASK_AQ
, MASK_AMOMAXU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
466 {"amomin.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_D
|MASK_AQ
, MASK_AMOMIN_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
467 {"amominu.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_D
|MASK_AQ
, MASK_AMOMINU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
468 {"lr.d.rl", 64, INSN_CLASS_A
, "d,0(s)", MATCH_LR_D
|MASK_RL
, MASK_LR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
469 {"sc.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_D
|MASK_RL
, MASK_SC_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
470 {"amoadd.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_D
|MASK_RL
, MASK_AMOADD_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
471 {"amoswap.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_D
|MASK_RL
, MASK_AMOSWAP_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
472 {"amoand.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_D
|MASK_RL
, MASK_AMOAND_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
473 {"amoor.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_D
|MASK_RL
, MASK_AMOOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
474 {"amoxor.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_D
|MASK_RL
, MASK_AMOXOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
475 {"amomax.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_D
|MASK_RL
, MASK_AMOMAX_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
476 {"amomaxu.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_D
|MASK_RL
, MASK_AMOMAXU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
477 {"amomin.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_D
|MASK_RL
, MASK_AMOMIN_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
478 {"amominu.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_D
|MASK_RL
, MASK_AMOMINU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
479 {"lr.d.aqrl", 64, INSN_CLASS_A
, "d,0(s)", MATCH_LR_D
|MASK_AQRL
, MASK_LR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
480 {"sc.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_D
|MASK_AQRL
, MASK_SC_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
481 {"amoadd.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_D
|MASK_AQRL
, MASK_AMOADD_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
482 {"amoswap.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_D
|MASK_AQRL
, MASK_AMOSWAP_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
483 {"amoand.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_D
|MASK_AQRL
, MASK_AMOAND_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
484 {"amoor.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_D
|MASK_AQRL
, MASK_AMOOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
485 {"amoxor.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_D
|MASK_AQRL
, MASK_AMOXOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
486 {"amomax.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_D
|MASK_AQRL
, MASK_AMOMAX_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
487 {"amomaxu.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_D
|MASK_AQRL
, MASK_AMOMAXU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
488 {"amomin.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_D
|MASK_AQRL
, MASK_AMOMIN_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
489 {"amominu.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_D
|MASK_AQRL
, MASK_AMOMINU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
491 /* Multiply/Divide instruction subset. */
492 {"mul", 0, INSN_CLASS_M
, "d,s,t", MATCH_MUL
, MASK_MUL
, match_opcode
, 0 },
493 {"mulh", 0, INSN_CLASS_M
, "d,s,t", MATCH_MULH
, MASK_MULH
, match_opcode
, 0 },
494 {"mulhu", 0, INSN_CLASS_M
, "d,s,t", MATCH_MULHU
, MASK_MULHU
, match_opcode
, 0 },
495 {"mulhsu", 0, INSN_CLASS_M
, "d,s,t", MATCH_MULHSU
, MASK_MULHSU
, match_opcode
, 0 },
496 {"div", 0, INSN_CLASS_M
, "d,s,t", MATCH_DIV
, MASK_DIV
, match_opcode
, 0 },
497 {"divu", 0, INSN_CLASS_M
, "d,s,t", MATCH_DIVU
, MASK_DIVU
, match_opcode
, 0 },
498 {"rem", 0, INSN_CLASS_M
, "d,s,t", MATCH_REM
, MASK_REM
, match_opcode
, 0 },
499 {"remu", 0, INSN_CLASS_M
, "d,s,t", MATCH_REMU
, MASK_REMU
, match_opcode
, 0 },
500 {"mulw", 64, INSN_CLASS_M
, "d,s,t", MATCH_MULW
, MASK_MULW
, match_opcode
, 0 },
501 {"divw", 64, INSN_CLASS_M
, "d,s,t", MATCH_DIVW
, MASK_DIVW
, match_opcode
, 0 },
502 {"divuw", 64, INSN_CLASS_M
, "d,s,t", MATCH_DIVUW
, MASK_DIVUW
, match_opcode
, 0 },
503 {"remw", 64, INSN_CLASS_M
, "d,s,t", MATCH_REMW
, MASK_REMW
, match_opcode
, 0 },
504 {"remuw", 64, INSN_CLASS_M
, "d,s,t", MATCH_REMUW
, MASK_REMUW
, match_opcode
, 0 },
506 /* Single-precision floating-point instruction subset. */
507 {"frcsr", 0, INSN_CLASS_F
, "d", MATCH_FRCSR
, MASK_FRCSR
, match_opcode
, INSN_ALIAS
},
508 {"frsr", 0, INSN_CLASS_F
, "d", MATCH_FRCSR
, MASK_FRCSR
, match_opcode
, INSN_ALIAS
},
509 {"fscsr", 0, INSN_CLASS_F
, "s", MATCH_FSCSR
, MASK_FSCSR
|MASK_RD
, match_opcode
, INSN_ALIAS
},
510 {"fscsr", 0, INSN_CLASS_F
, "d,s", MATCH_FSCSR
, MASK_FSCSR
, match_opcode
, INSN_ALIAS
},
511 {"fssr", 0, INSN_CLASS_F
, "s", MATCH_FSCSR
, MASK_FSCSR
|MASK_RD
, match_opcode
, INSN_ALIAS
},
512 {"fssr", 0, INSN_CLASS_F
, "d,s", MATCH_FSCSR
, MASK_FSCSR
, match_opcode
, INSN_ALIAS
},
513 {"frrm", 0, INSN_CLASS_F
, "d", MATCH_FRRM
, MASK_FRRM
, match_opcode
, INSN_ALIAS
},
514 {"fsrm", 0, INSN_CLASS_F
, "s", MATCH_FSRM
, MASK_FSRM
|MASK_RD
, match_opcode
, INSN_ALIAS
},
515 {"fsrm", 0, INSN_CLASS_F
, "d,s", MATCH_FSRM
, MASK_FSRM
, match_opcode
, INSN_ALIAS
},
516 {"fsrmi", 0, INSN_CLASS_F
, "d,Z", MATCH_FSRMI
, MASK_FSRMI
, match_opcode
, INSN_ALIAS
},
517 {"fsrmi", 0, INSN_CLASS_F
, "Z", MATCH_FSRMI
, MASK_FSRMI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
518 {"frflags", 0, INSN_CLASS_F
, "d", MATCH_FRFLAGS
, MASK_FRFLAGS
, match_opcode
, INSN_ALIAS
},
519 {"fsflags", 0, INSN_CLASS_F
, "s", MATCH_FSFLAGS
, MASK_FSFLAGS
|MASK_RD
, match_opcode
, INSN_ALIAS
},
520 {"fsflags", 0, INSN_CLASS_F
, "d,s", MATCH_FSFLAGS
, MASK_FSFLAGS
, match_opcode
, INSN_ALIAS
},
521 {"fsflagsi", 0, INSN_CLASS_F
, "d,Z", MATCH_FSFLAGSI
, MASK_FSFLAGSI
, match_opcode
, INSN_ALIAS
},
522 {"fsflagsi", 0, INSN_CLASS_F
, "Z", MATCH_FSFLAGSI
, MASK_FSFLAGSI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
523 {"flw", 32, INSN_CLASS_F_AND_C
, "D,Cm(Cc)", MATCH_C_FLWSP
, MASK_C_FLWSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
524 {"flw", 32, INSN_CLASS_F_AND_C
, "CD,Ck(Cs)", MATCH_C_FLW
, MASK_C_FLW
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
525 {"flw", 0, INSN_CLASS_F
, "D,o(s)", MATCH_FLW
, MASK_FLW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
526 {"flw", 0, INSN_CLASS_F
, "D,A,s", 0, (int) M_FLW
, match_never
, INSN_MACRO
},
527 {"fsw", 32, INSN_CLASS_F_AND_C
, "CT,CM(Cc)", MATCH_C_FSWSP
, MASK_C_FSWSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
528 {"fsw", 32, INSN_CLASS_F_AND_C
, "CD,Ck(Cs)", MATCH_C_FSW
, MASK_C_FSW
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
529 {"fsw", 0, INSN_CLASS_F
, "T,q(s)", MATCH_FSW
, MASK_FSW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
530 {"fsw", 0, INSN_CLASS_F
, "T,A,s", 0, (int) M_FSW
, match_never
, INSN_MACRO
},
531 {"fmv.x.w", 0, INSN_CLASS_F
, "d,S", MATCH_FMV_X_S
, MASK_FMV_X_S
, match_opcode
, 0 },
532 {"fmv.w.x", 0, INSN_CLASS_F
, "D,s", MATCH_FMV_S_X
, MASK_FMV_S_X
, match_opcode
, 0 },
533 {"fmv.x.s", 0, INSN_CLASS_F
, "d,S", MATCH_FMV_X_S
, MASK_FMV_X_S
, match_opcode
, 0 },
534 {"fmv.s.x", 0, INSN_CLASS_F
, "D,s", MATCH_FMV_S_X
, MASK_FMV_S_X
, match_opcode
, 0 },
535 {"fmv.s", 0, INSN_CLASS_F
, "D,U", MATCH_FSGNJ_S
, MASK_FSGNJ_S
, match_rs1_eq_rs2
, INSN_ALIAS
},
536 {"fneg.s", 0, INSN_CLASS_F
, "D,U", MATCH_FSGNJN_S
, MASK_FSGNJN_S
, match_rs1_eq_rs2
, INSN_ALIAS
},
537 {"fabs.s", 0, INSN_CLASS_F
, "D,U", MATCH_FSGNJX_S
, MASK_FSGNJX_S
, match_rs1_eq_rs2
, INSN_ALIAS
},
538 {"fsgnj.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FSGNJ_S
, MASK_FSGNJ_S
, match_opcode
, 0 },
539 {"fsgnjn.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FSGNJN_S
, MASK_FSGNJN_S
, match_opcode
, 0 },
540 {"fsgnjx.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FSGNJX_S
, MASK_FSGNJX_S
, match_opcode
, 0 },
541 {"fadd.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FADD_S
|MASK_RM
, MASK_FADD_S
|MASK_RM
, match_opcode
, 0 },
542 {"fadd.s", 0, INSN_CLASS_F
, "D,S,T,m", MATCH_FADD_S
, MASK_FADD_S
, match_opcode
, 0 },
543 {"fsub.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FSUB_S
|MASK_RM
, MASK_FSUB_S
|MASK_RM
, match_opcode
, 0 },
544 {"fsub.s", 0, INSN_CLASS_F
, "D,S,T,m", MATCH_FSUB_S
, MASK_FSUB_S
, match_opcode
, 0 },
545 {"fmul.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FMUL_S
|MASK_RM
, MASK_FMUL_S
|MASK_RM
, match_opcode
, 0 },
546 {"fmul.s", 0, INSN_CLASS_F
, "D,S,T,m", MATCH_FMUL_S
, MASK_FMUL_S
, match_opcode
, 0 },
547 {"fdiv.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FDIV_S
|MASK_RM
, MASK_FDIV_S
|MASK_RM
, match_opcode
, 0 },
548 {"fdiv.s", 0, INSN_CLASS_F
, "D,S,T,m", MATCH_FDIV_S
, MASK_FDIV_S
, match_opcode
, 0 },
549 {"fsqrt.s", 0, INSN_CLASS_F
, "D,S", MATCH_FSQRT_S
|MASK_RM
, MASK_FSQRT_S
|MASK_RM
, match_opcode
, 0 },
550 {"fsqrt.s", 0, INSN_CLASS_F
, "D,S,m", MATCH_FSQRT_S
, MASK_FSQRT_S
, match_opcode
, 0 },
551 {"fmin.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FMIN_S
, MASK_FMIN_S
, match_opcode
, 0 },
552 {"fmax.s", 0, INSN_CLASS_F
, "D,S,T", MATCH_FMAX_S
, MASK_FMAX_S
, match_opcode
, 0 },
553 {"fmadd.s", 0, INSN_CLASS_F
, "D,S,T,R", MATCH_FMADD_S
|MASK_RM
, MASK_FMADD_S
|MASK_RM
, match_opcode
, 0 },
554 {"fmadd.s", 0, INSN_CLASS_F
, "D,S,T,R,m", MATCH_FMADD_S
, MASK_FMADD_S
, match_opcode
, 0 },
555 {"fnmadd.s", 0, INSN_CLASS_F
, "D,S,T,R", MATCH_FNMADD_S
|MASK_RM
, MASK_FNMADD_S
|MASK_RM
, match_opcode
, 0 },
556 {"fnmadd.s", 0, INSN_CLASS_F
, "D,S,T,R,m", MATCH_FNMADD_S
, MASK_FNMADD_S
, match_opcode
, 0 },
557 {"fmsub.s", 0, INSN_CLASS_F
, "D,S,T,R", MATCH_FMSUB_S
|MASK_RM
, MASK_FMSUB_S
|MASK_RM
, match_opcode
, 0 },
558 {"fmsub.s", 0, INSN_CLASS_F
, "D,S,T,R,m", MATCH_FMSUB_S
, MASK_FMSUB_S
, match_opcode
, 0 },
559 {"fnmsub.s", 0, INSN_CLASS_F
, "D,S,T,R", MATCH_FNMSUB_S
|MASK_RM
, MASK_FNMSUB_S
|MASK_RM
, match_opcode
, 0 },
560 {"fnmsub.s", 0, INSN_CLASS_F
, "D,S,T,R,m", MATCH_FNMSUB_S
, MASK_FNMSUB_S
, match_opcode
, 0 },
561 {"fcvt.w.s", 0, INSN_CLASS_F
, "d,S", MATCH_FCVT_W_S
|MASK_RM
, MASK_FCVT_W_S
|MASK_RM
, match_opcode
, 0 },
562 {"fcvt.w.s", 0, INSN_CLASS_F
, "d,S,m", MATCH_FCVT_W_S
, MASK_FCVT_W_S
, match_opcode
, 0 },
563 {"fcvt.wu.s", 0, INSN_CLASS_F
, "d,S", MATCH_FCVT_WU_S
|MASK_RM
, MASK_FCVT_WU_S
|MASK_RM
, match_opcode
, 0 },
564 {"fcvt.wu.s", 0, INSN_CLASS_F
, "d,S,m", MATCH_FCVT_WU_S
, MASK_FCVT_WU_S
, match_opcode
, 0 },
565 {"fcvt.s.w", 0, INSN_CLASS_F
, "D,s", MATCH_FCVT_S_W
|MASK_RM
, MASK_FCVT_S_W
|MASK_RM
, match_opcode
, 0 },
566 {"fcvt.s.w", 0, INSN_CLASS_F
, "D,s,m", MATCH_FCVT_S_W
, MASK_FCVT_S_W
, match_opcode
, 0 },
567 {"fcvt.s.wu", 0, INSN_CLASS_F
, "D,s", MATCH_FCVT_S_WU
|MASK_RM
, MASK_FCVT_S_W
|MASK_RM
, match_opcode
, 0 },
568 {"fcvt.s.wu", 0, INSN_CLASS_F
, "D,s,m", MATCH_FCVT_S_WU
, MASK_FCVT_S_WU
, match_opcode
, 0 },
569 {"fclass.s", 0, INSN_CLASS_F
, "d,S", MATCH_FCLASS_S
, MASK_FCLASS_S
, match_opcode
, 0 },
570 {"feq.s", 0, INSN_CLASS_F
, "d,S,T", MATCH_FEQ_S
, MASK_FEQ_S
, match_opcode
, 0 },
571 {"flt.s", 0, INSN_CLASS_F
, "d,S,T", MATCH_FLT_S
, MASK_FLT_S
, match_opcode
, 0 },
572 {"fle.s", 0, INSN_CLASS_F
, "d,S,T", MATCH_FLE_S
, MASK_FLE_S
, match_opcode
, 0 },
573 {"fgt.s", 0, INSN_CLASS_F
, "d,T,S", MATCH_FLT_S
, MASK_FLT_S
, match_opcode
, 0 },
574 {"fge.s", 0, INSN_CLASS_F
, "d,T,S", MATCH_FLE_S
, MASK_FLE_S
, match_opcode
, 0 },
575 {"fcvt.l.s", 64, INSN_CLASS_F
, "d,S", MATCH_FCVT_L_S
|MASK_RM
, MASK_FCVT_L_S
|MASK_RM
, match_opcode
, 0 },
576 {"fcvt.l.s", 64, INSN_CLASS_F
, "d,S,m", MATCH_FCVT_L_S
, MASK_FCVT_L_S
, match_opcode
, 0 },
577 {"fcvt.lu.s", 64, INSN_CLASS_F
, "d,S", MATCH_FCVT_LU_S
|MASK_RM
, MASK_FCVT_LU_S
|MASK_RM
, match_opcode
, 0 },
578 {"fcvt.lu.s", 64, INSN_CLASS_F
, "d,S,m", MATCH_FCVT_LU_S
, MASK_FCVT_LU_S
, match_opcode
, 0 },
579 {"fcvt.s.l", 64, INSN_CLASS_F
, "D,s", MATCH_FCVT_S_L
|MASK_RM
, MASK_FCVT_S_L
|MASK_RM
, match_opcode
, 0 },
580 {"fcvt.s.l", 64, INSN_CLASS_F
, "D,s,m", MATCH_FCVT_S_L
, MASK_FCVT_S_L
, match_opcode
, 0 },
581 {"fcvt.s.lu", 64, INSN_CLASS_F
, "D,s", MATCH_FCVT_S_LU
|MASK_RM
, MASK_FCVT_S_L
|MASK_RM
, match_opcode
, 0 },
582 {"fcvt.s.lu", 64, INSN_CLASS_F
, "D,s,m", MATCH_FCVT_S_LU
, MASK_FCVT_S_LU
, match_opcode
, 0 },
584 /* Double-precision floating-point instruction subset. */
585 {"fld", 0, INSN_CLASS_D_AND_C
, "D,Cn(Cc)", MATCH_C_FLDSP
, MASK_C_FLDSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
586 {"fld", 0, INSN_CLASS_D_AND_C
, "CD,Cl(Cs)", MATCH_C_FLD
, MASK_C_FLD
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
587 {"fld", 0, INSN_CLASS_D
, "D,o(s)", MATCH_FLD
, MASK_FLD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
588 {"fld", 0, INSN_CLASS_D
, "D,A,s", 0, (int) M_FLD
, match_never
, INSN_MACRO
},
589 {"fsd", 0, INSN_CLASS_D_AND_C
, "CT,CN(Cc)", MATCH_C_FSDSP
, MASK_C_FSDSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
590 {"fsd", 0, INSN_CLASS_D_AND_C
, "CD,Cl(Cs)", MATCH_C_FSD
, MASK_C_FSD
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
591 {"fsd", 0, INSN_CLASS_D
, "T,q(s)", MATCH_FSD
, MASK_FSD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
592 {"fsd", 0, INSN_CLASS_D
, "T,A,s", 0, (int) M_FSD
, match_never
, INSN_MACRO
},
593 {"fmv.d", 0, INSN_CLASS_D
, "D,U", MATCH_FSGNJ_D
, MASK_FSGNJ_D
, match_rs1_eq_rs2
, INSN_ALIAS
},
594 {"fneg.d", 0, INSN_CLASS_D
, "D,U", MATCH_FSGNJN_D
, MASK_FSGNJN_D
, match_rs1_eq_rs2
, INSN_ALIAS
},
595 {"fabs.d", 0, INSN_CLASS_D
, "D,U", MATCH_FSGNJX_D
, MASK_FSGNJX_D
, match_rs1_eq_rs2
, INSN_ALIAS
},
596 {"fsgnj.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FSGNJ_D
, MASK_FSGNJ_D
, match_opcode
, 0 },
597 {"fsgnjn.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FSGNJN_D
, MASK_FSGNJN_D
, match_opcode
, 0 },
598 {"fsgnjx.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FSGNJX_D
, MASK_FSGNJX_D
, match_opcode
, 0 },
599 {"fadd.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FADD_D
|MASK_RM
, MASK_FADD_D
|MASK_RM
, match_opcode
, 0 },
600 {"fadd.d", 0, INSN_CLASS_D
, "D,S,T,m", MATCH_FADD_D
, MASK_FADD_D
, match_opcode
, 0 },
601 {"fsub.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FSUB_D
|MASK_RM
, MASK_FSUB_D
|MASK_RM
, match_opcode
, 0 },
602 {"fsub.d", 0, INSN_CLASS_D
, "D,S,T,m", MATCH_FSUB_D
, MASK_FSUB_D
, match_opcode
, 0 },
603 {"fmul.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FMUL_D
|MASK_RM
, MASK_FMUL_D
|MASK_RM
, match_opcode
, 0 },
604 {"fmul.d", 0, INSN_CLASS_D
, "D,S,T,m", MATCH_FMUL_D
, MASK_FMUL_D
, match_opcode
, 0 },
605 {"fdiv.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FDIV_D
|MASK_RM
, MASK_FDIV_D
|MASK_RM
, match_opcode
, 0 },
606 {"fdiv.d", 0, INSN_CLASS_D
, "D,S,T,m", MATCH_FDIV_D
, MASK_FDIV_D
, match_opcode
, 0 },
607 {"fsqrt.d", 0, INSN_CLASS_D
, "D,S", MATCH_FSQRT_D
|MASK_RM
, MASK_FSQRT_D
|MASK_RM
, match_opcode
, 0 },
608 {"fsqrt.d", 0, INSN_CLASS_D
, "D,S,m", MATCH_FSQRT_D
, MASK_FSQRT_D
, match_opcode
, 0 },
609 {"fmin.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FMIN_D
, MASK_FMIN_D
, match_opcode
, 0 },
610 {"fmax.d", 0, INSN_CLASS_D
, "D,S,T", MATCH_FMAX_D
, MASK_FMAX_D
, match_opcode
, 0 },
611 {"fmadd.d", 0, INSN_CLASS_D
, "D,S,T,R", MATCH_FMADD_D
|MASK_RM
, MASK_FMADD_D
|MASK_RM
, match_opcode
, 0 },
612 {"fmadd.d", 0, INSN_CLASS_D
, "D,S,T,R,m", MATCH_FMADD_D
, MASK_FMADD_D
, match_opcode
, 0 },
613 {"fnmadd.d", 0, INSN_CLASS_D
, "D,S,T,R", MATCH_FNMADD_D
|MASK_RM
, MASK_FNMADD_D
|MASK_RM
, match_opcode
, 0 },
614 {"fnmadd.d", 0, INSN_CLASS_D
, "D,S,T,R,m", MATCH_FNMADD_D
, MASK_FNMADD_D
, match_opcode
, 0 },
615 {"fmsub.d", 0, INSN_CLASS_D
, "D,S,T,R", MATCH_FMSUB_D
|MASK_RM
, MASK_FMSUB_D
|MASK_RM
, match_opcode
, 0 },
616 {"fmsub.d", 0, INSN_CLASS_D
, "D,S,T,R,m", MATCH_FMSUB_D
, MASK_FMSUB_D
, match_opcode
, 0 },
617 {"fnmsub.d", 0, INSN_CLASS_D
, "D,S,T,R", MATCH_FNMSUB_D
|MASK_RM
, MASK_FNMSUB_D
|MASK_RM
, match_opcode
, 0 },
618 {"fnmsub.d", 0, INSN_CLASS_D
, "D,S,T,R,m", MATCH_FNMSUB_D
, MASK_FNMSUB_D
, match_opcode
, 0 },
619 {"fcvt.w.d", 0, INSN_CLASS_D
, "d,S", MATCH_FCVT_W_D
|MASK_RM
, MASK_FCVT_W_D
|MASK_RM
, match_opcode
, 0 },
620 {"fcvt.w.d", 0, INSN_CLASS_D
, "d,S,m", MATCH_FCVT_W_D
, MASK_FCVT_W_D
, match_opcode
, 0 },
621 {"fcvt.wu.d", 0, INSN_CLASS_D
, "d,S", MATCH_FCVT_WU_D
|MASK_RM
, MASK_FCVT_WU_D
|MASK_RM
, match_opcode
, 0 },
622 {"fcvt.wu.d", 0, INSN_CLASS_D
, "d,S,m", MATCH_FCVT_WU_D
, MASK_FCVT_WU_D
, match_opcode
, 0 },
623 {"fcvt.d.w", 0, INSN_CLASS_D
, "D,s", MATCH_FCVT_D_W
, MASK_FCVT_D_W
|MASK_RM
, match_opcode
, 0 },
624 {"fcvt.d.wu", 0, INSN_CLASS_D
, "D,s", MATCH_FCVT_D_WU
, MASK_FCVT_D_WU
|MASK_RM
, match_opcode
, 0 },
625 {"fcvt.d.s", 0, INSN_CLASS_D
, "D,S", MATCH_FCVT_D_S
, MASK_FCVT_D_S
|MASK_RM
, match_opcode
, 0 },
626 {"fcvt.s.d", 0, INSN_CLASS_D
, "D,S", MATCH_FCVT_S_D
|MASK_RM
, MASK_FCVT_S_D
|MASK_RM
, match_opcode
, 0 },
627 {"fcvt.s.d", 0, INSN_CLASS_D
, "D,S,m", MATCH_FCVT_S_D
, MASK_FCVT_S_D
, match_opcode
, 0 },
628 {"fclass.d", 0, INSN_CLASS_D
, "d,S", MATCH_FCLASS_D
, MASK_FCLASS_D
, match_opcode
, 0 },
629 {"feq.d", 0, INSN_CLASS_D
, "d,S,T", MATCH_FEQ_D
, MASK_FEQ_D
, match_opcode
, 0 },
630 {"flt.d", 0, INSN_CLASS_D
, "d,S,T", MATCH_FLT_D
, MASK_FLT_D
, match_opcode
, 0 },
631 {"fle.d", 0, INSN_CLASS_D
, "d,S,T", MATCH_FLE_D
, MASK_FLE_D
, match_opcode
, 0 },
632 {"fgt.d", 0, INSN_CLASS_D
, "d,T,S", MATCH_FLT_D
, MASK_FLT_D
, match_opcode
, 0 },
633 {"fge.d", 0, INSN_CLASS_D
, "d,T,S", MATCH_FLE_D
, MASK_FLE_D
, match_opcode
, 0 },
634 {"fmv.x.d", 64, INSN_CLASS_D
, "d,S", MATCH_FMV_X_D
, MASK_FMV_X_D
, match_opcode
, 0 },
635 {"fmv.d.x", 64, INSN_CLASS_D
, "D,s", MATCH_FMV_D_X
, MASK_FMV_D_X
, match_opcode
, 0 },
636 {"fcvt.l.d", 64, INSN_CLASS_D
, "d,S", MATCH_FCVT_L_D
|MASK_RM
, MASK_FCVT_L_D
|MASK_RM
, match_opcode
, 0 },
637 {"fcvt.l.d", 64, INSN_CLASS_D
, "d,S,m", MATCH_FCVT_L_D
, MASK_FCVT_L_D
, match_opcode
, 0 },
638 {"fcvt.lu.d", 64, INSN_CLASS_D
, "d,S", MATCH_FCVT_LU_D
|MASK_RM
, MASK_FCVT_LU_D
|MASK_RM
, match_opcode
, 0 },
639 {"fcvt.lu.d", 64, INSN_CLASS_D
, "d,S,m", MATCH_FCVT_LU_D
, MASK_FCVT_LU_D
, match_opcode
, 0 },
640 {"fcvt.d.l", 64, INSN_CLASS_D
, "D,s", MATCH_FCVT_D_L
|MASK_RM
, MASK_FCVT_D_L
|MASK_RM
, match_opcode
, 0 },
641 {"fcvt.d.l", 64, INSN_CLASS_D
, "D,s,m", MATCH_FCVT_D_L
, MASK_FCVT_D_L
, match_opcode
, 0 },
642 {"fcvt.d.lu", 64, INSN_CLASS_D
, "D,s", MATCH_FCVT_D_LU
|MASK_RM
, MASK_FCVT_D_L
|MASK_RM
, match_opcode
, 0 },
643 {"fcvt.d.lu", 64, INSN_CLASS_D
, "D,s,m", MATCH_FCVT_D_LU
, MASK_FCVT_D_LU
, match_opcode
, 0 },
645 /* Quad-precision floating-point instruction subset. */
646 {"flq", 0, INSN_CLASS_Q
, "D,o(s)", MATCH_FLQ
, MASK_FLQ
, match_opcode
, INSN_DREF
|INSN_16_BYTE
},
647 {"flq", 0, INSN_CLASS_Q
, "D,A,s", 0, (int) M_FLQ
, match_never
, INSN_MACRO
},
648 {"fsq", 0, INSN_CLASS_Q
, "T,q(s)", MATCH_FSQ
, MASK_FSQ
, match_opcode
, INSN_DREF
|INSN_16_BYTE
},
649 {"fsq", 0, INSN_CLASS_Q
, "T,A,s", 0, (int) M_FSQ
, match_never
, INSN_MACRO
},
650 {"fmv.q", 0, INSN_CLASS_Q
, "D,U", MATCH_FSGNJ_Q
, MASK_FSGNJ_Q
, match_rs1_eq_rs2
, INSN_ALIAS
},
651 {"fneg.q", 0, INSN_CLASS_Q
, "D,U", MATCH_FSGNJN_Q
, MASK_FSGNJN_Q
, match_rs1_eq_rs2
, INSN_ALIAS
},
652 {"fabs.q", 0, INSN_CLASS_Q
, "D,U", MATCH_FSGNJX_Q
, MASK_FSGNJX_Q
, match_rs1_eq_rs2
, INSN_ALIAS
},
653 {"fsgnj.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FSGNJ_Q
, MASK_FSGNJ_Q
, match_opcode
, 0 },
654 {"fsgnjn.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FSGNJN_Q
, MASK_FSGNJN_Q
, match_opcode
, 0 },
655 {"fsgnjx.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FSGNJX_Q
, MASK_FSGNJX_Q
, match_opcode
, 0 },
656 {"fadd.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FADD_Q
|MASK_RM
, MASK_FADD_Q
|MASK_RM
, match_opcode
, 0 },
657 {"fadd.q", 0, INSN_CLASS_Q
, "D,S,T,m", MATCH_FADD_Q
, MASK_FADD_Q
, match_opcode
, 0 },
658 {"fsub.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FSUB_Q
|MASK_RM
, MASK_FSUB_Q
|MASK_RM
, match_opcode
, 0 },
659 {"fsub.q", 0, INSN_CLASS_Q
, "D,S,T,m", MATCH_FSUB_Q
, MASK_FSUB_Q
, match_opcode
, 0 },
660 {"fmul.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FMUL_Q
|MASK_RM
, MASK_FMUL_Q
|MASK_RM
, match_opcode
, 0 },
661 {"fmul.q", 0, INSN_CLASS_Q
, "D,S,T,m", MATCH_FMUL_Q
, MASK_FMUL_Q
, match_opcode
, 0 },
662 {"fdiv.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FDIV_Q
|MASK_RM
, MASK_FDIV_Q
|MASK_RM
, match_opcode
, 0 },
663 {"fdiv.q", 0, INSN_CLASS_Q
, "D,S,T,m", MATCH_FDIV_Q
, MASK_FDIV_Q
, match_opcode
, 0 },
664 {"fsqrt.q", 0, INSN_CLASS_Q
, "D,S", MATCH_FSQRT_Q
|MASK_RM
, MASK_FSQRT_Q
|MASK_RM
, match_opcode
, 0 },
665 {"fsqrt.q", 0, INSN_CLASS_Q
, "D,S,m", MATCH_FSQRT_Q
, MASK_FSQRT_Q
, match_opcode
, 0 },
666 {"fmin.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FMIN_Q
, MASK_FMIN_Q
, match_opcode
, 0 },
667 {"fmax.q", 0, INSN_CLASS_Q
, "D,S,T", MATCH_FMAX_Q
, MASK_FMAX_Q
, match_opcode
, 0 },
668 {"fmadd.q", 0, INSN_CLASS_Q
, "D,S,T,R", MATCH_FMADD_Q
|MASK_RM
, MASK_FMADD_Q
|MASK_RM
, match_opcode
, 0 },
669 {"fmadd.q", 0, INSN_CLASS_Q
, "D,S,T,R,m", MATCH_FMADD_Q
, MASK_FMADD_Q
, match_opcode
, 0 },
670 {"fnmadd.q", 0, INSN_CLASS_Q
, "D,S,T,R", MATCH_FNMADD_Q
|MASK_RM
, MASK_FNMADD_Q
|MASK_RM
, match_opcode
, 0 },
671 {"fnmadd.q", 0, INSN_CLASS_Q
, "D,S,T,R,m", MATCH_FNMADD_Q
, MASK_FNMADD_Q
, match_opcode
, 0 },
672 {"fmsub.q", 0, INSN_CLASS_Q
, "D,S,T,R", MATCH_FMSUB_Q
|MASK_RM
, MASK_FMSUB_Q
|MASK_RM
, match_opcode
, 0 },
673 {"fmsub.q", 0, INSN_CLASS_Q
, "D,S,T,R,m", MATCH_FMSUB_Q
, MASK_FMSUB_Q
, match_opcode
, 0 },
674 {"fnmsub.q", 0, INSN_CLASS_Q
, "D,S,T,R", MATCH_FNMSUB_Q
|MASK_RM
, MASK_FNMSUB_Q
|MASK_RM
, match_opcode
, 0 },
675 {"fnmsub.q", 0, INSN_CLASS_Q
, "D,S,T,R,m", MATCH_FNMSUB_Q
, MASK_FNMSUB_Q
, match_opcode
, 0 },
676 {"fcvt.w.q", 0, INSN_CLASS_Q
, "d,S", MATCH_FCVT_W_Q
|MASK_RM
, MASK_FCVT_W_Q
|MASK_RM
, match_opcode
, 0 },
677 {"fcvt.w.q", 0, INSN_CLASS_Q
, "d,S,m", MATCH_FCVT_W_Q
, MASK_FCVT_W_Q
, match_opcode
, 0 },
678 {"fcvt.wu.q", 0, INSN_CLASS_Q
, "d,S", MATCH_FCVT_WU_Q
|MASK_RM
, MASK_FCVT_WU_Q
|MASK_RM
, match_opcode
, 0 },
679 {"fcvt.wu.q", 0, INSN_CLASS_Q
, "d,S,m", MATCH_FCVT_WU_Q
, MASK_FCVT_WU_Q
, match_opcode
, 0 },
680 {"fcvt.q.w", 0, INSN_CLASS_Q
, "D,s", MATCH_FCVT_Q_W
, MASK_FCVT_Q_W
|MASK_RM
, match_opcode
, 0 },
681 {"fcvt.q.wu", 0, INSN_CLASS_Q
, "D,s", MATCH_FCVT_Q_WU
, MASK_FCVT_Q_WU
|MASK_RM
, match_opcode
, 0 },
682 {"fcvt.q.s", 0, INSN_CLASS_Q
, "D,S", MATCH_FCVT_Q_S
, MASK_FCVT_Q_S
|MASK_RM
, match_opcode
, 0 },
683 {"fcvt.q.d", 0, INSN_CLASS_Q
, "D,S", MATCH_FCVT_Q_D
, MASK_FCVT_Q_D
|MASK_RM
, match_opcode
, 0 },
684 {"fcvt.s.q", 0, INSN_CLASS_Q
, "D,S", MATCH_FCVT_S_Q
|MASK_RM
, MASK_FCVT_S_Q
|MASK_RM
, match_opcode
, 0 },
685 {"fcvt.s.q", 0, INSN_CLASS_Q
, "D,S,m", MATCH_FCVT_S_Q
, MASK_FCVT_S_Q
, match_opcode
, 0 },
686 {"fcvt.d.q", 0, INSN_CLASS_Q
, "D,S", MATCH_FCVT_D_Q
|MASK_RM
, MASK_FCVT_D_Q
|MASK_RM
, match_opcode
, 0 },
687 {"fcvt.d.q", 0, INSN_CLASS_Q
, "D,S,m", MATCH_FCVT_D_Q
, MASK_FCVT_D_Q
, match_opcode
, 0 },
688 {"fclass.q", 0, INSN_CLASS_Q
, "d,S", MATCH_FCLASS_Q
, MASK_FCLASS_Q
, match_opcode
, 0 },
689 {"feq.q", 0, INSN_CLASS_Q
, "d,S,T", MATCH_FEQ_Q
, MASK_FEQ_Q
, match_opcode
, 0 },
690 {"flt.q", 0, INSN_CLASS_Q
, "d,S,T", MATCH_FLT_Q
, MASK_FLT_Q
, match_opcode
, 0 },
691 {"fle.q", 0, INSN_CLASS_Q
, "d,S,T", MATCH_FLE_Q
, MASK_FLE_Q
, match_opcode
, 0 },
692 {"fgt.q", 0, INSN_CLASS_Q
, "d,T,S", MATCH_FLT_Q
, MASK_FLT_Q
, match_opcode
, 0 },
693 {"fge.q", 0, INSN_CLASS_Q
, "d,T,S", MATCH_FLE_Q
, MASK_FLE_Q
, match_opcode
, 0 },
694 {"fmv.x.q", 64, INSN_CLASS_Q
, "d,S", MATCH_FMV_X_Q
, MASK_FMV_X_Q
, match_opcode
, 0 },
695 {"fmv.q.x", 64, INSN_CLASS_Q
, "D,s", MATCH_FMV_Q_X
, MASK_FMV_Q_X
, match_opcode
, 0 },
696 {"fcvt.l.q", 64, INSN_CLASS_Q
, "d,S", MATCH_FCVT_L_Q
|MASK_RM
, MASK_FCVT_L_Q
|MASK_RM
, match_opcode
, 0 },
697 {"fcvt.l.q", 64, INSN_CLASS_Q
, "d,S,m", MATCH_FCVT_L_Q
, MASK_FCVT_L_Q
, match_opcode
, 0 },
698 {"fcvt.lu.q", 64, INSN_CLASS_Q
, "d,S", MATCH_FCVT_LU_Q
|MASK_RM
, MASK_FCVT_LU_Q
|MASK_RM
, match_opcode
, 0 },
699 {"fcvt.lu.q", 64, INSN_CLASS_Q
, "d,S,m", MATCH_FCVT_LU_Q
, MASK_FCVT_LU_Q
, match_opcode
, 0 },
700 {"fcvt.q.l", 64, INSN_CLASS_Q
, "D,s", MATCH_FCVT_Q_L
|MASK_RM
, MASK_FCVT_Q_L
|MASK_RM
, match_opcode
, 0 },
701 {"fcvt.q.l", 64, INSN_CLASS_Q
, "D,s,m", MATCH_FCVT_Q_L
, MASK_FCVT_Q_L
, match_opcode
, 0 },
702 {"fcvt.q.lu", 64, INSN_CLASS_Q
, "D,s", MATCH_FCVT_Q_LU
|MASK_RM
, MASK_FCVT_Q_L
|MASK_RM
, match_opcode
, 0 },
703 {"fcvt.q.lu", 64, INSN_CLASS_Q
, "D,s,m", MATCH_FCVT_Q_LU
, MASK_FCVT_Q_LU
, match_opcode
, 0 },
705 /* Compressed instructions. */
706 {"c.unimp", 0, INSN_CLASS_C
, "", 0, 0xffffU
, match_opcode
, 0 },
707 {"c.ebreak", 0, INSN_CLASS_C
, "", MATCH_C_EBREAK
, MASK_C_EBREAK
, match_opcode
, 0 },
708 {"c.jr", 0, INSN_CLASS_C
, "d", MATCH_C_JR
, MASK_C_JR
, match_rd_nonzero
, INSN_BRANCH
},
709 {"c.jalr", 0, INSN_CLASS_C
, "d", MATCH_C_JALR
, MASK_C_JALR
, match_rd_nonzero
, INSN_JSR
},
710 {"c.j", 0, INSN_CLASS_C
, "Ca", MATCH_C_J
, MASK_C_J
, match_opcode
, INSN_BRANCH
},
711 {"c.jal", 32, INSN_CLASS_C
, "Ca", MATCH_C_JAL
, MASK_C_JAL
, match_opcode
, INSN_JSR
},
712 {"c.beqz", 0, INSN_CLASS_C
, "Cs,Cp", MATCH_C_BEQZ
, MASK_C_BEQZ
, match_opcode
, INSN_CONDBRANCH
},
713 {"c.bnez", 0, INSN_CLASS_C
, "Cs,Cp", MATCH_C_BNEZ
, MASK_C_BNEZ
, match_opcode
, INSN_CONDBRANCH
},
714 {"c.lwsp", 0, INSN_CLASS_C
, "d,Cm(Cc)", MATCH_C_LWSP
, MASK_C_LWSP
, match_rd_nonzero
, 0 },
715 {"c.lw", 0, INSN_CLASS_C
, "Ct,Ck(Cs)", MATCH_C_LW
, MASK_C_LW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
716 {"c.swsp", 0, INSN_CLASS_C
, "CV,CM(Cc)", MATCH_C_SWSP
, MASK_C_SWSP
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
717 {"c.sw", 0, INSN_CLASS_C
, "Ct,Ck(Cs)", MATCH_C_SW
, MASK_C_SW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
718 {"c.nop", 0, INSN_CLASS_C
, "", MATCH_C_ADDI
, 0xffff, match_opcode
, INSN_ALIAS
},
719 {"c.nop", 0, INSN_CLASS_C
, "Cj", MATCH_C_ADDI
, MASK_C_ADDI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
720 {"c.mv", 0, INSN_CLASS_C
, "d,CV", MATCH_C_MV
, MASK_C_MV
, match_c_add_with_hint
, 0 },
721 {"c.lui", 0, INSN_CLASS_C
, "d,Cu", MATCH_C_LUI
, MASK_C_LUI
, match_c_lui_with_hint
, 0 },
722 {"c.li", 0, INSN_CLASS_C
, "d,Co", MATCH_C_LI
, MASK_C_LI
, match_opcode
, 0 },
723 {"c.addi4spn", 0, INSN_CLASS_C
, "Ct,Cc,CK", MATCH_C_ADDI4SPN
, MASK_C_ADDI4SPN
, match_c_addi4spn
, 0 },
724 {"c.addi16sp", 0, INSN_CLASS_C
, "Cc,CL", MATCH_C_ADDI16SP
, MASK_C_ADDI16SP
, match_c_addi16sp
, 0 },
725 {"c.addi", 0, INSN_CLASS_C
, "d,Co", MATCH_C_ADDI
, MASK_C_ADDI
, match_opcode
, 0 },
726 {"c.add", 0, INSN_CLASS_C
, "d,CV", MATCH_C_ADD
, MASK_C_ADD
, match_c_add_with_hint
, 0 },
727 {"c.sub", 0, INSN_CLASS_C
, "Cs,Ct", MATCH_C_SUB
, MASK_C_SUB
, match_opcode
, 0 },
728 {"c.and", 0, INSN_CLASS_C
, "Cs,Ct", MATCH_C_AND
, MASK_C_AND
, match_opcode
, 0 },
729 {"c.or", 0, INSN_CLASS_C
, "Cs,Ct", MATCH_C_OR
, MASK_C_OR
, match_opcode
, 0 },
730 {"c.xor", 0, INSN_CLASS_C
, "Cs,Ct", MATCH_C_XOR
, MASK_C_XOR
, match_opcode
, 0 },
731 {"c.slli", 0, INSN_CLASS_C
, "d,C>", MATCH_C_SLLI
, MASK_C_SLLI
, match_c_slli
, 0 },
732 {"c.srli", 0, INSN_CLASS_C
, "Cs,C>", MATCH_C_SRLI
, MASK_C_SRLI
, match_c_slli
, 0 },
733 {"c.srai", 0, INSN_CLASS_C
, "Cs,C>", MATCH_C_SRAI
, MASK_C_SRAI
, match_c_slli
, 0 },
734 {"c.slli64", 0, INSN_CLASS_C
, "d", MATCH_C_SLLI64
, MASK_C_SLLI64
, match_c_slli64
, 0 },
735 {"c.srli64", 0, INSN_CLASS_C
, "Cs", MATCH_C_SRLI64
, MASK_C_SRLI64
, match_c_slli64
, 0 },
736 {"c.srai64", 0, INSN_CLASS_C
, "Cs", MATCH_C_SRAI64
, MASK_C_SRAI64
, match_c_slli64
, 0 },
737 {"c.andi", 0, INSN_CLASS_C
, "Cs,Co", MATCH_C_ANDI
, MASK_C_ANDI
, match_opcode
, 0 },
738 {"c.addiw", 64, INSN_CLASS_C
, "d,Co", MATCH_C_ADDIW
, MASK_C_ADDIW
, match_rd_nonzero
, 0 },
739 {"c.addw", 64, INSN_CLASS_C
, "Cs,Ct", MATCH_C_ADDW
, MASK_C_ADDW
, match_opcode
, 0 },
740 {"c.subw", 64, INSN_CLASS_C
, "Cs,Ct", MATCH_C_SUBW
, MASK_C_SUBW
, match_opcode
, 0 },
741 {"c.ldsp", 64, INSN_CLASS_C
, "d,Cn(Cc)", MATCH_C_LDSP
, MASK_C_LDSP
, match_rd_nonzero
, INSN_DREF
|INSN_8_BYTE
},
742 {"c.ld", 64, INSN_CLASS_C
, "Ct,Cl(Cs)", MATCH_C_LD
, MASK_C_LD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
743 {"c.sdsp", 64, INSN_CLASS_C
, "CV,CN(Cc)", MATCH_C_SDSP
, MASK_C_SDSP
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
744 {"c.sd", 64, INSN_CLASS_C
, "Ct,Cl(Cs)", MATCH_C_SD
, MASK_C_SD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
745 {"c.fldsp", 0, INSN_CLASS_D_AND_C
, "D,Cn(Cc)", MATCH_C_FLDSP
, MASK_C_FLDSP
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
746 {"c.fld", 0, INSN_CLASS_D_AND_C
, "CD,Cl(Cs)", MATCH_C_FLD
, MASK_C_FLD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
747 {"c.fsdsp", 0, INSN_CLASS_D_AND_C
, "CT,CN(Cc)", MATCH_C_FSDSP
, MASK_C_FSDSP
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
748 {"c.fsd", 0, INSN_CLASS_D_AND_C
, "CD,Cl(Cs)", MATCH_C_FSD
, MASK_C_FSD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
749 {"c.flwsp", 32, INSN_CLASS_F_AND_C
, "D,Cm(Cc)", MATCH_C_FLWSP
, MASK_C_FLWSP
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
750 {"c.flw", 32, INSN_CLASS_F_AND_C
, "CD,Ck(Cs)", MATCH_C_FLW
, MASK_C_FLW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
751 {"c.fswsp", 32, INSN_CLASS_F_AND_C
, "CT,CM(Cc)", MATCH_C_FSWSP
, MASK_C_FSWSP
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
752 {"c.fsw", 32, INSN_CLASS_F_AND_C
, "CD,Ck(Cs)", MATCH_C_FSW
, MASK_C_FSW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
754 /* Supervisor instructions. */
755 {"csrr", 0, INSN_CLASS_ZICSR
,"d,E", MATCH_CSRRS
, MASK_CSRRS
|MASK_RS1
, match_opcode
, INSN_ALIAS
},
756 {"csrwi", 0, INSN_CLASS_ZICSR
,"E,Z", MATCH_CSRRWI
, MASK_CSRRWI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
757 {"csrsi", 0, INSN_CLASS_ZICSR
,"E,Z", MATCH_CSRRSI
, MASK_CSRRSI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
758 {"csrci", 0, INSN_CLASS_ZICSR
,"E,Z", MATCH_CSRRCI
, MASK_CSRRCI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
759 {"csrw", 0, INSN_CLASS_ZICSR
,"E,s", MATCH_CSRRW
, MASK_CSRRW
|MASK_RD
, match_opcode
, INSN_ALIAS
},
760 {"csrw", 0, INSN_CLASS_ZICSR
,"E,Z", MATCH_CSRRWI
, MASK_CSRRWI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
761 {"csrs", 0, INSN_CLASS_ZICSR
,"E,s", MATCH_CSRRS
, MASK_CSRRS
|MASK_RD
, match_opcode
, INSN_ALIAS
},
762 {"csrs", 0, INSN_CLASS_ZICSR
,"E,Z", MATCH_CSRRSI
, MASK_CSRRSI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
763 {"csrc", 0, INSN_CLASS_ZICSR
,"E,s", MATCH_CSRRC
, MASK_CSRRC
|MASK_RD
, match_opcode
, INSN_ALIAS
},
764 {"csrc", 0, INSN_CLASS_ZICSR
,"E,Z", MATCH_CSRRCI
, MASK_CSRRCI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
765 {"csrrwi", 0, INSN_CLASS_ZICSR
,"d,E,Z", MATCH_CSRRWI
, MASK_CSRRWI
, match_opcode
, 0 },
766 {"csrrsi", 0, INSN_CLASS_ZICSR
,"d,E,Z", MATCH_CSRRSI
, MASK_CSRRSI
, match_opcode
, 0 },
767 {"csrrci", 0, INSN_CLASS_ZICSR
,"d,E,Z", MATCH_CSRRCI
, MASK_CSRRCI
, match_opcode
, 0 },
768 {"csrrw", 0, INSN_CLASS_ZICSR
,"d,E,s", MATCH_CSRRW
, MASK_CSRRW
, match_opcode
, 0 },
769 {"csrrw", 0, INSN_CLASS_ZICSR
,"d,E,Z", MATCH_CSRRWI
, MASK_CSRRWI
, match_opcode
, INSN_ALIAS
},
770 {"csrrs", 0, INSN_CLASS_ZICSR
,"d,E,s", MATCH_CSRRS
, MASK_CSRRS
, match_opcode
, 0 },
771 {"csrrs", 0, INSN_CLASS_ZICSR
,"d,E,Z", MATCH_CSRRSI
, MASK_CSRRSI
, match_opcode
, INSN_ALIAS
},
772 {"csrrc", 0, INSN_CLASS_ZICSR
,"d,E,s", MATCH_CSRRC
, MASK_CSRRC
, match_opcode
, 0 },
773 {"csrrc", 0, INSN_CLASS_ZICSR
,"d,E,Z", MATCH_CSRRCI
, MASK_CSRRCI
, match_opcode
, INSN_ALIAS
},
774 {"uret", 0, INSN_CLASS_I
, "", MATCH_URET
, MASK_URET
, match_opcode
, 0 },
775 {"sret", 0, INSN_CLASS_I
, "", MATCH_SRET
, MASK_SRET
, match_opcode
, 0 },
776 {"hret", 0, INSN_CLASS_I
, "", MATCH_HRET
, MASK_HRET
, match_opcode
, 0 },
777 {"mret", 0, INSN_CLASS_I
, "", MATCH_MRET
, MASK_MRET
, match_opcode
, 0 },
778 {"dret", 0, INSN_CLASS_I
, "", MATCH_DRET
, MASK_DRET
, match_opcode
, 0 },
779 {"sfence.vm", 0, INSN_CLASS_I
, "", MATCH_SFENCE_VM
, MASK_SFENCE_VM
| MASK_RS1
, match_opcode
, 0 },
780 {"sfence.vm", 0, INSN_CLASS_I
, "s", MATCH_SFENCE_VM
, MASK_SFENCE_VM
, match_opcode
, 0 },
781 {"sfence.vma", 0, INSN_CLASS_I
, "", MATCH_SFENCE_VMA
, MASK_SFENCE_VMA
|MASK_RS1
|MASK_RS2
, match_opcode
, INSN_ALIAS
},
782 {"sfence.vma", 0, INSN_CLASS_I
, "s", MATCH_SFENCE_VMA
, MASK_SFENCE_VMA
|MASK_RS2
, match_opcode
, INSN_ALIAS
},
783 {"sfence.vma", 0, INSN_CLASS_I
, "s,t", MATCH_SFENCE_VMA
, MASK_SFENCE_VMA
, match_opcode
, 0 },
784 {"wfi", 0, INSN_CLASS_I
, "", MATCH_WFI
, MASK_WFI
, match_opcode
, 0 },
786 /* Terminate the list. */
787 {0, 0, INSN_CLASS_NONE
, 0, 0, 0, 0, 0}
790 /* Instruction format for .insn directive. */
791 const struct riscv_opcode riscv_insn_types
[] =
793 /* name, xlen, isa, operands, match, mask, match_func, pinfo. */
794 {"r", 0, INSN_CLASS_I
, "O4,F3,F7,d,s,t", 0, 0, match_opcode
, 0 },
795 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,D,s,t", 0, 0, match_opcode
, 0 },
796 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,d,S,t", 0, 0, match_opcode
, 0 },
797 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,D,S,t", 0, 0, match_opcode
, 0 },
798 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,d,s,T", 0, 0, match_opcode
, 0 },
799 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,D,s,T", 0, 0, match_opcode
, 0 },
800 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,d,S,T", 0, 0, match_opcode
, 0 },
801 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,D,S,T", 0, 0, match_opcode
, 0 },
802 {"r", 0, INSN_CLASS_I
, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode
, 0 },
803 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode
, 0 },
804 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode
, 0 },
805 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode
, 0 },
806 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode
, 0 },
807 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode
, 0 },
808 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode
, 0 },
809 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode
, 0 },
810 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode
, 0 },
811 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode
, 0 },
812 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode
, 0 },
813 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode
, 0 },
814 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode
, 0 },
815 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode
, 0 },
816 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode
, 0 },
817 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode
, 0 },
819 {"r4", 0, INSN_CLASS_I
, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode
, 0 },
820 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode
, 0 },
821 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode
, 0 },
822 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode
, 0 },
823 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode
, 0 },
824 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode
, 0 },
825 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode
, 0 },
826 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode
, 0 },
827 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode
, 0 },
828 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode
, 0 },
829 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode
, 0 },
830 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode
, 0 },
831 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode
, 0 },
832 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode
, 0 },
833 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode
, 0 },
834 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode
, 0 },
836 {"i", 0, INSN_CLASS_I
, "O4,F3,d,s,j", 0, 0, match_opcode
, 0 },
837 {"i", 0, INSN_CLASS_F
, "O4,F3,D,s,j", 0, 0, match_opcode
, 0 },
838 {"i", 0, INSN_CLASS_F
, "O4,F3,d,S,j", 0, 0, match_opcode
, 0 },
839 {"i", 0, INSN_CLASS_F
, "O4,F3,D,S,j", 0, 0, match_opcode
, 0 },
840 {"i", 0, INSN_CLASS_I
, "O4,F3,d,o(s)", 0, 0, match_opcode
, 0 },
841 {"i", 0, INSN_CLASS_F
, "O4,F3,D,o(s)", 0, 0, match_opcode
, 0 },
843 {"s", 0, INSN_CLASS_I
, "O4,F3,t,q(s)", 0, 0, match_opcode
, 0 },
844 {"s", 0, INSN_CLASS_F
, "O4,F3,T,q(s)", 0, 0, match_opcode
, 0 },
846 {"sb", 0, INSN_CLASS_I
, "O4,F3,s,t,p", 0, 0, match_opcode
, 0 },
847 {"sb", 0, INSN_CLASS_F
, "O4,F3,S,t,p", 0, 0, match_opcode
, 0 },
848 {"sb", 0, INSN_CLASS_F
, "O4,F3,s,T,p", 0, 0, match_opcode
, 0 },
849 {"sb", 0, INSN_CLASS_F
, "O4,F3,S,T,p", 0, 0, match_opcode
, 0 },
851 {"b", 0, INSN_CLASS_I
, "O4,F3,s,t,p", 0, 0, match_opcode
, 0 },
852 {"b", 0, INSN_CLASS_F
, "O4,F3,S,t,p", 0, 0, match_opcode
, 0 },
853 {"b", 0, INSN_CLASS_F
, "O4,F3,s,T,p", 0, 0, match_opcode
, 0 },
854 {"b", 0, INSN_CLASS_F
, "O4,F3,S,T,p", 0, 0, match_opcode
, 0 },
856 {"u", 0, INSN_CLASS_I
, "O4,d,u", 0, 0, match_opcode
, 0 },
857 {"u", 0, INSN_CLASS_F
, "O4,D,u", 0, 0, match_opcode
, 0 },
859 {"uj", 0, INSN_CLASS_I
, "O4,d,a", 0, 0, match_opcode
, 0 },
860 {"uj", 0, INSN_CLASS_F
, "O4,D,a", 0, 0, match_opcode
, 0 },
862 {"j", 0, INSN_CLASS_I
, "O4,d,a", 0, 0, match_opcode
, 0 },
863 {"j", 0, INSN_CLASS_F
, "O4,D,a", 0, 0, match_opcode
, 0 },
865 {"cr", 0, INSN_CLASS_C
, "O2,CF4,d,CV", 0, 0, match_opcode
, 0 },
866 {"cr", 0, INSN_CLASS_F_AND_C
, "O2,CF4,D,CV", 0, 0, match_opcode
, 0 },
867 {"cr", 0, INSN_CLASS_F_AND_C
, "O2,CF4,d,CT", 0, 0, match_opcode
, 0 },
868 {"cr", 0, INSN_CLASS_F_AND_C
, "O2,CF4,D,CT", 0, 0, match_opcode
, 0 },
870 {"ci", 0, INSN_CLASS_C
, "O2,CF3,d,Co", 0, 0, match_opcode
, 0 },
871 {"ci", 0, INSN_CLASS_F_AND_C
, "O2,CF3,D,Co", 0, 0, match_opcode
, 0 },
873 {"ciw", 0, INSN_CLASS_C
, "O2,CF3,Ct,C8", 0, 0, match_opcode
, 0 },
874 {"ciw", 0, INSN_CLASS_F_AND_C
, "O2,CF3,CD,C8", 0, 0, match_opcode
, 0 },
876 {"ca", 0, INSN_CLASS_C
, "O2,CF6,CF2,Cs,Ct", 0, 0, match_opcode
, 0 },
877 {"ca", 0, INSN_CLASS_F_AND_C
, "O2,CF6,CF2,CS,Ct", 0, 0, match_opcode
, 0 },
878 {"ca", 0, INSN_CLASS_F_AND_C
, "O2,CF6,CF2,Cs,CD", 0, 0, match_opcode
, 0 },
879 {"ca", 0, INSN_CLASS_F_AND_C
, "O2,CF6,CF2,CS,CD", 0, 0, match_opcode
, 0 },
881 {"cb", 0, INSN_CLASS_C
, "O2,CF3,Cs,Cp", 0, 0, match_opcode
, 0 },
882 {"cb", 0, INSN_CLASS_F_AND_C
, "O2,CF3,CS,Cp", 0, 0, match_opcode
, 0 },
884 {"cj", 0, INSN_CLASS_C
, "O2,CF3,Ca", 0, 0, match_opcode
, 0 },
886 /* Terminate the list. */
887 {0, 0, INSN_CLASS_NONE
, 0, 0, 0, 0, 0}
890 /* All standard extensions defined in all supported ISA spec. */
891 const struct riscv_ext_version riscv_ext_version_table
[] =
893 /* name, ISA spec, major version, minor version. */
894 {"e", ISA_SPEC_CLASS_20191213
, 1, 9},
895 {"e", ISA_SPEC_CLASS_20190608
, 1, 9},
896 {"e", ISA_SPEC_CLASS_2P2
, 1, 9},
898 {"i", ISA_SPEC_CLASS_20191213
, 2, 1},
899 {"i", ISA_SPEC_CLASS_20190608
, 2, 1},
900 {"i", ISA_SPEC_CLASS_2P2
, 2, 0},
902 {"m", ISA_SPEC_CLASS_20191213
, 2, 0},
903 {"m", ISA_SPEC_CLASS_20190608
, 2, 0},
904 {"m", ISA_SPEC_CLASS_2P2
, 2, 0},
906 {"a", ISA_SPEC_CLASS_20191213
, 2, 1},
907 {"a", ISA_SPEC_CLASS_20190608
, 2, 0},
908 {"a", ISA_SPEC_CLASS_2P2
, 2, 0},
910 {"f", ISA_SPEC_CLASS_20191213
, 2, 2},
911 {"f", ISA_SPEC_CLASS_20190608
, 2, 2},
912 {"f", ISA_SPEC_CLASS_2P2
, 2, 0},
914 {"d", ISA_SPEC_CLASS_20191213
, 2, 2},
915 {"d", ISA_SPEC_CLASS_20190608
, 2, 2},
916 {"d", ISA_SPEC_CLASS_2P2
, 2, 0},
918 {"q", ISA_SPEC_CLASS_20191213
, 2, 2},
919 {"q", ISA_SPEC_CLASS_20190608
, 2, 2},
920 {"q", ISA_SPEC_CLASS_2P2
, 2, 0},
922 {"c", ISA_SPEC_CLASS_20191213
, 2, 0},
923 {"c", ISA_SPEC_CLASS_20190608
, 2, 0},
924 {"c", ISA_SPEC_CLASS_2P2
, 2, 0},
926 {"zicsr", ISA_SPEC_CLASS_20191213
, 2, 0},
927 {"zicsr", ISA_SPEC_CLASS_20190608
, 2, 0},
929 {"zifencei", ISA_SPEC_CLASS_20191213
, 2, 0},
930 {"zifencei", ISA_SPEC_CLASS_20190608
, 2, 0},
932 {"zihintpause", ISA_SPEC_CLASS_DRAFT
, 1, 0},
934 /* Terminate the list. */
941 enum riscv_isa_spec_class
class;
944 /* List for all supported ISA spec versions. */
945 static const struct isa_spec_t isa_specs
[] =
947 {"2.2", ISA_SPEC_CLASS_2P2
},
948 {"20190608", ISA_SPEC_CLASS_20190608
},
949 {"20191213", ISA_SPEC_CLASS_20191213
},
951 /* Terminate the list. */
955 /* Get the corresponding ISA spec class by giving a ISA spec string. */
958 riscv_get_isa_spec_class (const char *s
,
959 enum riscv_isa_spec_class
*class)
961 const struct isa_spec_t
*version
;
966 for (version
= &isa_specs
[0]; version
->name
!= NULL
; ++version
)
967 if (strcmp (version
->name
, s
) == 0)
969 *class = version
->class;
973 /* Can not find the supported ISA spec. */