7 #include "opcode/rl78.h"
13 RL78_Opcode_Decoded * rl78;
14 int (* getbyte)(void *);
19 #define ID(x) rl78->id = RLO_##x, rl78->lineno = __LINE__
20 #define OP(n,t,r,a) (rl78->op[n].type = t, \
21 rl78->op[n].reg = r, \
22 rl78->op[n].addend = a )
23 #define OPX(n,t,r1,r2,a) \
24 (rl78->op[n].type = t, \
25 rl78->op[n].reg = r1, \
26 rl78->op[n].reg2 = r2, \
27 rl78->op[n].addend = a )
29 #define W() rl78->size = RL78_Word
31 #define AU ATTRIBUTE_UNUSED
32 #define GETBYTE() (ld->op [ld->rl78->n_bytes++] = ld->getbyte (ld->ptr))
33 #define B ((unsigned long) GETBYTE())
35 #define SYNTAX(x) rl78->syntax = x
37 #define UNSUPPORTED() \
38 rl78->syntax = "*unknown*"
40 #define RB(x) ((x)+RL78_Reg_X)
41 #define RW(x) ((x)+RL78_Reg_AX)
43 #define Fz rl78->flags = RL78_PSW_Z
44 #define Fza rl78->flags = RL78_PSW_Z | RL78_PSW_AC
45 #define Fzc rl78->flags = RL78_PSW_Z | RL78_PSW_CY
46 #define Fzac rl78->flags = RL78_PSW_Z | RL78_PSW_AC | RL78_PSW_CY
47 #define Fa rl78->flags = RL78_PSW_AC
48 #define Fc rl78->flags = RL78_PSW_CY
49 #define Fac rl78->flags = RL78_PSW_AC | RL78_PSW_CY
51 #define IMMU(bytes) immediate (bytes, 0, ld)
52 #define IMMS(bytes) immediate (bytes, 1, ld)
55 immediate (int bytes, int sign_extend, LocalData * ld)
63 if (sign_extend && (i & 0x80))
69 if (sign_extend && (i & 0x8000))
76 if (sign_extend && (i & 0x800000))
80 fprintf (stderr, "Programmer error: immediate() called with invalid byte count %d\n", bytes);
86 #define DC(c) OP (0, RL78_Operand_Immediate, 0, c)
87 #define DR(r) OP (0, RL78_Operand_Register, RL78_Reg_##r, 0)
88 #define DRB(r) OP (0, RL78_Operand_Register, RB(r), 0)
89 #define DRW(r) OP (0, RL78_Operand_Register, RW(r), 0)
90 #define DM(r,a) OP (0, RL78_Operand_Indirect, RL78_Reg_##r, a)
91 #define DM2(r1,r2,a) OPX (0, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a)
92 #define DE() rl78->op[0].use_es = 1
93 #define DB(b) set_bit (rl78->op, b)
94 #define DCY() DR(PSW); DB(0)
95 #define DPUSH() OP (0, RL78_Operand_PreDec, RL78_Reg_SP, 0);
97 #define SC(c) OP (1, RL78_Operand_Immediate, 0, c)
98 #define SR(r) OP (1, RL78_Operand_Register, RL78_Reg_##r, 0)
99 #define SRB(r) OP (1, RL78_Operand_Register, RB(r), 0)
100 #define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
101 #define SM(r,a) OP (1, RL78_Operand_Indirect, RL78_Reg_##r, a)
102 #define SM2(r1,r2,a) OPX (1, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a)
103 #define SE() rl78->op[1].use_es = 1
104 #define SB(b) set_bit (rl78->op+1, b)
105 #define SCY() SR(PSW); SB(0)
106 #define COND(c) rl78->op[1].condition = RL78_Condition_##c
107 #define SPOP() OP (1, RL78_Operand_PostInc, RL78_Reg_SP, 0);
110 set_bit (RL78_Opcode_Operand *op, int bit)
112 op->bit_number = bit;
114 case RL78_Operand_Register:
115 op->type = RL78_Operand_Bit;
117 case RL78_Operand_Indirect:
118 op->type = RL78_Operand_BitIndirect;
139 #define SADDR saddr (IMMU (1))
140 #define SFR sfr (IMMU (1))
143 rl78_decode_opcode (unsigned long pc AU,
144 RL78_Opcode_Decoded * rl78,
145 int (* getbyte)(void *),
148 LocalData lds, * ld = &lds;
149 unsigned char op_buf[20] = {0};
150 unsigned char *op = op_buf;
154 lds.getbyte = getbyte;
158 memset (rl78, 0, sizeof (*rl78));
162 /* Byte registers, not including A. */
163 /** VARY rba 000 010 011 100 101 110 111 */
164 /* Word registers, not including AX. */
165 /** VARY ra 01 10 11 */
167 /*----------------------------------------------------------------------*/
176 /*----------------------------------------------------------------------*/
178 /** 0000 1111 add %0, %e!1 */
179 ID(add); DR(A); SM(None, IMMU(2)); Fzac;
181 /** 0000 1101 add %0, %e1 */
182 ID(add); DR(A); SM(HL, 0); Fzac;
184 /** 0110 0001 1000 000 add %0, %e1 */
185 ID(add); DR(A); SM2(HL, B, 0); Fzac;
187 /** 0000 1110 add %0, %e1 */
188 ID(add); DR(A); SM(HL, IMMU(1)); Fzac;
190 /** 0110 0001 1000 0010 add %0, %e1 */
191 ID(add); DR(A); SM2(HL, C, 0); Fzac;
193 /** 0000 1100 add %0, #%1 */
194 ID(add); DR(A); SC(IMMU(1)); Fzac;
196 /** 0110 0001 0000 1rba add %0, %1 */
197 ID(add); DR(A); SRB(rba); Fzac;
199 /** 0000 1011 add %0, %1 */
200 ID(add); DR(A); SM(None, SADDR); Fzac;
202 /** 0110 0001 0000 0reg add %0, %1 */
203 ID(add); DRB(reg); SR(A); Fzac;
205 /** 0000 1010 add %0, #%1 */
206 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
208 /*----------------------------------------------------------------------*/
210 /** 0001 1111 addc %0, %e!1 */
211 ID(addc); DR(A); SM(None, IMMU(2)); Fzac;
213 /** 0001 1101 addc %0, %e1 */
214 ID(addc); DR(A); SM(HL, 0); Fzac;
216 /** 0110 0001 1001 0000 addc %0, %e1 */
217 ID(addc); DR(A); SM2(HL, B, 0); Fzac;
219 /** 0110 0001 1001 0010 addc %0, %e1 */
220 ID(addc); DR(A); SM2(HL, C, 0); Fzac;
222 /** 0001 1110 addc %0, %e1 */
223 ID(addc); DR(A); SM(HL, IMMU(1)); Fzac;
225 /** 0001 1100 addc %0, #%1 */
226 ID(addc); DR(A); SC(IMMU(1)); Fzac;
228 /** 0110 0001 0001 1rba addc %0, %1 */
229 ID(addc); DR(A); SRB(rba); Fzac;
231 /** 0110 0001 0001 0reg addc %0, %1 */
232 ID(addc); DRB(reg); SR(A); Fzac;
234 /** 0001 1011 addc %0, %1 */
235 ID(addc); DR(A); SM(None, SADDR); Fzac;
237 /** 0001 1010 addc %0, #%1 */
238 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
240 /*----------------------------------------------------------------------*/
242 /** 0000 0010 addw %0, %e!1 */
243 ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
245 /** 0110 0001 0000 1001 addw %0, %e1 */
246 ID(add); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
248 /** 0000 0100 addw %0, #%1 */
249 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
251 /** 0000 0rw1 addw %0, %1 */
252 ID(add); W(); DR(AX); SRW(rw); Fzac;
254 /** 0000 0110 addw %0, %1 */
255 ID(add); W(); DR(AX); SM(None, SADDR); Fzac;
257 /** 0001 0000 addw %0, #%1 */
258 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
260 /*----------------------------------------------------------------------*/
262 /** 0101 1111 and %0, %e!1 */
263 ID(and); DR(A); SM(None, IMMU(2)); Fz;
265 /** 0101 1101 and %0, %e1 */
266 ID(and); DR(A); SM(HL, 0); Fz;
268 /** 0110 0001 1101 0000 and %0, %e1 */
269 ID(and); DR(A); SM2(HL, B, 0); Fz;
271 /** 0101 1110 and %0, %e1 */
272 ID(and); DR(A); SM(HL, IMMU(1)); Fz;
274 /** 0110 0001 1101 0010 and %0, %e1 */
275 ID(and); DR(A); SM2(HL, C, 0); Fz;
277 /** 0101 1100 and %0, #%1 */
278 ID(and); DR(A); SC(IMMU(1)); Fz;
280 /** 0110 0001 0101 1rba and %0, %1 */
281 ID(and); DR(A); SRB(rba); Fz;
283 /** 0110 0001 0101 0reg and %0, %1 */
284 ID(and); DRB(reg); SR(A); Fz;
286 /** 0101 1011 and %0, %1 */
287 ID(and); DR(A); SM(None, SADDR); Fz;
289 /** 0101 1010 and %0, #%1 */
290 ID(and); DM(None, SADDR); SC(IMMU(1)); Fz;
292 /*----------------------------------------------------------------------*/
294 /** 0111 0001 1bit 0101 and1 cy, %e1 */
295 ID(and); DCY(); SM(HL, 0); SB(bit);
297 /** 0111 0001 1bit 1101 and1 cy, %1 */
298 ID(and); DCY(); SR(A); SB(bit);
300 /** 0111 0001 0bit 1101 and1 cy, %s1 */
301 ID(and); DCY(); SM(None, SFR); SB(bit);
303 /** 0111 0001 0bit 0101 and1 cy, %s1 */
304 ID(and); DCY(); SM(None, SADDR); SB(bit);
306 /*----------------------------------------------------------------------*/
308 /* Note that the branch insns need to be listed before the shift
309 ones, as "shift count of zero" means "branch insn" */
311 /** 1101 1100 bc $%a0 */
312 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(C);
314 /** 1101 1110 bnc $%a0 */
315 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NC);
317 /** 0110 0001 1100 0011 bh $%a0 */
318 ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(H);
320 /** 0110 0001 1101 0011 bnh $%a0 */
321 ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(NH);
323 /** 1101 1101 bz $%a0 */
324 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(Z);
326 /** 1101 1111 bnz $%a0 */
327 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NZ);
329 /*----------------------------------------------------------------------*/
331 /** 0011 0001 1bit 0101 bf %e1, $%a0 */
332 ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(F);
334 /** 0011 0001 0bit 0101 bf %1, $%a0 */
335 ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(F);
337 /** 0011 0001 1bit 0100 bf %s1, $%a0 */
338 ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
340 /** 0011 0001 0bit 0100 bf %s1, $%a0 */
341 ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
343 /*----------------------------------------------------------------------*/
345 /** 1110 1100 br !%!a0 */
346 ID(branch); DC(IMMU(3));
348 /** 1110 1101 br %!a0 */
349 ID(branch); DC(IMMU(2));
351 /** 1110 1110 br $%!a0 */
352 ID(branch); DC(pc+IMMS(2)+3);
354 /** 1110 1111 br $%a0 */
355 ID(branch); DC(pc+IMMS(1)+2);
357 /** 0110 0001 1100 1011 br ax */
360 /*----------------------------------------------------------------------*/
362 /** 1111 1111 brk1 */
365 /** 0110 0001 1100 1100 brk */
368 /*----------------------------------------------------------------------*/
370 /** 0011 0001 1bit 0011 bt %e1, $%a0 */
371 ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
373 /** 0011 0001 0bit 0011 bt %1, $%a0 */
374 ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T);
376 /** 0011 0001 1bit 0010 bt %s1, $%a0 */
377 ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
379 /** 0011 0001 0bit 0010 bt %s1, $%a0 */
380 ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
382 /*----------------------------------------------------------------------*/
384 /** 0011 0001 1bit 0001 btclr %e1, $%a0 */
385 ID(branch_cond_clear); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
387 /** 0011 0001 0bit 0001 btclr %1, $%a0 */
388 ID(branch_cond_clear); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T);
390 /** 0011 0001 1bit 0000 btclr %s1, $%a0 */
391 ID(branch_cond_clear); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
393 /** 0011 0001 0bit 0000 btclr %s1, $%a0 */
394 ID(branch_cond_clear); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
396 /*----------------------------------------------------------------------*/
398 /** 1111 1100 call !%!a0 */
399 ID(call); DC(IMMU(3));
401 /** 1111 1101 call %!a0 */
402 ID(call); DC(IMMU(2));
404 /** 1111 1110 call $%!a0 */
405 ID(call); DC(pc+IMMS(2)+3);
407 /** 0110 0001 11rg 1010 call %0 */
410 /** 0110 0001 1nnn 01mm callt [%x0] */
411 ID(call); DM(None, 0x80 + mm*16 + nnn*2);
413 /*----------------------------------------------------------------------*/
415 /** 0111 0001 0bit 1000 clr1 %e!0 */
416 ID(mov); DM(None, IMMU(2)); DB(bit); SC(0);
418 /** 0111 0001 1bit 0011 clr1 %e0 */
419 ID(mov); DM(HL, 0); DB(bit); SC(0);
421 /** 0111 0001 1bit 1011 clr1 %0 */
422 ID(mov); DR(A); DB(bit); SC(0);
424 /** 0111 0001 1000 1000 clr1 cy */
425 ID(mov); DCY(); SC(0);
427 /** 0111 0001 0bit 1011 clr1 %s0 */
429 ID(mov); DM(None, op0); DB(bit); SC(0);
430 if (op0 == RL78_SFR_PSW && bit == 7)
433 /** 0111 0001 0bit 0011 clr1 %0 */
434 ID(mov); DM(None, SADDR); DB(bit); SC(0);
436 /*----------------------------------------------------------------------*/
438 /** 1111 0101 clrb %e!0 */
439 ID(mov); DM(None, IMMU(2)); SC(0);
441 /** 1111 00rg clrb %0 */
442 ID(mov); DRB(rg); SC(0);
444 /** 1111 0100 clrb %0 */
445 ID(mov); DM(None, SADDR); SC(0);
447 /*----------------------------------------------------------------------*/
449 /** 1111 0110 clrw %0 */
450 ID(mov); DR(AX); SC(0);
452 /** 1111 0111 clrw %0 */
453 ID(mov); DR(BC); SC(0);
455 /*----------------------------------------------------------------------*/
457 /** 0100 0000 cmp %e!0, #%1 */
458 ID(cmp); DM(None, IMMU(2)); SC(IMMU(1)); Fzac;
460 /** 0100 1010 cmp %0, #%1 */
461 ID(cmp); DM(None, SADDR); SC(IMMU(1)); Fzac;
463 /** 0100 1111 cmp %0, %e!1 */
464 ID(cmp); DR(A); SM(None, IMMU(2)); Fzac;
466 /** 0100 1101 cmp %0, %e1 */
467 ID(cmp); DR(A); SM(HL, 0); Fzac;
469 /** 0110 0001 1100 0000 cmp %0, %e1 */
470 ID(cmp); DR(A); SM2(HL, B, 0); Fzac;
472 /** 0110 0001 1100 0010 cmp %0, %e1 */
473 ID(cmp); DR(A); SM2(HL, C, 0); Fzac;
475 /** 0100 1110 cmp %0, %e1 */
476 ID(cmp); DR(A); SM(HL, IMMU(1)); Fzac;
478 /** 0100 1100 cmp %0, #%1 */
479 ID(cmp); DR(A); SC(IMMU(1)); Fzac;
481 /** 0110 0001 0100 1rba cmp %0, %1 */
482 ID(cmp); DR(A); SRB(rba); Fzac;
484 /** 0110 0001 0100 0reg cmp %0, %1 */
485 ID(cmp); DRB(reg); SR(A); Fzac;
487 /** 0100 1011 cmp %0, %1 */
488 ID(cmp); DR(A); SM(None, SADDR); Fzac;
490 /*----------------------------------------------------------------------*/
492 /** 1101 0101 cmp0 %e!0 */
493 ID(cmp); DM(None, IMMU(2)); SC(0); Fzac;
495 /** 1101 00rg cmp0 %0 */
496 ID(cmp); DRB(rg); SC(0); Fzac;
498 /** 1101 0100 cmp0 %0 */
499 ID(cmp); DM(None, SADDR); SC(0); Fzac;
501 /*----------------------------------------------------------------------*/
503 /** 0110 0001 1101 1110 cmps %0, %e1 */
504 ID(cmp); DR(X); SM(HL, IMMU(1)); Fzac;
506 /*----------------------------------------------------------------------*/
508 /** 0100 0010 cmpw %0, %e!1 */
509 ID(cmp); W(); DR(AX); SM(None, IMMU(2)); Fzac;
511 /** 0110 0001 0100 1001 cmpw %0, %e1 */
512 ID(cmp); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
514 /** 0100 0100 cmpw %0, #%1 */
515 ID(cmp); W(); DR(AX); SC(IMMU(2)); Fzac;
517 /** 0100 0ra1 cmpw %0, %1 */
518 ID(cmp); W(); DR(AX); SRW(ra); Fzac;
520 /** 0100 0110 cmpw %0, %1 */
521 ID(cmp); W(); DR(AX); SM(None, SADDR); Fzac;
523 /*----------------------------------------------------------------------*/
525 /** 1011 0000 dec %e!0 */
526 ID(sub); DM(None, IMMU(2)); SC(1); Fza;
528 /** 0110 0001 0110 1001 dec %e0 */
529 ID(sub); DM(HL, IMMU(1)); SC(1); Fza;
531 /** 1001 0reg dec %0 */
532 ID(sub); DRB(reg); SC(1); Fza;
534 /** 1011 0100 dec %0 */
535 ID(sub); DM(None, SADDR); SC(1); Fza;
537 /*----------------------------------------------------------------------*/
539 /** 1011 0010 decw %e!0 */
540 ID(sub); W(); DM(None, IMMU(2)); SC(1);
542 /** 0110 0001 1000 1001 decw %e0 */
543 ID(sub); W(); DM(HL, IMMU(1)); SC(1);
545 /** 1011 0rg1 decw %0 */
546 ID(sub); W(); DRW(rg); SC(1);
548 /** 1011 0110 decw %0 */
549 ID(sub); W(); DM(None, SADDR); SC(1);
551 /*----------------------------------------------------------------------*/
553 /** 0110 0001 1110 1101 halt */
556 /*----------------------------------------------------------------------*/
558 /** 1010 0000 inc %e!0 */
559 ID(add); DM(None, IMMU(2)); SC(1); Fza;
561 /** 0110 0001 0101 1001 inc %e0 */
562 ID(add); DM(HL, IMMU(1)); SC(1); Fza;
564 /** 1000 0reg inc %0 */
565 ID(add); DRB(reg); SC(1); Fza;
567 /** 1010 0100 inc %0 */
568 ID(add); DM(None, SADDR); SC(1); Fza;
570 /*----------------------------------------------------------------------*/
572 /** 1010 0010 incw %e!0 */
573 ID(add); W(); DM(None, IMMU(2)); SC(1);
575 /** 0110 0001 0111 1001 incw %e0 */
576 ID(add); W(); DM(HL, IMMU(1)); SC(1);
578 /** 1010 0rg1 incw %0 */
579 ID(add); W(); DRW(rg); SC(1);
581 /** 1010 0110 incw %0 */
582 ID(add); W(); DM(None, SADDR); SC(1);
584 /*----------------------------------------------------------------------*/
586 /** 1100 1111 mov %e!0, #%1 */
587 ID(mov); DM(None, IMMU(2)); SC(IMMU(1));
589 /** 1001 1111 mov %e!0, %1 */
590 ID(mov); DM(None, IMMU(2)); SR(A);
592 /** 1001 1001 mov %e0,%1 */
593 ID(mov); DM(DE, 0); SR(A);
595 /** 1100 1010 mov %e0, #%1 */
596 ID(mov); DM(DE, IMMU(1)); SC(IMMU(1));
598 /** 1001 1010 mov %e0, %1 */
599 ID(mov); DM(DE, IMMU(1)); SR(A);
601 /** 1001 1011 mov %e0,%1 */
602 ID(mov); DM(HL, 0); SR(A);
604 /** 0110 0001 1101 1001 mov %e0, %1 */
605 ID(mov); DM2(HL, B, 0); SR(A);
607 /** 1100 1100 mov %e0, #%1 */
608 ID(mov); DM(HL, IMMU(1)); SC(IMMU(1));
610 /** 1001 1100 mov %e0, %1 */
611 ID(mov); DM(HL, IMMU(1)); SR(A);
613 /** 0110 0001 1111 1001 mov %e0, %1 */
614 ID(mov); DM2(HL, C, 0); SR(A);
616 /** 1100 1000 mov %0, #%1 */
617 ID(mov); DM(SP, IMMU(1)); SC(IMMU(1));
619 /** 1001 1000 mov %0, %1 */
620 ID(mov); DM(SP, IMMU(1)); SR(A);
622 /** 1000 1111 mov %0, %e!1 */
623 ID(mov); DR(A); SM(None, IMMU(2));
625 /** 1000 1001 mov %0, %e1 */
626 ID(mov); DR(A); SM(DE, 0);
628 /** 1000 1010 mov %0, %e1 */
629 ID(mov); DR(A); SM(DE, IMMU(1));
631 /** 1000 1011 mov %0, %e1 */
632 ID(mov); DR(A); SM(HL, 0);
634 /** 1000 1100 mov %0, %e1 */
635 ID(mov); DR(A); SM(HL, IMMU(1));
637 /** 0110 0001 1100 1001 mov %0, %e1 */
638 ID(mov); DR(A); SM2(HL, B, 0);
640 /** 0110 0001 1110 1001 mov %0, %e1 */
641 ID(mov); DR(A); SM2(HL, C, 0);
643 /** 1000 1000 mov %0, %e1 */
644 ID(mov); DR(A); SM(SP, IMMU(1));
646 /** 0101 0reg mov %0, #%1 */
647 ID(mov); DRB(reg); SC(IMMU(1));
649 /** 0110 0rba mov %0, %1 */
650 ID(mov); DR(A); SRB(rba);
652 /** 1000 1110 1111 1101 mov %0, %1 */
653 ID(mov); DR(A); SR(ES);
655 /** 0000 1001 mov %0, %e1 */
656 ID(mov); DR(A); SM(B, IMMU(2));
658 /** 0100 1001 mov %0, %e1 */
659 ID(mov); DR(A); SM(BC, IMMU(2));
661 /** 0010 1001 mov %0, %e1 */
662 ID(mov); DR(A); SM(C, IMMU(2));
664 /** 1000 1110 mov %0, %s1 */
665 ID(mov); DR(A); SM(None, SFR);
667 /** 1000 1101 mov %0, %1 */
668 ID(mov); DR(A); SM(None, SADDR);
670 /** 1110 1001 mov %0, %e!1 */
671 ID(mov); DR(B); SM(None, IMMU(2));
673 /** 0111 0rba mov %0, %1 */
674 ID(mov); DRB(rba); SR(A);
676 /** 1110 1000 mov %0, %1 */
677 ID(mov); DR(B); SM(None, SADDR);
679 /** 1111 1001 mov %0, %e!1 */
680 ID(mov); DR(C); SM(None, IMMU(2));
682 /** 1111 1000 mov %0, %1 */
683 ID(mov); DR(C); SM(None, SADDR);
685 /** 1101 1001 mov %0, %e!1 */
686 ID(mov); DR(X); SM(None, IMMU(2));
688 /** 1101 1000 mov %0, %1 */
689 ID(mov); DR(X); SM(None, SADDR);
691 /** 1001 1110 1111 1100 mov %0, %1 */
692 ID(mov); DR(CS); SR(A);
694 /** 0100 0001 mov %0, #%1 */
695 ID(mov); DR(ES); SC(IMMU(1));
697 /** 1001 1110 1111 1101 mov %0, %1 */
698 ID(mov); DR(ES); SR(A);
700 /** 0110 0001 1011 1000 mov %0, %1 */
701 ID(mov); DR(ES); SM(None, SADDR);
703 /** 0001 1001 mov %e0, #%1 */
704 ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
706 /** 0001 1000 mov %e0, %1 */
707 ID(mov); DM(B, IMMU(2)); SR(A);
709 /** 0011 1001 mov %e0, #%1 */
710 ID(mov); DM(BC, IMMU(2)); SC(IMMU(1));
712 /** 0100 1000 mov %e0, %1 */
713 ID(mov); DM(BC, IMMU(2)); SR(A);
715 /** 0011 1000 mov %e0, #%1 */
716 ID(mov); DM(C, IMMU(2)); SC(IMMU(1));
718 /** 0010 1000 mov %e0, %1 */
719 ID(mov); DM(C, IMMU(2)); SR(A);
721 /** 1100 1101 mov %0, #%1 */
722 ID(mov); DM(None, SADDR); SC(IMMU(1));
724 /** 1001 1101 mov %0, %1 */
725 ID(mov); DM(None, SADDR); SR(A);
727 /** 1100 1110 mov %s0, #%1 */
730 ID(mov); DM(None, op0); SC(op1);
735 rl78->syntax = "mulhu"; ID(mulhu);
738 rl78->syntax = "mulh"; ID(mulh);
741 rl78->syntax = "divhu"; ID(divhu);
744 rl78->syntax = "divwu"; ID(divwu);
747 rl78->syntax = "machu"; ID(machu);
750 rl78->syntax = "mach"; ID(mach);
754 /** 1001 1110 mov %0, %1 */
755 ID(mov); DM(None, SFR); SR(A);
757 /*----------------------------------------------------------------------*/
759 /** 0111 0001 1bit 0001 mov1 %e0, cy */
760 ID(mov); DM(HL, 0); DB(bit); SCY();
762 /** 0111 0001 1bit 1001 mov1 %e0, cy */
763 ID(mov); DR(A); DB(bit); SCY();
765 /** 0111 0001 1bit 0100 mov1 cy, %e1 */
766 ID(mov); DCY(); SM(HL, 0); SB(bit);
768 /** 0111 0001 1bit 1100 mov1 cy, %e1 */
769 ID(mov); DCY(); SR(A); SB(bit);
771 /** 0111 0001 0bit 0100 mov1 cy, %1 */
772 ID(mov); DCY(); SM(None, SADDR); SB(bit);
774 /** 0111 0001 0bit 1100 mov1 cy, %s1 */
775 ID(mov); DCY(); SM(None, SFR); SB(bit);
777 /** 0111 0001 0bit 0001 mov1 %0, cy */
778 ID(mov); DM(None, SADDR); DB(bit); SCY();
780 /** 0111 0001 0bit 1001 mov1 %s0, cy */
781 ID(mov); DM(None, SFR); DB(bit); SCY();
783 /*----------------------------------------------------------------------*/
785 /** 0110 0001 1100 1110 movs %e0, %1 */
786 ID(mov); DM(HL, IMMU(1)); SR(X); Fzc;
788 /*----------------------------------------------------------------------*/
790 /** 1011 1111 movw %e!0, %1 */
791 ID(mov); W(); DM(None, IMMU(2)); SR(AX);
793 /** 1011 1001 movw %e0, %1 */
794 ID(mov); W(); DM(DE, 0); SR(AX);
796 /** 1011 1010 movw %e0, %1 */
797 ID(mov); W(); DM(DE, IMMU(1)); SR(AX);
799 /** 1011 1011 movw %e0, %1 */
800 ID(mov); W(); DM(HL, 0); SR(AX);
802 /** 1011 1100 movw %e0, %1 */
803 ID(mov); W(); DM(HL, IMMU(1)); SR(AX);
805 /** 1011 1000 movw %0, %1 */
806 ID(mov); W(); DM(SP, IMMU(1)); SR(AX);
808 /** 1010 1111 movw %0, %e!1 */
809 ID(mov); W(); DR(AX); SM(None, IMMU(2));
812 /** 1010 1001 movw %0, %e1 */
813 ID(mov); W(); DR(AX); SM(DE, 0);
815 /** 1010 1010 movw %0, %e1 */
816 ID(mov); W(); DR(AX); SM(DE, IMMU(1));
818 /** 1010 1011 movw %0, %e1 */
819 ID(mov); W(); DR(AX); SM(HL, 0);
821 /** 1010 1100 movw %0, %e1 */
822 ID(mov); W(); DR(AX); SM(HL, IMMU(1));
824 /** 1010 1000 movw %0, %1 */
825 ID(mov); W(); DR(AX); SM(SP, IMMU(1));
827 /** 0011 0rg0 movw %0, #%1 */
828 ID(mov); W(); DRW(rg); SC(IMMU(2));
830 /** 0001 0ra1 movw %0, %1 */
831 ID(mov); W(); DR(AX); SRW(ra);
833 /** 0001 0ra0 movw %0, %1 */
834 ID(mov); W(); DRW(ra); SR(AX);
836 /** 0101 1001 movw %0, %e1 */
837 ID(mov); W(); DR(AX); SM(B, IMMU(2));
839 /** 0110 1001 movw %0, %e1 */
840 ID(mov); W(); DR(AX); SM(C, IMMU(2));
842 /** 0111 1001 movw %0, %e1 */
843 ID(mov); W(); DR(AX); SM(BC, IMMU(2));
845 /** 0101 1000 movw %e0, %1 */
846 ID(mov); W(); DM(B, IMMU(2)); SR(AX);
848 /** 0110 1000 movw %e0, %1 */
849 ID(mov); W(); DM(C, IMMU(2)); SR(AX);
851 /** 0111 1000 movw %e0, %1 */
852 ID(mov); W(); DM(BC, IMMU(2)); SR(AX);
854 /** 1010 1101 movw %0, %1 */
855 ID(mov); W(); DR(AX); SM(None, SADDR);
857 /** 1010 1110 movw %0, %s1 */
858 ID(mov); W(); DR(AX); SM(None, SFR);
860 /** 11ra 1011 movw %0, %e!1 */
861 ID(mov); W(); DRW(ra); SM(None, IMMU(2));
863 /** 11ra 1010 movw %0, %1 */
864 ID(mov); W(); DRW(ra); SM(None, SADDR);
866 /** 1100 1001 movw %0, #%1 */
867 ID(mov); W(); DM(None, SADDR); SC(IMMU(2));
869 /** 1011 1101 movw %0, %1 */
870 ID(mov); W(); DM(None, SADDR); SR(AX);
872 /** 1100 1011 movw %0, #%1 */
873 ID(mov); W(); DM(None, SFR); SC(IMMU(2));
875 /** 1011 1110 movw %0, %1 */
876 ID(mov); W(); DM(None, SFR); SR(AX);
878 /*----------------------------------------------------------------------*/
880 /** 1101 0110 mulu x */
883 /*----------------------------------------------------------------------*/
888 /*----------------------------------------------------------------------*/
890 /** 0111 0001 1100 0000 not1 cy */
891 ID(xor); DCY(); SC(1);
893 /*----------------------------------------------------------------------*/
895 /** 1110 0101 oneb %e!0 */
896 ID(mov); DM(None, IMMU(2)); SC(1);
898 /** 1110 00rg oneb %0 */
899 ID(mov); DRB(rg); SC(1);
901 /** 1110 0100 oneb %0 */
902 ID(mov); DM(None, SADDR); SC(1);
904 /*----------------------------------------------------------------------*/
906 /** 1110 0110 onew %0 */
907 ID(mov); DR(AX); SC(1);
909 /** 1110 0111 onew %0 */
910 ID(mov); DR(BC); SC(1);
912 /*----------------------------------------------------------------------*/
914 /** 0110 1111 or %0, %e!1 */
915 ID(or); DR(A); SM(None, IMMU(2)); Fz;
917 /** 0110 1101 or %0, %e1 */
918 ID(or); DR(A); SM(HL, 0); Fz;
920 /** 0110 0001 1110 0000 or %0, %e1 */
921 ID(or); DR(A); SM2(HL, B, 0); Fz;
923 /** 0110 1110 or %0, %e1 */
924 ID(or); DR(A); SM(HL, IMMU(1)); Fz;
926 /** 0110 0001 1110 0010 or %0, %e1 */
927 ID(or); DR(A); SM2(HL, C, 0); Fz;
929 /** 0110 1100 or %0, #%1 */
930 ID(or); DR(A); SC(IMMU(1)); Fz;
932 /** 0110 0001 0110 1rba or %0, %1 */
933 ID(or); DR(A); SRB(rba); Fz;
935 /** 0110 0001 0110 0reg or %0, %1 */
936 ID(or); DRB(reg); SR(A); Fz;
938 /** 0110 1011 or %0, %1 */
939 ID(or); DR(A); SM(None, SADDR); Fz;
941 /** 0110 1010 or %0, #%1 */
942 ID(or); DM(None, SADDR); SC(IMMU(1)); Fz;
944 /*----------------------------------------------------------------------*/
946 /** 0111 0001 1bit 0110 or1 cy, %e1 */
947 ID(or); DCY(); SM(HL, 0); SB(bit);
949 /** 0111 0001 1bit 1110 or1 cy, %1 */
950 ID(or); DCY(); SR(A); SB(bit);
952 /** 0111 0001 0bit 1110 or1 cy, %s1 */
953 ID(or); DCY(); SM(None, SFR); SB(bit);
955 /** 0111 0001 0bit 0110 or1 cy, %s1 */
956 ID(or); DCY(); SM(None, SADDR); SB(bit);
958 /*----------------------------------------------------------------------*/
960 /** 1100 0rg0 pop %0 */
961 ID(mov); W(); DRW(rg); SPOP();
963 /** 0110 0001 1100 1101 pop %s0 */
964 ID(mov); W(); DR(PSW); SPOP();
966 /*----------------------------------------------------------------------*/
968 /** 1100 0rg1 push %1 */
969 ID(mov); W(); DPUSH(); SRW(rg);
971 /** 0110 0001 1101 1101 push %s1 */
972 ID(mov); W(); DPUSH(); SR(PSW);
974 /*----------------------------------------------------------------------*/
979 /** 0110 0001 1111 1100 reti */
982 /** 0110 0001 1110 1100 retb */
985 /*----------------------------------------------------------------------*/
987 /** 0110 0001 1110 1011 rol %0, %1 */
988 ID(rol); DR(A); SC(1);
990 /** 0110 0001 1101 1100 rolc %0, %1 */
991 ID(rolc); DR(A); SC(1);
993 /** 0110 0001 111r 1110 rolwc %0, %1 */
994 ID(rolc); W(); DRW(r); SC(1);
996 /** 0110 0001 1101 1011 ror %0, %1 */
997 ID(ror); DR(A); SC(1);
999 /** 0110 0001 1111 1011 rorc %0, %1 */
1000 ID(rorc); DR(A); SC(1);
1002 /*----------------------------------------------------------------------*/
1004 /* Note that the branch insns need to be listed before the shift
1005 ones, as "shift count of zero" means "branch insn" */
1007 /** 0011 0001 0cnt 1011 sar %0, %1 */
1008 ID(sar); DR(A); SC(cnt);
1010 /** 0011 0001 wcnt 1111 sarw %0, %1 */
1011 ID(sar); W(); DR(AX); SC(wcnt);
1013 /*----------------------------------------------------------------------*/
1015 /** 0110 0001 11rb 1111 sel rb%1 */
1018 /*----------------------------------------------------------------------*/
1020 /** 0111 0001 0bit 0000 set1 %e!0 */
1021 ID(mov); DM(None, IMMU(2)); DB(bit); SC(1);
1023 /** 0111 0001 1bit 0010 set1 %e0 */
1024 ID(mov); DM(HL, 0); DB(bit); SC(1);
1026 /** 0111 0001 1bit 1010 set1 %0 */
1027 ID(mov); DR(A); DB(bit); SC(1);
1029 /** 0111 0001 1000 0000 set1 cy */
1030 ID(mov); DCY(); SC(1);
1032 /** 0111 0001 0bit 1010 set1 %s0 */
1034 ID(mov); DM(None, op0); DB(bit); SC(1);
1035 if (op0 == RL78_SFR_PSW && bit == 7)
1036 rl78->syntax = "ei";
1038 /** 0111 0001 0bit 0010 set1 %0 */
1039 ID(mov); DM(None, SADDR); DB(bit); SC(1);
1041 /*----------------------------------------------------------------------*/
1043 /** 0011 0001 0cnt 1001 shl %0, %1 */
1044 ID(shl); DR(A); SC(cnt);
1046 /** 0011 0001 0cnt 1000 shl %0, %1 */
1047 ID(shl); DR(B); SC(cnt);
1049 /** 0011 0001 0cnt 0111 shl %0, %1 */
1050 ID(shl); DR(C); SC(cnt);
1052 /** 0011 0001 wcnt 1101 shlw %0, %1 */
1053 ID(shl); W(); DR(AX); SC(wcnt);
1055 /** 0011 0001 wcnt 1100 shlw %0, %1 */
1056 ID(shl); W(); DR(BC); SC(wcnt);
1058 /*----------------------------------------------------------------------*/
1060 /** 0011 0001 0cnt 1010 shr %0, %1 */
1061 ID(shr); DR(A); SC(cnt);
1063 /** 0011 0001 wcnt 1110 shrw %0, %1 */
1064 ID(shr); W(); DR(AX); SC(wcnt);
1066 /*----------------------------------------------------------------------*/
1068 /** 0110 0001 1100 1000 sk%c1 */
1071 /** 0110 0001 1110 0011 sk%c1 */
1074 /** 0110 0001 1101 1000 sk%c1 */
1077 /** 0110 0001 1111 0011 sk%c1 */
1080 /** 0110 0001 1111 1000 sk%c1 */
1083 /** 0110 0001 1110 1000 sk%c1 */
1086 /*----------------------------------------------------------------------*/
1088 /** 0110 0001 1111 1101 stop */
1091 /*----------------------------------------------------------------------*/
1093 /** 0010 1111 sub %0, %e!1 */
1094 ID(sub); DR(A); SM(None, IMMU(2)); Fzac;
1096 /** 0010 1101 sub %0, %e1 */
1097 ID(sub); DR(A); SM(HL, 0); Fzac;
1099 /** 0110 0001 1010 000 sub %0, %e1 */
1100 ID(sub); DR(A); SM2(HL, B, 0); Fzac;
1102 /** 0010 1110 sub %0, %e1 */
1103 ID(sub); DR(A); SM(HL, IMMU(1)); Fzac;
1105 /** 0110 0001 1010 0010 sub %0, %e1 */
1106 ID(sub); DR(A); SM2(HL, C, 0); Fzac;
1108 /** 0010 1100 sub %0, #%1 */
1109 ID(sub); DR(A); SC(IMMU(1)); Fzac;
1111 /** 0110 0001 0010 1rba sub %0, %1 */
1112 ID(sub); DR(A); SRB(rba); Fzac;
1114 /** 0010 1011 sub %0, %1 */
1115 ID(sub); DR(A); SM(None, SADDR); Fzac;
1117 /** 0110 0001 0010 0reg sub %0, %1 */
1118 ID(sub); DRB(reg); SR(A); Fzac;
1120 /** 0010 1010 sub %0, #%1 */
1121 ID(sub); DM(None, SADDR); SC(IMMU(1)); Fzac;
1123 /*----------------------------------------------------------------------*/
1125 /** 0011 1111 subc %0, %e!1 */
1126 ID(subc); DR(A); SM(None, IMMU(2)); Fzac;
1128 /** 0011 1101 subc %0, %e1 */
1129 ID(subc); DR(A); SM(HL, 0); Fzac;
1131 /** 0110 0001 1011 0000 subc %0, %e1 */
1132 ID(subc); DR(A); SM2(HL, B, 0); Fzac;
1134 /** 0110 0001 1011 0010 subc %0, %e1 */
1135 ID(subc); DR(A); SM2(HL, C, 0); Fzac;
1137 /** 0011 1110 subc %0, %e1 */
1138 ID(subc); DR(A); SM(HL, IMMU(1)); Fzac;
1140 /** 0011 1100 subc %0, #%1 */
1141 ID(subc); DR(A); SC(IMMU(1)); Fzac;
1143 /** 0110 0001 0011 1rba subc %0, %1 */
1144 ID(subc); DR(A); SRB(rba); Fzac;
1146 /** 0110 0001 0011 0reg subc %0, %1 */
1147 ID(subc); DRB(reg); SR(A); Fzac;
1149 /** 0011 1011 subc %0, %1 */
1150 ID(subc); DR(A); SM(None, SADDR); Fzac;
1152 /** 0011 1010 subc %0, #%1 */
1153 ID(subc); DM(None, SADDR); SC(IMMU(1)); Fzac;
1155 /*----------------------------------------------------------------------*/
1157 /** 0010 0010 subw %0, %e!1 */
1158 ID(sub); W(); DR(AX); SM(None, IMMU(2)); Fzac;
1160 /** 0110 0001 0010 1001 subw %0, %e1 */
1161 ID(sub); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
1163 /** 0010 0100 subw %0, #%1 */
1164 ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac;
1166 /** 0010 0rw1 subw %0, %1 */
1167 ID(sub); W(); DR(AX); SRW(rw); Fzac;
1169 /** 0010 0110 subw %0, %1 */
1170 ID(sub); W(); DR(AX); SM(None, SADDR); Fzac;
1172 /** 0010 0000 subw %0, #%1 */
1173 ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac;
1175 /*----------------------------------------------------------------------*/
1177 /** 0110 0001 1010 1010 xch %0, %e!1 */
1178 ID(xch); DR(A); SM(None, IMMU(2));
1180 /** 0110 0001 1010 1110 xch %0, %e1 */
1181 ID(xch); DR(A); SM(DE, 0);
1183 /** 0110 0001 1010 1111 xch %0, %e1 */
1184 ID(xch); DR(A); SM(DE, IMMU(1));
1186 /** 0110 0001 1010 1100 xch %0, %e1 */
1187 ID(xch); DR(A); SM(HL, 0);
1189 /** 0110 0001 1011 1001 xch %0, %e1 */
1190 ID(xch); DR(A); SM2(HL, B, 0);
1192 /** 0110 0001 1010 1101 xch %0, %e1 */
1193 ID(xch); DR(A); SM(HL, IMMU(1));
1195 /** 0110 0001 1010 1001 xch %0, %e1 */
1196 ID(xch); DR(A); SM2(HL, C, 0);
1198 /** 0110 0001 1000 1reg xch %0, %1 */
1199 /* Note: DECW uses reg == X, so this must follow DECW */
1200 ID(xch); DR(A); SRB(reg);
1202 /** 0110 0001 1010 1000 xch %0, %1 */
1203 ID(xch); DR(A); SM(None, SADDR);
1205 /** 0110 0001 1010 1011 xch %0, %1 */
1206 ID(xch); DR(A); SM(None, SFR);
1208 /** 0000 1000 xch a, x */
1209 ID(xch); DR(A); SR(X);
1211 /*----------------------------------------------------------------------*/
1213 /** 0011 0ra1 xchw %0, %1 */
1214 ID(xch); W(); DR(AX); SRW(ra);
1216 /*----------------------------------------------------------------------*/
1218 /** 0111 1111 xor %0, %e!1 */
1219 ID(xor); DR(A); SM(None, IMMU(2)); Fz;
1221 /** 0111 1101 xor %0, %e1 */
1222 ID(xor); DR(A); SM(HL, 0); Fz;
1224 /** 0110 0001 1111 0000 xor %0, %e1 */
1225 ID(xor); DR(A); SM2(HL, B, 0); Fz;
1227 /** 0111 1110 xor %0, %e1 */
1228 ID(xor); DR(A); SM(HL, IMMU(1)); Fz;
1230 /** 0110 0001 1111 0010 xor %0, %e1 */
1231 ID(xor); DR(A); SM2(HL, C, 0); Fz;
1233 /** 0111 1100 xor %0, #%1 */
1234 ID(xor); DR(A); SC(IMMU(1)); Fz;
1236 /** 0110 0001 0111 1rba xor %0, %1 */
1237 ID(xor); DR(A); SRB(rba); Fz;
1239 /** 0110 0001 0111 0reg xor %0, %1 */
1240 ID(xor); DRB(reg); SR(A); Fz;
1242 /** 0111 1011 xor %0, %1 */
1243 ID(xor); DR(A); SM(None, SADDR); Fz;
1245 /** 0111 1010 xor %0, #%1 */
1246 ID(xor); DM(None, SADDR); SC(IMMU(1)); Fz;
1248 /*----------------------------------------------------------------------*/
1250 /** 0111 0001 1bit 0111 xor1 cy, %e1 */
1251 ID(xor); DCY(); SM(HL, 0); SB(bit);
1253 /** 0111 0001 1bit 1111 xor1 cy, %1 */
1254 ID(xor); DCY(); SR(A); SB(bit);
1256 /** 0111 0001 0bit 1111 xor1 cy, %s1 */
1257 ID(xor); DCY(); SM(None, SFR); SB(bit);
1259 /** 0111 0001 0bit 0111 xor1 cy, %s1 */
1260 ID(xor); DCY(); SM(None, SADDR); SB(bit);
1262 /*----------------------------------------------------------------------*/
1266 return rl78->n_bytes;