1 /* Disassembler code for Renesas RL78.
2 Copyright (C) 2011-2016 Free Software Foundation, Inc.
3 Contributed by Red Hat.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
29 #include "opcode/rl78.h"
32 #define DEBUG_SEMANTICS 0
37 disassemble_info
* dis
;
41 rl78_get_byte (void * vdata
)
44 RL78_Data
*rl78_data
= (RL78_Data
*) vdata
;
46 rl78_data
->dis
->read_memory_func (rl78_data
->pc
,
59 "x", "a", "c", "b", "e", "d", "l", "h",
60 "ax", "bc", "de", "hl",
61 "sp", "psw", "cs", "es", "pmc", "mem"
67 "t", "f", "c", "nc", "h", "nh", "z", "nz"
75 case RL78_Operand_Indirect
:
76 case RL78_Operand_BitIndirect
:
77 case RL78_Operand_PostInc
:
78 case RL78_Operand_PreDec
:
86 print_insn_rl78_common (bfd_vma addr
, disassemble_info
* dis
, RL78_Dis_Isa isa
)
90 RL78_Opcode_Decoded opcode
;
99 rv
= rl78_decode_opcode (addr
, &opcode
, rl78_get_byte
, &rl78_data
, isa
);
101 dis
->bytes_per_line
= 10;
103 #define PR (dis->fprintf_func)
104 #define PS (dis->stream)
105 #define PC(c) PR (PS, "%c", c)
113 case RLO_unknown
: s
= "uknown"; break;
114 case RLO_add
: s
= "add: %e0%0 += %e1%1"; break;
115 case RLO_addc
: s
= "addc: %e0%0 += %e1%1 + CY"; break;
116 case RLO_and
: s
= "and: %e0%0 &= %e1%1"; break;
117 case RLO_branch
: s
= "branch: pc = %e0%0"; break;
118 case RLO_branch_cond
: s
= "branch_cond: pc = %e0%0 if %c1 / %e1%1"; break;
119 case RLO_branch_cond_clear
: s
= "branch_cond_clear: pc = %e0%0 if %c1 / %e1%1, %e1%1 = 0"; break;
120 case RLO_call
: s
= "call: pc = %e1%0"; break;
121 case RLO_cmp
: s
= "cmp: %e0%0 - %e1%1"; break;
122 case RLO_mov
: s
= "mov: %e0%0 = %e1%1"; break;
123 case RLO_or
: s
= "or: %e0%0 |= %e1%1"; break;
124 case RLO_rol
: s
= "rol: %e0%0 <<= %e1%1"; break;
125 case RLO_rolc
: s
= "rol: %e0%0 <<= %e1%1,CY"; break;
126 case RLO_ror
: s
= "ror: %e0%0 >>= %e1%1"; break;
127 case RLO_rorc
: s
= "ror: %e0%0 >>= %e1%1,CY"; break;
128 case RLO_sar
: s
= "sar: %e0%0 >>= %e1%1 signed"; break;
129 case RLO_sel
: s
= "sel: rb = %1"; break;
130 case RLO_shr
: s
= "shr: %e0%0 >>= %e1%1 unsigned"; break;
131 case RLO_shl
: s
= "shl: %e0%0 <<= %e1%1"; break;
132 case RLO_skip
: s
= "skip: if %c1"; break;
133 case RLO_sub
: s
= "sub: %e0%0 -= %e1%1"; break;
134 case RLO_subc
: s
= "subc: %e0%0 -= %e1%1 - CY"; break;
135 case RLO_xch
: s
= "xch: %e0%0 <-> %e1%1"; break;
136 case RLO_xor
: s
= "xor: %e0%0 ^= %e1%1"; break;
139 sprintf(buf
, "%s%%W%%f\t\033[32m%s\033[0m", s
, opcode
.syntax
);
152 RL78_Opcode_Operand
* oper
;
184 goto no_more_modifiers
;
198 if (opcode
.size
== RL78_Word
)
199 PR (PS
, " \033[33mW\033[0m");
206 PR (PS
, " \033[35m");
208 if (opcode
.flags
& RL78_PSW_Z
)
209 { PR (PS
, "Z"); comma
= ","; }
210 if (opcode
.flags
& RL78_PSW_AC
)
211 { PR (PS
, "%sAC", comma
); comma
= ","; }
212 if (opcode
.flags
& RL78_PSW_CY
)
213 { PR (PS
, "%sCY", comma
); comma
= ","; }
222 oper
= *s
== '0' ? &opcode
.op
[0] : &opcode
.op
[1];
225 if (oper
->use_es
&& indirect_type (oper
->type
))
231 /* If we are going to display SP by name, we must omit the bang. */
232 if ((oper
->type
== RL78_Operand_Indirect
|| RL78_Operand_BitIndirect
)
233 && oper
->reg
== RL78_Reg_None
235 && ((oper
->addend
== 0xffff8 && opcode
.size
== RL78_Word
)
236 || (oper
->addend
== 0x0fff8 && do_es
&& opcode
.size
== RL78_Word
)))
244 PR (PS
, "%s", condition_names
[oper
->condition
]);
250 case RL78_Operand_Immediate
:
252 dis
->print_address_func (oper
->addend
, dis
);
254 || oper
->addend
> 999
255 || oper
->addend
< -999)
256 PR (PS
, "%#x", oper
->addend
);
258 PR (PS
, "%d", oper
->addend
);
261 case RL78_Operand_Register
:
262 PR (PS
, "%s", register_names
[oper
->reg
]);
265 case RL78_Operand_Bit
:
266 PR (PS
, "%s.%d", register_names
[oper
->reg
], oper
->bit_number
);
269 case RL78_Operand_Indirect
:
270 case RL78_Operand_BitIndirect
:
274 if (oper
->addend
== 0xffffa && do_sfr
&& opcode
.size
== RL78_Byte
)
276 else if (oper
->addend
== 0xffff8 && do_sfr
&& opcode
.size
== RL78_Word
)
278 else if (oper
->addend
== 0x0fff8 && do_sfr
&& do_es
&& opcode
.size
== RL78_Word
)
280 else if (oper
->addend
== 0xffff8 && do_sfr
&& opcode
.size
== RL78_Byte
)
282 else if (oper
->addend
== 0xffff9 && do_sfr
&& opcode
.size
== RL78_Byte
)
284 else if (oper
->addend
== 0xffffc && do_sfr
&& opcode
.size
== RL78_Byte
)
286 else if (oper
->addend
== 0xffffd && do_sfr
&& opcode
.size
== RL78_Byte
)
288 else if (oper
->addend
== 0xffffe && do_sfr
&& opcode
.size
== RL78_Byte
)
290 else if (oper
->addend
== 0xfffff && do_sfr
&& opcode
.size
== RL78_Byte
)
292 else if (oper
->addend
>= 0xffe20)
293 PR (PS
, "%#x", oper
->addend
);
296 int faddr
= oper
->addend
;
297 if (do_es
&& ! oper
->use_es
)
299 dis
->print_address_func (faddr
, dis
);
306 PR (PS
, "%d[%s]", oper
->addend
, register_names
[oper
->reg
]);
310 PR (PS
, "[%s", register_names
[oper
->reg
]);
311 if (oper
->reg2
!= RL78_Reg_None
)
312 PR (PS
, "+%s", register_names
[oper
->reg2
]);
313 if (oper
->addend
|| do_addr
)
314 PR (PS
, "+%d", oper
->addend
);
319 if (oper
->type
== RL78_Operand_BitIndirect
)
320 PR (PS
, ".%d", oper
->bit_number
);
324 /* Shouldn't happen - push and pop don't print
325 [SP] directly. But we *do* use them for
326 semantic debugging. */
327 case RL78_Operand_PostInc
:
328 PR (PS
, "[%s++]", register_names
[oper
->reg
]);
330 case RL78_Operand_PreDec
:
331 PR (PS
, "[--%s]", register_names
[oper
->reg
]);
336 /* If we ever print this, that means the
337 programmer tried to print an operand with a
338 type we don't expect. Print the line and
339 operand number from rl78-decode.opc for
341 PR (PS
, "???%d.%d", opcode
.lineno
, *s
- '0');
350 PR (PS
, "\t\033[34m(line %d)\033[0m", opcode
.lineno
);
358 print_insn_rl78 (bfd_vma addr
, disassemble_info
* dis
)
360 return print_insn_rl78_common (addr
, dis
, RL78_ISA_DEFAULT
);
364 print_insn_rl78_g10 (bfd_vma addr
, disassemble_info
* dis
)
366 return print_insn_rl78_common (addr
, dis
, RL78_ISA_G10
);
370 print_insn_rl78_g13 (bfd_vma addr
, disassemble_info
* dis
)
372 return print_insn_rl78_common (addr
, dis
, RL78_ISA_G13
);
376 print_insn_rl78_g14 (bfd_vma addr
, disassemble_info
* dis
)
378 return print_insn_rl78_common (addr
, dis
, RL78_ISA_G14
);
382 rl78_get_disassembler (bfd
*abfd
)
384 int cpu
= abfd
->tdata
.elf_obj_data
->elf_header
->e_flags
& E_FLAG_RL78_CPU_MASK
;
387 case E_FLAG_RL78_G10
:
388 return print_insn_rl78_g10
;
389 case E_FLAG_RL78_G13
:
390 return print_insn_rl78_g13
;
391 case E_FLAG_RL78_G14
:
392 return print_insn_rl78_g14
;
394 return print_insn_rl78
;