1 /* Definitions for SH opcodes.
2 Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2003, 2004
3 Free Software Foundation, Inc.
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
155 X_REG_N
, /* Only used for argument parsing. */
156 X_REG_M
, /* Only used for argument parsing. */
174 A_X0_NUM
, A_X1_NUM
, A_Y0_NUM
, A_Y1_NUM
,
175 A_M0_NUM
, A_A1G_NUM
, A_M1_NUM
, A_A0G_NUM
179 #define arch_sh1 0x0001
180 #define arch_sh2 0x0002
181 #define arch_sh3 0x0004
182 #define arch_sh3e 0x0008
183 #define arch_sh4 0x0010
184 #define arch_sh2e 0x0020
185 #define arch_sh4a 0x0040
186 #define arch_sh_dsp 0x0100
187 #define arch_sh3_dsp 0x0200
188 #define arch_sh4al_dsp 0x0400
189 #define arch_sh4_nofpu 0x1000
190 #define arch_sh4a_nofpu 0x2000
191 #define arch_sh4_nommu_nofpu 0x4000 /* no mmu nor fpu */
193 #define arch_sh1_up (arch_sh1 | arch_sh2_up)
194 #define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh3_up | arch_sh_dsp)
195 #define arch_sh2e_up (arch_sh2e | arch_sh3e_up)
196 #define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \
197 | arch_sh4_nommu_nofpu_up)
198 #define arch_sh3e_up (arch_sh3e | arch_sh4_up)
199 #define arch_sh4_up (arch_sh4 | arch_sh4a_up)
200 #define arch_sh4a_up (arch_sh4a)
202 #define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up)
203 #define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up)
204 #define arch_sh4al_dsp_up (arch_sh4al_dsp)
206 #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up)
208 #define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up)
209 #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up)
211 #define arch_sh_any_with_mmu (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \
212 | arch_sh4_nofp_up) /* arch _sh3_up omitting arch_sh4_nommu_nofpu */
218 sh_nibble_type nibbles
[5];
224 const sh_opcode_info sh_table
[] =
226 /* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM
,A_REG_N
},{HEX_7
,REG_N
,IMM0_8
}, arch_sh1_up
},
228 /* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M
,A_REG_N
},{HEX_3
,REG_N
,REG_M
,HEX_C
}, arch_sh1_up
},
230 /* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M
,A_REG_N
},{HEX_3
,REG_N
,REG_M
,HEX_E
}, arch_sh1_up
},
232 /* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M
,A_REG_N
},{HEX_3
,REG_N
,REG_M
,HEX_F
}, arch_sh1_up
},
234 /* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM
,A_R0
},{HEX_C
,HEX_9
,IMM0_8
}, arch_sh1_up
},
236 /* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M
,A_REG_N
},{HEX_2
,REG_N
,REG_M
,HEX_9
}, arch_sh1_up
},
238 /* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM
,A_R0_GBR
},{HEX_C
,HEX_D
,IMM0_8
}, arch_sh1_up
},
240 /* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12
},{HEX_A
,BRANCH_12
}, arch_sh1_up
},
242 /* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12
},{HEX_B
,BRANCH_12
}, arch_sh1_up
},
244 /* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8
},{HEX_8
,HEX_9
,BRANCH_8
}, arch_sh1_up
},
246 /* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8
},{HEX_8
,HEX_B
,BRANCH_8
}, arch_sh1_up
},
248 /* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8
},{HEX_8
,HEX_D
,BRANCH_8
}, arch_sh2_up
},
250 /* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8
},{HEX_8
,HEX_D
,BRANCH_8
}, arch_sh2_up
},
252 /* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8
},{HEX_8
,HEX_F
,BRANCH_8
}, arch_sh2_up
},
254 /* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8
},{HEX_8
,HEX_F
,BRANCH_8
}, arch_sh2_up
},
256 /* 0000000010001000 clrdmxy */{"clrdmxy",{0},{HEX_0
,HEX_0
,HEX_8
,HEX_8
}, arch_sh4al_dsp_up
},
258 /* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0
,HEX_0
,HEX_2
,HEX_8
}, arch_sh1_up
},
260 /* 0000000001001000 clrs */{"clrs",{0},{HEX_0
,HEX_0
,HEX_4
,HEX_8
}, arch_sh1_up
},
262 /* 0000000000001000 clrt */{"clrt",{0},{HEX_0
,HEX_0
,HEX_0
,HEX_8
}, arch_sh1_up
},
264 /* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM
,A_R0
},{HEX_8
,HEX_8
,IMM0_8
}, arch_sh1_up
},
266 /* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M
,A_REG_N
},{HEX_3
,REG_N
,REG_M
,HEX_0
}, arch_sh1_up
},
268 /* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M
,A_REG_N
},{HEX_3
,REG_N
,REG_M
,HEX_3
}, arch_sh1_up
},
270 /* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M
,A_REG_N
},{HEX_3
,REG_N
,REG_M
,HEX_7
}, arch_sh1_up
},
272 /* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M
,A_REG_N
},{HEX_3
,REG_N
,REG_M
,HEX_6
}, arch_sh1_up
},
274 /* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M
,A_REG_N
},{HEX_3
,REG_N
,REG_M
,HEX_2
}, arch_sh1_up
},
276 /* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N
},{HEX_4
,REG_N
,HEX_1
,HEX_5
}, arch_sh1_up
},
278 /* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N
},{HEX_4
,REG_N
,HEX_1
,HEX_1
}, arch_sh1_up
},
280 /* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M
,A_REG_N
},{HEX_2
,REG_N
,REG_M
,HEX_C
}, arch_sh1_up
},
282 /* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M
,A_REG_N
},{HEX_2
,REG_N
,REG_M
,HEX_7
}, arch_sh1_up
},
284 /* 0000000000011001 div0u */{"div0u",{0},{HEX_0
,HEX_0
,HEX_1
,HEX_9
}, arch_sh1_up
},
286 /* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M
,A_REG_N
},{HEX_3
,REG_N
,REG_M
,HEX_4
}, arch_sh1_up
},
288 /* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_E
}, arch_sh1_up
},
290 /* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_F
}, arch_sh1_up
},
292 /* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_C
}, arch_sh1_up
},
294 /* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_D
}, arch_sh1_up
},
296 /* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N
},{HEX_0
,REG_N
,HEX_E
,HEX_3
}, arch_sh4a_nofp_up
},
298 /* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N
},{HEX_4
,REG_N
,HEX_2
,HEX_B
}, arch_sh1_up
},
300 /* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N
},{HEX_4
,REG_N
,HEX_0
,HEX_B
}, arch_sh1_up
},
302 /* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N
,A_SR
},{HEX_4
,REG_N
,HEX_0
,HEX_E
}, arch_sh1_up
},
304 /* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N
,A_GBR
},{HEX_4
,REG_N
,HEX_1
,HEX_E
}, arch_sh1_up
},
306 /* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N
,A_SGR
},{HEX_4
,REG_N
,HEX_3
,HEX_A
}, arch_sh4_nommu_nofpu_up
},
308 /* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N
,A_VBR
},{HEX_4
,REG_N
,HEX_2
,HEX_E
}, arch_sh1_up
},
310 /* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N
,A_MOD
},{HEX_4
,REG_N
,HEX_5
,HEX_E
}, arch_sh_dsp_up
},
312 /* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N
,A_RE
},{HEX_4
,REG_N
,HEX_7
,HEX_E
}, arch_sh_dsp_up
},
314 /* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N
,A_RS
},{HEX_4
,REG_N
,HEX_6
,HEX_E
}, arch_sh_dsp_up
},
316 /* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N
,A_SSR
},{HEX_4
,REG_N
,HEX_3
,HEX_E
}, arch_sh3_up
},
318 /* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N
,A_SPC
},{HEX_4
,REG_N
,HEX_4
,HEX_E
}, arch_sh3_up
},
320 /* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N
,A_DBR
},{HEX_4
,REG_N
,HEX_F
,HEX_A
}, arch_sh4_nommu_nofpu_up
},
322 /* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N
,A_REG_B
},{HEX_4
,REG_N
,REG_B
,HEX_E
}, arch_sh3_up
},
324 /* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N
,A_SR
},{HEX_4
,REG_N
,HEX_0
,HEX_7
}, arch_sh1_up
},
326 /* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N
,A_GBR
},{HEX_4
,REG_N
,HEX_1
,HEX_7
}, arch_sh1_up
},
328 /* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N
,A_VBR
},{HEX_4
,REG_N
,HEX_2
,HEX_7
}, arch_sh1_up
},
330 /* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N
,A_SGR
},{HEX_4
,REG_N
,HEX_3
,HEX_6
}, arch_sh4_nommu_nofpu_up
},
332 /* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N
,A_MOD
},{HEX_4
,REG_N
,HEX_5
,HEX_7
}, arch_sh_dsp_up
},
334 /* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N
,A_RE
},{HEX_4
,REG_N
,HEX_7
,HEX_7
}, arch_sh_dsp_up
},
336 /* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N
,A_RS
},{HEX_4
,REG_N
,HEX_6
,HEX_7
}, arch_sh_dsp_up
},
338 /* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N
,A_SSR
},{HEX_4
,REG_N
,HEX_3
,HEX_7
}, arch_sh3_up
},
340 /* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N
,A_SPC
},{HEX_4
,REG_N
,HEX_4
,HEX_7
}, arch_sh3_up
},
342 /* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N
,A_DBR
},{HEX_4
,REG_N
,HEX_F
,HEX_6
}, arch_sh4_nommu_nofpu_up
},
344 /* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N
,A_REG_B
},{HEX_4
,REG_N
,REG_B
,HEX_7
}, arch_sh3_up
},
346 /* 0100mmmm00110100 ldrc <REG_M> */{"ldrc",{A_REG_M
},{HEX_4
,REG_M
,HEX_3
,HEX_4
}, arch_sh4al_dsp_up
},
347 /* 10001010i8*1.... ldrc #<imm> */{"ldrc",{A_IMM
},{HEX_8
,HEX_A
,IMM0_8
}, arch_sh4al_dsp_up
},
349 /* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC
},{HEX_8
,HEX_E
,PCRELIMM_8BY2
}, arch_sh_dsp_up
},
351 /* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC
},{HEX_8
,HEX_C
,PCRELIMM_8BY2
}, arch_sh_dsp_up
},
353 /* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N
,A_MACH
},{HEX_4
,REG_N
,HEX_0
,HEX_A
}, arch_sh1_up
},
355 /* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N
,A_MACL
},{HEX_4
,REG_N
,HEX_1
,HEX_A
}, arch_sh1_up
},
357 /* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N
,A_PR
},{HEX_4
,REG_N
,HEX_2
,HEX_A
}, arch_sh1_up
},
359 /* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N
,A_DSR
},{HEX_4
,REG_N
,HEX_6
,HEX_A
}, arch_sh_dsp_up
},
361 /* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N
,A_A0
},{HEX_4
,REG_N
,HEX_7
,HEX_A
}, arch_sh_dsp_up
},
363 /* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N
,A_X0
},{HEX_4
,REG_N
,HEX_8
,HEX_A
}, arch_sh_dsp_up
},
365 /* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N
,A_X1
},{HEX_4
,REG_N
,HEX_9
,HEX_A
}, arch_sh_dsp_up
},
367 /* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N
,A_Y0
},{HEX_4
,REG_N
,HEX_A
,HEX_A
}, arch_sh_dsp_up
},
369 /* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N
,A_Y1
},{HEX_4
,REG_N
,HEX_B
,HEX_A
}, arch_sh_dsp_up
},
371 /* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M
,FPUL_N
},{HEX_4
,REG_M
,HEX_5
,HEX_A
}, arch_sh2e_up
},
373 /* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M
,FPSCR_N
},{HEX_4
,REG_M
,HEX_6
,HEX_A
}, arch_sh2e_up
},
375 /* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N
,A_MACH
},{HEX_4
,REG_N
,HEX_0
,HEX_6
}, arch_sh1_up
},
377 /* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N
,A_MACL
},{HEX_4
,REG_N
,HEX_1
,HEX_6
}, arch_sh1_up
},
379 /* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N
,A_PR
},{HEX_4
,REG_N
,HEX_2
,HEX_6
}, arch_sh1_up
},
381 /* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N
,A_DSR
},{HEX_4
,REG_N
,HEX_6
,HEX_6
}, arch_sh_dsp_up
},
383 /* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N
,A_A0
},{HEX_4
,REG_N
,HEX_7
,HEX_6
}, arch_sh_dsp_up
},
385 /* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N
,A_X0
},{HEX_4
,REG_N
,HEX_8
,HEX_6
}, arch_sh_dsp_up
},
387 /* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N
,A_X1
},{HEX_4
,REG_N
,HEX_9
,HEX_6
}, arch_sh_dsp_up
},
389 /* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N
,A_Y0
},{HEX_4
,REG_N
,HEX_A
,HEX_6
}, arch_sh_dsp_up
},
391 /* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N
,A_Y1
},{HEX_4
,REG_N
,HEX_B
,HEX_6
}, arch_sh_dsp_up
},
393 /* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M
,FPUL_N
},{HEX_4
,REG_M
,HEX_5
,HEX_6
}, arch_sh2e_up
},
395 /* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M
,FPSCR_N
},{HEX_4
,REG_M
,HEX_6
,HEX_6
}, arch_sh2e_up
},
397 /* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0
,HEX_0
,HEX_3
,HEX_8
}, arch_sh_any_with_mmu
},
399 /* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M
,A_INC_N
},{HEX_4
,REG_N
,REG_M
,HEX_F
}, arch_sh1_up
},
401 /* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM
,A_REG_N
},{HEX_E
,REG_N
,IMM0_8
}, arch_sh1_up
},
403 /* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_3
}, arch_sh1_up
},
405 /* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M
,A_IND_R0_REG_N
},{HEX_0
,REG_N
,REG_M
,HEX_4
}, arch_sh1_up
},
407 /* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M
,A_DEC_N
},{HEX_2
,REG_N
,REG_M
,HEX_4
}, arch_sh1_up
},
409 /* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M
,A_IND_N
},{HEX_2
,REG_N
,REG_M
,HEX_0
}, arch_sh1_up
},
411 /* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M
,A_R0
},{HEX_8
,HEX_4
,REG_M
,IMM0_4
}, arch_sh1_up
},
413 /* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR
,A_R0
},{HEX_C
,HEX_4
,IMM0_8
}, arch_sh1_up
},
415 /* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M
,A_REG_N
},{HEX_0
,REG_N
,REG_M
,HEX_C
}, arch_sh1_up
},
417 /* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_4
}, arch_sh1_up
},
419 /* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_0
}, arch_sh1_up
},
421 /* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0
,A_DISP_REG_M
},{HEX_8
,HEX_0
,REG_M
,IMM1_4
}, arch_sh1_up
},
423 /* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0
,A_DISP_GBR
},{HEX_C
,HEX_0
,IMM1_8
}, arch_sh1_up
},
425 /* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M
,A_DISP_REG_N
},{HEX_1
,REG_N
,REG_M
,IMM1_4BY4
}, arch_sh1_up
},
427 /* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M
,A_IND_R0_REG_N
},{HEX_0
,REG_N
,REG_M
,HEX_6
}, arch_sh1_up
},
429 /* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M
,A_DEC_N
},{HEX_2
,REG_N
,REG_M
,HEX_6
}, arch_sh1_up
},
431 /* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M
,A_IND_N
},{HEX_2
,REG_N
,REG_M
,HEX_2
}, arch_sh1_up
},
433 /* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M
,A_REG_N
},{HEX_5
,REG_N
,REG_M
,IMM0_4BY4
}, arch_sh1_up
},
435 /* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR
,A_R0
},{HEX_C
,HEX_6
,IMM0_8BY4
}, arch_sh1_up
},
437 /* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC
,A_REG_N
},{HEX_D
,REG_N
,PCRELIMM_8BY4
}, arch_sh1_up
},
439 /* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M
,A_REG_N
},{HEX_0
,REG_N
,REG_M
,HEX_E
}, arch_sh1_up
},
441 /* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_6
}, arch_sh1_up
},
443 /* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_2
}, arch_sh1_up
},
445 /* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0
,A_DISP_GBR
},{HEX_C
,HEX_2
,IMM1_8BY4
}, arch_sh1_up
},
447 /* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M
,A_IND_R0_REG_N
},{HEX_0
,REG_N
,REG_M
,HEX_5
}, arch_sh1_up
},
449 /* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M
,A_DEC_N
},{HEX_2
,REG_N
,REG_M
,HEX_5
}, arch_sh1_up
},
451 /* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M
,A_IND_N
},{HEX_2
,REG_N
,REG_M
,HEX_1
}, arch_sh1_up
},
453 /* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M
,A_R0
},{HEX_8
,HEX_5
,REG_M
,IMM0_4BY2
}, arch_sh1_up
},
455 /* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR
,A_R0
},{HEX_C
,HEX_5
,IMM0_8BY2
}, arch_sh1_up
},
457 /* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC
,A_REG_N
},{HEX_9
,REG_N
,PCRELIMM_8BY2
}, arch_sh1_up
},
459 /* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M
,A_REG_N
},{HEX_0
,REG_N
,REG_M
,HEX_D
}, arch_sh1_up
},
461 /* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_5
}, arch_sh1_up
},
463 /* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_1
}, arch_sh1_up
},
465 /* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0
,A_DISP_REG_M
},{HEX_8
,HEX_1
,REG_M
,IMM1_4BY2
}, arch_sh1_up
},
467 /* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0
,A_DISP_GBR
},{HEX_C
,HEX_1
,IMM1_8BY2
}, arch_sh1_up
},
469 /* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC
,A_R0
},{HEX_C
,HEX_7
,PCRELIMM_8BY4
}, arch_sh1_up
},
470 /* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0
,A_IND_N
},{HEX_0
,REG_N
,HEX_C
,HEX_3
}, arch_sh4_nommu_nofpu_up
},
472 /* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0
,A_IND_N
},{HEX_0
,REG_N
,HEX_7
,HEX_3
}, arch_sh4a_nofp_up
},
473 /* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M
,A_R0
},{HEX_0
,REG_M
,HEX_6
,HEX_3
}, arch_sh4a_nofp_up
},
475 /* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N
},{HEX_0
,REG_N
,HEX_2
,HEX_9
}, arch_sh1_up
},
477 /* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M
,A_R0
},{HEX_4
,REG_M
,HEX_A
,HEX_9
}, arch_sh4a_nofp_up
},
478 /* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M
,A_R0
},{HEX_4
,REG_M
,HEX_E
,HEX_9
}, arch_sh4a_nofp_up
},
480 /* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M
,A_REG_N
},{HEX_2
,REG_N
,REG_M
,HEX_F
}, arch_sh1_up
},
481 /* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M
,A_REG_N
},{HEX_2
,REG_N
,REG_M
,HEX_F
}, arch_sh1_up
},
483 /* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M
,A_REG_N
},{HEX_0
,REG_N
,REG_M
,HEX_7
}, arch_sh2_up
},
485 /* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M
,A_REG_N
},{HEX_2
,REG_N
,REG_M
,HEX_E
}, arch_sh1_up
},
486 /* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M
,A_REG_N
},{HEX_2
,REG_N
,REG_M
,HEX_E
}, arch_sh1_up
},
488 /* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_B
}, arch_sh1_up
},
490 /* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_A
}, arch_sh1_up
},
492 /* 0000000000001001 nop */{"nop",{0},{HEX_0
,HEX_0
,HEX_0
,HEX_9
}, arch_sh1_up
},
494 /* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_7
}, arch_sh1_up
},
495 /* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N
},{HEX_0
,REG_N
,HEX_9
,HEX_3
}, arch_sh4_nommu_nofpu_up
},
497 /* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N
},{HEX_0
,REG_N
,HEX_A
,HEX_3
}, arch_sh4_nommu_nofpu_up
},
499 /* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N
},{HEX_0
,REG_N
,HEX_B
,HEX_3
}, arch_sh4_nommu_nofpu_up
},
502 /* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM
,A_R0
},{HEX_C
,HEX_B
,IMM0_8
}, arch_sh1_up
},
504 /* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M
,A_REG_N
},{HEX_2
,REG_N
,REG_M
,HEX_B
}, arch_sh1_up
},
506 /* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM
,A_R0_GBR
},{HEX_C
,HEX_F
,IMM0_8
}, arch_sh1_up
},
508 /* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N
},{HEX_0
,REG_N
,HEX_8
,HEX_3
}, arch_sh4_nommu_nofpu_up
},
510 /* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N
},{HEX_0
,REG_N
,HEX_D
,HEX_3
}, arch_sh4a_nofp_up
},
512 /* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N
},{HEX_4
,REG_N
,HEX_2
,HEX_4
}, arch_sh1_up
},
514 /* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N
},{HEX_4
,REG_N
,HEX_2
,HEX_5
}, arch_sh1_up
},
516 /* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N
},{HEX_4
,REG_N
,HEX_0
,HEX_4
}, arch_sh1_up
},
518 /* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N
},{HEX_4
,REG_N
,HEX_0
,HEX_5
}, arch_sh1_up
},
520 /* 0000000000101011 rte */{"rte",{0},{HEX_0
,HEX_0
,HEX_2
,HEX_B
}, arch_sh1_up
},
522 /* 0000000000001011 rts */{"rts",{0},{HEX_0
,HEX_0
,HEX_0
,HEX_B
}, arch_sh1_up
},
524 /* 0000000010011000 setdmx */{"setdmx",{0},{HEX_0
,HEX_0
,HEX_9
,HEX_8
}, arch_sh4al_dsp_up
},
525 /* 0000000011001000 setdmy */{"setdmy",{0},{HEX_0
,HEX_0
,HEX_C
,HEX_8
}, arch_sh4al_dsp_up
},
527 /* 0000000001011000 sets */{"sets",{0},{HEX_0
,HEX_0
,HEX_5
,HEX_8
}, arch_sh1_up
},
528 /* 0000000000011000 sett */{"sett",{0},{HEX_0
,HEX_0
,HEX_1
,HEX_8
}, arch_sh1_up
},
530 /* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N
},{HEX_4
,REG_N
,HEX_1
,HEX_4
}, arch_sh_dsp_up
},
532 /* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM
},{HEX_8
,HEX_2
,IMM0_8
}, arch_sh_dsp_up
},
534 /* repeat start end <REG_N> */{"repeat",{A_DISP_PC
,A_DISP_PC
,A_REG_N
},{REPEAT
,REG_N
,HEX_1
,HEX_4
}, arch_sh_dsp_up
},
536 /* repeat start end #<imm> */{"repeat",{A_DISP_PC
,A_DISP_PC
,A_IMM
},{REPEAT
,HEX_2
,IMM0_8
,HEX_8
}, arch_sh_dsp_up
},
538 /* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M
,A_REG_N
},{HEX_4
,REG_N
,REG_M
,HEX_C
}, arch_sh3_up
},
540 /* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M
,A_REG_N
},{HEX_4
,REG_N
,REG_M
,HEX_D
}, arch_sh3_up
},
542 /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N
},{HEX_4
,REG_N
,HEX_2
,HEX_0
}, arch_sh1_up
},
544 /* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N
},{HEX_4
,REG_N
,HEX_2
,HEX_1
}, arch_sh1_up
},
546 /* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N
},{HEX_4
,REG_N
,HEX_0
,HEX_0
}, arch_sh1_up
},
548 /* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N
},{HEX_4
,REG_N
,HEX_2
,HEX_8
}, arch_sh1_up
},
550 /* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N
},{HEX_4
,REG_N
,HEX_0
,HEX_8
}, arch_sh1_up
},
552 /* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N
},{HEX_4
,REG_N
,HEX_1
,HEX_8
}, arch_sh1_up
},
554 /* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N
},{HEX_4
,REG_N
,HEX_0
,HEX_1
}, arch_sh1_up
},
556 /* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N
},{HEX_4
,REG_N
,HEX_2
,HEX_9
}, arch_sh1_up
},
558 /* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N
},{HEX_4
,REG_N
,HEX_0
,HEX_9
}, arch_sh1_up
},
560 /* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N
},{HEX_4
,REG_N
,HEX_1
,HEX_9
}, arch_sh1_up
},
562 /* 0000000000011011 sleep */{"sleep",{0},{HEX_0
,HEX_0
,HEX_1
,HEX_B
}, arch_sh1_up
},
564 /* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR
,A_REG_N
},{HEX_0
,REG_N
,HEX_0
,HEX_2
}, arch_sh1_up
},
566 /* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR
,A_REG_N
},{HEX_0
,REG_N
,HEX_1
,HEX_2
}, arch_sh1_up
},
568 /* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR
,A_REG_N
},{HEX_0
,REG_N
,HEX_2
,HEX_2
}, arch_sh1_up
},
570 /* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD
,A_REG_N
},{HEX_0
,REG_N
,HEX_5
,HEX_2
}, arch_sh_dsp_up
},
572 /* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE
,A_REG_N
},{HEX_0
,REG_N
,HEX_7
,HEX_2
}, arch_sh_dsp_up
},
574 /* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS
,A_REG_N
},{HEX_0
,REG_N
,HEX_6
,HEX_2
}, arch_sh_dsp_up
},
576 /* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR
,A_REG_N
},{HEX_0
,REG_N
,HEX_3
,HEX_2
}, arch_sh3_up
},
578 /* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC
,A_REG_N
},{HEX_0
,REG_N
,HEX_4
,HEX_2
}, arch_sh3_up
},
580 /* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR
,A_REG_N
},{HEX_0
,REG_N
,HEX_3
,HEX_A
}, arch_sh4_nommu_nofpu_up
},
582 /* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR
,A_REG_N
},{HEX_0
,REG_N
,HEX_F
,HEX_A
}, arch_sh4_nommu_nofpu_up
},
584 /* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B
,A_REG_N
},{HEX_0
,REG_N
,REG_B
,HEX_2
}, arch_sh3_up
},
586 /* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR
,A_DEC_N
},{HEX_4
,REG_N
,HEX_0
,HEX_3
}, arch_sh1_up
},
588 /* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR
,A_DEC_N
},{HEX_4
,REG_N
,HEX_2
,HEX_3
}, arch_sh1_up
},
590 /* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD
,A_DEC_N
},{HEX_4
,REG_N
,HEX_5
,HEX_3
}, arch_sh_dsp_up
},
592 /* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE
,A_DEC_N
},{HEX_4
,REG_N
,HEX_7
,HEX_3
}, arch_sh_dsp_up
},
594 /* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS
,A_DEC_N
},{HEX_4
,REG_N
,HEX_6
,HEX_3
}, arch_sh_dsp_up
},
596 /* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR
,A_DEC_N
},{HEX_4
,REG_N
,HEX_3
,HEX_3
}, arch_sh3_up
},
598 /* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC
,A_DEC_N
},{HEX_4
,REG_N
,HEX_4
,HEX_3
}, arch_sh3_up
},
600 /* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR
,A_DEC_N
},{HEX_4
,REG_N
,HEX_1
,HEX_3
}, arch_sh1_up
},
602 /* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR
,A_DEC_N
},{HEX_4
,REG_N
,HEX_3
,HEX_2
}, arch_sh4_nommu_nofpu_up
},
604 /* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR
,A_DEC_N
},{HEX_4
,REG_N
,HEX_F
,HEX_2
}, arch_sh4_nommu_nofpu_up
},
606 /* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B
,A_DEC_N
},{HEX_4
,REG_N
,REG_B
,HEX_3
}, arch_sh3_up
},
608 /* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH
,A_REG_N
},{HEX_0
,REG_N
,HEX_0
,HEX_A
}, arch_sh1_up
},
610 /* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL
,A_REG_N
},{HEX_0
,REG_N
,HEX_1
,HEX_A
}, arch_sh1_up
},
612 /* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR
,A_REG_N
},{HEX_0
,REG_N
,HEX_2
,HEX_A
}, arch_sh1_up
},
614 /* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR
,A_REG_N
},{HEX_0
,REG_N
,HEX_6
,HEX_A
}, arch_sh_dsp_up
},
616 /* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0
,A_REG_N
},{HEX_0
,REG_N
,HEX_7
,HEX_A
}, arch_sh_dsp_up
},
618 /* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0
,A_REG_N
},{HEX_0
,REG_N
,HEX_8
,HEX_A
}, arch_sh_dsp_up
},
620 /* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1
,A_REG_N
},{HEX_0
,REG_N
,HEX_9
,HEX_A
}, arch_sh_dsp_up
},
622 /* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0
,A_REG_N
},{HEX_0
,REG_N
,HEX_A
,HEX_A
}, arch_sh_dsp_up
},
624 /* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1
,A_REG_N
},{HEX_0
,REG_N
,HEX_B
,HEX_A
}, arch_sh_dsp_up
},
626 /* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M
,A_REG_N
},{HEX_0
,REG_N
,HEX_5
,HEX_A
}, arch_sh2e_up
},
628 /* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M
,A_REG_N
},{HEX_0
,REG_N
,HEX_6
,HEX_A
}, arch_sh2e_up
},
630 /* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH
,A_DEC_N
},{HEX_4
,REG_N
,HEX_0
,HEX_2
}, arch_sh1_up
},
632 /* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL
,A_DEC_N
},{HEX_4
,REG_N
,HEX_1
,HEX_2
}, arch_sh1_up
},
634 /* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR
,A_DEC_N
},{HEX_4
,REG_N
,HEX_2
,HEX_2
}, arch_sh1_up
},
636 /* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR
,A_DEC_N
},{HEX_4
,REG_N
,HEX_6
,HEX_2
}, arch_sh_dsp_up
},
638 /* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0
,A_DEC_N
},{HEX_4
,REG_N
,HEX_7
,HEX_2
}, arch_sh_dsp_up
},
640 /* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0
,A_DEC_N
},{HEX_4
,REG_N
,HEX_8
,HEX_2
}, arch_sh_dsp_up
},
642 /* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1
,A_DEC_N
},{HEX_4
,REG_N
,HEX_9
,HEX_2
}, arch_sh_dsp_up
},
644 /* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0
,A_DEC_N
},{HEX_4
,REG_N
,HEX_A
,HEX_2
}, arch_sh_dsp_up
},
646 /* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1
,A_DEC_N
},{HEX_4
,REG_N
,HEX_B
,HEX_2
}, arch_sh_dsp_up
},
648 /* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M
,A_DEC_N
},{HEX_4
,REG_N
,HEX_5
,HEX_2
}, arch_sh2e_up
},
650 /* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M
,A_DEC_N
},{HEX_4
,REG_N
,HEX_6
,HEX_2
}, arch_sh2e_up
},
652 /* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M
,A_REG_N
},{HEX_3
,REG_N
,REG_M
,HEX_8
}, arch_sh1_up
},
654 /* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M
,A_REG_N
},{HEX_3
,REG_N
,REG_M
,HEX_A
}, arch_sh1_up
},
656 /* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M
,A_REG_N
},{HEX_3
,REG_N
,REG_M
,HEX_B
}, arch_sh1_up
},
658 /* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_8
}, arch_sh1_up
},
660 /* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M
,A_REG_N
},{HEX_6
,REG_N
,REG_M
,HEX_9
}, arch_sh1_up
},
662 /* 0000000010101011 synco */{"synco",{0},{HEX_0
,HEX_0
,HEX_A
,HEX_B
}, arch_sh4a_nofp_up
},
664 /* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N
},{HEX_4
,REG_N
,HEX_1
,HEX_B
}, arch_sh1_up
},
666 /* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM
},{HEX_C
,HEX_3
,IMM0_8
}, arch_sh1_up
},
668 /* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM
,A_R0
},{HEX_C
,HEX_8
,IMM0_8
}, arch_sh1_up
},
670 /* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M
,A_REG_N
},{HEX_2
,REG_N
,REG_M
,HEX_8
}, arch_sh1_up
},
672 /* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM
,A_R0_GBR
},{HEX_C
,HEX_C
,IMM0_8
}, arch_sh1_up
},
674 /* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM
,A_R0
},{HEX_C
,HEX_A
,IMM0_8
}, arch_sh1_up
},
676 /* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M
,A_REG_N
},{HEX_2
,REG_N
,REG_M
,HEX_A
}, arch_sh1_up
},
678 /* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM
,A_R0_GBR
},{HEX_C
,HEX_E
,IMM0_8
}, arch_sh1_up
},
680 /* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M
,A_REG_N
},{HEX_2
,REG_N
,REG_M
,HEX_D
}, arch_sh1_up
},
682 /* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M
,A_REG_N
},{HEX_0
,REG_N
,REG_M
,HEX_7
}, arch_sh1_up
},
684 /* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N
},{HEX_4
,REG_N
,HEX_1
,HEX_0
}, arch_sh2_up
},
686 /* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M
,A_REG_N
},{HEX_3
,REG_N
,REG_M
,HEX_D
}, arch_sh2_up
},
688 /* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M
,A_REG_N
},{HEX_3
,REG_N
,REG_M
,HEX_5
}, arch_sh2_up
},
690 /* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M
,A_INC_N
},{HEX_0
,REG_N
,REG_M
,HEX_F
}, arch_sh2_up
},
692 /* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N
},{HEX_0
,REG_N
,HEX_2
,HEX_3
}, arch_sh2_up
},
694 /* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N
},{HEX_0
,REG_N
,HEX_0
,HEX_3
}, arch_sh2_up
},
696 /* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N
,DSP_REG_M
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_0
}, arch_sh_dsp_up
},
698 /* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N
,DSP_REG_M
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_4
}, arch_sh_dsp_up
},
700 /* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N
,DSP_REG_M
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_8
}, arch_sh_dsp_up
},
702 /* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N
,DSP_REG_M
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_C
}, arch_sh_dsp_up
},
704 /* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M
,A_DEC_N
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_1
}, arch_sh_dsp_up
},
706 /* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M
,A_IND_N
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_5
}, arch_sh_dsp_up
},
708 /* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M
,A_INC_N
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_9
}, arch_sh_dsp_up
},
710 /* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M
,AS_PMOD_N
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_D
}, arch_sh_dsp_up
},
712 /* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N
,DSP_REG_M
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_2
}, arch_sh_dsp_up
},
714 /* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N
,DSP_REG_M
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_6
}, arch_sh_dsp_up
},
716 /* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N
,DSP_REG_M
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_A
}, arch_sh_dsp_up
},
718 /* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N
,DSP_REG_M
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_E
}, arch_sh_dsp_up
},
720 /* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M
,A_DEC_N
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_3
}, arch_sh_dsp_up
},
722 /* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M
,A_IND_N
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_7
}, arch_sh_dsp_up
},
724 /* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M
,A_INC_N
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_B
}, arch_sh_dsp_up
},
726 /* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M
,AS_PMOD_N
},{HEX_F
,SDT_REG_N
,REG_M
,HEX_F
}, arch_sh_dsp_up
},
728 /* 0*0*0*00** nopx */ {"nopx",{0},{PPI
,NOPX
}, arch_sh_dsp_up
},
729 /* *0*0*0**00 nopy */ {"nopy",{0},{PPI
,NOPY
}, arch_sh_dsp_up
},
730 /* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N
,DSP_REG_X
},{PPI
,MOVX
,HEX_1
}, arch_sh_dsp_up
},
731 /* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N
,DSP_REG_X
},{PPI
,MOVX
,HEX_2
}, arch_sh_dsp_up
},
732 /* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N
,DSP_REG_X
},{PPI
,MOVX
,HEX_3
}, arch_sh_dsp_up
},
733 /* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M
,AX_IND_N
},{PPI
,MOVX
,HEX_9
}, arch_sh_dsp_up
},
734 /* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M
,AX_INC_N
},{PPI
,MOVX
,HEX_A
}, arch_sh_dsp_up
},
735 /* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M
,AX_PMOD_N
},{PPI
,MOVX
,HEX_B
}, arch_sh_dsp_up
},
737 /* nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> */ {"movx.w",{AXY_IND_N
,DSP_REG_XY
},{PPI
,MOVX_NOPY
,HEX_0
,HEX_4
}, arch_sh4al_dsp_up
},
738 /* nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> */{"movx.w",{AXY_INC_N
,DSP_REG_XY
},{PPI
,MOVX_NOPY
,HEX_0
,HEX_8
}, arch_sh4al_dsp_up
},
739 /* nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.w",{AXY_PMOD_N
,DSP_REG_XY
},{PPI
,MOVX_NOPY
,HEX_0
,HEX_C
}, arch_sh4al_dsp_up
},
740 /* nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> */ {"movx.w",{DSP_REG_AX
,AXY_IND_N
},{PPI
,MOVX_NOPY
,HEX_2
,HEX_4
}, arch_sh4al_dsp_up
},
741 /* nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ */{"movx.w",{DSP_REG_AX
,AXY_INC_N
},{PPI
,MOVX_NOPY
,HEX_2
,HEX_8
}, arch_sh4al_dsp_up
},
742 /* nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.w",{DSP_REG_AX
,AXY_PMOD_N
},{PPI
,MOVX_NOPY
,HEX_2
,HEX_C
}, arch_sh4al_dsp_up
},
744 /* nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> */ {"movx.l",{AXY_IND_N
,DSP_REG_XY
},{PPI
,MOVX_NOPY
,HEX_1
,HEX_4
}, arch_sh4al_dsp_up
},
745 /* nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> */{"movx.l",{AXY_INC_N
,DSP_REG_XY
},{PPI
,MOVX_NOPY
,HEX_1
,HEX_8
}, arch_sh4al_dsp_up
},
746 /* nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.l",{AXY_PMOD_N
,DSP_REG_XY
},{PPI
,MOVX_NOPY
,HEX_1
,HEX_C
}, arch_sh4al_dsp_up
},
747 /* nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> */ {"movx.l",{DSP_REG_AX
,AXY_IND_N
},{PPI
,MOVX_NOPY
,HEX_3
,HEX_4
}, arch_sh4al_dsp_up
},
748 /* nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ */{"movx.l",{DSP_REG_AX
,AXY_INC_N
},{PPI
,MOVX_NOPY
,HEX_3
,HEX_8
}, arch_sh4al_dsp_up
},
749 /* nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.l",{DSP_REG_AX
,AXY_PMOD_N
},{PPI
,MOVX_NOPY
,HEX_3
,HEX_C
}, arch_sh4al_dsp_up
},
751 /* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N
,DSP_REG_Y
},{PPI
,MOVY
,HEX_1
}, arch_sh_dsp_up
},
752 /* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N
,DSP_REG_Y
},{PPI
,MOVY
,HEX_2
}, arch_sh_dsp_up
},
753 /* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N
,DSP_REG_Y
},{PPI
,MOVY
,HEX_3
}, arch_sh_dsp_up
},
754 /* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M
,AY_IND_N
},{PPI
,MOVY
,HEX_9
}, arch_sh_dsp_up
},
755 /* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M
,AY_INC_N
},{PPI
,MOVY
,HEX_A
}, arch_sh_dsp_up
},
756 /* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M
,AY_PMOD_N
},{PPI
,MOVY
,HEX_B
}, arch_sh_dsp_up
},
758 /* nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> */ {"movy.w",{AYX_IND_N
,DSP_REG_YX
},{PPI
,MOVY_NOPX
,HEX_0
,HEX_1
}, arch_sh4al_dsp_up
},
759 /* nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> */{"movy.w",{AYX_INC_N
,DSP_REG_YX
},{PPI
,MOVY_NOPX
,HEX_0
,HEX_2
}, arch_sh4al_dsp_up
},
760 /* nnmm000011 movy.w @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.w",{AYX_PMOD_N
,DSP_REG_YX
},{PPI
,MOVY_NOPX
,HEX_0
,HEX_3
}, arch_sh4al_dsp_up
},
761 /* nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> */ {"movy.w",{DSP_REG_AY
,AYX_IND_N
},{PPI
,MOVY_NOPX
,HEX_1
,HEX_1
}, arch_sh4al_dsp_up
},
762 /* nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.w",{DSP_REG_AY
,AYX_INC_N
},{PPI
,MOVY_NOPX
,HEX_1
,HEX_2
}, arch_sh4al_dsp_up
},
763 /* nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.w",{DSP_REG_AY
,AYX_PMOD_N
},{PPI
,MOVY_NOPX
,HEX_1
,HEX_3
}, arch_sh4al_dsp_up
},
765 /* nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> */ {"movy.l",{AYX_IND_N
,DSP_REG_YX
},{PPI
,MOVY_NOPX
,HEX_2
,HEX_1
}, arch_sh4al_dsp_up
},
766 /* nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> */{"movy.l",{AYX_INC_N
,DSP_REG_YX
},{PPI
,MOVY_NOPX
,HEX_2
,HEX_2
}, arch_sh4al_dsp_up
},
767 /* nnmm100011 movy.l @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.l",{AYX_PMOD_N
,DSP_REG_YX
},{PPI
,MOVY_NOPX
,HEX_2
,HEX_3
}, arch_sh4al_dsp_up
},
768 /* nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> */ {"movy.l",{DSP_REG_AY
,AYX_IND_N
},{PPI
,MOVY_NOPX
,HEX_3
,HEX_1
}, arch_sh4al_dsp_up
},
769 /* nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.l",{DSP_REG_AY
,AYX_INC_N
},{PPI
,MOVY_NOPX
,HEX_3
,HEX_2
}, arch_sh4al_dsp_up
},
770 /* nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.l",{DSP_REG_AY
,AYX_PMOD_N
},{PPI
,MOVY_NOPX
,HEX_3
,HEX_3
}, arch_sh4al_dsp_up
},
772 /* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E
,DSP_REG_F
,DSP_REG_G
},{PPI
,PMUL
}, arch_sh_dsp_up
},
773 /* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
774 {"psubc",{DSP_REG_X
,DSP_REG_Y
,DSP_REG_N
},{PPI
,PPI3
,HEX_A
,HEX_0
}, arch_sh_dsp_up
},
775 /* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
776 {"paddc",{DSP_REG_X
,DSP_REG_Y
,DSP_REG_N
},{PPI
,PPI3
,HEX_B
,HEX_0
}, arch_sh_dsp_up
},
777 /* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */
778 {"pcmp", {DSP_REG_X
,DSP_REG_Y
},{PPI
,PPI3
,HEX_8
,HEX_4
}, arch_sh_dsp_up
},
779 /* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
780 {"pwsb", {DSP_REG_X
,DSP_REG_Y
,DSP_REG_N
},{PPI
,PPI3
,HEX_A
,HEX_4
}, arch_sh_dsp_up
},
781 /* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
782 {"pwad", {DSP_REG_X
,DSP_REG_Y
,DSP_REG_N
},{PPI
,PPI3
,HEX_B
,HEX_4
}, arch_sh_dsp_up
},
783 /* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */
784 {"pabs", {DSP_REG_X
,DSP_REG_N
},{PPI
,PPI3NC
,HEX_8
,HEX_8
}, arch_sh_dsp_up
},
785 /* 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> */
786 {"pabs", {DSP_REG_X
,DSP_REG_N
},{PPI
,PPIC
,HEX_8
,HEX_9
,HEX_1
}, arch_sh4al_dsp_up
},
787 /* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
788 {"pabs", {DSP_REG_Y
,DSP_REG_N
},{PPI
,PPI3NC
,HEX_A
,HEX_8
}, arch_sh_dsp_up
},
789 /* 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
790 {"pabs", {DSP_REG_Y
,DSP_REG_N
},{PPI
,PPIC
,HEX_A
,HEX_9
,HEX_4
}, arch_sh4al_dsp_up
},
791 /* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */
792 {"prnd", {DSP_REG_X
,DSP_REG_N
},{PPI
,PPI3NC
,HEX_9
,HEX_8
}, arch_sh_dsp_up
},
793 /* 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> */
794 {"prnd", {DSP_REG_X
,DSP_REG_N
},{PPI
,PPIC
,HEX_9
,HEX_9
,HEX_1
}, arch_sh4al_dsp_up
},
795 /* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
796 {"prnd", {DSP_REG_Y
,DSP_REG_N
},{PPI
,PPI3NC
,HEX_B
,HEX_8
}, arch_sh_dsp_up
},
797 /* 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
798 {"prnd", {DSP_REG_Y
,DSP_REG_N
},{PPI
,PPIC
,HEX_B
,HEX_9
,HEX_4
}, arch_sh4al_dsp_up
},
800 {"dct",{0},{PPI
,PDC
,HEX_1
}, arch_sh_dsp_up
},
801 {"dcf",{0},{PPI
,PDC
,HEX_2
}, arch_sh_dsp_up
},
803 /* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
804 {"pshl", {DSP_REG_X
,DSP_REG_Y
,DSP_REG_N
},{PPI
,PPIC
,HEX_8
,HEX_1
}, arch_sh_dsp_up
},
805 /* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM
,DSP_REG_N
},{PPI
,PSH
,HEX_0
}, arch_sh_dsp_up
},
806 /* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
807 {"psha", {DSP_REG_X
,DSP_REG_Y
,DSP_REG_N
},{PPI
,PPIC
,HEX_9
,HEX_1
}, arch_sh_dsp_up
},
808 /* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM
,DSP_REG_N
},{PPI
,PSH
,HEX_1
}, arch_sh_dsp_up
},
809 /* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
810 {"psub", {DSP_REG_X
,DSP_REG_Y
,DSP_REG_N
},{PPI
,PPIC
,HEX_A
,HEX_1
}, arch_sh_dsp_up
},
811 /* 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> */
812 {"psub", {DSP_REG_Y
,DSP_REG_X
,DSP_REG_N
},{PPI
,PPIC
,HEX_8
,HEX_5
}, arch_sh4al_dsp_up
},
813 /* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
814 {"padd", {DSP_REG_X
,DSP_REG_Y
,DSP_REG_N
},{PPI
,PPIC
,HEX_B
,HEX_1
}, arch_sh_dsp_up
},
815 /* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
816 {"pand", {DSP_REG_X
,DSP_REG_Y
,DSP_REG_N
},{PPI
,PPIC
,HEX_9
,HEX_5
}, arch_sh_dsp_up
},
817 /* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
818 {"pxor", {DSP_REG_X
,DSP_REG_Y
,DSP_REG_N
},{PPI
,PPIC
,HEX_A
,HEX_5
}, arch_sh_dsp_up
},
819 /* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
820 {"por", {DSP_REG_X
,DSP_REG_Y
,DSP_REG_N
},{PPI
,PPIC
,HEX_B
,HEX_5
}, arch_sh_dsp_up
},
821 /* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */
822 {"pdec", {DSP_REG_X
,DSP_REG_N
},{PPI
,PPIC
,HEX_8
,HEX_9
}, arch_sh_dsp_up
},
823 /* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */
824 {"pdec", {DSP_REG_Y
,DSP_REG_N
},{PPI
,PPIC
,HEX_A
,HEX_9
}, arch_sh_dsp_up
},
825 /* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */
826 {"pinc", {DSP_REG_X
,DSP_REG_N
},{PPI
,PPIC
,HEX_9
,HEX_9
,HEX_XX00
}, arch_sh_dsp_up
},
827 /* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */
828 {"pinc", {DSP_REG_Y
,DSP_REG_N
},{PPI
,PPIC
,HEX_B
,HEX_9
,HEX_00YY
}, arch_sh_dsp_up
},
829 /* 10001101xxyynnnn pclr <DSP_REG_N> */
830 {"pclr", {DSP_REG_N
},{PPI
,PPIC
,HEX_8
,HEX_D
}, arch_sh_dsp_up
},
831 /* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */
832 {"pdmsb", {DSP_REG_X
,DSP_REG_N
},{PPI
,PPIC
,HEX_9
,HEX_D
,HEX_XX00
}, arch_sh_dsp_up
},
833 /* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */
834 {"pdmsb", {DSP_REG_Y
,DSP_REG_N
},{PPI
,PPIC
,HEX_B
,HEX_D
,HEX_00YY
}, arch_sh_dsp_up
},
835 /* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */
836 {"pneg", {DSP_REG_X
,DSP_REG_N
},{PPI
,PPIC
,HEX_C
,HEX_9
}, arch_sh_dsp_up
},
837 /* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */
838 {"pneg", {DSP_REG_Y
,DSP_REG_N
},{PPI
,PPIC
,HEX_E
,HEX_9
}, arch_sh_dsp_up
},
839 /* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */
840 {"pcopy", {DSP_REG_X
,DSP_REG_N
},{PPI
,PPIC
,HEX_D
,HEX_9
}, arch_sh_dsp_up
},
841 /* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */
842 {"pcopy", {DSP_REG_Y
,DSP_REG_N
},{PPI
,PPIC
,HEX_F
,HEX_9
}, arch_sh_dsp_up
},
843 /* 11001101xxyynnnn psts MACH,<DSP_REG_N> */
844 {"psts", {A_MACH
,DSP_REG_N
},{PPI
,PPIC
,HEX_C
,HEX_D
}, arch_sh_dsp_up
},
845 /* 11011101xxyynnnn psts MACL,<DSP_REG_N> */
846 {"psts", {A_MACL
,DSP_REG_N
},{PPI
,PPIC
,HEX_D
,HEX_D
}, arch_sh_dsp_up
},
847 /* 11101101xxyynnnn plds <DSP_REG_N>,MACH */
848 {"plds", {DSP_REG_N
,A_MACH
},{PPI
,PPIC
,HEX_E
,HEX_D
}, arch_sh_dsp_up
},
849 /* 11111101xxyynnnn plds <DSP_REG_N>,MACL */
850 {"plds", {DSP_REG_N
,A_MACL
},{PPI
,PPIC
,HEX_F
,HEX_D
}, arch_sh_dsp_up
},
851 /* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */
852 {"pswap", {DSP_REG_X
,DSP_REG_N
},{PPI
,PPIC
,HEX_9
,HEX_D
,HEX_1
}, arch_sh4al_dsp_up
},
853 /* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */
854 {"pswap", {DSP_REG_Y
,DSP_REG_N
},{PPI
,PPIC
,HEX_B
,HEX_D
,HEX_4
}, arch_sh4al_dsp_up
},
856 /* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N
},{HEX_F
,REG_N
,HEX_5
,HEX_D
}, arch_sh2e_up
},
857 /* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N
},{HEX_F
,REG_N
,HEX_5
,HEX_D
}, arch_sh4_up
},
859 /* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M
,F_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_0
}, arch_sh2e_up
},
860 /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M
,D_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_0
}, arch_sh4_up
},
862 /* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M
,F_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_4
}, arch_sh2e_up
},
863 /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M
,D_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_4
}, arch_sh4_up
},
865 /* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M
,F_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_5
}, arch_sh2e_up
},
866 /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M
,D_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_5
}, arch_sh4_up
},
868 /* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N
,FPUL_M
},{HEX_F
,REG_N_D
,HEX_B
,HEX_D
}, arch_sh4_up
},
870 /* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M
,D_REG_N
},{HEX_F
,REG_N_D
,HEX_A
,HEX_D
}, arch_sh4_up
},
872 /* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M
,F_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_3
}, arch_sh2e_up
},
873 /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M
,D_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_3
}, arch_sh4_up
},
875 /* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M
,V_REG_N
},{HEX_F
,REG_NM
,HEX_E
,HEX_D
}, arch_sh4_up
},
877 /* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N
},{HEX_F
,REG_N
,HEX_8
,HEX_D
}, arch_sh2e_up
},
879 /* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N
},{HEX_F
,REG_N
,HEX_9
,HEX_D
}, arch_sh2e_up
},
881 /* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N
,FPUL_M
},{HEX_F
,REG_N
,HEX_1
,HEX_D
}, arch_sh2e_up
},
883 /* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M
,F_REG_N
},{HEX_F
,REG_N
,HEX_2
,HEX_D
}, arch_sh2e_up
},
884 /* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M
,D_REG_N
},{HEX_F
,REG_N
,HEX_2
,HEX_D
}, arch_sh4_up
},
886 /* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0
,F_REG_M
,F_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_E
}, arch_sh2e_up
},
888 /* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M
,F_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_C
}, arch_sh2e_up
},
889 /* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M
,DX_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_C
}, arch_sh4_up
},
891 /* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M
,F_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_8
}, arch_sh2e_up
},
892 /* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M
,DX_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_8
}, arch_sh4_up
},
894 /* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M
,A_IND_N
},{HEX_F
,REG_N
,REG_M
,HEX_A
}, arch_sh2e_up
},
895 /* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M
,A_IND_N
},{HEX_F
,REG_N
,REG_M
,HEX_A
}, arch_sh4_up
},
897 /* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M
,F_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_9
}, arch_sh2e_up
},
898 /* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M
,DX_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_9
}, arch_sh4_up
},
900 /* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M
,A_DEC_N
},{HEX_F
,REG_N
,REG_M
,HEX_B
}, arch_sh2e_up
},
901 /* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M
,A_DEC_N
},{HEX_F
,REG_N
,REG_M
,HEX_B
}, arch_sh4_up
},
903 /* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M
,F_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_6
}, arch_sh2e_up
},
904 /* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M
,DX_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_6
}, arch_sh4_up
},
906 /* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M
,A_IND_R0_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_7
}, arch_sh2e_up
},
907 /* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M
,A_IND_R0_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_7
}, arch_sh4_up
},
909 /* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M
,DX_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_8
}, arch_sh4_up
},
911 /* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M
,A_IND_N
},{HEX_F
,REG_N
,REG_M
,HEX_A
}, arch_sh4_up
},
913 /* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M
,DX_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_9
}, arch_sh4_up
},
915 /* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M
,A_DEC_N
},{HEX_F
,REG_N
,REG_M
,HEX_B
}, arch_sh4_up
},
917 /* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M
,DX_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_6
}, arch_sh4_up
},
919 /* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M
,A_IND_R0_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_7
}, arch_sh4_up
},
921 /* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M
,F_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_8
}, arch_sh2e_up
},
923 /* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M
,A_IND_N
},{HEX_F
,REG_N
,REG_M
,HEX_A
}, arch_sh2e_up
},
925 /* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M
,F_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_9
}, arch_sh2e_up
},
927 /* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M
,A_DEC_N
},{HEX_F
,REG_N
,REG_M
,HEX_B
}, arch_sh2e_up
},
929 /* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M
,F_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_6
}, arch_sh2e_up
},
931 /* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M
,A_IND_R0_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_7
}, arch_sh2e_up
},
933 /* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M
,F_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_2
}, arch_sh2e_up
},
934 /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M
,D_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_2
}, arch_sh4_up
},
936 /* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N
},{HEX_F
,REG_N
,HEX_4
,HEX_D
}, arch_sh2e_up
},
937 /* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N
},{HEX_F
,REG_N
,HEX_4
,HEX_D
}, arch_sh4_up
},
939 /* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F
,HEX_7
,HEX_F
,HEX_D
}, arch_sh4a_up
},
941 /* 1111101111111101 frchg */{"frchg",{0},{HEX_F
,HEX_B
,HEX_F
,HEX_D
}, arch_sh4_up
},
943 /* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M
,D_REG_N
},{HEX_F
,REG_N_D
,HEX_F
,HEX_D
}, arch_sh4_up
},
945 /* 1111001111111101 fschg */{"fschg",{0},{HEX_F
,HEX_3
,HEX_F
,HEX_D
}, arch_sh4_up
},
947 /* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N
},{HEX_F
,REG_N
,HEX_6
,HEX_D
}, arch_sh3e_up
},
948 /* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N
},{HEX_F
,REG_N
,HEX_6
,HEX_D
}, arch_sh4_up
},
950 /* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N
},{HEX_F
,REG_N
,HEX_7
,HEX_D
}, arch_sh4_up
},
952 /* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M
,F_REG_N
},{HEX_F
,REG_N
,HEX_0
,HEX_D
}, arch_sh2e_up
},
954 /* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M
,F_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_1
}, arch_sh2e_up
},
955 /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M
,D_REG_N
},{HEX_F
,REG_N
,REG_M
,HEX_1
}, arch_sh4_up
},
957 /* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N
,FPUL_M
},{HEX_F
,REG_N
,HEX_3
,HEX_D
}, arch_sh2e_up
},
958 /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N
,FPUL_M
},{HEX_F
,REG_N
,HEX_3
,HEX_D
}, arch_sh4_up
},
960 /* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4
,V_REG_N
},{HEX_F
,REG_N_B01
,HEX_F
,HEX_D
}, arch_sh4_up
},
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