1 /* Disassembly routines for TMS320C30 architecture
2 Copyright (C) 1998-2019 Free Software Foundation, Inc.
3 Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
25 #include "disassemble.h"
26 #include "opcode/tic30.h"
29 #define PARALLEL_INSN 2
31 /* Gets the type of instruction based on the top 2 or 3 bits of the
33 #define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000)
35 /* Instruction types. */
36 #define TWO_OPERAND_1 0x00000000
37 #define TWO_OPERAND_2 0x40000000
38 #define THREE_OPERAND 0x20000000
39 #define PAR_STORE 0xC0000000
40 #define MUL_ADDS 0x80000000
41 #define BRANCHES 0x60000000
43 /* Specific instruction id bits. */
44 #define NORMAL_IDEN 0x1F800000
45 #define PAR_STORE_IDEN 0x3E000000
46 #define MUL_ADD_IDEN 0x2C000000
47 #define BR_IMM_IDEN 0x1F000000
48 #define BR_COND_IDEN 0x1C3F0000
50 /* Addressing modes. */
51 #define AM_REGISTER 0x00000000
52 #define AM_DIRECT 0x00200000
53 #define AM_INDIRECT 0x00400000
54 #define AM_IMM 0x00600000
56 #define P_FIELD 0x03000000
59 #define LDP_INSN 0x08700000
61 /* TMS320C30 program counter for current instruction. */
62 static unsigned int _pc
;
72 get_tic30_instruction (unsigned long insn_word
, struct instruction
*insn
)
74 switch (GET_TYPE (insn_word
))
79 insn
->type
= NORMAL_INSN
;
81 insn_template
*current_optab
= (insn_template
*) tic30_optab
;
83 for (; current_optab
< tic30_optab_end
; current_optab
++)
85 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
87 if (current_optab
->operands
== 0)
89 if (current_optab
->base_opcode
== insn_word
)
91 insn
->tm
= current_optab
;
95 else if ((current_optab
->base_opcode
& NORMAL_IDEN
) == (insn_word
& NORMAL_IDEN
))
97 insn
->tm
= current_optab
;
106 insn
->type
= PARALLEL_INSN
;
108 partemplate
*current_optab
= (partemplate
*) tic30_paroptab
;
110 for (; current_optab
< tic30_paroptab_end
; current_optab
++)
112 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
114 if ((current_optab
->base_opcode
& PAR_STORE_IDEN
)
115 == (insn_word
& PAR_STORE_IDEN
))
117 insn
->ptm
= current_optab
;
126 insn
->type
= PARALLEL_INSN
;
128 partemplate
*current_optab
= (partemplate
*) tic30_paroptab
;
130 for (; current_optab
< tic30_paroptab_end
; current_optab
++)
132 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
134 if ((current_optab
->base_opcode
& MUL_ADD_IDEN
)
135 == (insn_word
& MUL_ADD_IDEN
))
137 insn
->ptm
= current_optab
;
146 insn
->type
= NORMAL_INSN
;
148 insn_template
*current_optab
= (insn_template
*) tic30_optab
;
150 for (; current_optab
< tic30_optab_end
; current_optab
++)
152 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
154 if (current_optab
->operand_types
[0] & Imm24
)
156 if ((current_optab
->base_opcode
& BR_IMM_IDEN
)
157 == (insn_word
& BR_IMM_IDEN
))
159 insn
->tm
= current_optab
;
163 else if (current_optab
->operands
> 0)
165 if ((current_optab
->base_opcode
& BR_COND_IDEN
)
166 == (insn_word
& BR_COND_IDEN
))
168 insn
->tm
= current_optab
;
174 if ((current_optab
->base_opcode
& (BR_COND_IDEN
| 0x00800000))
175 == (insn_word
& (BR_COND_IDEN
| 0x00800000)))
177 insn
->tm
= current_optab
;
192 get_register_operand (unsigned char fragment
, char *buffer
)
194 const reg
*current_reg
= tic30_regtab
;
198 for (; current_reg
< tic30_regtab_end
; current_reg
++)
200 if ((fragment
& 0x1F) == current_reg
->opcode
)
202 strcpy (buffer
, current_reg
->name
);
210 get_indirect_operand (unsigned short fragment
,
220 /* Determine which bits identify the sections of the indirect
221 operand based on the size in bytes. */
225 mod
= (fragment
& 0x00F8) >> 3;
226 arnum
= (fragment
& 0x0007);
230 mod
= (fragment
& 0xF800) >> 11;
231 arnum
= (fragment
& 0x0700) >> 8;
232 disp
= (fragment
& 0x00FF);
238 const ind_addr_type
*current_ind
= tic30_indaddr_tab
;
240 for (; current_ind
< tic30_indaddrtab_end
; current_ind
++)
242 if (current_ind
->modfield
== mod
)
244 if (current_ind
->displacement
== IMPLIED_DISP
&& size
== 2)
252 len
= strlen (current_ind
->syntax
);
253 for (i
= 0, bufcnt
= 0; i
< len
; i
++, bufcnt
++)
255 buffer
[bufcnt
] = current_ind
->syntax
[i
];
257 && buffer
[bufcnt
- 1] == 'a'
258 && buffer
[bufcnt
] == 'r')
259 buffer
[++bufcnt
] = arnum
+ '0';
260 if (buffer
[bufcnt
] == '('
261 && current_ind
->displacement
== DISP_REQUIRED
)
263 sprintf (&buffer
[bufcnt
+ 1], "%u", disp
);
264 bufcnt
+= strlen (&buffer
[bufcnt
+ 1]);
267 buffer
[bufcnt
+ 1] = '\0';
277 cnvt_tmsfloat_ieee (unsigned long tmsfloat
, int size
, float *ieeefloat
)
279 unsigned long exponent
, sign
, mant
;
288 if ((tmsfloat
& 0x0000F000) == 0x00008000)
289 tmsfloat
= 0x80000000;
293 tmsfloat
= (long) tmsfloat
>> 4;
296 exponent
= tmsfloat
& 0xFF000000;
297 if (exponent
== 0x80000000)
302 exponent
+= 0x7F000000;
303 sign
= (tmsfloat
& 0x00800000) << 8;
304 mant
= tmsfloat
& 0x007FFFFF;
305 if (exponent
== 0xFF000000)
311 *ieeefloat
= HUGE_VALF
;
313 *ieeefloat
= -HUGE_VALF
;
316 *ieeefloat
= 1.0 / 0.0;
318 *ieeefloat
= -1.0 / 0.0;
325 mant
= (~mant
) & 0x007FFFFF;
327 exponent
+= mant
& 0x00800000;
328 exponent
&= 0x7F800000;
331 if (tmsfloat
== 0x80000000)
332 sign
= mant
= exponent
= 0;
333 tmsfloat
= sign
| exponent
| mant
;
340 print_two_operand (disassemble_info
*info
,
341 unsigned long insn_word
,
342 struct instruction
*insn
)
345 char operand
[2][13] =
352 if (insn
->tm
== NULL
)
354 strcpy (name
, insn
->tm
->name
);
355 if (insn
->tm
->opcode_modifier
== AddressMode
)
358 /* Determine whether instruction is a store or a normal instruction. */
359 if ((insn
->tm
->operand_types
[1] & (Direct
| Indirect
))
360 == (Direct
| Indirect
))
370 /* Get the destination register. */
371 if (insn
->tm
->operands
== 2)
372 get_register_operand ((insn_word
& 0x001F0000) >> 16, operand
[dest_op
]);
373 /* Get the source operand based on addressing mode. */
374 switch (insn_word
& AddressMode
)
377 /* Check for the NOP instruction before getting the operand. */
378 if ((insn
->tm
->operand_types
[0] & NotReq
) == 0)
379 get_register_operand ((insn_word
& 0x0000001F), operand
[src_op
]);
382 sprintf (operand
[src_op
], "@0x%lX", (insn_word
& 0x0000FFFF));
385 get_indirect_operand ((insn_word
& 0x0000FFFF), 2, operand
[src_op
]);
388 /* Get the value of the immediate operand based on variable type. */
389 switch (insn
->tm
->imm_arg_type
)
392 cnvt_tmsfloat_ieee ((insn_word
& 0x0000FFFF), 2, &f_number
);
393 sprintf (operand
[src_op
], "%2.2f", f_number
);
396 sprintf (operand
[src_op
], "%d", (short) (insn_word
& 0x0000FFFF));
399 sprintf (operand
[src_op
], "%lu", (insn_word
& 0x0000FFFF));
404 /* Handle special case for LDP instruction. */
405 if ((insn_word
& 0xFFFFFF00) == LDP_INSN
)
407 strcpy (name
, "ldp");
408 sprintf (operand
[0], "0x%06lX", (insn_word
& 0x000000FF) << 16);
409 operand
[1][0] = '\0';
413 /* Handle case for stack and rotate instructions. */
414 else if (insn
->tm
->operands
== 1)
416 if (insn
->tm
->opcode_modifier
== StackOp
)
417 get_register_operand ((insn_word
& 0x001F0000) >> 16, operand
[0]);
419 /* Output instruction to stream. */
420 info
->fprintf_func (info
->stream
, " %s %s%c%s", name
,
421 operand
[0][0] ? operand
[0] : "",
422 operand
[1][0] ? ',' : ' ',
423 operand
[1][0] ? operand
[1] : "");
428 print_three_operand (disassemble_info
*info
,
429 unsigned long insn_word
,
430 struct instruction
*insn
)
432 char operand
[3][13] =
439 if (insn
->tm
== NULL
)
441 switch (insn_word
& AddressMode
)
444 get_register_operand ((insn_word
& 0x000000FF), operand
[0]);
445 get_register_operand ((insn_word
& 0x0000FF00) >> 8, operand
[1]);
448 get_register_operand ((insn_word
& 0x000000FF), operand
[0]);
449 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1]);
452 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0]);
453 get_register_operand ((insn_word
& 0x0000FF00) >> 8, operand
[1]);
456 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0]);
457 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1]);
462 if (insn
->tm
->operands
== 3)
463 get_register_operand ((insn_word
& 0x001F0000) >> 16, operand
[2]);
464 info
->fprintf_func (info
->stream
, " %s %s,%s%c%s", insn
->tm
->name
,
465 operand
[0], operand
[1],
466 operand
[2][0] ? ',' : ' ',
467 operand
[2][0] ? operand
[2] : "");
472 print_par_insn (disassemble_info
*info
,
473 unsigned long insn_word
,
474 struct instruction
*insn
)
478 char operand
[2][3][13] =
492 if (insn
->ptm
== NULL
)
494 /* Parse out the names of each of the parallel instructions from the
495 q_insn1_insn2 format. */
496 name1
= (char *) strdup (insn
->ptm
->name
+ 2);
498 len
= strlen (name1
);
499 for (i
= 0; i
< len
; i
++)
503 name2
= &name1
[i
+ 1];
508 /* Get the operands of the instruction based on the operand order. */
509 switch (insn
->ptm
->oporder
)
512 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][0]);
513 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
514 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
515 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][1]);
518 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][0]);
519 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][0]);
520 get_register_operand ((insn_word
>> 19) & 0x07, operand
[1][1]);
521 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][1]);
524 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][1]);
525 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
526 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
527 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][0]);
530 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][0]);
531 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
532 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
533 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][1]);
534 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][2]);
537 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][1]);
538 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
539 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
540 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][0]);
541 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][2]);
544 if (insn_word
& 0x00800000)
545 get_register_operand (0x01, operand
[0][2]);
547 get_register_operand (0x00, operand
[0][2]);
548 if (insn_word
& 0x00400000)
549 get_register_operand (0x03, operand
[1][2]);
551 get_register_operand (0x02, operand
[1][2]);
552 switch (insn_word
& P_FIELD
)
555 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][1]);
556 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[0][0]);
557 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][1]);
558 get_register_operand ((insn_word
>> 19) & 0x07, operand
[1][0]);
561 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[1][0]);
562 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[0][0]);
563 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][1]);
564 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][1]);
567 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[1][1]);
568 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][0]);
569 get_register_operand ((insn_word
>> 16) & 0x07, operand
[0][1]);
570 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][0]);
573 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[1][1]);
574 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[0][0]);
575 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
576 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][1]);
583 info
->fprintf_func (info
->stream
, " %s %s,%s%c%s", name1
,
584 operand
[0][0], operand
[0][1],
585 operand
[0][2][0] ? ',' : ' ',
586 operand
[0][2][0] ? operand
[0][2] : "");
587 info
->fprintf_func (info
->stream
, "\n\t\t\t|| %s %s,%s%c%s", name2
,
588 operand
[1][0], operand
[1][1],
589 operand
[1][2][0] ? ',' : ' ',
590 operand
[1][2][0] ? operand
[1][2] : "");
596 print_branch (disassemble_info
*info
,
597 unsigned long insn_word
,
598 struct instruction
*insn
)
600 char operand
[2][13] =
605 unsigned long address
;
608 if (insn
->tm
== NULL
)
610 /* Get the operands for 24-bit immediate jumps. */
611 if (insn
->tm
->operand_types
[0] & Imm24
)
613 address
= insn_word
& 0x00FFFFFF;
614 sprintf (operand
[0], "0x%lX", address
);
617 /* Get the operand for the trap instruction. */
618 else if (insn
->tm
->operand_types
[0] & IVector
)
620 address
= insn_word
& 0x0000001F;
621 sprintf (operand
[0], "0x%lX", address
);
625 address
= insn_word
& 0x0000FFFF;
626 /* Get the operands for the DB instructions. */
627 if (insn
->tm
->operands
== 2)
629 get_register_operand (((insn_word
& 0x01C00000) >> 22) + REG_AR0
, operand
[0]);
630 if (insn_word
& PCRel
)
632 sprintf (operand
[1], "%d", (short) address
);
636 get_register_operand (insn_word
& 0x0000001F, operand
[1]);
638 /* Get the operands for the standard branches. */
639 else if (insn
->tm
->operands
== 1)
641 if (insn_word
& PCRel
)
643 address
= (short) address
;
644 sprintf (operand
[0], "%ld", address
);
648 get_register_operand (insn_word
& 0x0000001F, operand
[0]);
651 info
->fprintf_func (info
->stream
, " %s %s%c%s", insn
->tm
->name
,
652 operand
[0][0] ? operand
[0] : "",
653 operand
[1][0] ? ',' : ' ',
654 operand
[1][0] ? operand
[1] : "");
655 /* Print destination of branch in relation to current symbol. */
656 if (print_label
&& info
->symbols
)
658 asymbol
*sym
= *info
->symbols
;
660 if ((insn
->tm
->opcode_modifier
== PCRel
) && (insn_word
& PCRel
))
662 address
= (_pc
+ 1 + (short) address
) - ((sym
->section
->vma
+ sym
->value
) / 4);
663 /* Check for delayed instruction, if so adjust destination. */
664 if (insn_word
& 0x00200000)
669 address
-= ((sym
->section
->vma
+ sym
->value
) / 4);
672 info
->fprintf_func (info
->stream
, " <%s>", sym
->name
);
674 info
->fprintf_func (info
->stream
, " <%s %c %lu>", sym
->name
,
675 ((short) address
< 0) ? '-' : '+',
682 print_insn_tic30 (bfd_vma pc
, disassemble_info
*info
)
684 unsigned long insn_word
;
685 struct instruction insn
= { 0, NULL
, NULL
};
686 bfd_vma bufaddr
= pc
- info
->buffer_vma
;
688 /* Obtain the current instruction word from the buffer. */
689 insn_word
= (*(info
->buffer
+ bufaddr
) << 24) | (*(info
->buffer
+ bufaddr
+ 1) << 16) |
690 (*(info
->buffer
+ bufaddr
+ 2) << 8) | *(info
->buffer
+ bufaddr
+ 3);
692 /* Get the instruction refered to by the current instruction word
693 and print it out based on its type. */
694 if (!get_tic30_instruction (insn_word
, &insn
))
696 switch (GET_TYPE (insn_word
))
700 if (!print_two_operand (info
, insn_word
, &insn
))
704 if (!print_three_operand (info
, insn_word
, &insn
))
709 if (!print_par_insn (info
, insn_word
, &insn
))
713 if (!print_branch (info
, insn_word
, &insn
))
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