1 /* Disassembly routines for TMS320C30 architecture
2 Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
24 #include "opcode/tic30.h"
27 #define PARALLEL_INSN 2
29 /* Gets the type of instruction based on the top 2 or 3 bits of the
31 #define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000)
33 /* Instruction types. */
34 #define TWO_OPERAND_1 0x00000000
35 #define TWO_OPERAND_2 0x40000000
36 #define THREE_OPERAND 0x20000000
37 #define PAR_STORE 0xC0000000
38 #define MUL_ADDS 0x80000000
39 #define BRANCHES 0x60000000
41 /* Specific instruction id bits. */
42 #define NORMAL_IDEN 0x1F800000
43 #define PAR_STORE_IDEN 0x3E000000
44 #define MUL_ADD_IDEN 0x2C000000
45 #define BR_IMM_IDEN 0x1F000000
46 #define BR_COND_IDEN 0x1C3F0000
48 /* Addressing modes. */
49 #define AM_REGISTER 0x00000000
50 #define AM_DIRECT 0x00200000
51 #define AM_INDIRECT 0x00400000
52 #define AM_IMM 0x00600000
54 #define P_FIELD 0x03000000
57 #define LDP_INSN 0x08700000
59 /* TMS320C30 program counter for current instruction. */
60 static unsigned int _pc
;
69 int get_tic30_instruction
PARAMS ((unsigned long, struct instruction
*));
71 PARAMS ((disassemble_info
*, unsigned long, struct instruction
*));
72 int print_three_operand
73 PARAMS ((disassemble_info
*, unsigned long, struct instruction
*));
75 PARAMS ((disassemble_info
*, unsigned long, struct instruction
*));
77 PARAMS ((disassemble_info
*, unsigned long, struct instruction
*));
78 int get_indirect_operand
PARAMS ((unsigned short, int, char *));
79 int get_register_operand
PARAMS ((unsigned char, char *));
80 int cnvt_tmsfloat_ieee
PARAMS ((unsigned long, int, float *));
83 print_insn_tic30 (pc
, info
)
85 disassemble_info
*info
;
87 unsigned long insn_word
;
88 struct instruction insn
= { 0, NULL
, NULL
};
89 bfd_vma bufaddr
= pc
- info
->buffer_vma
;
90 /* Obtain the current instruction word from the buffer. */
91 insn_word
= (*(info
->buffer
+ bufaddr
) << 24) | (*(info
->buffer
+ bufaddr
+ 1) << 16) |
92 (*(info
->buffer
+ bufaddr
+ 2) << 8) | *(info
->buffer
+ bufaddr
+ 3);
94 /* Get the instruction refered to by the current instruction word
95 and print it out based on its type. */
96 if (!get_tic30_instruction (insn_word
, &insn
))
98 switch (GET_TYPE (insn_word
))
102 if (!print_two_operand (info
, insn_word
, &insn
))
106 if (!print_three_operand (info
, insn_word
, &insn
))
111 if (!print_par_insn (info
, insn_word
, &insn
))
115 if (!print_branch (info
, insn_word
, &insn
))
123 get_tic30_instruction (insn_word
, insn
)
124 unsigned long insn_word
;
125 struct instruction
*insn
;
127 switch (GET_TYPE (insn_word
))
132 insn
->type
= NORMAL_INSN
;
134 template *current_optab
= (template *) tic30_optab
;
135 for (; current_optab
< tic30_optab_end
; current_optab
++)
137 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
139 if (current_optab
->operands
== 0)
141 if (current_optab
->base_opcode
== insn_word
)
143 insn
->tm
= current_optab
;
147 else if ((current_optab
->base_opcode
& NORMAL_IDEN
) == (insn_word
& NORMAL_IDEN
))
149 insn
->tm
= current_optab
;
157 insn
->type
= PARALLEL_INSN
;
159 partemplate
*current_optab
= (partemplate
*) tic30_paroptab
;
160 for (; current_optab
< tic30_paroptab_end
; current_optab
++)
162 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
164 if ((current_optab
->base_opcode
& PAR_STORE_IDEN
) == (insn_word
& PAR_STORE_IDEN
))
166 insn
->ptm
= current_optab
;
174 insn
->type
= PARALLEL_INSN
;
176 partemplate
*current_optab
= (partemplate
*) tic30_paroptab
;
177 for (; current_optab
< tic30_paroptab_end
; current_optab
++)
179 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
181 if ((current_optab
->base_opcode
& MUL_ADD_IDEN
) == (insn_word
& MUL_ADD_IDEN
))
183 insn
->ptm
= current_optab
;
191 insn
->type
= NORMAL_INSN
;
193 template *current_optab
= (template *) tic30_optab
;
194 for (; current_optab
< tic30_optab_end
; current_optab
++)
196 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
198 if (current_optab
->operand_types
[0] & Imm24
)
200 if ((current_optab
->base_opcode
& BR_IMM_IDEN
) == (insn_word
& BR_IMM_IDEN
))
202 insn
->tm
= current_optab
;
206 else if (current_optab
->operands
> 0)
208 if ((current_optab
->base_opcode
& BR_COND_IDEN
) == (insn_word
& BR_COND_IDEN
))
210 insn
->tm
= current_optab
;
216 if ((current_optab
->base_opcode
& (BR_COND_IDEN
| 0x00800000)) == (insn_word
& (BR_COND_IDEN
| 0x00800000)))
218 insn
->tm
= current_optab
;
233 print_two_operand (info
, insn_word
, insn
)
234 disassemble_info
*info
;
235 unsigned long insn_word
;
236 struct instruction
*insn
;
239 char operand
[2][13] =
245 if (insn
->tm
== NULL
)
247 strcpy (name
, insn
->tm
->name
);
248 if (insn
->tm
->opcode_modifier
== AddressMode
)
251 /* Determine whether instruction is a store or a normal instruction. */
252 if ((insn
->tm
->operand_types
[1] & (Direct
| Indirect
)) == (Direct
| Indirect
))
262 /* Get the destination register. */
263 if (insn
->tm
->operands
== 2)
264 get_register_operand ((insn_word
& 0x001F0000) >> 16, operand
[dest_op
]);
265 /* Get the source operand based on addressing mode. */
266 switch (insn_word
& AddressMode
)
269 /* Check for the NOP instruction before getting the operand. */
270 if ((insn
->tm
->operand_types
[0] & NotReq
) == 0)
271 get_register_operand ((insn_word
& 0x0000001F), operand
[src_op
]);
274 sprintf (operand
[src_op
], "@0x%lX", (insn_word
& 0x0000FFFF));
277 get_indirect_operand ((insn_word
& 0x0000FFFF), 2, operand
[src_op
]);
280 /* Get the value of the immediate operand based on variable type. */
281 switch (insn
->tm
->imm_arg_type
)
284 cnvt_tmsfloat_ieee ((insn_word
& 0x0000FFFF), 2, &f_number
);
285 sprintf (operand
[src_op
], "%2.2f", f_number
);
288 sprintf (operand
[src_op
], "%d", (short) (insn_word
& 0x0000FFFF));
291 sprintf (operand
[src_op
], "%lu", (insn_word
& 0x0000FFFF));
296 /* Handle special case for LDP instruction. */
297 if ((insn_word
& 0xFFFFFF00) == LDP_INSN
)
299 strcpy (name
, "ldp");
300 sprintf (operand
[0], "0x%06lX", (insn_word
& 0x000000FF) << 16);
301 operand
[1][0] = '\0';
305 /* Handle case for stack and rotate instructions. */
306 else if (insn
->tm
->operands
== 1)
308 if (insn
->tm
->opcode_modifier
== StackOp
)
310 get_register_operand ((insn_word
& 0x001F0000) >> 16, operand
[0]);
313 /* Output instruction to stream. */
314 info
->fprintf_func (info
->stream
, " %s %s%c%s", name
,
315 operand
[0][0] ? operand
[0] : "",
316 operand
[1][0] ? ',' : ' ',
317 operand
[1][0] ? operand
[1] : "");
322 print_three_operand (info
, insn_word
, insn
)
323 disassemble_info
*info
;
324 unsigned long insn_word
;
325 struct instruction
*insn
;
327 char operand
[3][13] =
333 if (insn
->tm
== NULL
)
335 switch (insn_word
& AddressMode
)
338 get_register_operand ((insn_word
& 0x000000FF), operand
[0]);
339 get_register_operand ((insn_word
& 0x0000FF00) >> 8, operand
[1]);
342 get_register_operand ((insn_word
& 0x000000FF), operand
[0]);
343 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1]);
346 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0]);
347 get_register_operand ((insn_word
& 0x0000FF00) >> 8, operand
[1]);
350 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0]);
351 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1]);
356 if (insn
->tm
->operands
== 3)
357 get_register_operand ((insn_word
& 0x001F0000) >> 16, operand
[2]);
358 info
->fprintf_func (info
->stream
, " %s %s,%s%c%s", insn
->tm
->name
,
359 operand
[0], operand
[1],
360 operand
[2][0] ? ',' : ' ',
361 operand
[2][0] ? operand
[2] : "");
366 print_par_insn (info
, insn_word
, insn
)
367 disassemble_info
*info
;
368 unsigned long insn_word
;
369 struct instruction
*insn
;
373 char operand
[2][3][13] =
384 if (insn
->ptm
== NULL
)
386 /* Parse out the names of each of the parallel instructions from the
387 q_insn1_insn2 format. */
388 name1
= (char *) strdup (insn
->ptm
->name
+ 2);
390 len
= strlen (name1
);
391 for (i
= 0; i
< len
; i
++)
395 name2
= &name1
[i
+ 1];
400 /* Get the operands of the instruction based on the operand order. */
401 switch (insn
->ptm
->oporder
)
404 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][0]);
405 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
406 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
407 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][1]);
410 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][0]);
411 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][0]);
412 get_register_operand ((insn_word
>> 19) & 0x07, operand
[1][1]);
413 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][1]);
416 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][1]);
417 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
418 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
419 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][0]);
422 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][0]);
423 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
424 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
425 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][1]);
426 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][2]);
429 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][1]);
430 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
431 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
432 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][0]);
433 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][2]);
436 if (insn_word
& 0x00800000)
437 get_register_operand (0x01, operand
[0][2]);
439 get_register_operand (0x00, operand
[0][2]);
440 if (insn_word
& 0x00400000)
441 get_register_operand (0x03, operand
[1][2]);
443 get_register_operand (0x02, operand
[1][2]);
444 switch (insn_word
& P_FIELD
)
447 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][1]);
448 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[0][0]);
449 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][1]);
450 get_register_operand ((insn_word
>> 19) & 0x07, operand
[1][0]);
453 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[1][0]);
454 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[0][0]);
455 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][1]);
456 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][1]);
459 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[1][1]);
460 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][0]);
461 get_register_operand ((insn_word
>> 16) & 0x07, operand
[0][1]);
462 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][0]);
465 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[1][1]);
466 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[0][0]);
467 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
468 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][1]);
475 info
->fprintf_func (info
->stream
, " %s %s,%s%c%s", name1
,
476 operand
[0][0], operand
[0][1],
477 operand
[0][2][0] ? ',' : ' ',
478 operand
[0][2][0] ? operand
[0][2] : "");
479 info
->fprintf_func (info
->stream
, "\n\t\t\t|| %s %s,%s%c%s", name2
,
480 operand
[1][0], operand
[1][1],
481 operand
[1][2][0] ? ',' : ' ',
482 operand
[1][2][0] ? operand
[1][2] : "");
488 print_branch (info
, insn_word
, insn
)
489 disassemble_info
*info
;
490 unsigned long insn_word
;
491 struct instruction
*insn
;
493 char operand
[2][13] =
497 unsigned long address
;
500 if (insn
->tm
== NULL
)
502 /* Get the operands for 24-bit immediate jumps. */
503 if (insn
->tm
->operand_types
[0] & Imm24
)
505 address
= insn_word
& 0x00FFFFFF;
506 sprintf (operand
[0], "0x%lX", address
);
509 /* Get the operand for the trap instruction. */
510 else if (insn
->tm
->operand_types
[0] & IVector
)
512 address
= insn_word
& 0x0000001F;
513 sprintf (operand
[0], "0x%lX", address
);
517 address
= insn_word
& 0x0000FFFF;
518 /* Get the operands for the DB instructions. */
519 if (insn
->tm
->operands
== 2)
521 get_register_operand (((insn_word
& 0x01C00000) >> 22) + REG_AR0
, operand
[0]);
522 if (insn_word
& PCRel
)
524 sprintf (operand
[1], "%d", (short) address
);
528 get_register_operand (insn_word
& 0x0000001F, operand
[1]);
530 /* Get the operands for the standard branches. */
531 else if (insn
->tm
->operands
== 1)
533 if (insn_word
& PCRel
)
535 address
= (short) address
;
536 sprintf (operand
[0], "%ld", address
);
540 get_register_operand (insn_word
& 0x0000001F, operand
[0]);
543 info
->fprintf_func (info
->stream
, " %s %s%c%s", insn
->tm
->name
,
544 operand
[0][0] ? operand
[0] : "",
545 operand
[1][0] ? ',' : ' ',
546 operand
[1][0] ? operand
[1] : "");
547 /* Print destination of branch in relation to current symbol. */
548 if (print_label
&& info
->symbols
)
550 asymbol
*sym
= *info
->symbols
;
552 if ((insn
->tm
->opcode_modifier
== PCRel
) && (insn_word
& PCRel
))
554 address
= (_pc
+ 1 + (short) address
) - ((sym
->section
->vma
+ sym
->value
) / 4);
555 /* Check for delayed instruction, if so adjust destination. */
556 if (insn_word
& 0x00200000)
561 address
-= ((sym
->section
->vma
+ sym
->value
) / 4);
564 info
->fprintf_func (info
->stream
, " <%s>", sym
->name
);
566 info
->fprintf_func (info
->stream
, " <%s %c %d>", sym
->name
,
567 ((short) address
< 0) ? '-' : '+',
574 get_indirect_operand (fragment
, size
, buffer
)
575 unsigned short fragment
;
585 /* Determine which bits identify the sections of the indirect
586 operand based on the size in bytes. */
590 mod
= (fragment
& 0x00F8) >> 3;
591 arnum
= (fragment
& 0x0007);
595 mod
= (fragment
& 0xF800) >> 11;
596 arnum
= (fragment
& 0x0700) >> 8;
597 disp
= (fragment
& 0x00FF);
603 const ind_addr_type
*current_ind
= tic30_indaddr_tab
;
604 for (; current_ind
< tic30_indaddrtab_end
; current_ind
++)
606 if (current_ind
->modfield
== mod
)
608 if (current_ind
->displacement
== IMPLIED_DISP
&& size
== 2)
617 len
= strlen (current_ind
->syntax
);
618 for (i
= 0, bufcnt
= 0; i
< len
; i
++, bufcnt
++)
620 buffer
[bufcnt
] = current_ind
->syntax
[i
];
621 if (buffer
[bufcnt
- 1] == 'a' && buffer
[bufcnt
] == 'r')
622 buffer
[++bufcnt
] = arnum
+ '0';
623 if (buffer
[bufcnt
] == '('
624 && current_ind
->displacement
== DISP_REQUIRED
)
626 sprintf (&buffer
[bufcnt
+ 1], "%u", disp
);
627 bufcnt
+= strlen (&buffer
[bufcnt
+ 1]);
630 buffer
[bufcnt
+ 1] = '\0';
640 get_register_operand (fragment
, buffer
)
641 unsigned char fragment
;
644 const reg
*current_reg
= tic30_regtab
;
648 for (; current_reg
< tic30_regtab_end
; current_reg
++)
650 if ((fragment
& 0x1F) == current_reg
->opcode
)
652 strcpy (buffer
, current_reg
->name
);
660 cnvt_tmsfloat_ieee (tmsfloat
, size
, ieeefloat
)
661 unsigned long tmsfloat
;
665 unsigned long exp
, sign
, mant
;
669 if ((tmsfloat
& 0x0000F000) == 0x00008000)
670 tmsfloat
= 0x80000000;
674 tmsfloat
= (long) tmsfloat
>> 4;
677 exp
= tmsfloat
& 0xFF000000;
678 if (exp
== 0x80000000)
684 sign
= (tmsfloat
& 0x00800000) << 8;
685 mant
= tmsfloat
& 0x007FFFFF;
686 if (exp
== 0xFF000000)
691 *ieeefloat
= 1.0 / 0.0;
693 *ieeefloat
= -1.0 / 0.0;
699 mant
= (~mant
) & 0x007FFFFF;
701 exp
+= mant
& 0x00800000;
705 if (tmsfloat
== 0x80000000)
706 sign
= mant
= exp
= 0;
707 tmsfloat
= sign
| exp
| mant
;
708 *ieeefloat
= *((float *) &tmsfloat
);
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