1 /* Disassembly routines for TMS320C30 architecture
2 Copyright 1998, 1999, 2000, 2002, 2005, 2007, 2009
3 Free Software Foundation, Inc.
4 Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
27 #include "opcode/tic30.h"
30 #define PARALLEL_INSN 2
32 /* Gets the type of instruction based on the top 2 or 3 bits of the
34 #define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000)
36 /* Instruction types. */
37 #define TWO_OPERAND_1 0x00000000
38 #define TWO_OPERAND_2 0x40000000
39 #define THREE_OPERAND 0x20000000
40 #define PAR_STORE 0xC0000000
41 #define MUL_ADDS 0x80000000
42 #define BRANCHES 0x60000000
44 /* Specific instruction id bits. */
45 #define NORMAL_IDEN 0x1F800000
46 #define PAR_STORE_IDEN 0x3E000000
47 #define MUL_ADD_IDEN 0x2C000000
48 #define BR_IMM_IDEN 0x1F000000
49 #define BR_COND_IDEN 0x1C3F0000
51 /* Addressing modes. */
52 #define AM_REGISTER 0x00000000
53 #define AM_DIRECT 0x00200000
54 #define AM_INDIRECT 0x00400000
55 #define AM_IMM 0x00600000
57 #define P_FIELD 0x03000000
60 #define LDP_INSN 0x08700000
62 /* TMS320C30 program counter for current instruction. */
63 static unsigned int _pc
;
73 get_tic30_instruction (unsigned long insn_word
, struct instruction
*insn
)
75 switch (GET_TYPE (insn_word
))
80 insn
->type
= NORMAL_INSN
;
82 insn_template
*current_optab
= (insn_template
*) tic30_optab
;
84 for (; current_optab
< tic30_optab_end
; current_optab
++)
86 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
88 if (current_optab
->operands
== 0)
90 if (current_optab
->base_opcode
== insn_word
)
92 insn
->tm
= current_optab
;
96 else if ((current_optab
->base_opcode
& NORMAL_IDEN
) == (insn_word
& NORMAL_IDEN
))
98 insn
->tm
= current_optab
;
107 insn
->type
= PARALLEL_INSN
;
109 partemplate
*current_optab
= (partemplate
*) tic30_paroptab
;
111 for (; current_optab
< tic30_paroptab_end
; current_optab
++)
113 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
115 if ((current_optab
->base_opcode
& PAR_STORE_IDEN
)
116 == (insn_word
& PAR_STORE_IDEN
))
118 insn
->ptm
= current_optab
;
127 insn
->type
= PARALLEL_INSN
;
129 partemplate
*current_optab
= (partemplate
*) tic30_paroptab
;
131 for (; current_optab
< tic30_paroptab_end
; current_optab
++)
133 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
135 if ((current_optab
->base_opcode
& MUL_ADD_IDEN
)
136 == (insn_word
& MUL_ADD_IDEN
))
138 insn
->ptm
= current_optab
;
147 insn
->type
= NORMAL_INSN
;
149 insn_template
*current_optab
= (insn_template
*) tic30_optab
;
151 for (; current_optab
< tic30_optab_end
; current_optab
++)
153 if (GET_TYPE (current_optab
->base_opcode
) == GET_TYPE (insn_word
))
155 if (current_optab
->operand_types
[0] & Imm24
)
157 if ((current_optab
->base_opcode
& BR_IMM_IDEN
)
158 == (insn_word
& BR_IMM_IDEN
))
160 insn
->tm
= current_optab
;
164 else if (current_optab
->operands
> 0)
166 if ((current_optab
->base_opcode
& BR_COND_IDEN
)
167 == (insn_word
& BR_COND_IDEN
))
169 insn
->tm
= current_optab
;
175 if ((current_optab
->base_opcode
& (BR_COND_IDEN
| 0x00800000))
176 == (insn_word
& (BR_COND_IDEN
| 0x00800000)))
178 insn
->tm
= current_optab
;
193 get_register_operand (unsigned char fragment
, char *buffer
)
195 const reg
*current_reg
= tic30_regtab
;
199 for (; current_reg
< tic30_regtab_end
; current_reg
++)
201 if ((fragment
& 0x1F) == current_reg
->opcode
)
203 strcpy (buffer
, current_reg
->name
);
211 get_indirect_operand (unsigned short fragment
,
221 /* Determine which bits identify the sections of the indirect
222 operand based on the size in bytes. */
226 mod
= (fragment
& 0x00F8) >> 3;
227 arnum
= (fragment
& 0x0007);
231 mod
= (fragment
& 0xF800) >> 11;
232 arnum
= (fragment
& 0x0700) >> 8;
233 disp
= (fragment
& 0x00FF);
239 const ind_addr_type
*current_ind
= tic30_indaddr_tab
;
241 for (; current_ind
< tic30_indaddrtab_end
; current_ind
++)
243 if (current_ind
->modfield
== mod
)
245 if (current_ind
->displacement
== IMPLIED_DISP
&& size
== 2)
253 len
= strlen (current_ind
->syntax
);
254 for (i
= 0, bufcnt
= 0; i
< len
; i
++, bufcnt
++)
256 buffer
[bufcnt
] = current_ind
->syntax
[i
];
257 if (buffer
[bufcnt
- 1] == 'a' && buffer
[bufcnt
] == 'r')
258 buffer
[++bufcnt
] = arnum
+ '0';
259 if (buffer
[bufcnt
] == '('
260 && current_ind
->displacement
== DISP_REQUIRED
)
262 sprintf (&buffer
[bufcnt
+ 1], "%u", disp
);
263 bufcnt
+= strlen (&buffer
[bufcnt
+ 1]);
266 buffer
[bufcnt
+ 1] = '\0';
276 cnvt_tmsfloat_ieee (unsigned long tmsfloat
, int size
, float *ieeefloat
)
278 unsigned long exponent
, sign
, mant
;
287 if ((tmsfloat
& 0x0000F000) == 0x00008000)
288 tmsfloat
= 0x80000000;
292 tmsfloat
= (long) tmsfloat
>> 4;
295 exponent
= tmsfloat
& 0xFF000000;
296 if (exponent
== 0x80000000)
301 exponent
+= 0x7F000000;
302 sign
= (tmsfloat
& 0x00800000) << 8;
303 mant
= tmsfloat
& 0x007FFFFF;
304 if (exponent
== 0xFF000000)
310 *ieeefloat
= HUGE_VALF
;
312 *ieeefloat
= -HUGE_VALF
;
315 *ieeefloat
= 1.0 / 0.0;
317 *ieeefloat
= -1.0 / 0.0;
324 mant
= (~mant
) & 0x007FFFFF;
326 exponent
+= mant
& 0x00800000;
327 exponent
&= 0x7F800000;
330 if (tmsfloat
== 0x80000000)
331 sign
= mant
= exponent
= 0;
332 tmsfloat
= sign
| exponent
| mant
;
339 print_two_operand (disassemble_info
*info
,
340 unsigned long insn_word
,
341 struct instruction
*insn
)
344 char operand
[2][13] =
351 if (insn
->tm
== NULL
)
353 strcpy (name
, insn
->tm
->name
);
354 if (insn
->tm
->opcode_modifier
== AddressMode
)
357 /* Determine whether instruction is a store or a normal instruction. */
358 if ((insn
->tm
->operand_types
[1] & (Direct
| Indirect
))
359 == (Direct
| Indirect
))
369 /* Get the destination register. */
370 if (insn
->tm
->operands
== 2)
371 get_register_operand ((insn_word
& 0x001F0000) >> 16, operand
[dest_op
]);
372 /* Get the source operand based on addressing mode. */
373 switch (insn_word
& AddressMode
)
376 /* Check for the NOP instruction before getting the operand. */
377 if ((insn
->tm
->operand_types
[0] & NotReq
) == 0)
378 get_register_operand ((insn_word
& 0x0000001F), operand
[src_op
]);
381 sprintf (operand
[src_op
], "@0x%lX", (insn_word
& 0x0000FFFF));
384 get_indirect_operand ((insn_word
& 0x0000FFFF), 2, operand
[src_op
]);
387 /* Get the value of the immediate operand based on variable type. */
388 switch (insn
->tm
->imm_arg_type
)
391 cnvt_tmsfloat_ieee ((insn_word
& 0x0000FFFF), 2, &f_number
);
392 sprintf (operand
[src_op
], "%2.2f", f_number
);
395 sprintf (operand
[src_op
], "%d", (short) (insn_word
& 0x0000FFFF));
398 sprintf (operand
[src_op
], "%lu", (insn_word
& 0x0000FFFF));
403 /* Handle special case for LDP instruction. */
404 if ((insn_word
& 0xFFFFFF00) == LDP_INSN
)
406 strcpy (name
, "ldp");
407 sprintf (operand
[0], "0x%06lX", (insn_word
& 0x000000FF) << 16);
408 operand
[1][0] = '\0';
412 /* Handle case for stack and rotate instructions. */
413 else if (insn
->tm
->operands
== 1)
415 if (insn
->tm
->opcode_modifier
== StackOp
)
416 get_register_operand ((insn_word
& 0x001F0000) >> 16, operand
[0]);
418 /* Output instruction to stream. */
419 info
->fprintf_func (info
->stream
, " %s %s%c%s", name
,
420 operand
[0][0] ? operand
[0] : "",
421 operand
[1][0] ? ',' : ' ',
422 operand
[1][0] ? operand
[1] : "");
427 print_three_operand (disassemble_info
*info
,
428 unsigned long insn_word
,
429 struct instruction
*insn
)
431 char operand
[3][13] =
438 if (insn
->tm
== NULL
)
440 switch (insn_word
& AddressMode
)
443 get_register_operand ((insn_word
& 0x000000FF), operand
[0]);
444 get_register_operand ((insn_word
& 0x0000FF00) >> 8, operand
[1]);
447 get_register_operand ((insn_word
& 0x000000FF), operand
[0]);
448 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1]);
451 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0]);
452 get_register_operand ((insn_word
& 0x0000FF00) >> 8, operand
[1]);
455 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0]);
456 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1]);
461 if (insn
->tm
->operands
== 3)
462 get_register_operand ((insn_word
& 0x001F0000) >> 16, operand
[2]);
463 info
->fprintf_func (info
->stream
, " %s %s,%s%c%s", insn
->tm
->name
,
464 operand
[0], operand
[1],
465 operand
[2][0] ? ',' : ' ',
466 operand
[2][0] ? operand
[2] : "");
471 print_par_insn (disassemble_info
*info
,
472 unsigned long insn_word
,
473 struct instruction
*insn
)
477 char operand
[2][3][13] =
491 if (insn
->ptm
== NULL
)
493 /* Parse out the names of each of the parallel instructions from the
494 q_insn1_insn2 format. */
495 name1
= (char *) strdup (insn
->ptm
->name
+ 2);
497 len
= strlen (name1
);
498 for (i
= 0; i
< len
; i
++)
502 name2
= &name1
[i
+ 1];
507 /* Get the operands of the instruction based on the operand order. */
508 switch (insn
->ptm
->oporder
)
511 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][0]);
512 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
513 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
514 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][1]);
517 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][0]);
518 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][0]);
519 get_register_operand ((insn_word
>> 19) & 0x07, operand
[1][1]);
520 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][1]);
523 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][1]);
524 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
525 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
526 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][0]);
529 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][0]);
530 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
531 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
532 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][1]);
533 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][2]);
536 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][1]);
537 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][1]);
538 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
539 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][0]);
540 get_register_operand ((insn_word
>> 22) & 0x07, operand
[0][2]);
543 if (insn_word
& 0x00800000)
544 get_register_operand (0x01, operand
[0][2]);
546 get_register_operand (0x00, operand
[0][2]);
547 if (insn_word
& 0x00400000)
548 get_register_operand (0x03, operand
[1][2]);
550 get_register_operand (0x02, operand
[1][2]);
551 switch (insn_word
& P_FIELD
)
554 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[0][1]);
555 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[0][0]);
556 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][1]);
557 get_register_operand ((insn_word
>> 19) & 0x07, operand
[1][0]);
560 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[1][0]);
561 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[0][0]);
562 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][1]);
563 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][1]);
566 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[1][1]);
567 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[1][0]);
568 get_register_operand ((insn_word
>> 16) & 0x07, operand
[0][1]);
569 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][0]);
572 get_indirect_operand ((insn_word
& 0x000000FF), 1, operand
[1][1]);
573 get_indirect_operand ((insn_word
& 0x0000FF00) >> 8, 1, operand
[0][0]);
574 get_register_operand ((insn_word
>> 16) & 0x07, operand
[1][0]);
575 get_register_operand ((insn_word
>> 19) & 0x07, operand
[0][1]);
582 info
->fprintf_func (info
->stream
, " %s %s,%s%c%s", name1
,
583 operand
[0][0], operand
[0][1],
584 operand
[0][2][0] ? ',' : ' ',
585 operand
[0][2][0] ? operand
[0][2] : "");
586 info
->fprintf_func (info
->stream
, "\n\t\t\t|| %s %s,%s%c%s", name2
,
587 operand
[1][0], operand
[1][1],
588 operand
[1][2][0] ? ',' : ' ',
589 operand
[1][2][0] ? operand
[1][2] : "");
595 print_branch (disassemble_info
*info
,
596 unsigned long insn_word
,
597 struct instruction
*insn
)
599 char operand
[2][13] =
604 unsigned long address
;
607 if (insn
->tm
== NULL
)
609 /* Get the operands for 24-bit immediate jumps. */
610 if (insn
->tm
->operand_types
[0] & Imm24
)
612 address
= insn_word
& 0x00FFFFFF;
613 sprintf (operand
[0], "0x%lX", address
);
616 /* Get the operand for the trap instruction. */
617 else if (insn
->tm
->operand_types
[0] & IVector
)
619 address
= insn_word
& 0x0000001F;
620 sprintf (operand
[0], "0x%lX", address
);
624 address
= insn_word
& 0x0000FFFF;
625 /* Get the operands for the DB instructions. */
626 if (insn
->tm
->operands
== 2)
628 get_register_operand (((insn_word
& 0x01C00000) >> 22) + REG_AR0
, operand
[0]);
629 if (insn_word
& PCRel
)
631 sprintf (operand
[1], "%d", (short) address
);
635 get_register_operand (insn_word
& 0x0000001F, operand
[1]);
637 /* Get the operands for the standard branches. */
638 else if (insn
->tm
->operands
== 1)
640 if (insn_word
& PCRel
)
642 address
= (short) address
;
643 sprintf (operand
[0], "%ld", address
);
647 get_register_operand (insn_word
& 0x0000001F, operand
[0]);
650 info
->fprintf_func (info
->stream
, " %s %s%c%s", insn
->tm
->name
,
651 operand
[0][0] ? operand
[0] : "",
652 operand
[1][0] ? ',' : ' ',
653 operand
[1][0] ? operand
[1] : "");
654 /* Print destination of branch in relation to current symbol. */
655 if (print_label
&& info
->symbols
)
657 asymbol
*sym
= *info
->symbols
;
659 if ((insn
->tm
->opcode_modifier
== PCRel
) && (insn_word
& PCRel
))
661 address
= (_pc
+ 1 + (short) address
) - ((sym
->section
->vma
+ sym
->value
) / 4);
662 /* Check for delayed instruction, if so adjust destination. */
663 if (insn_word
& 0x00200000)
668 address
-= ((sym
->section
->vma
+ sym
->value
) / 4);
671 info
->fprintf_func (info
->stream
, " <%s>", sym
->name
);
673 info
->fprintf_func (info
->stream
, " <%s %c %d>", sym
->name
,
674 ((short) address
< 0) ? '-' : '+',
681 print_insn_tic30 (bfd_vma pc
, disassemble_info
*info
)
683 unsigned long insn_word
;
684 struct instruction insn
= { 0, NULL
, NULL
};
685 bfd_vma bufaddr
= pc
- info
->buffer_vma
;
687 /* Obtain the current instruction word from the buffer. */
688 insn_word
= (*(info
->buffer
+ bufaddr
) << 24) | (*(info
->buffer
+ bufaddr
+ 1) << 16) |
689 (*(info
->buffer
+ bufaddr
+ 2) << 8) | *(info
->buffer
+ bufaddr
+ 3);
691 /* Get the instruction refered to by the current instruction word
692 and print it out based on its type. */
693 if (!get_tic30_instruction (insn_word
, &insn
))
695 switch (GET_TYPE (insn_word
))
699 if (!print_two_operand (info
, insn_word
, &insn
))
703 if (!print_three_operand (info
, insn_word
, &insn
))
708 if (!print_par_insn (info
, insn_word
, &insn
))
712 if (!print_branch (info
, insn_word
, &insn
))
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