1 /* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils.
3 Copyright 2002, 2003, 2005, 2007 Free Software Foundation, Inc.
5 Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
7 This file is part of the GNU opcodes library.
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
25 #include "libiberty.h"
27 #include "opcode/tic4x.h"
31 #define TIC4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */
32 #define TIC4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions. */
53 static int tic4x_version
= 0;
54 static int tic4x_dp
= 0;
57 tic4x_pc_offset (unsigned int op
)
59 /* Determine the PC offset for a C[34]x instruction.
60 This could be simplified using some boolean algebra
61 but at the expense of readability. */
65 case 0x62: /* call (C4x) */
66 case 0x64: /* rptb (C4x) */
70 case 0x65: /* rptbd (C4x) */
79 switch ((op
& 0xffe00000) >> 20)
82 case 0x720: /* callB */
83 case 0x740: /* trapB */
87 case 0x6a6: /* bBat */
88 case 0x6aa: /* bBaf */
89 case 0x722: /* lajB */
90 case 0x748: /* latB */
91 case 0x798: /* rptbd */
98 switch ((op
& 0xfe200000) >> 20)
100 case 0x6e0: /* dbB */
103 case 0x6e2: /* dbBd */
114 tic4x_print_char (struct disassemble_info
* info
, char ch
)
117 (*info
->fprintf_func
) (info
->stream
, "%c", ch
);
122 tic4x_print_str (struct disassemble_info
*info
, char *str
)
125 (*info
->fprintf_func
) (info
->stream
, "%s", str
);
130 tic4x_print_register (struct disassemble_info
*info
, unsigned long regno
)
132 static tic4x_register_t
** registertable
= NULL
;
135 if (registertable
== NULL
)
137 registertable
= xmalloc (sizeof (tic4x_register_t
*) * REG_TABLE_SIZE
);
138 for (i
= 0; i
< tic3x_num_registers
; i
++)
139 registertable
[tic3x_registers
[i
].regno
] = (tic4x_register_t
*) (tic3x_registers
+ i
);
140 if (IS_CPU_TIC4X (tic4x_version
))
142 /* Add C4x additional registers, overwriting
143 any C3x registers if necessary. */
144 for (i
= 0; i
< tic4x_num_registers
; i
++)
145 registertable
[tic4x_registers
[i
].regno
] =
146 (tic4x_register_t
*)(tic4x_registers
+ i
);
149 if ((int) regno
> (IS_CPU_TIC4X (tic4x_version
) ? TIC4X_REG_MAX
: TIC3X_REG_MAX
))
152 (*info
->fprintf_func
) (info
->stream
, "%s", registertable
[regno
]->name
);
157 tic4x_print_addr (struct disassemble_info
*info
, unsigned long addr
)
160 (*info
->print_address_func
)(addr
, info
);
165 tic4x_print_relative (struct disassemble_info
*info
,
168 unsigned long opcode
)
170 return tic4x_print_addr (info
, pc
+ offset
+ tic4x_pc_offset (opcode
));
174 tic4x_print_direct (struct disassemble_info
*info
, unsigned long arg
)
178 (*info
->fprintf_func
) (info
->stream
, "@");
179 tic4x_print_addr (info
, arg
+ (tic4x_dp
<< 16));
184 /* FIXME: make the floating point stuff not rely on host
185 floating point arithmetic. */
188 tic4x_print_ftoa (unsigned int val
, FILE *stream
, fprintf_ftype pfunc
)
195 e
= EXTRS (val
, 31, 24); /* Exponent. */
198 s
= EXTRU (val
, 23, 23); /* Sign bit. */
199 f
= EXTRU (val
, 22, 0); /* Mantissa. */
204 num
= f
/ (double)(1 << 23);
205 num
= ldexp (num
, e
);
207 (*pfunc
)(stream
, "%.9g", num
);
212 tic4x_print_immed (struct disassemble_info
*info
,
227 (*info
->fprintf_func
) (info
->stream
, "%ld", (long) arg
);
232 (*info
->fprintf_func
) (info
->stream
, "%lu", arg
);
236 e
= EXTRS (arg
, 15, 12);
239 s
= EXTRU (arg
, 11, 11);
240 f
= EXTRU (arg
, 10, 0);
245 num
= f
/ (double)(1 << 11);
246 num
= ldexp (num
, e
);
248 (*info
->fprintf_func
) (info
->stream
, "%f", num
);
251 e
= EXTRS (arg
, 31, 24);
254 s
= EXTRU (arg
, 23, 23);
255 f
= EXTRU (arg
, 22, 0);
260 num
= f
/ (double)(1 << 23);
261 num
= ldexp (num
, e
);
263 (*info
->fprintf_func
) (info
->stream
, "%f", num
);
270 tic4x_print_cond (struct disassemble_info
*info
, unsigned int cond
)
272 static tic4x_cond_t
**condtable
= NULL
;
275 if (condtable
== NULL
)
277 condtable
= xmalloc (sizeof (tic4x_cond_t
*) * 32);
278 for (i
= 0; i
< tic4x_num_conds
; i
++)
279 condtable
[tic4x_conds
[i
].cond
] = (tic4x_cond_t
*)(tic4x_conds
+ i
);
281 if (cond
> 31 || condtable
[cond
] == NULL
)
284 (*info
->fprintf_func
) (info
->stream
, "%s", condtable
[cond
]->name
);
289 tic4x_print_indirect (struct disassemble_info
*info
,
303 case INDIRECT_TIC4X
: /* *+ARn(disp) */
304 disp
= EXTRU (arg
, 7, 3);
305 aregno
= EXTRU (arg
, 2, 0) + REG_AR0
;
310 aregno
= EXTRU (arg
, 2, 0) + REG_AR0
;
311 modn
= EXTRU (arg
, 7, 3);
314 disp
= EXTRU (arg
, 7, 0);
315 aregno
= EXTRU (arg
, 10, 8) + REG_AR0
;
316 modn
= EXTRU (arg
, 15, 11);
317 if (modn
> 7 && disp
!= 0)
321 (*info
->fprintf_func
)(info
->stream
, "# internal error: Unknown indirect type %d", type
);
324 if (modn
> TIC3X_MODN_MAX
)
326 a
= tic4x_indirects
[modn
].name
;
332 tic4x_print_register (info
, aregno
);
335 tic4x_print_immed (info
, IMMED_UINT
, disp
);
338 tic4x_print_str (info
, "ir0");
341 tic4x_print_str (info
, "ir1");
344 tic4x_print_char (info
, *a
);
353 tic4x_print_op (struct disassemble_info
*info
,
354 unsigned long instruction
,
360 char *parallel
= NULL
;
362 /* Print instruction name. */
364 while (*s
&& parallel
== NULL
)
369 if (! tic4x_print_cond (info
, EXTRU (instruction
, 20, 16)))
373 if (! tic4x_print_cond (info
, EXTRU (instruction
, 27, 23)))
377 parallel
= s
+ 1; /* Skip past `_' in name. */
380 tic4x_print_char (info
, *s
);
386 /* Print arguments. */
389 tic4x_print_char (info
, ' ');
395 case '*': /* Indirect 0--15. */
396 if (! tic4x_print_indirect (info
, INDIRECT_LONG
,
397 EXTRU (instruction
, 15, 0)))
401 case '#': /* Only used for ldp, ldpk. */
402 tic4x_print_immed (info
, IMMED_UINT
, EXTRU (instruction
, 15, 0));
405 case '@': /* Direct 0--15. */
406 tic4x_print_direct (info
, EXTRU (instruction
, 15, 0));
409 case 'A': /* Address register 24--22. */
410 if (! tic4x_print_register (info
, EXTRU (instruction
, 24, 22) +
415 case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb
417 if (IS_CPU_TIC4X (tic4x_version
))
418 tic4x_print_relative (info
, pc
, EXTRS (instruction
, 23, 0),
421 tic4x_print_addr (info
, EXTRU (instruction
, 23, 0));
424 case 'C': /* Indirect (short C4x) 0--7. */
425 if (! IS_CPU_TIC4X (tic4x_version
))
427 if (! tic4x_print_indirect (info
, INDIRECT_TIC4X
,
428 EXTRU (instruction
, 7, 0)))
433 /* Cockup if get here... */
436 case 'E': /* Register 0--7. */
438 if (! tic4x_print_register (info
, EXTRU (instruction
, 7, 0)))
442 case 'F': /* 16-bit float immediate 0--15. */
443 tic4x_print_immed (info
, IMMED_SFLOAT
,
444 EXTRU (instruction
, 15, 0));
447 case 'i': /* Extended indirect 0--7. */
448 if (EXTRU (instruction
, 7, 5) == 7)
450 if (!tic4x_print_register (info
, EXTRU (instruction
, 4, 0)))
456 case 'I': /* Indirect (short) 0--7. */
457 if (! tic4x_print_indirect (info
, INDIRECT_SHORT
,
458 EXTRU (instruction
, 7, 0)))
462 case 'j': /* Extended indirect 8--15 */
463 if (EXTRU (instruction
, 15, 13) == 7)
465 if (! tic4x_print_register (info
, EXTRU (instruction
, 12, 8)))
470 case 'J': /* Indirect (short) 8--15. */
471 if (! tic4x_print_indirect (info
, INDIRECT_SHORT
,
472 EXTRU (instruction
, 15, 8)))
476 case 'G': /* Register 8--15. */
478 if (! tic4x_print_register (info
, EXTRU (instruction
, 15, 8)))
482 case 'H': /* Register 16--18. */
483 if (! tic4x_print_register (info
, EXTRU (instruction
, 18, 16)))
487 case 'K': /* Register 19--21. */
488 if (! tic4x_print_register (info
, EXTRU (instruction
, 21, 19)))
492 case 'L': /* Register 22--24. */
493 if (! tic4x_print_register (info
, EXTRU (instruction
, 24, 22)))
497 case 'M': /* Register 22--22. */
498 tic4x_print_register (info
, EXTRU (instruction
, 22, 22) + REG_R2
);
501 case 'N': /* Register 23--23. */
502 tic4x_print_register (info
, EXTRU (instruction
, 23, 23) + REG_R0
);
505 case 'O': /* Indirect (short C4x) 8--15. */
506 if (! IS_CPU_TIC4X (tic4x_version
))
508 if (! tic4x_print_indirect (info
, INDIRECT_TIC4X
,
509 EXTRU (instruction
, 15, 8)))
513 case 'P': /* Displacement 0--15 (used by Bcond and BcondD). */
514 tic4x_print_relative (info
, pc
, EXTRS (instruction
, 15, 0),
518 case 'Q': /* Register 0--15. */
520 if (! tic4x_print_register (info
, EXTRU (instruction
, 15, 0)))
524 case 'R': /* Register 16--20. */
526 if (! tic4x_print_register (info
, EXTRU (instruction
, 20, 16)))
530 case 'S': /* 16-bit signed immediate 0--15. */
531 tic4x_print_immed (info
, IMMED_SINT
,
532 EXTRS (instruction
, 15, 0));
535 case 'T': /* 5-bit signed immediate 16--20 (C4x stik). */
536 if (! IS_CPU_TIC4X (tic4x_version
))
538 if (! tic4x_print_immed (info
, IMMED_SUINT
,
539 EXTRU (instruction
, 20, 16)))
543 case 'U': /* 16-bit unsigned int immediate 0--15. */
544 tic4x_print_immed (info
, IMMED_SUINT
, EXTRU (instruction
, 15, 0));
547 case 'V': /* 5/9-bit unsigned vector 0--4/8. */
548 tic4x_print_immed (info
, IMMED_SUINT
,
549 IS_CPU_TIC4X (tic4x_version
) ?
550 EXTRU (instruction
, 8, 0) :
551 EXTRU (instruction
, 4, 0) & ~0x20);
554 case 'W': /* 8-bit signed immediate 0--7. */
555 if (! IS_CPU_TIC4X (tic4x_version
))
557 tic4x_print_immed (info
, IMMED_SINT
, EXTRS (instruction
, 7, 0));
560 case 'X': /* Expansion register 4--0. */
561 val
= EXTRU (instruction
, 4, 0) + REG_IVTP
;
562 if (val
< REG_IVTP
|| val
> REG_TVTP
)
564 if (! tic4x_print_register (info
, val
))
568 case 'Y': /* Address register 16--20. */
569 val
= EXTRU (instruction
, 20, 16);
570 if (val
< REG_AR0
|| val
> REG_SP
)
572 if (! tic4x_print_register (info
, val
))
576 case 'Z': /* Expansion register 16--20. */
577 val
= EXTRU (instruction
, 20, 16) + REG_IVTP
;
578 if (val
< REG_IVTP
|| val
> REG_TVTP
)
580 if (! tic4x_print_register (info
, val
))
584 case '|': /* Parallel instruction. */
585 tic4x_print_str (info
, " || ");
586 tic4x_print_str (info
, parallel
);
587 tic4x_print_char (info
, ' ');
591 tic4x_print_char (info
, ',');
595 tic4x_print_char (info
, *s
);
604 tic4x_hash_opcode_special (tic4x_inst_t
**optable_special
,
605 const tic4x_inst_t
*inst
)
609 for (i
= 0;i
< TIC4X_SPESOP_SIZE
; i
++)
610 if (optable_special
[i
] != NULL
611 && optable_special
[i
]->opcode
== inst
->opcode
)
613 /* Collision (we have it already) - overwrite. */
614 optable_special
[i
] = (tic4x_inst_t
*) inst
;
618 for (i
= 0; i
< TIC4X_SPESOP_SIZE
; i
++)
619 if (optable_special
[i
] == NULL
)
621 /* Add the new opcode. */
622 optable_special
[i
] = (tic4x_inst_t
*) inst
;
626 /* This should never occur. This happens if the number of special
627 instructions exceeds TIC4X_SPESOP_SIZE. Please increase the variable
630 printf ("optable_special[] is full, please increase TIC4X_SPESOP_SIZE!\n");
635 tic4x_hash_opcode (tic4x_inst_t
**optable
,
636 tic4x_inst_t
**optable_special
,
637 const tic4x_inst_t
*inst
,
638 const unsigned long tic4x_oplevel
)
641 int opcode
= inst
->opcode
>> (32 - TIC4X_HASH_SIZE
);
642 int opmask
= inst
->opmask
>> (32 - TIC4X_HASH_SIZE
);
644 /* Use a TIC4X_HASH_SIZE bit index as a hash index. We should
645 have unique entries so there's no point having a linked list
647 for (j
= opcode
; j
< opmask
; j
++)
648 if ((j
& opmask
) == opcode
649 && inst
->oplevel
& tic4x_oplevel
)
652 /* We should only have collisions for synonyms like
654 if (optable
[j
] != NULL
)
655 printf ("Collision at index %d, %s and %s\n",
656 j
, optable
[j
]->name
, inst
->name
);
658 /* Catch those ops that collide with others already inside the
659 hash, and have a opmask greater than the one we use in the
660 hash. Store them in a special-list, that will handle full
661 32-bit INSN, not only the first 11-bit (or so). */
662 if (optable
[j
] != NULL
663 && inst
->opmask
& ~(opmask
<< (32 - TIC4X_HASH_SIZE
)))
665 /* Add the instruction already on the list. */
666 tic4x_hash_opcode_special (optable_special
, optable
[j
]);
668 /* Add the new instruction. */
669 tic4x_hash_opcode_special (optable_special
, inst
);
672 optable
[j
] = (tic4x_inst_t
*) inst
;
676 /* Disassemble the instruction in 'instruction'.
677 'pc' should be the address of this instruction, it will
678 be used to print the target address if this is a relative jump or call
679 the disassembled instruction is written to 'info'.
680 The function returns the length of this instruction in words. */
683 tic4x_disassemble (unsigned long pc
,
684 unsigned long instruction
,
685 struct disassemble_info
*info
)
687 static tic4x_inst_t
**optable
= NULL
;
688 static tic4x_inst_t
**optable_special
= NULL
;
691 unsigned long tic4x_oplevel
;
693 tic4x_version
= info
->mach
;
695 tic4x_oplevel
= (IS_CPU_TIC4X (tic4x_version
)) ? OP_C4X
: 0;
696 tic4x_oplevel
|= OP_C3X
| OP_LPWR
| OP_IDLE2
| OP_ENH
;
700 optable
= xcalloc (sizeof (tic4x_inst_t
*), (1 << TIC4X_HASH_SIZE
));
702 optable_special
= xcalloc (sizeof (tic4x_inst_t
*), TIC4X_SPESOP_SIZE
);
704 /* Install opcodes in reverse order so that preferred
705 forms overwrite synonyms. */
706 for (i
= tic4x_num_insts
- 1; i
>= 0; i
--)
707 tic4x_hash_opcode (optable
, optable_special
, &tic4x_insts
[i
],
710 /* We now need to remove the insn that are special from the
711 "normal" optable, to make the disasm search this extra list
713 for (i
= 0; i
< TIC4X_SPESOP_SIZE
; i
++)
714 if (optable_special
[i
] != NULL
)
715 optable
[optable_special
[i
]->opcode
>> (32 - TIC4X_HASH_SIZE
)] = NULL
;
718 /* See if we can pick up any loading of the DP register... */
719 if ((instruction
>> 16) == 0x5070 || (instruction
>> 16) == 0x1f70)
720 tic4x_dp
= EXTRU (instruction
, 15, 0);
722 p
= optable
[instruction
>> (32 - TIC4X_HASH_SIZE
)];
725 if (((instruction
& p
->opmask
) == p
->opcode
)
726 && tic4x_print_op (NULL
, instruction
, p
, pc
))
727 tic4x_print_op (info
, instruction
, p
, pc
);
729 (*info
->fprintf_func
) (info
->stream
, "%08lx", instruction
);
733 for (i
= 0; i
<TIC4X_SPESOP_SIZE
; i
++)
734 if (optable_special
[i
] != NULL
735 && optable_special
[i
]->opcode
== instruction
)
737 (*info
->fprintf_func
)(info
->stream
, "%s", optable_special
[i
]->name
);
740 if (i
== TIC4X_SPESOP_SIZE
)
741 (*info
->fprintf_func
) (info
->stream
, "%08lx", instruction
);
744 /* Return size of insn in words. */
748 /* The entry point from objdump and gdb. */
750 print_insn_tic4x (bfd_vma memaddr
, struct disassemble_info
*info
)
757 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
760 (*info
->memory_error_func
) (status
, memaddr
, info
);
765 op
= bfd_getl32 (buffer
);
766 info
->bytes_per_line
= 4;
767 info
->bytes_per_chunk
= 4;
768 info
->octets_per_byte
= 4;
769 info
->display_endian
= BFD_ENDIAN_LITTLE
;
770 return tic4x_disassemble (pc
, op
, info
) * 4;
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