1 /* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils.
3 Copyright (C) 2002-2016 Free Software Foundation, Inc.
5 Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
7 This file is part of the GNU opcodes library.
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "libiberty.h"
28 #include "opcode/tic4x.h"
32 #define TIC4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */
33 #define TIC4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions. */
54 static int tic4x_version
= 0;
55 static int tic4x_dp
= 0;
58 tic4x_pc_offset (unsigned int op
)
60 /* Determine the PC offset for a C[34]x instruction.
61 This could be simplified using some boolean algebra
62 but at the expense of readability. */
66 case 0x62: /* call (C4x) */
67 case 0x64: /* rptb (C4x) */
71 case 0x65: /* rptbd (C4x) */
80 switch ((op
& 0xffe00000) >> 20)
83 case 0x720: /* callB */
84 case 0x740: /* trapB */
88 case 0x6a6: /* bBat */
89 case 0x6aa: /* bBaf */
90 case 0x722: /* lajB */
91 case 0x748: /* latB */
92 case 0x798: /* rptbd */
99 switch ((op
& 0xfe200000) >> 20)
101 case 0x6e0: /* dbB */
104 case 0x6e2: /* dbBd */
115 tic4x_print_char (struct disassemble_info
* info
, char ch
)
118 (*info
->fprintf_func
) (info
->stream
, "%c", ch
);
123 tic4x_print_str (struct disassemble_info
*info
, const char *str
)
126 (*info
->fprintf_func
) (info
->stream
, "%s", str
);
131 tic4x_print_register (struct disassemble_info
*info
, unsigned long regno
)
133 static tic4x_register_t
** registertable
= NULL
;
136 if (registertable
== NULL
)
138 registertable
= xmalloc (sizeof (tic4x_register_t
*) * REG_TABLE_SIZE
);
139 for (i
= 0; i
< tic3x_num_registers
; i
++)
140 registertable
[tic3x_registers
[i
].regno
] = (tic4x_register_t
*) (tic3x_registers
+ i
);
141 if (IS_CPU_TIC4X (tic4x_version
))
143 /* Add C4x additional registers, overwriting
144 any C3x registers if necessary. */
145 for (i
= 0; i
< tic4x_num_registers
; i
++)
146 registertable
[tic4x_registers
[i
].regno
] =
147 (tic4x_register_t
*)(tic4x_registers
+ i
);
150 if ((int) regno
> (IS_CPU_TIC4X (tic4x_version
) ? TIC4X_REG_MAX
: TIC3X_REG_MAX
))
153 (*info
->fprintf_func
) (info
->stream
, "%s", registertable
[regno
]->name
);
158 tic4x_print_addr (struct disassemble_info
*info
, unsigned long addr
)
161 (*info
->print_address_func
)(addr
, info
);
166 tic4x_print_relative (struct disassemble_info
*info
,
169 unsigned long opcode
)
171 return tic4x_print_addr (info
, pc
+ offset
+ tic4x_pc_offset (opcode
));
175 tic4x_print_direct (struct disassemble_info
*info
, unsigned long arg
)
179 (*info
->fprintf_func
) (info
->stream
, "@");
180 tic4x_print_addr (info
, arg
+ (tic4x_dp
<< 16));
185 /* FIXME: make the floating point stuff not rely on host
186 floating point arithmetic. */
189 tic4x_print_ftoa (unsigned int val
, FILE *stream
, fprintf_ftype pfunc
)
196 e
= EXTRS (val
, 31, 24); /* Exponent. */
199 s
= EXTRU (val
, 23, 23); /* Sign bit. */
200 f
= EXTRU (val
, 22, 0); /* Mantissa. */
205 num
= f
/ (double)(1 << 23);
206 num
= ldexp (num
, e
);
208 (*pfunc
)(stream
, "%.9g", num
);
213 tic4x_print_immed (struct disassemble_info
*info
,
228 (*info
->fprintf_func
) (info
->stream
, "%ld", (long) arg
);
233 (*info
->fprintf_func
) (info
->stream
, "%lu", arg
);
237 e
= EXTRS (arg
, 15, 12);
240 s
= EXTRU (arg
, 11, 11);
241 f
= EXTRU (arg
, 10, 0);
246 num
= f
/ (double)(1 << 11);
247 num
= ldexp (num
, e
);
249 (*info
->fprintf_func
) (info
->stream
, "%f", num
);
252 e
= EXTRS (arg
, 31, 24);
255 s
= EXTRU (arg
, 23, 23);
256 f
= EXTRU (arg
, 22, 0);
261 num
= f
/ (double)(1 << 23);
262 num
= ldexp (num
, e
);
264 (*info
->fprintf_func
) (info
->stream
, "%f", num
);
271 tic4x_print_cond (struct disassemble_info
*info
, unsigned int cond
)
273 static tic4x_cond_t
**condtable
= NULL
;
276 if (condtable
== NULL
)
278 condtable
= xmalloc (sizeof (tic4x_cond_t
*) * 32);
279 for (i
= 0; i
< tic4x_num_conds
; i
++)
280 condtable
[tic4x_conds
[i
].cond
] = (tic4x_cond_t
*)(tic4x_conds
+ i
);
282 if (cond
> 31 || condtable
[cond
] == NULL
)
285 (*info
->fprintf_func
) (info
->stream
, "%s", condtable
[cond
]->name
);
290 tic4x_print_indirect (struct disassemble_info
*info
,
304 case INDIRECT_TIC4X
: /* *+ARn(disp) */
305 disp
= EXTRU (arg
, 7, 3);
306 aregno
= EXTRU (arg
, 2, 0) + REG_AR0
;
311 aregno
= EXTRU (arg
, 2, 0) + REG_AR0
;
312 modn
= EXTRU (arg
, 7, 3);
315 disp
= EXTRU (arg
, 7, 0);
316 aregno
= EXTRU (arg
, 10, 8) + REG_AR0
;
317 modn
= EXTRU (arg
, 15, 11);
318 if (modn
> 7 && disp
!= 0)
322 (*info
->fprintf_func
)(info
->stream
, "# internal error: Unknown indirect type %d", type
);
325 if (modn
> TIC3X_MODN_MAX
)
327 a
= tic4x_indirects
[modn
].name
;
333 tic4x_print_register (info
, aregno
);
336 tic4x_print_immed (info
, IMMED_UINT
, disp
);
339 tic4x_print_str (info
, "ir0");
342 tic4x_print_str (info
, "ir1");
345 tic4x_print_char (info
, *a
);
354 tic4x_print_op (struct disassemble_info
*info
,
355 unsigned long instruction
,
361 const char *parallel
= NULL
;
363 /* Print instruction name. */
365 while (*s
&& parallel
== NULL
)
370 if (! tic4x_print_cond (info
, EXTRU (instruction
, 20, 16)))
374 if (! tic4x_print_cond (info
, EXTRU (instruction
, 27, 23)))
378 parallel
= s
+ 1; /* Skip past `_' in name. */
381 tic4x_print_char (info
, *s
);
387 /* Print arguments. */
390 tic4x_print_char (info
, ' ');
396 case '*': /* Indirect 0--15. */
397 if (! tic4x_print_indirect (info
, INDIRECT_LONG
,
398 EXTRU (instruction
, 15, 0)))
402 case '#': /* Only used for ldp, ldpk. */
403 tic4x_print_immed (info
, IMMED_UINT
, EXTRU (instruction
, 15, 0));
406 case '@': /* Direct 0--15. */
407 tic4x_print_direct (info
, EXTRU (instruction
, 15, 0));
410 case 'A': /* Address register 24--22. */
411 if (! tic4x_print_register (info
, EXTRU (instruction
, 24, 22) +
416 case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb
418 if (IS_CPU_TIC4X (tic4x_version
))
419 tic4x_print_relative (info
, pc
, EXTRS (instruction
, 23, 0),
422 tic4x_print_addr (info
, EXTRU (instruction
, 23, 0));
425 case 'C': /* Indirect (short C4x) 0--7. */
426 if (! IS_CPU_TIC4X (tic4x_version
))
428 if (! tic4x_print_indirect (info
, INDIRECT_TIC4X
,
429 EXTRU (instruction
, 7, 0)))
434 /* Cockup if get here... */
437 case 'E': /* Register 0--7. */
439 if (! tic4x_print_register (info
, EXTRU (instruction
, 7, 0)))
443 case 'F': /* 16-bit float immediate 0--15. */
444 tic4x_print_immed (info
, IMMED_SFLOAT
,
445 EXTRU (instruction
, 15, 0));
448 case 'i': /* Extended indirect 0--7. */
449 if (EXTRU (instruction
, 7, 5) == 7)
451 if (!tic4x_print_register (info
, EXTRU (instruction
, 4, 0)))
457 case 'I': /* Indirect (short) 0--7. */
458 if (! tic4x_print_indirect (info
, INDIRECT_SHORT
,
459 EXTRU (instruction
, 7, 0)))
463 case 'j': /* Extended indirect 8--15 */
464 if (EXTRU (instruction
, 15, 13) == 7)
466 if (! tic4x_print_register (info
, EXTRU (instruction
, 12, 8)))
472 case 'J': /* Indirect (short) 8--15. */
473 if (! tic4x_print_indirect (info
, INDIRECT_SHORT
,
474 EXTRU (instruction
, 15, 8)))
478 case 'G': /* Register 8--15. */
480 if (! tic4x_print_register (info
, EXTRU (instruction
, 15, 8)))
484 case 'H': /* Register 16--18. */
485 if (! tic4x_print_register (info
, EXTRU (instruction
, 18, 16)))
489 case 'K': /* Register 19--21. */
490 if (! tic4x_print_register (info
, EXTRU (instruction
, 21, 19)))
494 case 'L': /* Register 22--24. */
495 if (! tic4x_print_register (info
, EXTRU (instruction
, 24, 22)))
499 case 'M': /* Register 22--22. */
500 tic4x_print_register (info
, EXTRU (instruction
, 22, 22) + REG_R2
);
503 case 'N': /* Register 23--23. */
504 tic4x_print_register (info
, EXTRU (instruction
, 23, 23) + REG_R0
);
507 case 'O': /* Indirect (short C4x) 8--15. */
508 if (! IS_CPU_TIC4X (tic4x_version
))
510 if (! tic4x_print_indirect (info
, INDIRECT_TIC4X
,
511 EXTRU (instruction
, 15, 8)))
515 case 'P': /* Displacement 0--15 (used by Bcond and BcondD). */
516 tic4x_print_relative (info
, pc
, EXTRS (instruction
, 15, 0),
520 case 'Q': /* Register 0--15. */
522 if (! tic4x_print_register (info
, EXTRU (instruction
, 15, 0)))
526 case 'R': /* Register 16--20. */
528 if (! tic4x_print_register (info
, EXTRU (instruction
, 20, 16)))
532 case 'S': /* 16-bit signed immediate 0--15. */
533 tic4x_print_immed (info
, IMMED_SINT
,
534 EXTRS (instruction
, 15, 0));
537 case 'T': /* 5-bit signed immediate 16--20 (C4x stik). */
538 if (! IS_CPU_TIC4X (tic4x_version
))
540 if (! tic4x_print_immed (info
, IMMED_SUINT
,
541 EXTRU (instruction
, 20, 16)))
545 case 'U': /* 16-bit unsigned int immediate 0--15. */
546 tic4x_print_immed (info
, IMMED_SUINT
, EXTRU (instruction
, 15, 0));
549 case 'V': /* 5/9-bit unsigned vector 0--4/8. */
550 tic4x_print_immed (info
, IMMED_SUINT
,
551 IS_CPU_TIC4X (tic4x_version
) ?
552 EXTRU (instruction
, 8, 0) :
553 EXTRU (instruction
, 4, 0) & ~0x20);
556 case 'W': /* 8-bit signed immediate 0--7. */
557 if (! IS_CPU_TIC4X (tic4x_version
))
559 tic4x_print_immed (info
, IMMED_SINT
, EXTRS (instruction
, 7, 0));
562 case 'X': /* Expansion register 4--0. */
563 val
= EXTRU (instruction
, 4, 0) + REG_IVTP
;
564 if (val
< REG_IVTP
|| val
> REG_TVTP
)
566 if (! tic4x_print_register (info
, val
))
570 case 'Y': /* Address register 16--20. */
571 val
= EXTRU (instruction
, 20, 16);
572 if (val
< REG_AR0
|| val
> REG_SP
)
574 if (! tic4x_print_register (info
, val
))
578 case 'Z': /* Expansion register 16--20. */
579 val
= EXTRU (instruction
, 20, 16) + REG_IVTP
;
580 if (val
< REG_IVTP
|| val
> REG_TVTP
)
582 if (! tic4x_print_register (info
, val
))
586 case '|': /* Parallel instruction. */
587 tic4x_print_str (info
, " || ");
588 tic4x_print_str (info
, parallel
);
589 tic4x_print_char (info
, ' ');
593 tic4x_print_char (info
, ',');
597 tic4x_print_char (info
, *s
);
606 tic4x_hash_opcode_special (tic4x_inst_t
**optable_special
,
607 const tic4x_inst_t
*inst
)
611 for (i
= 0;i
< TIC4X_SPESOP_SIZE
; i
++)
612 if (optable_special
[i
] != NULL
613 && optable_special
[i
]->opcode
== inst
->opcode
)
615 /* Collision (we have it already) - overwrite. */
616 optable_special
[i
] = (tic4x_inst_t
*) inst
;
620 for (i
= 0; i
< TIC4X_SPESOP_SIZE
; i
++)
621 if (optable_special
[i
] == NULL
)
623 /* Add the new opcode. */
624 optable_special
[i
] = (tic4x_inst_t
*) inst
;
628 /* This should never occur. This happens if the number of special
629 instructions exceeds TIC4X_SPESOP_SIZE. Please increase the variable
632 printf ("optable_special[] is full, please increase TIC4X_SPESOP_SIZE!\n");
637 tic4x_hash_opcode (tic4x_inst_t
**optable
,
638 tic4x_inst_t
**optable_special
,
639 const tic4x_inst_t
*inst
,
640 const unsigned long tic4x_oplevel
)
643 int opcode
= inst
->opcode
>> (32 - TIC4X_HASH_SIZE
);
644 int opmask
= inst
->opmask
>> (32 - TIC4X_HASH_SIZE
);
646 /* Use a TIC4X_HASH_SIZE bit index as a hash index. We should
647 have unique entries so there's no point having a linked list
649 for (j
= opcode
; j
< opmask
; j
++)
650 if ((j
& opmask
) == opcode
651 && inst
->oplevel
& tic4x_oplevel
)
654 /* We should only have collisions for synonyms like
656 if (optable
[j
] != NULL
)
657 printf ("Collision at index %d, %s and %s\n",
658 j
, optable
[j
]->name
, inst
->name
);
660 /* Catch those ops that collide with others already inside the
661 hash, and have a opmask greater than the one we use in the
662 hash. Store them in a special-list, that will handle full
663 32-bit INSN, not only the first 11-bit (or so). */
664 if (optable
[j
] != NULL
665 && inst
->opmask
& ~(opmask
<< (32 - TIC4X_HASH_SIZE
)))
667 /* Add the instruction already on the list. */
668 tic4x_hash_opcode_special (optable_special
, optable
[j
]);
670 /* Add the new instruction. */
671 tic4x_hash_opcode_special (optable_special
, inst
);
674 optable
[j
] = (tic4x_inst_t
*) inst
;
678 /* Disassemble the instruction in 'instruction'.
679 'pc' should be the address of this instruction, it will
680 be used to print the target address if this is a relative jump or call
681 the disassembled instruction is written to 'info'.
682 The function returns the length of this instruction in words. */
685 tic4x_disassemble (unsigned long pc
,
686 unsigned long instruction
,
687 struct disassemble_info
*info
)
689 static tic4x_inst_t
**optable
= NULL
;
690 static tic4x_inst_t
**optable_special
= NULL
;
693 unsigned long tic4x_oplevel
;
695 tic4x_version
= info
->mach
;
697 tic4x_oplevel
= (IS_CPU_TIC4X (tic4x_version
)) ? OP_C4X
: 0;
698 tic4x_oplevel
|= OP_C3X
| OP_LPWR
| OP_IDLE2
| OP_ENH
;
702 optable
= xcalloc (sizeof (tic4x_inst_t
*), (1 << TIC4X_HASH_SIZE
));
704 optable_special
= xcalloc (sizeof (tic4x_inst_t
*), TIC4X_SPESOP_SIZE
);
706 /* Install opcodes in reverse order so that preferred
707 forms overwrite synonyms. */
708 for (i
= tic4x_num_insts
- 1; i
>= 0; i
--)
709 tic4x_hash_opcode (optable
, optable_special
, &tic4x_insts
[i
],
712 /* We now need to remove the insn that are special from the
713 "normal" optable, to make the disasm search this extra list
715 for (i
= 0; i
< TIC4X_SPESOP_SIZE
; i
++)
716 if (optable_special
[i
] != NULL
)
717 optable
[optable_special
[i
]->opcode
>> (32 - TIC4X_HASH_SIZE
)] = NULL
;
720 /* See if we can pick up any loading of the DP register... */
721 if ((instruction
>> 16) == 0x5070 || (instruction
>> 16) == 0x1f70)
722 tic4x_dp
= EXTRU (instruction
, 15, 0);
724 p
= optable
[instruction
>> (32 - TIC4X_HASH_SIZE
)];
727 if (((instruction
& p
->opmask
) == p
->opcode
)
728 && tic4x_print_op (NULL
, instruction
, p
, pc
))
729 tic4x_print_op (info
, instruction
, p
, pc
);
731 (*info
->fprintf_func
) (info
->stream
, "%08lx", instruction
);
735 for (i
= 0; i
<TIC4X_SPESOP_SIZE
; i
++)
736 if (optable_special
[i
] != NULL
737 && optable_special
[i
]->opcode
== instruction
)
739 (*info
->fprintf_func
)(info
->stream
, "%s", optable_special
[i
]->name
);
742 if (i
== TIC4X_SPESOP_SIZE
)
743 (*info
->fprintf_func
) (info
->stream
, "%08lx", instruction
);
746 /* Return size of insn in words. */
750 /* The entry point from objdump and gdb. */
752 print_insn_tic4x (bfd_vma memaddr
, struct disassemble_info
*info
)
759 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
762 (*info
->memory_error_func
) (status
, memaddr
, info
);
767 op
= bfd_getl32 (buffer
);
768 info
->bytes_per_line
= 4;
769 info
->bytes_per_chunk
= 4;
770 info
->octets_per_byte
= 4;
771 info
->display_endian
= BFD_ENDIAN_LITTLE
;
772 return tic4x_disassemble (pc
, op
, info
) * 4;
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