1 /* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils.
3 Copyright 2002 Free Software Foundation, Inc.
5 Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 #include "libiberty.h"
24 #include "opcode/tic4x.h"
28 #define C4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */
29 #define C4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions */
50 static int c4x_version
= 0;
51 static int c4x_dp
= 0;
53 static int c4x_pc_offset
54 PARAMS ((unsigned int));
55 static int c4x_print_char
56 PARAMS ((struct disassemble_info
*, char));
57 static int c4x_print_str
58 PARAMS ((struct disassemble_info
*, char *));
59 static int c4x_print_register
60 PARAMS ((struct disassemble_info
*, unsigned long));
61 static int c4x_print_addr
62 PARAMS ((struct disassemble_info
*, unsigned long));
63 static int c4x_print_relative
64 PARAMS ((struct disassemble_info
*, unsigned long, long, unsigned long));
66 PARAMS ((unsigned int, FILE *, fprintf_ftype
));
67 static int c4x_print_direct
68 PARAMS ((struct disassemble_info
*, unsigned long));
69 static int c4x_print_immed
70 PARAMS ((struct disassemble_info
*, immed_t
, unsigned long));
71 static int c4x_print_cond
72 PARAMS ((struct disassemble_info
*, unsigned int));
73 static int c4x_print_indirect
74 PARAMS ((struct disassemble_info
*, indirect_t
, unsigned long));
75 static int c4x_print_op
76 PARAMS ((struct disassemble_info
*, unsigned long, c4x_inst_t
*, unsigned long));
77 static void c4x_hash_opcode_special
78 PARAMS ((c4x_inst_t
**, const c4x_inst_t
*));
79 static void c4x_hash_opcode
80 PARAMS ((c4x_inst_t
**, c4x_inst_t
**, const c4x_inst_t
*, unsigned long));
81 static int c4x_disassemble
82 PARAMS ((unsigned long, unsigned long, struct disassemble_info
*));
84 PARAMS ((bfd_vma
, struct disassemble_info
*));
91 /* Determine the PC offset for a C[34]x instruction.
92 This could be simplified using some boolean algebra
93 but at the expense of readability. */
97 case 0x62: /* call (C4x) */
98 case 0x64: /* rptb (C4x) */
102 case 0x65: /* rptbd (C4x) */
111 switch ((op
& 0xffe00000) >> 20)
114 case 0x720: /* callB */
115 case 0x740: /* trapB */
118 case 0x6a2: /* bBd */
119 case 0x6a6: /* bBat */
120 case 0x6aa: /* bBaf */
121 case 0x722: /* lajB */
122 case 0x748: /* latB */
123 case 0x798: /* rptbd */
130 switch ((op
& 0xfe200000) >> 20)
132 case 0x6e0: /* dbB */
135 case 0x6e2: /* dbBd */
146 c4x_print_char (info
, ch
)
147 struct disassemble_info
* info
;
151 (*info
->fprintf_func
) (info
->stream
, "%c", ch
);
156 c4x_print_str (info
, str
)
157 struct disassemble_info
*info
;
161 (*info
->fprintf_func
) (info
->stream
, "%s", str
);
166 c4x_print_register (info
, regno
)
167 struct disassemble_info
*info
;
170 static c4x_register_t
**registertable
= NULL
;
173 if (registertable
== NULL
)
175 registertable
= (c4x_register_t
**)
176 xmalloc (sizeof (c4x_register_t
*) * REG_TABLE_SIZE
);
177 for (i
= 0; i
< c3x_num_registers
; i
++)
178 registertable
[c3x_registers
[i
].regno
] = (void *)&c3x_registers
[i
];
179 if (IS_CPU_C4X (c4x_version
))
181 /* Add C4x additional registers, overwriting
182 any C3x registers if necessary. */
183 for (i
= 0; i
< c4x_num_registers
; i
++)
184 registertable
[c4x_registers
[i
].regno
] = (void *)&c4x_registers
[i
];
187 if ((int) regno
> (IS_CPU_C4X (c4x_version
) ? C4X_REG_MAX
: C3X_REG_MAX
))
190 (*info
->fprintf_func
) (info
->stream
, "%s", registertable
[regno
]->name
);
195 c4x_print_addr (info
, addr
)
196 struct disassemble_info
*info
;
200 (*info
->print_address_func
)(addr
, info
);
205 c4x_print_relative (info
, pc
, offset
, opcode
)
206 struct disassemble_info
*info
;
209 unsigned long opcode
;
211 return c4x_print_addr (info
, pc
+ offset
+ c4x_pc_offset (opcode
));
215 c4x_print_direct (info
, arg
)
216 struct disassemble_info
*info
;
221 (*info
->fprintf_func
) (info
->stream
, "@");
222 c4x_print_addr (info
, arg
+ (c4x_dp
<< 16));
227 /* FIXME: make the floating point stuff not rely on host
228 floating point arithmetic. */
230 c4x_print_ftoa (val
, stream
, pfunc
)
240 e
= EXTRS (val
, 31, 24); /* exponent */
243 s
= EXTRU (val
, 23, 23); /* sign bit */
244 f
= EXTRU (val
, 22, 0); /* mantissa */
249 num
= f
/ (double)(1 << 23);
250 num
= ldexp (num
, e
);
252 (*pfunc
)(stream
, "%.9g", num
);
256 c4x_print_immed (info
, type
, arg
)
257 struct disassemble_info
*info
;
272 (*info
->fprintf_func
) (info
->stream
, "%d", (long)arg
);
277 (*info
->fprintf_func
) (info
->stream
, "%u", arg
);
281 e
= EXTRS (arg
, 15, 12);
284 s
= EXTRU (arg
, 11, 11);
285 f
= EXTRU (arg
, 10, 0);
290 num
= f
/ (double)(1 << 11);
291 num
= ldexp (num
, e
);
293 (*info
->fprintf_func
) (info
->stream
, "%f", num
);
296 e
= EXTRS (arg
, 31, 24);
299 s
= EXTRU (arg
, 23, 23);
300 f
= EXTRU (arg
, 22, 0);
305 num
= f
/ (double)(1 << 23);
306 num
= ldexp (num
, e
);
308 (*info
->fprintf_func
) (info
->stream
, "%f", num
);
315 c4x_print_cond (info
, cond
)
316 struct disassemble_info
*info
;
319 static c4x_cond_t
**condtable
= NULL
;
322 if (condtable
== NULL
)
324 condtable
= (c4x_cond_t
**)xmalloc (sizeof (c4x_cond_t
*) * 32);
325 for (i
= 0; i
< num_conds
; i
++)
326 condtable
[c4x_conds
[i
].cond
] = (void *)&c4x_conds
[i
];
328 if (cond
> 31 || condtable
[cond
] == NULL
)
331 (*info
->fprintf_func
) (info
->stream
, "%s", condtable
[cond
]->name
);
336 c4x_print_indirect (info
, type
, arg
)
337 struct disassemble_info
*info
;
351 case INDIRECT_C4X
: /* *+ARn(disp) */
352 disp
= EXTRU (arg
, 7, 3);
353 aregno
= EXTRU (arg
, 2, 0) + REG_AR0
;
358 aregno
= EXTRU (arg
, 2, 0) + REG_AR0
;
359 modn
= EXTRU (arg
, 7, 3);
362 disp
= EXTRU (arg
, 7, 0);
363 aregno
= EXTRU (arg
, 10, 8) + REG_AR0
;
364 modn
= EXTRU (arg
, 15, 11);
365 if (modn
> 7 && disp
!= 0)
371 if (modn
> C3X_MODN_MAX
)
373 a
= c4x_indirects
[modn
].name
;
379 c4x_print_register (info
, aregno
);
382 c4x_print_immed (info
, IMMED_UINT
, disp
);
385 c4x_print_str (info
, "ir0");
388 c4x_print_str (info
, "ir1");
391 c4x_print_char (info
, *a
);
400 c4x_print_op (info
, instruction
, p
, pc
)
401 struct disassemble_info
*info
;
402 unsigned long instruction
;
408 char *parallel
= NULL
;
410 /* Print instruction name. */
412 while (*s
&& parallel
== NULL
)
417 if (! c4x_print_cond (info
, EXTRU (instruction
, 20, 16)))
421 if (! c4x_print_cond (info
, EXTRU (instruction
, 27, 23)))
425 parallel
= s
+ 1; /* Skip past `_' in name */
428 c4x_print_char (info
, *s
);
434 /* Print arguments. */
437 c4x_print_char (info
, ' ');
443 case '*': /* indirect 0--15 */
444 if (! c4x_print_indirect (info
, INDIRECT_LONG
,
445 EXTRU (instruction
, 15, 0)))
449 case '#': /* only used for ldp, ldpk */
450 c4x_print_immed (info
, IMMED_UINT
, EXTRU (instruction
, 15, 0));
453 case '@': /* direct 0--15 */
454 c4x_print_direct (info
, EXTRU (instruction
, 15, 0));
457 case 'A': /* address register 24--22 */
458 if (! c4x_print_register (info
, EXTRU (instruction
, 24, 22) +
463 case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb
465 if (IS_CPU_C4X (c4x_version
))
466 c4x_print_relative (info
, pc
, EXTRS (instruction
, 23, 0),
469 c4x_print_addr (info
, EXTRU (instruction
, 23, 0));
472 case 'C': /* indirect (short C4x) 0--7 */
473 if (! IS_CPU_C4X (c4x_version
))
475 if (! c4x_print_indirect (info
, INDIRECT_C4X
,
476 EXTRU (instruction
, 7, 0)))
481 /* Cockup if get here... */
484 case 'E': /* register 0--7 */
486 if (! c4x_print_register (info
, EXTRU (instruction
, 7, 0)))
490 case 'F': /* 16-bit float immediate 0--15 */
491 c4x_print_immed (info
, IMMED_SFLOAT
,
492 EXTRU (instruction
, 15, 0));
495 case 'i': /* Extended indirect 0--7 */
496 if ( EXTRU (instruction
, 7, 5) == 7 )
498 if( !c4x_print_register (info
, EXTRU (instruction
, 4, 0)) )
504 case 'I': /* indirect (short) 0--7 */
505 if (! c4x_print_indirect (info
, INDIRECT_SHORT
,
506 EXTRU (instruction
, 7, 0)))
510 case 'j': /* Extended indirect 8--15 */
511 if ( EXTRU (instruction
, 15, 13) == 7 )
513 if( !c4x_print_register (info
, EXTRU (instruction
, 12, 8)) )
518 case 'J': /* indirect (short) 8--15 */
519 if (! c4x_print_indirect (info
, INDIRECT_SHORT
,
520 EXTRU (instruction
, 15, 8)))
524 case 'G': /* register 8--15 */
526 if (! c4x_print_register (info
, EXTRU (instruction
, 15, 8)))
530 case 'H': /* register 16--18 */
531 if (! c4x_print_register (info
, EXTRU (instruction
, 18, 16)))
535 case 'K': /* register 19--21 */
536 if (! c4x_print_register (info
, EXTRU (instruction
, 21, 19)))
540 case 'L': /* register 22--24 */
541 if (! c4x_print_register (info
, EXTRU (instruction
, 24, 22)))
545 case 'M': /* register 22--22 */
546 c4x_print_register (info
, EXTRU (instruction
, 22, 22) + REG_R2
);
549 case 'N': /* register 23--23 */
550 c4x_print_register (info
, EXTRU (instruction
, 23, 23) + REG_R0
);
553 case 'O': /* indirect (short C4x) 8--15 */
554 if (! IS_CPU_C4X (c4x_version
))
556 if (! c4x_print_indirect (info
, INDIRECT_C4X
,
557 EXTRU (instruction
, 15, 8)))
561 case 'P': /* displacement 0--15 (used by Bcond and BcondD) */
562 c4x_print_relative (info
, pc
, EXTRS (instruction
, 15, 0),
566 case 'Q': /* register 0--15 */
568 if (! c4x_print_register (info
, EXTRU (instruction
, 15, 0)))
572 case 'R': /* register 16--20 */
574 if (! c4x_print_register (info
, EXTRU (instruction
, 20, 16)))
578 case 'S': /* 16-bit signed immediate 0--15 */
579 c4x_print_immed (info
, IMMED_SINT
,
580 EXTRS (instruction
, 15, 0));
583 case 'T': /* 5-bit signed immediate 16--20 (C4x stik) */
584 if (! IS_CPU_C4X (c4x_version
))
586 if (! c4x_print_immed (info
, IMMED_SUINT
,
587 EXTRU (instruction
, 20, 16)))
591 case 'U': /* 16-bit unsigned int immediate 0--15 */
592 c4x_print_immed (info
, IMMED_SUINT
, EXTRU (instruction
, 15, 0));
595 case 'V': /* 5/9-bit unsigned vector 0--4/8 */
596 c4x_print_immed (info
, IMMED_SUINT
,
597 IS_CPU_C4X (c4x_version
) ?
598 EXTRU (instruction
, 8, 0) :
599 EXTRU (instruction
, 4, 0) & ~0x20);
602 case 'W': /* 8-bit signed immediate 0--7 */
603 if (! IS_CPU_C4X (c4x_version
))
605 c4x_print_immed (info
, IMMED_SINT
, EXTRS (instruction
, 7, 0));
608 case 'X': /* expansion register 4--0 */
609 val
= EXTRU (instruction
, 4, 0) + REG_IVTP
;
610 if (val
< REG_IVTP
|| val
> REG_TVTP
)
612 if (! c4x_print_register (info
, val
))
616 case 'Y': /* address register 16--20 */
617 val
= EXTRU (instruction
, 20, 16);
618 if (val
< REG_AR0
|| val
> REG_SP
)
620 if (! c4x_print_register (info
, val
))
624 case 'Z': /* expansion register 16--20 */
625 val
= EXTRU (instruction
, 20, 16) + REG_IVTP
;
626 if (val
< REG_IVTP
|| val
> REG_TVTP
)
628 if (! c4x_print_register (info
, val
))
632 case '|': /* Parallel instruction */
633 c4x_print_str (info
, " || ");
634 c4x_print_str (info
, parallel
);
635 c4x_print_char (info
, ' ');
639 c4x_print_char (info
, ',');
643 c4x_print_char (info
, *s
);
652 c4x_hash_opcode_special (optable_special
, inst
)
653 c4x_inst_t
**optable_special
;
654 const c4x_inst_t
*inst
;
658 for( i
=0; i
<C4X_SPESOP_SIZE
; i
++ )
659 if( optable_special
[i
] != NULL
660 && optable_special
[i
]->opcode
== inst
->opcode
)
662 /* Collision (we have it already) - overwrite */
663 optable_special
[i
] = (void *)inst
;
667 for( i
=0; i
<C4X_SPESOP_SIZE
; i
++ )
668 if( optable_special
[i
] == NULL
)
670 /* Add the new opcode */
671 optable_special
[i
] = (void *)inst
;
675 /* This should never occur. This happens if the number of special
676 instructions exceeds C4X_SPESOP_SIZE. Please increase the variable
679 printf("optable_special[] is full, please increase C4X_SPESOP_SIZE!\n");
684 c4x_hash_opcode (optable
, optable_special
, inst
, c4x_oplevel
)
685 c4x_inst_t
**optable
;
686 c4x_inst_t
**optable_special
;
687 const c4x_inst_t
*inst
;
688 const unsigned long c4x_oplevel
;
691 int opcode
= inst
->opcode
>> (32 - C4X_HASH_SIZE
);
692 int opmask
= inst
->opmask
>> (32 - C4X_HASH_SIZE
);
694 /* Use a C4X_HASH_SIZE bit index as a hash index. We should
695 have unique entries so there's no point having a linked list
697 for (j
= opcode
; j
< opmask
; j
++)
698 if ( (j
& opmask
) == opcode
699 && inst
->oplevel
& c4x_oplevel
)
702 /* We should only have collisions for synonyms like
704 if (optable
[j
] != NULL
)
705 printf("Collision at index %d, %s and %s\n",
706 j
, optable
[j
]->name
, inst
->name
);
708 /* Catch those ops that collide with others already inside the
709 hash, and have a opmask greater than the one we use in the
710 hash. Store them in a special-list, that will handle full
711 32-bit INSN, not only the first 11-bit (or so). */
712 if ( optable
[j
] != NULL
713 && inst
->opmask
& ~(opmask
<< (32 - C4X_HASH_SIZE
)) )
715 /* Add the instruction already on the list */
716 c4x_hash_opcode_special(optable_special
, optable
[j
]);
718 /* Add the new instruction */
719 c4x_hash_opcode_special(optable_special
, inst
);
722 optable
[j
] = (void *)inst
;
726 /* Disassemble the instruction in 'instruction'.
727 'pc' should be the address of this instruction, it will
728 be used to print the target address if this is a relative jump or call
729 the disassembled instruction is written to 'info'.
730 The function returns the length of this instruction in words. */
733 c4x_disassemble (pc
, instruction
, info
)
735 unsigned long instruction
;
736 struct disassemble_info
*info
;
738 static c4x_inst_t
**optable
= NULL
;
739 static c4x_inst_t
**optable_special
= NULL
;
742 unsigned long c4x_oplevel
;
744 c4x_version
= info
->mach
;
746 c4x_oplevel
= (IS_CPU_C4X (c4x_version
)) ? OP_C4X
: 0;
747 c4x_oplevel
|= OP_C3X
|OP_LPWR
|OP_IDLE2
|OP_ENH
;
751 optable
= (c4x_inst_t
**)
752 xcalloc (sizeof (c4x_inst_t
*), (1 << C4X_HASH_SIZE
));
754 optable_special
= (c4x_inst_t
**)
755 xcalloc (sizeof (c4x_inst_t
*), C4X_SPESOP_SIZE
);
757 /* Install opcodes in reverse order so that preferred
758 forms overwrite synonyms. */
759 for (i
= c4x_num_insts
- 1; i
>= 0; i
--)
760 c4x_hash_opcode (optable
, optable_special
, &c4x_insts
[i
], c4x_oplevel
);
762 /* We now need to remove the insn that are special from the
763 "normal" optable, to make the disasm search this extra list
766 for (i
=0; i
<C4X_SPESOP_SIZE
; i
++)
767 if ( optable_special
[i
] != NULL
)
768 optable
[optable_special
[i
]->opcode
>> (32 - C4X_HASH_SIZE
)] = NULL
;
771 /* See if we can pick up any loading of the DP register... */
772 if ((instruction
>> 16) == 0x5070 || (instruction
>> 16) == 0x1f70)
773 c4x_dp
= EXTRU (instruction
, 15, 0);
775 p
= optable
[instruction
>> (32 - C4X_HASH_SIZE
)];
778 if ( ((instruction
& p
->opmask
) == p
->opcode
)
779 && c4x_print_op (NULL
, instruction
, p
, pc
) )
780 c4x_print_op (info
, instruction
, p
, pc
);
782 (*info
->fprintf_func
) (info
->stream
, "%08x", instruction
);
786 for (i
= 0; i
<C4X_SPESOP_SIZE
; i
++)
787 if (optable_special
[i
] != NULL
788 && optable_special
[i
]->opcode
== instruction
)
790 (*info
->fprintf_func
)(info
->stream
, "%s", optable_special
[i
]->name
);
793 if (i
==C4X_SPESOP_SIZE
)
794 (*info
->fprintf_func
) (info
->stream
, "%08x", instruction
);
797 /* Return size of insn in words. */
801 /* The entry point from objdump and gdb. */
803 print_insn_tic4x (memaddr
, info
)
805 struct disassemble_info
*info
;
812 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
815 (*info
->memory_error_func
) (status
, memaddr
, info
);
820 op
= bfd_getl32 (buffer
);
821 info
->bytes_per_line
= 4;
822 info
->bytes_per_chunk
= 4;
823 info
->octets_per_byte
= 4;
824 info
->display_endian
= BFD_ENDIAN_LITTLE
;
825 return c4x_disassemble (pc
, op
, info
) * 4;
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