opcodes/tic4x-dis.c

   1 /* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils.
   2
   3    Copyright (C) 2002-2019 Free Software Foundation, Inc.
   4
   5    Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
   6
   7    This file is part of the GNU opcodes library.
   8
   9    This library is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <math.h>
  26 #include "libiberty.h"
  27 #include "disassemble.h"
  28 #include "opcode/tic4x.h"
  29
  30 #define TIC4X_DEBUG 0
  31
  32 #define TIC4X_HASH_SIZE   11   /* 11 (bits) and above should give unique entries.  */
  33 #define TIC4X_SPESOP_SIZE 8    /* Max 8. ops for special instructions.  */
  34
  35 typedef enum
  36 {
  37   IMMED_SINT,
  38   IMMED_SUINT,
  39   IMMED_SFLOAT,
  40   IMMED_INT,
  41   IMMED_UINT,
  42   IMMED_FLOAT
  43 }
  44 immed_t;
  45
  46 typedef enum
  47 {
  48   INDIRECT_SHORT,
  49   INDIRECT_LONG,
  50   INDIRECT_TIC4X
  51 }
  52 indirect_t;
  53
  54 static int tic4x_version = 0;
  55 static int tic4x_dp = 0;
  56
  57 static int
  58 tic4x_pc_offset (unsigned int op)
  59 {
  60   /* Determine the PC offset for a C[34]x instruction.
  61      This could be simplified using some boolean algebra
  62      but at the expense of readability.  */
  63   switch (op >> 24)
  64     {
  65     case 0x60:  /* br */
  66     case 0x62:  /* call  (C4x) */
  67     case 0x64:  /* rptb  (C4x) */
  68       return 1;
  69     case 0x61:  /* brd */
  70     case 0x63:  /* laj */
  71     case 0x65:  /* rptbd (C4x) */
  72       return 3;
  73     case 0x66:  /* swi */
  74     case 0x67:
  75       return 0;
  76     default:
  77       break;
  78     }
  79
  80   switch ((op & 0xffe00000) >> 20)
  81     {
  82     case 0x6a0: /* bB */
  83     case 0x720: /* callB */
  84     case 0x740: /* trapB */
  85       return 1;
  86
  87     case 0x6a2: /* bBd */
  88     case 0x6a6: /* bBat */
  89     case 0x6aa: /* bBaf */
  90     case 0x722: /* lajB */
  91     case 0x748: /* latB */
  92     case 0x798: /* rptbd */
  93       return 3;
  94
  95     default:
  96       break;
  97     }
  98
  99   switch ((op & 0xfe200000) >> 20)
 100     {
 101     case 0x6e0: /* dbB */
 102       return 1;
 103
 104     case 0x6e2: /* dbBd */
 105       return 3;
 106
 107     default:
 108       break;
 109     }
 110
 111   return 0;
 112 }
 113
 114 static int
 115 tic4x_print_char (struct disassemble_info * info, char ch)
 116 {
 117   if (info != NULL)
 118     (*info->fprintf_func) (info->stream, "%c", ch);
 119   return 1;
 120 }
 121
 122 static int
 123 tic4x_print_str (struct disassemble_info *info, const char *str)
 124 {
 125   if (info != NULL)
 126     (*info->fprintf_func) (info->stream, "%s", str);
 127   return 1;
 128 }
 129
 130 static int
 131 tic4x_print_register (struct disassemble_info *info, unsigned long regno)
 132 {
 133   static tic4x_register_t ** registertable = NULL;
 134   unsigned int i;
 135
 136   if (registertable == NULL)
 137     {
 138       registertable = xmalloc (sizeof (tic4x_register_t *) * REG_TABLE_SIZE);
 139       for (i = 0; i < tic3x_num_registers; i++)
 140         registertable[tic3x_registers[i].regno]
 141           = (tic4x_register_t *) (tic3x_registers + i);
 142       if (IS_CPU_TIC4X (tic4x_version))
 143         {
 144           /* Add C4x additional registers, overwriting
 145              any C3x registers if necessary.  */
 146           for (i = 0; i < tic4x_num_registers; i++)
 147             registertable[tic4x_registers[i].regno]
 148               = (tic4x_register_t *)(tic4x_registers + i);
 149         }
 150     }
 151   if (regno > (IS_CPU_TIC4X (tic4x_version) ? TIC4X_REG_MAX : TIC3X_REG_MAX)
 152       || registertable[regno] == NULL)
 153     return 0;
 154   if (info != NULL)
 155     (*info->fprintf_func) (info->stream, "%s", registertable[regno]->name);
 156   return 1;
 157 }
 158
 159 static int
 160 tic4x_print_addr (struct disassemble_info *info, unsigned long addr)
 161 {
 162   if (info != NULL)
 163     (*info->print_address_func)(addr, info);
 164   return 1;
 165 }
 166
 167 static int
 168 tic4x_print_relative (struct disassemble_info *info,
 169                       unsigned long pc,
 170                       long offset,
 171                       unsigned long opcode)
 172 {
 173   return tic4x_print_addr (info, pc + offset + tic4x_pc_offset (opcode));
 174 }
 175
 176 static int
 177 tic4x_print_direct (struct disassemble_info *info, unsigned long arg)
 178 {
 179   if (info != NULL)
 180     {
 181       (*info->fprintf_func) (info->stream, "@");
 182       tic4x_print_addr (info, arg + (tic4x_dp << 16));
 183     }
 184   return 1;
 185 }
 186 #if 0
 187 /* FIXME: make the floating point stuff not rely on host
 188    floating point arithmetic.  */
 189
 190 static void
 191 tic4x_print_ftoa (unsigned int val, FILE *stream, fprintf_ftype pfunc)
 192 {
 193   int e;
 194   int s;
 195   int f;
 196   double num = 0.0;
 197
 198   e = EXTRS (val, 31, 24);      /* Exponent.  */
 199   if (e != -128)
 200     {
 201       s = EXTRU (val, 23, 23);  /* Sign bit.  */
 202       f = EXTRU (val, 22, 0);   /* Mantissa.  */
 203       if (s)
 204         f += -2 * (1 << 23);
 205       else
 206         f += (1 << 23);
 207       num = f / (double)(1 << 23);
 208       num = ldexp (num, e);
 209     }
 210   (*pfunc)(stream, "%.9g", num);
 211 }
 212 #endif
 213
 214 static int
 215 tic4x_print_immed (struct disassemble_info *info,
 216                    immed_t type,
 217                    unsigned long arg)
 218 {
 219   int s;
 220   int f;
 221   int e;
 222   double num = 0.0;
 223
 224   if (info == NULL)
 225     return 1;
 226   switch (type)
 227     {
 228     case IMMED_SINT:
 229     case IMMED_INT:
 230       (*info->fprintf_func) (info->stream, "%ld", (long) arg);
 231       break;
 232
 233     case IMMED_SUINT:
 234     case IMMED_UINT:
 235       (*info->fprintf_func) (info->stream, "%lu", arg);
 236       break;
 237
 238     case IMMED_SFLOAT:
 239       e = EXTRS (arg, 15, 12);
 240       if (e != -8)
 241         {
 242           s = EXTRU (arg, 11, 11);
 243           f = EXTRU (arg, 10, 0);
 244           if (s)
 245             f += -2 * (1 << 11);
 246           else
 247             f += (1 << 11);
 248           num = f / (double)(1 << 11);
 249           num = ldexp (num, e);
 250         }
 251       (*info->fprintf_func) (info->stream, "%f", num);
 252       break;
 253     case IMMED_FLOAT:
 254       e = EXTRS (arg, 31, 24);
 255       if (e != -128)
 256         {
 257           s = EXTRU (arg, 23, 23);
 258           f = EXTRU (arg, 22, 0);
 259           if (s)
 260             f += -2 * (1 << 23);
 261           else
 262             f += (1 << 23);
 263           num = f / (double)(1 << 23);
 264           num = ldexp (num, e);
 265         }
 266       (*info->fprintf_func) (info->stream, "%f", num);
 267       break;
 268     }
 269   return 1;
 270 }
 271
 272 static int
 273 tic4x_print_cond (struct disassemble_info *info, unsigned int cond)
 274 {
 275   static tic4x_cond_t **condtable = NULL;
 276   unsigned int i;
 277
 278   if (condtable == NULL)
 279     {
 280       condtable = xmalloc (sizeof (tic4x_cond_t *) * 32);
 281       for (i = 0; i < tic4x_num_conds; i++)
 282         condtable[tic4x_conds[i].cond] = (tic4x_cond_t *)(tic4x_conds + i);
 283     }
 284   if (cond > 31 || condtable[cond] == NULL)
 285     return 0;
 286   if (info != NULL)
 287     (*info->fprintf_func) (info->stream, "%s", condtable[cond]->name);
 288   return 1;
 289 }
 290
 291 static int
 292 tic4x_print_indirect (struct disassemble_info *info,
 293                       indirect_t type,
 294                       unsigned long arg)
 295 {
 296   unsigned int aregno;
 297   unsigned int modn;
 298   unsigned int disp;
 299   const char *a;
 300
 301   aregno = 0;
 302   modn = 0;
 303   disp = 1;
 304   switch(type)
 305     {
 306     case INDIRECT_TIC4X:                /* *+ARn(disp) */
 307       disp = EXTRU (arg, 7, 3);
 308       aregno = EXTRU (arg, 2, 0) + REG_AR0;
 309       modn = 0;
 310       break;
 311     case INDIRECT_SHORT:
 312       disp = 1;
 313       aregno = EXTRU (arg, 2, 0) + REG_AR0;
 314       modn = EXTRU (arg, 7, 3);
 315       break;
 316     case INDIRECT_LONG:
 317       disp = EXTRU (arg, 7, 0);
 318       aregno = EXTRU (arg, 10, 8) + REG_AR0;
 319       modn = EXTRU (arg, 15, 11);
 320       if (modn > 7 && disp != 0)
 321         return 0;
 322       break;
 323     default:
 324         (*info->fprintf_func)(info->stream, "# internal error: Unknown indirect type %d", type);
 325         return 0;
 326     }
 327   if (modn > TIC3X_MODN_MAX)
 328     return 0;
 329   a = tic4x_indirects[modn].name;
 330   while (*a)
 331     {
 332       switch (*a)
 333         {
 334         case 'a':
 335           tic4x_print_register (info, aregno);
 336           break;
 337         case 'd':
 338           tic4x_print_immed (info, IMMED_UINT, disp);
 339           break;
 340         case 'y':
 341           tic4x_print_str (info, "ir0");
 342           break;
 343         case 'z':
 344           tic4x_print_str (info, "ir1");
 345           break;
 346         default:
 347           tic4x_print_char (info, *a);
 348           break;
 349         }
 350       a++;
 351     }
 352   return 1;
 353 }
 354
 355 static int
 356 tic4x_print_op (struct disassemble_info *info,
 357                 unsigned long instruction,
 358                 tic4x_inst_t *p,
 359                 unsigned long pc)
 360 {
 361   int val;
 362   const char *s;
 363   const char *parallel = NULL;
 364
 365   /* Print instruction name.  */
 366   s = p->name;
 367   while (*s && parallel == NULL)
 368     {
 369       switch (*s)
 370         {
 371         case 'B':
 372           if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16)))
 373             return 0;
 374           break;
 375         case 'C':
 376           if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23)))
 377             return 0;
 378           break;
 379         case '_':
 380           parallel = s + 1;     /* Skip past `_' in name.  */
 381           break;
 382         default:
 383           tic4x_print_char (info, *s);
 384           break;
 385         }
 386       s++;
 387     }
 388
 389   /* Print arguments.  */
 390   s = p->args;
 391   if (*s)
 392     tic4x_print_char (info, ' ');
 393
 394   while (*s)
 395     {
 396       switch (*s)
 397         {
 398         case '*': /* Indirect 0--15.  */
 399           if (! tic4x_print_indirect (info, INDIRECT_LONG,
 400                                       EXTRU (instruction, 15, 0)))
 401             return 0;
 402           break;
 403
 404         case '#': /* Only used for ldp, ldpk.  */
 405           tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
 406           break;
 407
 408         case '@': /* Direct 0--15.  */
 409           tic4x_print_direct (info, EXTRU (instruction, 15, 0));
 410           break;
 411
 412         case 'A': /* Address register 24--22.  */
 413           if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) +
 414                                       REG_AR0))
 415             return 0;
 416           break;
 417
 418         case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb
 419                      address 0--23.  */
 420           if (IS_CPU_TIC4X (tic4x_version))
 421             tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0),
 422                                   p->opcode);
 423           else
 424             tic4x_print_addr (info, EXTRU (instruction, 23, 0));
 425           break;
 426
 427         case 'C': /* Indirect (short C4x) 0--7.  */
 428           if (! IS_CPU_TIC4X (tic4x_version))
 429             return 0;
 430           if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
 431                                       EXTRU (instruction, 7, 0)))
 432             return 0;
 433           break;
 434
 435         case 'D':
 436           /* Cockup if get here...  */
 437           break;
 438
 439         case 'E': /* Register 0--7.  */
 440         case 'e':
 441           if (! tic4x_print_register (info, EXTRU (instruction, 7, 0)))
 442             return 0;
 443           break;
 444
 445         case 'F': /* 16-bit float immediate 0--15.  */
 446           tic4x_print_immed (info, IMMED_SFLOAT,
 447                              EXTRU (instruction, 15, 0));
 448           break;
 449
 450         case 'i': /* Extended indirect 0--7.  */
 451           if (EXTRU (instruction, 7, 5) == 7)
 452             {
 453               if (!tic4x_print_register (info, EXTRU (instruction, 4, 0)))
 454                 return 0;
 455               break;
 456             }
 457           /* Fallthrough */
 458
 459         case 'I': /* Indirect (short) 0--7.  */
 460           if (! tic4x_print_indirect (info, INDIRECT_SHORT,
 461                                       EXTRU (instruction, 7, 0)))
 462             return 0;
 463           break;
 464
 465         case 'j': /* Extended indirect 8--15 */
 466           if (EXTRU (instruction, 15, 13) == 7)
 467             {
 468               if (! tic4x_print_register (info, EXTRU (instruction, 12, 8)))
 469                 return 0;
 470               break;
 471             }
 472           /* Fall through.  */
 473
 474         case 'J': /* Indirect (short) 8--15.  */
 475           if (! tic4x_print_indirect (info, INDIRECT_SHORT,
 476                                       EXTRU (instruction, 15, 8)))
 477             return 0;
 478           break;
 479
 480         case 'G': /* Register 8--15.  */
 481         case 'g':
 482           if (! tic4x_print_register (info, EXTRU (instruction, 15, 8)))
 483             return 0;
 484           break;
 485
 486         case 'H': /* Register 16--18.  */
 487           if (! tic4x_print_register (info, EXTRU (instruction, 18, 16)))
 488             return 0;
 489           break;
 490
 491         case 'K': /* Register 19--21.  */
 492           if (! tic4x_print_register (info, EXTRU (instruction, 21, 19)))
 493             return 0;
 494           break;
 495
 496         case 'L': /* Register 22--24.  */
 497           if (! tic4x_print_register (info, EXTRU (instruction, 24, 22)))
 498             return 0;
 499           break;
 500
 501         case 'M': /* Register 22--22.  */
 502           tic4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2);
 503           break;
 504
 505         case 'N': /* Register 23--23.  */
 506           tic4x_print_register (info, EXTRU (instruction, 23, 23) + REG_R0);
 507           break;
 508
 509         case 'O': /* Indirect (short C4x) 8--15.  */
 510           if (! IS_CPU_TIC4X (tic4x_version))
 511             return 0;
 512           if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
 513                                       EXTRU (instruction, 15, 8)))
 514             return 0;
 515           break;
 516
 517         case 'P': /* Displacement 0--15 (used by Bcond and BcondD).  */
 518           tic4x_print_relative (info, pc, EXTRS (instruction, 15, 0),
 519                                 p->opcode);
 520           break;
 521
 522         case 'Q': /* Register 0--15.  */
 523         case 'q':
 524           if (! tic4x_print_register (info, EXTRU (instruction, 15, 0)))
 525             return 0;
 526           break;
 527
 528         case 'R': /* Register 16--20.  */
 529         case 'r':
 530           if (! tic4x_print_register (info, EXTRU (instruction, 20, 16)))
 531             return 0;
 532           break;
 533
 534         case 'S': /* 16-bit signed immediate 0--15.  */
 535           tic4x_print_immed (info, IMMED_SINT,
 536                              EXTRS (instruction, 15, 0));
 537           break;
 538
 539         case 'T': /* 5-bit signed immediate 16--20  (C4x stik).  */
 540           if (! IS_CPU_TIC4X (tic4x_version))
 541             return 0;
 542           if (! tic4x_print_immed (info, IMMED_SUINT,
 543                                    EXTRU (instruction, 20, 16)))
 544             return 0;
 545           break;
 546
 547         case 'U': /* 16-bit unsigned int immediate 0--15.  */
 548           tic4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0));
 549           break;
 550
 551         case 'V': /* 5/9-bit unsigned vector 0--4/8.  */
 552           tic4x_print_immed (info, IMMED_SUINT,
 553                              IS_CPU_TIC4X (tic4x_version) ?
 554                              EXTRU (instruction, 8, 0) :
 555                              EXTRU (instruction, 4, 0) & ~0x20);
 556           break;
 557
 558         case 'W': /* 8-bit signed immediate 0--7.  */
 559           if (! IS_CPU_TIC4X (tic4x_version))
 560             return 0;
 561           tic4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0));
 562           break;
 563
 564         case 'X': /* Expansion register 4--0.  */
 565           val = EXTRU (instruction, 4, 0) + REG_IVTP;
 566           if (val < REG_IVTP || val > REG_TVTP)
 567             return 0;
 568           if (! tic4x_print_register (info, val))
 569             return 0;
 570           break;
 571
 572         case 'Y': /* Address register 16--20.  */
 573           val = EXTRU (instruction, 20, 16);
 574           if (val < REG_AR0 || val > REG_SP)
 575             return 0;
 576           if (! tic4x_print_register (info, val))
 577             return 0;
 578           break;
 579
 580         case 'Z': /* Expansion register 16--20.  */
 581           val = EXTRU (instruction, 20, 16) + REG_IVTP;
 582           if (val < REG_IVTP || val > REG_TVTP)
 583             return 0;
 584           if (! tic4x_print_register (info, val))
 585             return 0;
 586           break;
 587
 588         case '|':       /* Parallel instruction.  */
 589           tic4x_print_str (info, " || ");
 590           tic4x_print_str (info, parallel);
 591           tic4x_print_char (info, ' ');
 592           break;
 593
 594         case ';':
 595           tic4x_print_char (info, ',');
 596           break;
 597
 598         default:
 599           tic4x_print_char (info, *s);
 600           break;
 601         }
 602       s++;
 603     }
 604   return 1;
 605 }
 606
 607 static void
 608 tic4x_hash_opcode_special (tic4x_inst_t **optable_special,
 609                            const tic4x_inst_t *inst)
 610 {
 611   int i;
 612
 613   for (i = 0;i < TIC4X_SPESOP_SIZE; i++)
 614     if (optable_special[i] != NULL
 615         && optable_special[i]->opcode == inst->opcode)
 616       {
 617         /* Collision (we have it already) - overwrite.  */
 618         optable_special[i] = (tic4x_inst_t *) inst;
 619         return;
 620       }
 621
 622   for (i = 0; i < TIC4X_SPESOP_SIZE; i++)
 623     if (optable_special[i] == NULL)
 624       {
 625         /* Add the new opcode.  */
 626         optable_special[i] = (tic4x_inst_t *) inst;
 627         return;
 628       }
 629
 630   /* This should never occur. This happens if the number of special
 631      instructions exceeds TIC4X_SPESOP_SIZE. Please increase the variable
 632      of this variable */
 633 #if TIC4X_DEBUG
 634   printf ("optable_special[] is full, please increase TIC4X_SPESOP_SIZE!\n");
 635 #endif
 636 }
 637
 638 static void
 639 tic4x_hash_opcode (tic4x_inst_t **optable,
 640                    tic4x_inst_t **optable_special,
 641                    const tic4x_inst_t *inst,
 642                    const unsigned long tic4x_oplevel)
 643 {
 644   unsigned int j;
 645   unsigned int opcode = inst->opcode >> (32 - TIC4X_HASH_SIZE);
 646   unsigned int opmask = inst->opmask >> (32 - TIC4X_HASH_SIZE);
 647
 648   /* Use a TIC4X_HASH_SIZE bit index as a hash index.  We should
 649      have unique entries so there's no point having a linked list
 650      for each entry?  */
 651   for (j = opcode; j < opmask; j++)
 652     if ((j & opmask) == opcode
 653          && inst->oplevel & tic4x_oplevel)
 654       {
 655 #if TIC4X_DEBUG
 656         /* We should only have collisions for synonyms like
 657            ldp for ldi.  */
 658         if (optable[j] != NULL)
 659           printf ("Collision at index %d, %s and %s\n",
 660                   j, optable[j]->name, inst->name);
 661 #endif
 662         /* Catch those ops that collide with others already inside the
 663            hash, and have a opmask greater than the one we use in the
 664            hash. Store them in a special-list, that will handle full
 665            32-bit INSN, not only the first 11-bit (or so). */
 666         if (optable[j] != NULL
 667             && inst->opmask & ~(opmask << (32 - TIC4X_HASH_SIZE)))
 668           {
 669             /* Add the instruction already on the list.  */
 670             tic4x_hash_opcode_special (optable_special, optable[j]);
 671
 672             /* Add the new instruction.  */
 673             tic4x_hash_opcode_special (optable_special, inst);
 674           }
 675
 676         optable[j] = (tic4x_inst_t *) inst;
 677       }
 678 }
 679
 680 /* Disassemble the instruction in 'instruction'.
 681    'pc' should be the address of this instruction, it will
 682    be used to print the target address if this is a relative jump or call
 683    the disassembled instruction is written to 'info'.
 684    The function returns the length of this instruction in words.  */
 685
 686 static int
 687 tic4x_disassemble (unsigned long pc,
 688                    unsigned long instruction,
 689                    struct disassemble_info *info)
 690 {
 691   static tic4x_inst_t **optable = NULL;
 692   static tic4x_inst_t **optable_special = NULL;
 693   tic4x_inst_t *p;
 694   int i;
 695   unsigned long tic4x_oplevel;
 696
 697   tic4x_version = info->mach;
 698
 699   tic4x_oplevel  = (IS_CPU_TIC4X (tic4x_version)) ? OP_C4X : 0;
 700   tic4x_oplevel |= OP_C3X | OP_LPWR | OP_IDLE2 | OP_ENH;
 701
 702   if (optable == NULL)
 703     {
 704       optable = xcalloc (sizeof (tic4x_inst_t *), (1 << TIC4X_HASH_SIZE));
 705
 706       optable_special = xcalloc (sizeof (tic4x_inst_t *), TIC4X_SPESOP_SIZE);
 707
 708       /* Install opcodes in reverse order so that preferred
 709          forms overwrite synonyms.  */
 710       for (i = tic4x_num_insts - 1; i >= 0; i--)
 711         tic4x_hash_opcode (optable, optable_special, &tic4x_insts[i],
 712                            tic4x_oplevel);
 713
 714       /* We now need to remove the insn that are special from the
 715          "normal" optable, to make the disasm search this extra list
 716          for them.  */
 717       for (i = 0; i < TIC4X_SPESOP_SIZE; i++)
 718         if (optable_special[i] != NULL)
 719           optable[optable_special[i]->opcode >> (32 - TIC4X_HASH_SIZE)] = NULL;
 720     }
 721
 722   /* See if we can pick up any loading of the DP register...  */
 723   if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70)
 724     tic4x_dp = EXTRU (instruction, 15, 0);
 725
 726   p = optable[instruction >> (32 - TIC4X_HASH_SIZE)];
 727   if (p != NULL)
 728     {
 729       if (((instruction & p->opmask) == p->opcode)
 730            && tic4x_print_op (NULL, instruction, p, pc))
 731         tic4x_print_op (info, instruction, p, pc);
 732       else
 733         (*info->fprintf_func) (info->stream, "%08lx", instruction);
 734     }
 735   else
 736     {
 737       for (i = 0; i<TIC4X_SPESOP_SIZE; i++)
 738         if (optable_special[i] != NULL
 739             && optable_special[i]->opcode == instruction)
 740           {
 741             (*info->fprintf_func)(info->stream, "%s", optable_special[i]->name);
 742             break;
 743           }
 744       if (i == TIC4X_SPESOP_SIZE)
 745         (*info->fprintf_func) (info->stream, "%08lx", instruction);
 746     }
 747
 748   /* Return size of insn in words.  */
 749   return 1;
 750 }
 751
 752 /* The entry point from objdump and gdb.  */
 753 int
 754 print_insn_tic4x (bfd_vma memaddr, struct disassemble_info *info)
 755 {
 756   int status;
 757   unsigned long pc;
 758   unsigned long op;
 759   bfd_byte buffer[4];
 760
 761   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
 762   if (status != 0)
 763     {
 764       (*info->memory_error_func) (status, memaddr, info);
 765       return -1;
 766     }
 767
 768   pc = memaddr;
 769   op = bfd_getl32 (buffer);
 770   info->bytes_per_line = 4;
 771   info->bytes_per_chunk = 4;
 772   info->octets_per_byte = 4;
 773   info->display_endian = BFD_ENDIAN_LITTLE;
 774   return tic4x_disassemble (pc, op, info) * 4;
 775 }