1 /* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils.
3 Copyright 2002, 2003, 2005 Free Software Foundation, Inc.
5 Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
23 #include "libiberty.h"
25 #include "opcode/tic4x.h"
29 #define TIC4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */
30 #define TIC4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions. */
51 static int tic4x_version
= 0;
52 static int tic4x_dp
= 0;
55 tic4x_pc_offset (unsigned int op
)
57 /* Determine the PC offset for a C[34]x instruction.
58 This could be simplified using some boolean algebra
59 but at the expense of readability. */
63 case 0x62: /* call (C4x) */
64 case 0x64: /* rptb (C4x) */
68 case 0x65: /* rptbd (C4x) */
77 switch ((op
& 0xffe00000) >> 20)
80 case 0x720: /* callB */
81 case 0x740: /* trapB */
85 case 0x6a6: /* bBat */
86 case 0x6aa: /* bBaf */
87 case 0x722: /* lajB */
88 case 0x748: /* latB */
89 case 0x798: /* rptbd */
96 switch ((op
& 0xfe200000) >> 20)
101 case 0x6e2: /* dbBd */
112 tic4x_print_char (struct disassemble_info
* info
, char ch
)
115 (*info
->fprintf_func
) (info
->stream
, "%c", ch
);
120 tic4x_print_str (struct disassemble_info
*info
, char *str
)
123 (*info
->fprintf_func
) (info
->stream
, "%s", str
);
128 tic4x_print_register (struct disassemble_info
*info
, unsigned long regno
)
130 static tic4x_register_t
** registertable
= NULL
;
133 if (registertable
== NULL
)
135 registertable
= xmalloc (sizeof (tic4x_register_t
*) * REG_TABLE_SIZE
);
136 for (i
= 0; i
< tic3x_num_registers
; i
++)
137 registertable
[tic3x_registers
[i
].regno
] = (tic4x_register_t
*) (tic3x_registers
+ i
);
138 if (IS_CPU_TIC4X (tic4x_version
))
140 /* Add C4x additional registers, overwriting
141 any C3x registers if necessary. */
142 for (i
= 0; i
< tic4x_num_registers
; i
++)
143 registertable
[tic4x_registers
[i
].regno
] =
144 (tic4x_register_t
*)(tic4x_registers
+ i
);
147 if ((int) regno
> (IS_CPU_TIC4X (tic4x_version
) ? TIC4X_REG_MAX
: TIC3X_REG_MAX
))
150 (*info
->fprintf_func
) (info
->stream
, "%s", registertable
[regno
]->name
);
155 tic4x_print_addr (struct disassemble_info
*info
, unsigned long addr
)
158 (*info
->print_address_func
)(addr
, info
);
163 tic4x_print_relative (struct disassemble_info
*info
,
166 unsigned long opcode
)
168 return tic4x_print_addr (info
, pc
+ offset
+ tic4x_pc_offset (opcode
));
172 tic4x_print_direct (struct disassemble_info
*info
, unsigned long arg
)
176 (*info
->fprintf_func
) (info
->stream
, "@");
177 tic4x_print_addr (info
, arg
+ (tic4x_dp
<< 16));
182 /* FIXME: make the floating point stuff not rely on host
183 floating point arithmetic. */
186 tic4x_print_ftoa (unsigned int val
, FILE *stream
, fprintf_ftype pfunc
)
193 e
= EXTRS (val
, 31, 24); /* Exponent. */
196 s
= EXTRU (val
, 23, 23); /* Sign bit. */
197 f
= EXTRU (val
, 22, 0); /* Mantissa. */
202 num
= f
/ (double)(1 << 23);
203 num
= ldexp (num
, e
);
205 (*pfunc
)(stream
, "%.9g", num
);
210 tic4x_print_immed (struct disassemble_info
*info
,
225 (*info
->fprintf_func
) (info
->stream
, "%ld", (long) arg
);
230 (*info
->fprintf_func
) (info
->stream
, "%lu", arg
);
234 e
= EXTRS (arg
, 15, 12);
237 s
= EXTRU (arg
, 11, 11);
238 f
= EXTRU (arg
, 10, 0);
243 num
= f
/ (double)(1 << 11);
244 num
= ldexp (num
, e
);
246 (*info
->fprintf_func
) (info
->stream
, "%f", num
);
249 e
= EXTRS (arg
, 31, 24);
252 s
= EXTRU (arg
, 23, 23);
253 f
= EXTRU (arg
, 22, 0);
258 num
= f
/ (double)(1 << 23);
259 num
= ldexp (num
, e
);
261 (*info
->fprintf_func
) (info
->stream
, "%f", num
);
268 tic4x_print_cond (struct disassemble_info
*info
, unsigned int cond
)
270 static tic4x_cond_t
**condtable
= NULL
;
273 if (condtable
== NULL
)
275 condtable
= xmalloc (sizeof (tic4x_cond_t
*) * 32);
276 for (i
= 0; i
< tic4x_num_conds
; i
++)
277 condtable
[tic4x_conds
[i
].cond
] = (tic4x_cond_t
*)(tic4x_conds
+ i
);
279 if (cond
> 31 || condtable
[cond
] == NULL
)
282 (*info
->fprintf_func
) (info
->stream
, "%s", condtable
[cond
]->name
);
287 tic4x_print_indirect (struct disassemble_info
*info
,
301 case INDIRECT_TIC4X
: /* *+ARn(disp) */
302 disp
= EXTRU (arg
, 7, 3);
303 aregno
= EXTRU (arg
, 2, 0) + REG_AR0
;
308 aregno
= EXTRU (arg
, 2, 0) + REG_AR0
;
309 modn
= EXTRU (arg
, 7, 3);
312 disp
= EXTRU (arg
, 7, 0);
313 aregno
= EXTRU (arg
, 10, 8) + REG_AR0
;
314 modn
= EXTRU (arg
, 15, 11);
315 if (modn
> 7 && disp
!= 0)
319 (*info
->fprintf_func
)(info
->stream
, "# internal error: Unknown indirect type %d", type
);
322 if (modn
> TIC3X_MODN_MAX
)
324 a
= tic4x_indirects
[modn
].name
;
330 tic4x_print_register (info
, aregno
);
333 tic4x_print_immed (info
, IMMED_UINT
, disp
);
336 tic4x_print_str (info
, "ir0");
339 tic4x_print_str (info
, "ir1");
342 tic4x_print_char (info
, *a
);
351 tic4x_print_op (struct disassemble_info
*info
,
352 unsigned long instruction
,
358 char *parallel
= NULL
;
360 /* Print instruction name. */
362 while (*s
&& parallel
== NULL
)
367 if (! tic4x_print_cond (info
, EXTRU (instruction
, 20, 16)))
371 if (! tic4x_print_cond (info
, EXTRU (instruction
, 27, 23)))
375 parallel
= s
+ 1; /* Skip past `_' in name. */
378 tic4x_print_char (info
, *s
);
384 /* Print arguments. */
387 tic4x_print_char (info
, ' ');
393 case '*': /* Indirect 0--15. */
394 if (! tic4x_print_indirect (info
, INDIRECT_LONG
,
395 EXTRU (instruction
, 15, 0)))
399 case '#': /* Only used for ldp, ldpk. */
400 tic4x_print_immed (info
, IMMED_UINT
, EXTRU (instruction
, 15, 0));
403 case '@': /* Direct 0--15. */
404 tic4x_print_direct (info
, EXTRU (instruction
, 15, 0));
407 case 'A': /* Address register 24--22. */
408 if (! tic4x_print_register (info
, EXTRU (instruction
, 24, 22) +
413 case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb
415 if (IS_CPU_TIC4X (tic4x_version
))
416 tic4x_print_relative (info
, pc
, EXTRS (instruction
, 23, 0),
419 tic4x_print_addr (info
, EXTRU (instruction
, 23, 0));
422 case 'C': /* Indirect (short C4x) 0--7. */
423 if (! IS_CPU_TIC4X (tic4x_version
))
425 if (! tic4x_print_indirect (info
, INDIRECT_TIC4X
,
426 EXTRU (instruction
, 7, 0)))
431 /* Cockup if get here... */
434 case 'E': /* Register 0--7. */
436 if (! tic4x_print_register (info
, EXTRU (instruction
, 7, 0)))
440 case 'F': /* 16-bit float immediate 0--15. */
441 tic4x_print_immed (info
, IMMED_SFLOAT
,
442 EXTRU (instruction
, 15, 0));
445 case 'i': /* Extended indirect 0--7. */
446 if (EXTRU (instruction
, 7, 5) == 7)
448 if (!tic4x_print_register (info
, EXTRU (instruction
, 4, 0)))
454 case 'I': /* Indirect (short) 0--7. */
455 if (! tic4x_print_indirect (info
, INDIRECT_SHORT
,
456 EXTRU (instruction
, 7, 0)))
460 case 'j': /* Extended indirect 8--15 */
461 if (EXTRU (instruction
, 15, 13) == 7)
463 if (! tic4x_print_register (info
, EXTRU (instruction
, 12, 8)))
468 case 'J': /* Indirect (short) 8--15. */
469 if (! tic4x_print_indirect (info
, INDIRECT_SHORT
,
470 EXTRU (instruction
, 15, 8)))
474 case 'G': /* Register 8--15. */
476 if (! tic4x_print_register (info
, EXTRU (instruction
, 15, 8)))
480 case 'H': /* Register 16--18. */
481 if (! tic4x_print_register (info
, EXTRU (instruction
, 18, 16)))
485 case 'K': /* Register 19--21. */
486 if (! tic4x_print_register (info
, EXTRU (instruction
, 21, 19)))
490 case 'L': /* Register 22--24. */
491 if (! tic4x_print_register (info
, EXTRU (instruction
, 24, 22)))
495 case 'M': /* Register 22--22. */
496 tic4x_print_register (info
, EXTRU (instruction
, 22, 22) + REG_R2
);
499 case 'N': /* Register 23--23. */
500 tic4x_print_register (info
, EXTRU (instruction
, 23, 23) + REG_R0
);
503 case 'O': /* Indirect (short C4x) 8--15. */
504 if (! IS_CPU_TIC4X (tic4x_version
))
506 if (! tic4x_print_indirect (info
, INDIRECT_TIC4X
,
507 EXTRU (instruction
, 15, 8)))
511 case 'P': /* Displacement 0--15 (used by Bcond and BcondD). */
512 tic4x_print_relative (info
, pc
, EXTRS (instruction
, 15, 0),
516 case 'Q': /* Register 0--15. */
518 if (! tic4x_print_register (info
, EXTRU (instruction
, 15, 0)))
522 case 'R': /* Register 16--20. */
524 if (! tic4x_print_register (info
, EXTRU (instruction
, 20, 16)))
528 case 'S': /* 16-bit signed immediate 0--15. */
529 tic4x_print_immed (info
, IMMED_SINT
,
530 EXTRS (instruction
, 15, 0));
533 case 'T': /* 5-bit signed immediate 16--20 (C4x stik). */
534 if (! IS_CPU_TIC4X (tic4x_version
))
536 if (! tic4x_print_immed (info
, IMMED_SUINT
,
537 EXTRU (instruction
, 20, 16)))
541 case 'U': /* 16-bit unsigned int immediate 0--15. */
542 tic4x_print_immed (info
, IMMED_SUINT
, EXTRU (instruction
, 15, 0));
545 case 'V': /* 5/9-bit unsigned vector 0--4/8. */
546 tic4x_print_immed (info
, IMMED_SUINT
,
547 IS_CPU_TIC4X (tic4x_version
) ?
548 EXTRU (instruction
, 8, 0) :
549 EXTRU (instruction
, 4, 0) & ~0x20);
552 case 'W': /* 8-bit signed immediate 0--7. */
553 if (! IS_CPU_TIC4X (tic4x_version
))
555 tic4x_print_immed (info
, IMMED_SINT
, EXTRS (instruction
, 7, 0));
558 case 'X': /* Expansion register 4--0. */
559 val
= EXTRU (instruction
, 4, 0) + REG_IVTP
;
560 if (val
< REG_IVTP
|| val
> REG_TVTP
)
562 if (! tic4x_print_register (info
, val
))
566 case 'Y': /* Address register 16--20. */
567 val
= EXTRU (instruction
, 20, 16);
568 if (val
< REG_AR0
|| val
> REG_SP
)
570 if (! tic4x_print_register (info
, val
))
574 case 'Z': /* Expansion register 16--20. */
575 val
= EXTRU (instruction
, 20, 16) + REG_IVTP
;
576 if (val
< REG_IVTP
|| val
> REG_TVTP
)
578 if (! tic4x_print_register (info
, val
))
582 case '|': /* Parallel instruction. */
583 tic4x_print_str (info
, " || ");
584 tic4x_print_str (info
, parallel
);
585 tic4x_print_char (info
, ' ');
589 tic4x_print_char (info
, ',');
593 tic4x_print_char (info
, *s
);
602 tic4x_hash_opcode_special (tic4x_inst_t
**optable_special
,
603 const tic4x_inst_t
*inst
)
607 for (i
= 0;i
< TIC4X_SPESOP_SIZE
; i
++)
608 if (optable_special
[i
] != NULL
609 && optable_special
[i
]->opcode
== inst
->opcode
)
611 /* Collision (we have it already) - overwrite. */
612 optable_special
[i
] = (tic4x_inst_t
*) inst
;
616 for (i
= 0; i
< TIC4X_SPESOP_SIZE
; i
++)
617 if (optable_special
[i
] == NULL
)
619 /* Add the new opcode. */
620 optable_special
[i
] = (tic4x_inst_t
*) inst
;
624 /* This should never occur. This happens if the number of special
625 instructions exceeds TIC4X_SPESOP_SIZE. Please increase the variable
628 printf ("optable_special[] is full, please increase TIC4X_SPESOP_SIZE!\n");
633 tic4x_hash_opcode (tic4x_inst_t
**optable
,
634 tic4x_inst_t
**optable_special
,
635 const tic4x_inst_t
*inst
,
636 const unsigned long tic4x_oplevel
)
639 int opcode
= inst
->opcode
>> (32 - TIC4X_HASH_SIZE
);
640 int opmask
= inst
->opmask
>> (32 - TIC4X_HASH_SIZE
);
642 /* Use a TIC4X_HASH_SIZE bit index as a hash index. We should
643 have unique entries so there's no point having a linked list
645 for (j
= opcode
; j
< opmask
; j
++)
646 if ((j
& opmask
) == opcode
647 && inst
->oplevel
& tic4x_oplevel
)
650 /* We should only have collisions for synonyms like
652 if (optable
[j
] != NULL
)
653 printf ("Collision at index %d, %s and %s\n",
654 j
, optable
[j
]->name
, inst
->name
);
656 /* Catch those ops that collide with others already inside the
657 hash, and have a opmask greater than the one we use in the
658 hash. Store them in a special-list, that will handle full
659 32-bit INSN, not only the first 11-bit (or so). */
660 if (optable
[j
] != NULL
661 && inst
->opmask
& ~(opmask
<< (32 - TIC4X_HASH_SIZE
)))
663 /* Add the instruction already on the list. */
664 tic4x_hash_opcode_special (optable_special
, optable
[j
]);
666 /* Add the new instruction. */
667 tic4x_hash_opcode_special (optable_special
, inst
);
670 optable
[j
] = (tic4x_inst_t
*) inst
;
674 /* Disassemble the instruction in 'instruction'.
675 'pc' should be the address of this instruction, it will
676 be used to print the target address if this is a relative jump or call
677 the disassembled instruction is written to 'info'.
678 The function returns the length of this instruction in words. */
681 tic4x_disassemble (unsigned long pc
,
682 unsigned long instruction
,
683 struct disassemble_info
*info
)
685 static tic4x_inst_t
**optable
= NULL
;
686 static tic4x_inst_t
**optable_special
= NULL
;
689 unsigned long tic4x_oplevel
;
691 tic4x_version
= info
->mach
;
693 tic4x_oplevel
= (IS_CPU_TIC4X (tic4x_version
)) ? OP_C4X
: 0;
694 tic4x_oplevel
|= OP_C3X
| OP_LPWR
| OP_IDLE2
| OP_ENH
;
698 optable
= xcalloc (sizeof (tic4x_inst_t
*), (1 << TIC4X_HASH_SIZE
));
700 optable_special
= xcalloc (sizeof (tic4x_inst_t
*), TIC4X_SPESOP_SIZE
);
702 /* Install opcodes in reverse order so that preferred
703 forms overwrite synonyms. */
704 for (i
= tic4x_num_insts
- 1; i
>= 0; i
--)
705 tic4x_hash_opcode (optable
, optable_special
, &tic4x_insts
[i
],
708 /* We now need to remove the insn that are special from the
709 "normal" optable, to make the disasm search this extra list
711 for (i
= 0; i
< TIC4X_SPESOP_SIZE
; i
++)
712 if (optable_special
[i
] != NULL
)
713 optable
[optable_special
[i
]->opcode
>> (32 - TIC4X_HASH_SIZE
)] = NULL
;
716 /* See if we can pick up any loading of the DP register... */
717 if ((instruction
>> 16) == 0x5070 || (instruction
>> 16) == 0x1f70)
718 tic4x_dp
= EXTRU (instruction
, 15, 0);
720 p
= optable
[instruction
>> (32 - TIC4X_HASH_SIZE
)];
723 if (((instruction
& p
->opmask
) == p
->opcode
)
724 && tic4x_print_op (NULL
, instruction
, p
, pc
))
725 tic4x_print_op (info
, instruction
, p
, pc
);
727 (*info
->fprintf_func
) (info
->stream
, "%08lx", instruction
);
731 for (i
= 0; i
<TIC4X_SPESOP_SIZE
; i
++)
732 if (optable_special
[i
] != NULL
733 && optable_special
[i
]->opcode
== instruction
)
735 (*info
->fprintf_func
)(info
->stream
, "%s", optable_special
[i
]->name
);
738 if (i
== TIC4X_SPESOP_SIZE
)
739 (*info
->fprintf_func
) (info
->stream
, "%08lx", instruction
);
742 /* Return size of insn in words. */
746 /* The entry point from objdump and gdb. */
748 print_insn_tic4x (bfd_vma memaddr
, struct disassemble_info
*info
)
755 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
758 (*info
->memory_error_func
) (status
, memaddr
, info
);
763 op
= bfd_getl32 (buffer
);
764 info
->bytes_per_line
= 4;
765 info
->bytes_per_chunk
= 4;
766 info
->octets_per_byte
= 4;
767 info
->display_endian
= BFD_ENDIAN_LITTLE
;
768 return tic4x_disassemble (pc
, op
, info
) * 4;
This page took 0.044342 seconds and 4 git commands to generate.