eff4ebb8ff1457a36320ee6e514315e2a9267402
1 /* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils.
3 Copyright 2002 Free Software Foundation, Inc.
5 Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 #include "libiberty.h"
24 #include "opcode/tic4x.h"
28 #define C4X_HASH_SIZE 11 /* 11 and above should give unique entries. */
49 static int c4x_version
= 0;
50 static int c4x_dp
= 0;
53 c4x_pc_offset (unsigned int op
)
55 /* Determine the PC offset for a C[34]x instruction.
56 This could be simplified using some boolean algebra
57 but at the expense of readability. */
61 case 0x62: /* call (C4x) */
62 case 0x64: /* rptb (C4x) */
66 case 0x65: /* rptbd (C4x) */
75 switch ((op
& 0xffe00000) >> 20)
78 case 0x720: /* callB */
79 case 0x740: /* trapB */
83 case 0x6a6: /* bBat */
84 case 0x6aa: /* bBaf */
85 case 0x722: /* lajB */
86 case 0x748: /* latB */
87 case 0x798: /* rptbd */
94 switch ((op
& 0xfe200000) >> 20)
99 case 0x6e2: /* dbBd */
110 c4x_print_char (struct disassemble_info
* info
, char ch
)
113 (*info
->fprintf_func
) (info
->stream
, "%c", ch
);
118 c4x_print_str (struct disassemble_info
*info
, char *str
)
121 (*info
->fprintf_func
) (info
->stream
, "%s", str
);
126 c4x_print_register (struct disassemble_info
*info
,
129 static c4x_register_t
**registertable
= NULL
;
132 if (registertable
== NULL
)
134 registertable
= (c4x_register_t
**)
135 xmalloc (sizeof (c4x_register_t
*) * REG_TABLE_SIZE
);
136 for (i
= 0; i
< c3x_num_registers
; i
++)
137 registertable
[c3x_registers
[i
].regno
] = (void *)&c3x_registers
[i
];
138 if (IS_CPU_C4X (c4x_version
))
140 /* Add C4x additional registers, overwriting
141 any C3x registers if necessary. */
142 for (i
= 0; i
< c4x_num_registers
; i
++)
143 registertable
[c4x_registers
[i
].regno
] = (void *)&c4x_registers
[i
];
146 if ((int) regno
> (IS_CPU_C4X (c4x_version
) ? C4X_REG_MAX
: C3X_REG_MAX
))
149 (*info
->fprintf_func
) (info
->stream
, "%s", registertable
[regno
]->name
);
154 c4x_print_addr (struct disassemble_info
*info
,
158 (*info
->print_address_func
)(addr
, info
);
163 c4x_print_relative (struct disassemble_info
*info
,
166 unsigned long opcode
)
168 return c4x_print_addr (info
, pc
+ offset
+ c4x_pc_offset (opcode
));
172 c4x_print_direct (struct disassemble_info
*info
,
177 (*info
->fprintf_func
) (info
->stream
, "@");
178 c4x_print_addr (info
, arg
+ (c4x_dp
<< 16));
183 /* FIXME: make the floating point stuff not rely on host
184 floating point arithmetic. */
186 c4x_print_ftoa (unsigned int val
,
195 e
= EXTRS (val
, 31, 24); /* exponent */
198 s
= EXTRU (val
, 23, 23); /* sign bit */
199 f
= EXTRU (val
, 22, 0); /* mantissa */
204 num
= f
/ (double)(1 << 23);
205 num
= ldexp (num
, e
);
207 (*pfunc
)(stream
, "%.9g", num
);
211 c4x_print_immed (struct disassemble_info
*info
,
226 (*info
->fprintf_func
) (info
->stream
, "%d", (long)arg
);
231 (*info
->fprintf_func
) (info
->stream
, "%u", arg
);
235 e
= EXTRS (arg
, 15, 12);
238 s
= EXTRU (arg
, 11, 11);
239 f
= EXTRU (arg
, 10, 0);
244 num
= f
/ (double)(1 << 11);
245 num
= ldexp (num
, e
);
247 (*info
->fprintf_func
) (info
->stream
, "%f", num
);
250 e
= EXTRS (arg
, 31, 24);
253 s
= EXTRU (arg
, 23, 23);
254 f
= EXTRU (arg
, 22, 0);
259 num
= f
/ (double)(1 << 23);
260 num
= ldexp (num
, e
);
262 (*info
->fprintf_func
) (info
->stream
, "%f", num
);
269 c4x_print_cond (struct disassemble_info
*info
,
272 static c4x_cond_t
**condtable
= NULL
;
275 if (condtable
== NULL
)
277 condtable
= (c4x_cond_t
**)xmalloc (sizeof (c4x_cond_t
*) * 32);
278 for (i
= 0; i
< num_conds
; i
++)
279 condtable
[c4x_conds
[i
].cond
] = (void *)&c4x_conds
[i
];
281 if (cond
> 31 || condtable
[cond
] == NULL
)
284 (*info
->fprintf_func
) (info
->stream
, "%s", condtable
[cond
]->name
);
289 c4x_print_indirect (struct disassemble_info
*info
,
303 case INDIRECT_C4X
: /* *+ARn(disp) */
304 disp
= EXTRU (arg
, 7, 3);
305 aregno
= EXTRU (arg
, 2, 0) + REG_AR0
;
310 aregno
= EXTRU (arg
, 2, 0) + REG_AR0
;
311 modn
= EXTRU (arg
, 7, 3);
314 disp
= EXTRU (arg
, 7, 0);
315 aregno
= EXTRU (arg
, 10, 8) + REG_AR0
;
316 modn
= EXTRU (arg
, 15, 11);
317 if (modn
> 7 && disp
!= 0)
323 if (modn
> C3X_MODN_MAX
)
325 a
= c4x_indirects
[modn
].name
;
331 c4x_print_register (info
, aregno
);
334 c4x_print_immed (info
, IMMED_UINT
, disp
);
337 c4x_print_str (info
, "ir0");
340 c4x_print_str (info
, "ir1");
343 c4x_print_char (info
, *a
);
352 c4x_print_op (struct disassemble_info
*info
,
353 unsigned long instruction
,
354 c4x_inst_t
*p
, unsigned long pc
)
358 char *parallel
= NULL
;
360 /* Print instruction name. */
362 while (*s
&& parallel
== NULL
)
367 if (! c4x_print_cond (info
, EXTRU (instruction
, 20, 16)))
371 if (! c4x_print_cond (info
, EXTRU (instruction
, 27, 23)))
375 parallel
= s
+ 1; /* Skip past `_' in name */
378 c4x_print_char (info
, *s
);
384 /* Print arguments. */
387 c4x_print_char (info
, ' ');
393 case '*': /* indirect 0--15 */
394 if (! c4x_print_indirect (info
, INDIRECT_LONG
,
395 EXTRU (instruction
, 15, 0)))
399 case '#': /* only used for ldp, ldpk */
400 c4x_print_immed (info
, IMMED_UINT
, EXTRU (instruction
, 15, 0));
403 case '@': /* direct 0--15 */
404 c4x_print_direct (info
, EXTRU (instruction
, 15, 0));
407 case 'A': /* address register 24--22 */
408 if (! c4x_print_register (info
, EXTRU (instruction
, 24, 22) +
413 case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb
415 if (IS_CPU_C4X (c4x_version
))
416 c4x_print_relative (info
, pc
, EXTRS (instruction
, 23, 0),
419 c4x_print_addr (info
, EXTRU (instruction
, 23, 0));
422 case 'C': /* indirect (short C4x) 0--7 */
423 if (! IS_CPU_C4X (c4x_version
))
425 if (! c4x_print_indirect (info
, INDIRECT_C4X
,
426 EXTRU (instruction
, 7, 0)))
431 /* Cockup if get here... */
434 case 'E': /* register 0--7 */
435 if (! c4x_print_register (info
, EXTRU (instruction
, 7, 0)))
439 case 'F': /* 16-bit float immediate 0--15 */
440 c4x_print_immed (info
, IMMED_SFLOAT
,
441 EXTRU (instruction
, 15, 0));
444 case 'I': /* indirect (short) 0--7 */
445 if (! c4x_print_indirect (info
, INDIRECT_SHORT
,
446 EXTRU (instruction
, 7, 0)))
450 case 'J': /* indirect (short) 8--15 */
451 if (! c4x_print_indirect (info
, INDIRECT_SHORT
,
452 EXTRU (instruction
, 15, 8)))
456 case 'G': /* register 8--15 */
457 if (! c4x_print_register (info
, EXTRU (instruction
, 15, 8)))
461 case 'H': /* register 16--18 */
462 if (! c4x_print_register (info
, EXTRU (instruction
, 18, 16)))
466 case 'K': /* register 19--21 */
467 if (! c4x_print_register (info
, EXTRU (instruction
, 21, 19)))
471 case 'L': /* register 22--24 */
472 if (! c4x_print_register (info
, EXTRU (instruction
, 24, 22)))
476 case 'M': /* register 22--22 */
477 c4x_print_register (info
, EXTRU (instruction
, 22, 22) + REG_R2
);
480 case 'N': /* register 23--23 */
481 c4x_print_register (info
, EXTRU (instruction
, 22, 22) + REG_R0
);
484 case 'O': /* indirect (short C4x) 8--15 */
485 if (! IS_CPU_C4X (c4x_version
))
487 if (! c4x_print_indirect (info
, INDIRECT_C4X
,
488 EXTRU (instruction
, 15, 8)))
492 case 'P': /* displacement 0--15 (used by Bcond and BcondD) */
493 c4x_print_relative (info
, pc
, EXTRS (instruction
, 15, 0),
497 case 'Q': /* register 0--15 */
498 if (! c4x_print_register (info
, EXTRU (instruction
, 15, 0)))
502 case 'R': /* register 16--20 */
503 if (! c4x_print_register (info
, EXTRU (instruction
, 20, 16)))
507 case 'S': /* 16-bit signed immediate 0--15 */
508 c4x_print_immed (info
, IMMED_SINT
,
509 EXTRS (instruction
, 15, 0));
512 case 'T': /* 5-bit signed immediate 16--20 (C4x stik) */
513 if (! IS_CPU_C4X (c4x_version
))
515 if (! c4x_print_immed (info
, IMMED_SUINT
,
516 EXTRU (instruction
, 20, 16)))
520 case 'U': /* 16-bit unsigned int immediate 0--15 */
521 c4x_print_immed (info
, IMMED_SUINT
, EXTRU (instruction
, 15, 0));
524 case 'V': /* 5/9-bit unsigned vector 0--4/8 */
525 c4x_print_immed (info
, IMMED_SUINT
,
526 IS_CPU_C4X (c4x_version
) ?
527 EXTRU (instruction
, 8, 0) :
528 EXTRU (instruction
, 4, 0) & ~0x20);
531 case 'W': /* 8-bit signed immediate 0--7 */
532 if (! IS_CPU_C4X (c4x_version
))
534 c4x_print_immed (info
, IMMED_SINT
, EXTRS (instruction
, 7, 0));
537 case 'X': /* expansion register 4--0 */
538 val
= EXTRU (instruction
, 4, 0) + REG_IVTP
;
539 if (val
< REG_IVTP
|| val
> REG_TVTP
)
541 if (! c4x_print_register (info
, val
))
545 case 'Y': /* address register 16--20 */
546 val
= EXTRU (instruction
, 20, 16);
547 if (val
< REG_AR0
|| val
> REG_SP
)
549 if (! c4x_print_register (info
, val
))
553 case 'Z': /* expansion register 16--20 */
554 val
= EXTRU (instruction
, 20, 16) + REG_IVTP
;
555 if (val
< REG_IVTP
|| val
> REG_TVTP
)
557 if (! c4x_print_register (info
, val
))
561 case '|': /* Parallel instruction */
562 c4x_print_str (info
, " || ");
563 c4x_print_str (info
, parallel
);
564 c4x_print_char (info
, ' ');
568 c4x_print_char (info
, ',');
572 c4x_print_char (info
, *s
);
581 c4x_hash_opcode (c4x_inst_t
**optable
,
582 const c4x_inst_t
*inst
)
585 int opcode
= inst
->opcode
>> (32 - C4X_HASH_SIZE
);
586 int opmask
= inst
->opmask
>> (32 - C4X_HASH_SIZE
);
588 /* Use a C4X_HASH_SIZE bit index as a hash index. We should
589 have unique entries so there's no point having a linked list
591 for (j
= opcode
; j
< opmask
; j
++)
592 if ((j
& opmask
) == opcode
)
595 /* We should only have collisions for synonyms like
597 if (optable
[j
] != NULL
)
598 printf("Collision at index %d, %s and %s\n",
599 j
, optable
[j
]->name
, inst
->name
);
601 optable
[j
] = (void *)inst
;
605 /* Disassemble the instruction in 'instruction'.
606 'pc' should be the address of this instruction, it will
607 be used to print the target address if this is a relative jump or call
608 the disassembled instruction is written to 'info'.
609 The function returns the length of this instruction in words. */
612 c4x_disassemble (unsigned long pc
,
613 unsigned long instruction
,
614 struct disassemble_info
*info
)
616 static c4x_inst_t
**optable
= NULL
;
620 c4x_version
= info
->mach
;
624 optable
= (c4x_inst_t
**)
625 xcalloc (sizeof (c4x_inst_t
*), (1 << C4X_HASH_SIZE
));
626 /* Install opcodes in reverse order so that preferred
627 forms overwrite synonyms. */
628 for (i
= c3x_num_insts
- 1; i
>= 0; i
--)
629 c4x_hash_opcode (optable
, &c3x_insts
[i
]);
630 if (IS_CPU_C4X (c4x_version
))
632 for (i
= c4x_num_insts
- 1; i
>= 0; i
--)
633 c4x_hash_opcode (optable
, &c4x_insts
[i
]);
637 /* See if we can pick up any loading of the DP register... */
638 if ((instruction
>> 16) == 0x5070 || (instruction
>> 16) == 0x1f70)
639 c4x_dp
= EXTRU (instruction
, 15, 0);
641 p
= optable
[instruction
>> (32 - C4X_HASH_SIZE
)];
642 if (p
!= NULL
&& ((instruction
& p
->opmask
) == p
->opcode
)
643 && c4x_print_op (NULL
, instruction
, p
, pc
))
644 c4x_print_op (info
, instruction
, p
, pc
);
646 (*info
->fprintf_func
) (info
->stream
, "%08x", instruction
);
648 /* Return size of insn in words. */
652 /* The entry point from objdump and gdb. */
654 print_insn_tic4x (memaddr
, info
)
656 struct disassemble_info
*info
;
663 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
666 (*info
->memory_error_func
) (status
, memaddr
, info
);
671 op
= bfd_getl32 (buffer
);
672 info
->bytes_per_line
= 4;
673 info
->bytes_per_chunk
= 4;
674 info
->octets_per_byte
= 4;
675 info
->display_endian
= BFD_ENDIAN_LITTLE
;
676 return c4x_disassemble (pc
, op
, info
) * 4;
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