1 /* Disassemble V850 instructions.
2 Copyright (C) 1996-2019 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
25 #include "opcode/v850.h"
26 #include "disassemble.h"
29 static const char *const v850_reg_names
[] =
31 "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7",
32 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
33 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
34 "r24", "r25", "r26", "r27", "r28", "r29", "ep", "lp"
37 static const char *const v850_sreg_names
[] =
39 "eipc/vip/mpm", "eipsw/mpc", "fepc/tid", "fepsw/ppa", "ecr/vmecr", "psw/vmtid",
40 "sr6/fpsr/vmadr/dcc", "sr7/fpepc/dc0",
41 "sr8/fpst/vpecr/dcv1", "sr9/fpcc/vptid", "sr10/fpcfg/vpadr/spal", "sr11/spau",
42 "sr12/vdecr/ipa0l", "eiic/vdtid/ipa0u", "feic/ipa1l", "dbic/ipa1u",
43 "ctpc/ipa2l", "ctpsw/ipa2u", "dbpc/ipa3l", "dbpsw/ipa3u", "ctbp/dpa0l",
44 "dir/dpa0u", "bpc/dpa0u", "asid/dpa1l",
45 "bpav/dpa1u", "bpam/dpa2l", "bpdv/dpa2u", "bpdm/dpa3l", "eiwr/dpa3u",
46 "fewr", "dbwr", "bsel"
49 static const char *const v850_cc_names
[] =
51 "v", "c/l", "z", "nh", "s/n", "t", "lt", "le",
52 "nv", "nc/nl", "nz", "h", "ns/p", "sa", "ge", "gt"
55 static const char *const v850_float_cc_names
[] =
57 "f/t", "un/or", "eq/neq", "ueq/ogl", "olt/uge", "ult/oge", "ole/ugt", "ule/ogt",
58 "sf/st", "ngle/gle", "seq/sne", "ngl/gl", "lt/nlt", "nge/ge", "le/nle", "ngt/gt"
62 static const char *const v850_vreg_names
[] =
64 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", "vr8", "vr9",
65 "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", "vr16", "vr17", "vr18",
66 "vr19", "vr20", "vr21", "vr22", "vr23", "vr24", "vr25", "vr26", "vr27",
67 "vr28", "vr29", "vr30", "vr31"
70 static const char *const v850_cacheop_names
[] =
72 "chbii", "cibii", "cfali", "cisti", "cildi", "chbid", "chbiwbd",
73 "chbwbd", "cibid", "cibiwbd", "cibwbd", "cfald", "cistd", "cildd"
76 static const int v850_cacheop_codes
[] =
78 0x00, 0x20, 0x40, 0x60, 0x61, 0x04, 0x06,
79 0x07, 0x24, 0x26, 0x27, 0x44, 0x64, 0x65, -1
82 static const char *const v850_prefop_names
[] =
85 static const int v850_prefop_codes
[] =
89 print_value (int flags
,
91 struct disassemble_info
*info
,
94 if (flags
& V850_PCREL
)
96 bfd_vma addr
= value
+ memaddr
;
98 if (flags
& V850_INVERSE_PCREL
)
99 addr
= memaddr
- value
;
100 info
->print_address_func (addr
, info
);
102 else if (flags
& V850_OPERAND_DISP
)
104 if (flags
& V850_OPERAND_SIGNED
)
106 info
->fprintf_func (info
->stream
, "%ld", value
);
110 info
->fprintf_func (info
->stream
, "%lu", value
);
113 else if ((flags
& V850E_IMMEDIATE32
)
114 || (flags
& V850E_IMMEDIATE16HI
))
116 info
->fprintf_func (info
->stream
, "0x%lx", value
);
120 if (flags
& V850_OPERAND_SIGNED
)
122 info
->fprintf_func (info
->stream
, "%ld", value
);
126 info
->fprintf_func (info
->stream
, "%lu", value
);
132 get_operand_value (const struct v850_operand
*operand
,
136 struct disassemble_info
* info
,
143 if ((operand
->flags
& V850E_IMMEDIATE16
)
144 || (operand
->flags
& V850E_IMMEDIATE16HI
))
146 int status
= info
->read_memory_func (memaddr
+ bytes_read
, buffer
, 2, info
);
150 value
= bfd_getl16 (buffer
);
152 if (operand
->flags
& V850E_IMMEDIATE16HI
)
154 else if (value
& 0x8000)
155 value
|= (-1UL << 16);
161 info
->memory_error_func (status
, memaddr
+ bytes_read
, info
);
166 if (operand
->flags
& V850E_IMMEDIATE23
)
168 int status
= info
->read_memory_func (memaddr
+ 2, buffer
, 4, info
);
172 value
= bfd_getl32 (buffer
);
174 value
= (operand
->extract
) (value
, invalid
);
180 info
->memory_error_func (status
, memaddr
+ bytes_read
, info
);
185 if (operand
->flags
& V850E_IMMEDIATE32
)
187 int status
= info
->read_memory_func (memaddr
+ bytes_read
, buffer
, 4, info
);
192 value
= bfd_getl32 (buffer
);
198 info
->memory_error_func (status
, memaddr
+ bytes_read
, info
);
203 if (operand
->extract
)
204 value
= (operand
->extract
) (insn
, invalid
);
207 if (operand
->bits
== -1)
208 value
= (insn
& operand
->shift
);
210 value
= (insn
>> operand
->shift
) & ((1 << operand
->bits
) - 1);
212 if (operand
->flags
& V850_OPERAND_SIGNED
)
213 value
= ((long)(value
<< (sizeof (long)*8 - operand
->bits
))
214 >> (sizeof (long)*8 - operand
->bits
));
222 disassemble (bfd_vma memaddr
,
223 struct disassemble_info
*info
,
227 struct v850_opcode
*op
= (struct v850_opcode
*) v850_opcodes
;
228 const struct v850_operand
*operand
;
230 int target_processor
;
236 target_processor
= PROCESSOR_V850
;
240 target_processor
= PROCESSOR_V850E
;
243 case bfd_mach_v850e1
:
244 target_processor
= PROCESSOR_V850E
;
247 case bfd_mach_v850e2
:
248 target_processor
= PROCESSOR_V850E2
;
251 case bfd_mach_v850e2v3
:
252 target_processor
= PROCESSOR_V850E2V3
;
255 case bfd_mach_v850e3v5
:
256 target_processor
= PROCESSOR_V850E3V5
;
260 /* If this is a two byte insn, then mask off the high bits. */
264 /* Find the opcode. */
267 if ((op
->mask
& insn
) == op
->opcode
268 && (op
->processors
& target_processor
)
269 && !(op
->processors
& PROCESSOR_OPTION_ALIAS
))
271 /* Code check start. */
272 const unsigned char *opindex_ptr
;
276 for (opindex_ptr
= op
->operands
, opnum
= 1;
278 opindex_ptr
++, opnum
++)
283 operand
= &v850_operands
[*opindex_ptr
];
285 value
= get_operand_value (operand
, insn
, bytes_read
, memaddr
,
291 if ((operand
->flags
& V850_NOT_R0
) && value
== 0 && (op
->memop
) <=2)
294 if ((operand
->flags
& V850_NOT_SA
) && value
== 0xd)
297 if ((operand
->flags
& V850_NOT_IMM0
) && value
== 0)
301 /* Code check end. */
304 (*info
->fprintf_func
) (info
->stream
, "%s\t", op
->name
);
306 fprintf (stderr
, "match: insn: %lx, mask: %lx, opcode: %lx, name: %s\n",
307 insn
, op
->mask
, op
->opcode
, op
->name
);
311 /* Now print the operands.
313 MEMOP is the operand number at which a memory
314 address specification starts, or zero if this
315 instruction has no memory addresses.
317 A memory address is always two arguments.
319 This information allows us to determine when to
320 insert commas into the output stream as well as
321 when to insert disp[reg] expressions onto the
324 for (opindex_ptr
= op
->operands
, opnum
= 1;
326 opindex_ptr
++, opnum
++)
328 bfd_boolean square
= FALSE
;
333 operand
= &v850_operands
[*opindex_ptr
];
335 value
= get_operand_value (operand
, insn
, bytes_read
, memaddr
,
338 /* The first operand is always output without any
341 For the following arguments:
343 If memop && opnum == memop + 1, then we need '[' since
344 we're about to output the register used in a memory
347 If memop && opnum == memop + 2, then we need ']' since
348 we just finished the register in a memory reference. We
349 also need a ',' before this operand.
351 Else we just need a comma.
353 We may need to output a trailing ']' if the last operand
354 in an instruction is the register for a memory address.
356 The exception (and there's always an exception) are the
357 "jmp" insn which needs square brackets around it's only
358 register argument, and the clr1/not1/set1/tst1 insns
359 which [...] around their second register argument. */
362 if (operand
->flags
& V850_OPERAND_BANG
)
366 else if (operand
->flags
& V850_OPERAND_PERCENT
)
371 if (opnum
== 1 && opnum
== memop
)
373 info
->fprintf_func (info
->stream
, "%s[", prefix
);
376 else if ( (strcmp ("stc.w", op
->name
) == 0
377 || strcmp ("cache", op
->name
) == 0
378 || strcmp ("pref", op
->name
) == 0)
379 && opnum
== 2 && opnum
== memop
)
381 info
->fprintf_func (info
->stream
, ", [");
384 else if ( (strcmp (op
->name
, "pushsp") == 0
385 || strcmp (op
->name
, "popsp") == 0
386 || strcmp (op
->name
, "dbpush" ) == 0)
389 info
->fprintf_func (info
->stream
, "-");
392 && (v850_operands
[*(opindex_ptr
- 1)].flags
393 & V850_OPERAND_DISP
) != 0
396 info
->fprintf_func (info
->stream
, "%s[", prefix
);
400 && ( op
->opcode
== 0x00e407e0 /* clr1 */
401 || op
->opcode
== 0x00e207e0 /* not1 */
402 || op
->opcode
== 0x00e007e0 /* set1 */
403 || op
->opcode
== 0x00e607e0 /* tst1 */
406 info
->fprintf_func (info
->stream
, ", %s[", prefix
);
410 info
->fprintf_func (info
->stream
, ", %s", prefix
);
412 /* Extract the flags, ignoring ones which do not
413 effect disassembly output. */
414 flag
= operand
->flags
& (V850_OPERAND_REG
418 | V850E_OPERAND_REG_LIST
421 | V850_OPERAND_CACHEOP
422 | V850_OPERAND_PREFOP
423 | V850_OPERAND_FLOAT_CC
);
427 case V850_OPERAND_REG
:
428 info
->fprintf_func (info
->stream
, "%s", v850_reg_names
[value
]);
430 case (V850_OPERAND_REG
|V850_REG_EVEN
):
431 info
->fprintf_func (info
->stream
, "%s", v850_reg_names
[value
* 2]);
433 case V850_OPERAND_EP
:
434 info
->fprintf_func (info
->stream
, "ep");
436 case V850_OPERAND_SRG
:
437 info
->fprintf_func (info
->stream
, "%s", v850_sreg_names
[value
]);
439 case V850E_OPERAND_REG_LIST
:
441 static int list12_regs
[32] = { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
442 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 };
445 unsigned long int mask
= 0;
448 switch (operand
->shift
)
450 case 0xffe00001: regs
= list12_regs
; break;
452 /* xgettext:c-format */
453 opcodes_error_handler (_("unknown operand shift: %x"),
458 for (i
= 0; i
< 32; i
++)
460 if (value
& (1 << i
))
465 mask
|= (1 << regs
[ i
]);
468 /* xgettext:c-format */
469 opcodes_error_handler (_("unknown reg: %d"), i
);
479 info
->fprintf_func (info
->stream
, "{");
488 for (bit
= 0; bit
< 32; bit
++)
489 if (mask
& (1 << bit
))
491 unsigned long int first
= bit
;
492 unsigned long int last
;
495 info
->fprintf_func (info
->stream
, ", ");
499 info
->fprintf_func (info
->stream
, "%s", v850_reg_names
[first
]);
501 for (bit
++; bit
< 32; bit
++)
502 if ((mask
& (1 << bit
)) == 0)
507 if (last
> first
+ 1)
509 info
->fprintf_func (info
->stream
, " - %s", v850_reg_names
[ last
- 1 ]);
515 info
->fprintf_func (info
->stream
, "%sPC", mask
? ", " : "");
518 info
->fprintf_func (info
->stream
, "}");
522 case V850_OPERAND_CC
:
523 info
->fprintf_func (info
->stream
, "%s", v850_cc_names
[value
]);
526 case V850_OPERAND_FLOAT_CC
:
527 info
->fprintf_func (info
->stream
, "%s", v850_float_cc_names
[value
]);
530 case V850_OPERAND_CACHEOP
:
534 for (idx
= 0; v850_cacheop_codes
[idx
] != -1; idx
++)
536 if (value
== v850_cacheop_codes
[idx
])
538 info
->fprintf_func (info
->stream
, "%s",
539 v850_cacheop_names
[idx
]);
540 goto MATCH_CACHEOP_CODE
;
543 info
->fprintf_func (info
->stream
, "%d", (int) value
);
548 case V850_OPERAND_PREFOP
:
552 for (idx
= 0; v850_prefop_codes
[idx
] != -1; idx
++)
554 if (value
== v850_prefop_codes
[idx
])
556 info
->fprintf_func (info
->stream
, "%s",
557 v850_prefop_names
[idx
]);
558 goto MATCH_PREFOP_CODE
;
561 info
->fprintf_func (info
->stream
, "%d", (int) value
);
566 case V850_OPERAND_VREG
:
567 info
->fprintf_func (info
->stream
, "%s", v850_vreg_names
[value
]);
571 print_value (operand
->flags
, memaddr
, info
, value
);
576 (*info
->fprintf_func
) (info
->stream
, "]");
590 print_insn_v850 (bfd_vma memaddr
, struct disassemble_info
* info
)
592 int status
, status2
, match
;
594 int length
= 0, code_length
= 0;
595 unsigned long insn
= 0, insn2
= 0;
596 int target_processor
;
602 target_processor
= PROCESSOR_V850
;
606 target_processor
= PROCESSOR_V850E
;
609 case bfd_mach_v850e1
:
610 target_processor
= PROCESSOR_V850E
;
613 case bfd_mach_v850e2
:
614 target_processor
= PROCESSOR_V850E2
;
617 case bfd_mach_v850e2v3
:
618 target_processor
= PROCESSOR_V850E2V3
;
621 case bfd_mach_v850e3v5
:
622 target_processor
= PROCESSOR_V850E3V5
;
626 status
= info
->read_memory_func (memaddr
, buffer
, 2, info
);
630 info
->memory_error_func (status
, memaddr
, info
);
634 insn
= bfd_getl16 (buffer
);
636 status2
= info
->read_memory_func (memaddr
+2, buffer
, 2 , info
);
640 insn2
= bfd_getl16 (buffer
);
641 /* fprintf (stderr, "insn2 0x%08lx\n", insn2); */
646 && ((target_processor
& PROCESSOR_V850E2_UP
) != 0))
648 if ((insn
& 0xffff) == 0x02e0 /* jr 32bit */
649 && !status2
&& (insn2
& 0x1) == 0)
654 else if ((insn
& 0xffe0) == 0x02e0 /* jarl 32bit */
655 && !status2
&& (insn2
& 0x1) == 0)
660 else if ((insn
& 0xffe0) == 0x06e0 /* jmp 32bit */
661 && !status2
&& (insn2
& 0x1) == 0)
669 && ((target_processor
& PROCESSOR_V850E3V5_UP
) != 0))
671 if ( ((insn
& 0xffe0) == 0x07a0 /* ld.dw 23bit (v850e3v5) */
672 && !status2
&& (insn2
& 0x000f) == 0x0009)
673 || ((insn
& 0xffe0) == 0x07a0 /* st.dw 23bit (v850e3v5) */
674 && !status2
&& (insn2
& 0x000f) == 0x000f))
682 && ((target_processor
& PROCESSOR_V850E2V3_UP
) != 0))
684 if (((insn
& 0xffe0) == 0x0780 /* ld.b 23bit */
685 && !status2
&& (insn2
& 0x000f) == 0x0005)
686 || ((insn
& 0xffe0) == 0x07a0 /* ld.bu 23bit */
687 && !status2
&& (insn2
& 0x000f) == 0x0005)
688 || ((insn
& 0xffe0) == 0x0780 /* ld.h 23bit */
689 && !status2
&& (insn2
& 0x000f) == 0x0007)
690 || ((insn
& 0xffe0) == 0x07a0 /* ld.hu 23bit */
691 && !status2
&& (insn2
& 0x000f) == 0x0007)
692 || ((insn
& 0xffe0) == 0x0780 /* ld.w 23bit */
693 && !status2
&& (insn2
& 0x000f) == 0x0009))
698 else if (((insn
& 0xffe0) == 0x0780 /* st.b 23bit */
699 && !status2
&& (insn2
& 0x000f) == 0x000d)
700 || ((insn
& 0xffe0) == 0x07a0 /* st.h 23bit */
701 && !status2
&& (insn2
& 0x000f) == 0x000d)
702 || ((insn
& 0xffe0) == 0x0780 /* st.w 23bit */
703 && !status2
&& (insn2
& 0x000f) == 0x000f))
711 && target_processor
!= PROCESSOR_V850
)
713 if ((insn
& 0xffe0) == 0x0620) /* 32 bit MOV */
718 else if ((insn
& 0xffc0) == 0x0780 /* prepare {list}, imm5, imm16<<16 */
719 && !status2
&& (insn2
& 0x001f) == 0x0013)
724 else if ((insn
& 0xffc0) == 0x0780 /* prepare {list}, imm5, imm16 */
725 && !status2
&& (insn2
& 0x001f) == 0x000b)
730 else if ((insn
& 0xffc0) == 0x0780 /* prepare {list}, imm5, imm32 */
731 && !status2
&& (insn2
& 0x001f) == 0x001b)
740 && (insn
& 0x0600) == 0x0600))
742 /* This is a 4 byte insn. */
743 status
= info
->read_memory_func (memaddr
, buffer
, 4, info
);
746 insn
= bfd_getl32 (buffer
);
749 length
= code_length
= 4;
753 if (code_length
> length
)
755 status
= info
->read_memory_func (memaddr
+ length
, buffer
, code_length
- length
, info
);
760 if (length
== 0 && !status
)
761 length
= code_length
= 2;
766 /* when the last 2 bytes of section is 0xffff, length will be 0 and cause infinitive loop */
770 match
= disassemble (memaddr
, info
, length
, insn
);
776 status
= info
->read_memory_func (memaddr
, buffer
, code_length
, info
);
778 while (l
< code_length
)
780 if (code_length
- l
== 2)
782 insn
= bfd_getl16 (buffer
+ l
) & 0xffff;
783 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", insn
);
788 insn
= bfd_getl32 (buffer
+ l
);
789 info
->fprintf_func (info
->stream
, ".long\t0x%08lx", insn
);
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