opcodes/v850-opc.c

   1 /* Assemble V850 instructions.
   2    Copyright (C) 1996 Free Software Foundation, Inc.
   3
   4 This program is free software; you can redistribute it and/or modify
   5 it under the terms of the GNU General Public License as published by
   6 the Free Software Foundation; either version 2 of the License, or
   7 (at your option) any later version.
   8
   9 This program is distributed in the hope that it will be useful,
  10 but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 GNU General Public License for more details.
  13
  14 You should have received a copy of the GNU General Public License
  15 along with this program; if not, write to the Free Software
  16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  17
  18 #include "ansidecl.h"
  19 #include "opcode/v850.h"
  20
  21 /* Local insertion and extraction functions.  */
  22 static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
  23 static long extract_d9 PARAMS ((unsigned long, int *));
  24 static unsigned long insert_d22 PARAMS ((unsigned long, long, const char **));
  25 static long extract_d22 PARAMS ((unsigned long, int *));
  26 static unsigned long insert_d16_15 PARAMS ((unsigned long, long,
  27                                             const char **));
  28 static long extract_d16_15 PARAMS ((unsigned long, int *));
  29 static unsigned long insert_d8_7 PARAMS ((unsigned long, long, const char **));
  30 static long extract_d8_7 PARAMS ((unsigned long, int *));
  31 static unsigned long insert_d8_6 PARAMS ((unsigned long, long, const char **));
  32 static long extract_d8_6 PARAMS ((unsigned long, int *));
  33
  34 /* regular opcode */
  35 #define OP(x)           ((x & 0x3f) << 5)
  36 #define OP_MASK         OP(0x3f)
  37
  38 /* conditional branch opcode */
  39 #define BOP(x)          ((0x0b << 7) | (x & 0x0f))
  40 #define BOP_MASK        ((0x0f << 7) | 0x0f)
  41
  42 /* one-word opcodes */
  43 #define one(x)          ((unsigned int) (x))
  44
  45 /* two-word opcodes */
  46 #define two(x,y)        ((unsigned int) (x) | ((unsigned int) (y) << 16))
  47
  48
  49 \f
  50 const struct v850_operand v850_operands[] = {
  51 #define UNUSED  0
  52   { 0, 0, 0, 0, 0 },
  53
  54 /* The R1 field in a format 1, 6, 7, or 9 insn. */
  55 #define R1      (UNUSED+1)
  56   { 5, 0, 0, 0, V850_OPERAND_REG },
  57
  58 /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
  59 #define R2      (R1+1)
  60   { 5, 11, 0, 0, V850_OPERAND_REG },
  61
  62 /* The IMM5 field in a format 2 insn. */
  63 #define I5      (R2+1)
  64   { 5, 0, 0, 0, V850_OPERAND_SIGNED },
  65
  66 #define I5U     (I5+1)
  67   { 5, 0, 0, 0, 0 },
  68
  69 /* The IMM16 field in a format 6 insn. */
  70 #define I16     (I5U+1)
  71   { 16, 16, 0, 0, V850_OPERAND_SIGNED },
  72
  73 /* The signed DISP7 field in a format 4 insn. */
  74 #define D7      (I16+1)
  75   { 7, 0, 0, 0, 0},
  76
  77 /* The DISP9 field in a format 3 insn. */
  78 #define D9      (D7+1)
  79   { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED | V850_OPERAND_DISP },
  80
  81 /* The DISP16 field in a format 6 insn. */
  82 #define D16_15  (D9+1)
  83   { 16, 16, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED },
  84
  85 /* The DISP22 field in a format 4 insn. */
  86 #define D22     (D16_15+1)
  87   { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP },
  88
  89 #define B3      (D22+1)
  90 /* The 3 bit immediate field in format 8 insn.  */
  91   { 3, 11, 0, 0, 0 },
  92
  93 #define CCCC    (B3+1)
  94 /* The 4 bit condition code in a setf instruction */
  95   { 4, 0, 0, 0, V850_OPERAND_CC },
  96
  97 /* The unsigned DISP8_7 field in a format 4 insn. */
  98 #define D8_7    (CCCC+1)
  99   { 8, 0, insert_d8_7, extract_d8_7, 0 },
 100
 101 /* The unsigned DISP8_6 field in a format 4 insn. */
 102 #define D8_6    (D8_7+1)
 103   { 8, 0, insert_d8_6, extract_d8_6, 0 },
 104
 105 /* System register operands.  */
 106 #define SR1     (D8_6+1)
 107   { 5, 0, 0, 0, V850_OPERAND_SRG },
 108
 109 /* EP Register.  */
 110 #define EP      (SR1+1)
 111   { 0, 0, 0, 0, V850_OPERAND_EP },
 112
 113 /* The IMM16 field (unsigned0 in a format 6 insn. */
 114 #define I16U    (EP+1)
 115   { 16, 16, 0, 0, 0},
 116
 117 /* The R2 field as a system register.  */
 118 #define SR2     (I16U+1)
 119   { 5, 11, 0, 0, V850_OPERAND_SRG },
 120
 121 /* The DISP16 field in a format 8 insn. */
 122 #define D16     (SR2+1)
 123   { 16, 16, 0, 0, V850_OPERAND_SIGNED },
 124
 125 } ;
 126
 127 \f
 128 /* reg-reg instruction format (Format I) */
 129 #define IF1     {R1, R2}
 130
 131 /* imm-reg instruction format (Format II) */
 132 #define IF2     {I5, R2}
 133
 134 /* conditional branch instruction format (Format III) */
 135 #define IF3     {D9}
 136
 137 /* 16-bit load/store instruction (Format IV) */
 138 #define IF4A    {D7, EP, R2}
 139 #define IF4B    {R2, D7, EP}
 140 #define IF4C    {D8_7, EP, R2}
 141 #define IF4D    {R2, D8_7, EP}
 142 #define IF4E    {D8_6, EP, R2}
 143 #define IF4F    {R2, D8_6, EP}
 144
 145 /* Jump instruction (Format V) */
 146 #define IF5     {D22}
 147
 148 /* 3 operand instruction (Format VI) */
 149 #define IF6     {I16, R1, R2}
 150
 151 /* 3 operand instruction (Format VI) */
 152 #define IF6U    {I16U, R1, R2}
 153
 154 /* 32-bit load/store half/word instruction (Format VII) */
 155 #define IF7A    {D16_15, R1, R2}
 156 #define IF7B    {R2, D16_15, R1}
 157
 158 /* 32-bit load/store byte instruction (Format VII) */
 159 #define IF7C    {D16, R1, R2}
 160 #define IF7D    {R2, D16, R1}
 161
 162 /* Bit manipulation function.  */
 163
 164
 165 \f
 166 /* The opcode table.
 167
 168    The format of the opcode table is:
 169
 170    NAME         OPCODE          MASK            { OPERANDS }
 171
 172    NAME is the name of the instruction.
 173    OPCODE is the instruction opcode.
 174    MASK is the opcode mask; this is used to tell the disassembler
 175      which bits in the actual opcode must match OPCODE.
 176    OPERANDS is the list of operands.
 177
 178    The disassembler reads the table in order and prints the first
 179    instruction which matches, so this table is sorted to put more
 180    specific instructions before more general instructions.  It is also
 181    sorted by major opcode.  */
 182
 183 const struct v850_opcode v850_opcodes[] = {
 184 { "breakpoint", 0xffff,                 0xffff,         0,    0 },
 185 /* load/store instructions */
 186 { "sld.b",      one(0x0300),            one(0x0780),    IF4A, 1 },
 187 { "sld.h",      one(0x0400),            one(0x0780),    IF4C, 1 },
 188 { "sld.w",      one(0x0500),            one(0x0781),    IF4E, 1 },
 189 { "sst.b",      one(0x0380),            one(0x0780),    IF4B, 2 },
 190 { "sst.h",      one(0x0480),            one(0x0780),    IF4D, 2 },
 191 { "sst.w",      one(0x0501),            one(0x0781),    IF4F, 2 },
 192
 193 { "ld.b",       two(0x0700,0x0000),     two (0x07e0,0x0000),    IF7C, 1 },
 194 { "ld.h",       two(0x0720,0x0000),     two (0x07e0,0x0001),    IF7A, 1 },
 195 { "ld.w",       two(0x0720,0x0001),     two (0x07e0,0x0001),    IF7A, 1 },
 196 { "st.b",       two(0x0740,0x0000),     two (0x07e0,0x0000),    IF7D, 2 },
 197 { "st.h",       two(0x0760,0x0000),     two (0x07e0,0x0001),    IF7B, 2 },
 198 { "st.w",       two(0x0760,0x0001),     two (0x07e0,0x0001),    IF7B, 2 },
 199
 200 /* arithmetic operation instructions */
 201 { "nop",        one(0x00),              one(0xffff),            {0}, 0 },
 202 { "mov",        OP(0x00),               OP_MASK,        IF1, 0 },
 203 { "mov",        OP(0x10),               OP_MASK,        IF2, 0 },
 204 { "movea",      OP(0x31),               OP_MASK,        IF6, 0 },
 205 { "movhi",      OP(0x32),               OP_MASK,        IF6, 0 },
 206 { "add",        OP(0x0e),               OP_MASK,        IF1, 0 },
 207 { "add",        OP(0x12),               OP_MASK,        IF2, 0 },
 208 { "addi",       OP(0x30),               OP_MASK,        IF6, 0 },
 209 { "sub",        OP(0x0d),               OP_MASK,        IF1, 0 },
 210 { "subr",       OP(0x0c),               OP_MASK,        IF1, 0 },
 211 { "mulh",       OP(0x07),               OP_MASK,        IF1, 0 },
 212 { "mulh",       OP(0x17),               OP_MASK,        IF2, 0 },
 213 { "mulhi",      OP(0x37),               OP_MASK,        IF6, 0 },
 214 { "divh",       OP(0x02),               OP_MASK,        IF1, 0 },
 215 { "cmp",        OP(0x0f),               OP_MASK,        IF1, 0 },
 216 { "cmp",        OP(0x13),               OP_MASK,        IF2, 0 },
 217 { "setf",       two(0x07e0,0x0000),     two(0x07f0,0xffff), {CCCC,R2}, 0 },
 218
 219 /* saturated operation instructions */
 220 { "satadd",     OP(0x06),               OP_MASK,        IF1, 0 },
 221 { "satadd",     OP(0x11),               OP_MASK,        IF2, 0 },
 222 { "satsub",     OP(0x05),               OP_MASK,        IF1, 0 },
 223 { "satsubi",    OP(0x33),               OP_MASK,        IF6, 0 },
 224 { "satsubr",    OP(0x04),               OP_MASK,        IF1, 0 },
 225
 226 /* logical operation instructions */
 227 { "tst",        OP(0x0b),               OP_MASK,        IF1, 0 },
 228 { "or",         OP(0x08),               OP_MASK,        IF1, 0 },
 229 { "ori",        OP(0x34),               OP_MASK,        IF6U, 0 },
 230 { "and",        OP(0x0a),               OP_MASK,        IF1, 0 },
 231 { "andi",       OP(0x36),               OP_MASK,        IF6U, 0 },
 232 { "xor",        OP(0x09),               OP_MASK,        IF1, 0 },
 233 { "xori",       OP(0x35),               OP_MASK,        IF6U, 0 },
 234 { "not",        OP(0x01),               OP_MASK,        IF1, 0 },
 235 { "sar",        OP(0x15),               OP_MASK,        {I5U, R2}, 0 },
 236 { "sar",        two(0x07e0,0x00a0),     two(0x07e0,0xffff),     {R1,R2}, 0 },
 237 { "shl",        OP(0x16),               OP_MASK,                {I5U, R2}, 0 },
 238 { "shl",        two(0x07e0,0x00c0),     two(0x07e0,0xffff),     {R1,R2}, 0 },
 239 { "shr",        OP(0x14),               OP_MASK,                {I5U, R2}, 0 },
 240 { "shr",        two(0x07e0,0x0080),     two(0x07e0,0xffff),     {R1,R2}, 0 },
 241
 242 /* branch instructions */
 243         /* signed integer */
 244 { "bgt",        BOP(0xf),               BOP_MASK,       IF3, 0 },
 245 { "bge",        BOP(0xe),               BOP_MASK,       IF3, 0 },
 246 { "blt",        BOP(0x6),               BOP_MASK,       IF3, 0 },
 247 { "ble",        BOP(0x7),               BOP_MASK,       IF3, 0 },
 248         /* unsigned integer */
 249 { "bh",         BOP(0xb),               BOP_MASK,       IF3, 0 },
 250 { "bnh",        BOP(0x3),               BOP_MASK,       IF3, 0 },
 251 { "bl",         BOP(0x1),               BOP_MASK,       IF3, 0 },
 252 { "bnl",        BOP(0x9),               BOP_MASK,       IF3, 0 },
 253         /* common */
 254 { "be",         BOP(0x2),               BOP_MASK,       IF3, 0 },
 255 { "bne",        BOP(0xa),               BOP_MASK,       IF3, 0 },
 256         /* others */
 257 { "bv",         BOP(0x0),               BOP_MASK,       IF3, 0 },
 258 { "bnv",        BOP(0x8),               BOP_MASK,       IF3, 0 },
 259 { "bn",         BOP(0x4),               BOP_MASK,       IF3, 0 },
 260 { "bp",         BOP(0xc),               BOP_MASK,       IF3, 0 },
 261 { "bc",         BOP(0x1),               BOP_MASK,       IF3, 0 },
 262 { "bnc",        BOP(0x9),               BOP_MASK,       IF3, 0 },
 263 { "bz",         BOP(0x2),               BOP_MASK,       IF3, 0 },
 264 { "bnz",        BOP(0xa),               BOP_MASK,       IF3, 0 },
 265 { "br",         BOP(0x5),               BOP_MASK,       IF3, 0 },
 266 { "bsa",        BOP(0xd),               BOP_MASK,       IF3, 0 },
 267
 268 { "jmp",        one(0x0060),            one(0xffe0),    { R1}, 1 },
 269 { "jr",         one(0x0780),            two(0xffc0,0x0001),{ D22 }, 0 },
 270 { "jarl",       one(0x0780),            two(0x07c0,0x0001),{ D22, R2 }, 0 },
 271
 272 /* bit manipulation instructions */
 273 { "set1",       two(0x07c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 2 },
 274 { "not1",       two(0x47c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 2 },
 275 { "clr1",       two(0x87c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 2 },
 276 { "tst1",       two(0xc7c0,0x0000),     two(0xc7e0,0x0000),     {B3, D16, R1}, 2 },
 277
 278 /* special instructions */
 279 { "di",         two(0x07e0,0x0160),     two(0xffff,0xffff),     {0}, 0 },
 280 { "ei",         two(0x87e0,0x0160),     two(0xffff,0xffff),     {0}, 0 },
 281 { "halt",       two(0x07e0,0x0120),     two(0xffff,0xffff),     {0}, 0 },
 282 { "reti",       two(0x07e0,0x0140),     two(0xffff,0xffff),     {0}, 0 },
 283 { "trap",       two(0x07e0,0x0100),     two(0xffe0,0xffff),     {I5U}, 0 },
 284 { "ldsr",       two(0x07e0,0x0020),     two(0x07e0,0xffff),     {R1,SR2}, 0 },
 285 { "stsr",       two(0x07e0,0x0040),     two(0x07e0,0xffff),     {SR1,R2}, 0 },
 286 { 0, 0, 0, {0}, 0 },
 287
 288 } ;
 289
 290 const int v850_num_opcodes =
 291   sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
 292
 293 \f
 294 /* The functions used to insert and extract complicated operands.  */
 295
 296 static unsigned long
 297 insert_d9 (insn, value, errmsg)
 298      unsigned long insn;
 299      long value;
 300      const char **errmsg;
 301 {
 302   if (value > 0xff || value < -0x100)
 303     *errmsg = "branch value out of range";
 304
 305   if ((value % 2) != 0)
 306     *errmsg = "branch to odd offset";
 307
 308   return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
 309 }
 310
 311 static long
 312 extract_d9 (insn, invalid)
 313      unsigned long insn;
 314      int *invalid;
 315 {
 316   long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
 317
 318   if ((insn & 0x8000) != 0)
 319     ret -= 0x0200;
 320
 321   return ret;
 322 }
 323
 324 static unsigned long
 325 insert_d22 (insn, value, errmsg)
 326      unsigned long insn;
 327      long value;
 328      const char **errmsg;
 329 {
 330   if (value > 0x1fffff || value < -0x200000)
 331     *errmsg = "branch value out of range";
 332
 333   if ((value % 2) != 0)
 334     *errmsg = "branch to odd offset";
 335
 336   return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16));
 337 }
 338
 339 static long
 340 extract_d22 (insn, invalid)
 341      unsigned long insn;
 342      int *invalid;
 343 {
 344   int ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16);
 345
 346   return ((ret << 10) >> 10);
 347 }
 348
 349 static unsigned long
 350 insert_d16_15 (insn, value, errmsg)
 351      unsigned long insn;
 352      long value;
 353      const char **errmsg;
 354 {
 355   if (value > 0x7fff || value < -0x8000)
 356     *errmsg = "value out of range";
 357
 358   if ((value % 2) != 0)
 359     *errmsg = "load/store half/word at odd offset";
 360
 361   return (insn | ((value & 0xfffe) << 16));
 362 }
 363
 364 static long
 365 extract_d16_15 (insn, invalid)
 366      unsigned long insn;
 367      int *invalid;
 368 {
 369   int ret = ((insn & 0xfffe0000) >> 16);
 370
 371   return ((ret << 16) >> 16);
 372 }
 373
 374 static unsigned long
 375 insert_d8_7 (insn, value, errmsg)
 376      unsigned long insn;
 377      long value;
 378      const char **errmsg;
 379 {
 380   if (value > 0xff || value < 0)
 381     *errmsg = "short load/store half value out of range";
 382
 383   if ((value % 2) != 0)
 384     *errmsg = "short load/store half at odd offset";
 385
 386   value >>= 1;
 387
 388   return (insn | (value & 0x7f));
 389 }
 390
 391 static long
 392 extract_d8_7 (insn, invalid)
 393      unsigned long insn;
 394      int *invalid;
 395 {
 396   int ret = (insn & 0x7f);
 397
 398   return ret << 1;
 399 }
 400
 401 static unsigned long
 402 insert_d8_6 (insn, value, errmsg)
 403      unsigned long insn;
 404      long value;
 405      const char **errmsg;
 406 {
 407   if (value > 0xff || value < 0)
 408     *errmsg = "short load/store word value out of range";
 409
 410   if ((value % 4) != 0)
 411     *errmsg = "short load/store word at odd offset";
 412
 413   value >>= 1;
 414
 415   return (insn | (value & 0x7e));
 416 }
 417
 418 static long
 419 extract_d8_6 (insn, invalid)
 420      unsigned long insn;
 421      int *invalid;
 422 {
 423   int ret = (insn & 0x7e);
 424
 425   return ret << 1;
 426 }