opcodes/v850-opc.c

   1 /* Assemble V850 instructions.
   2    Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc.
   3
   4 This program is free software; you can redistribute it and/or modify
   5 it under the terms of the GNU General Public License as published by
   6 the Free Software Foundation; either version 2 of the License, or
   7 (at your option) any later version.
   8
   9 This program is distributed in the hope that it will be useful,
  10 but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 GNU General Public License for more details.
  13
  14 You should have received a copy of the GNU General Public License
  15 along with this program; if not, write to the Free Software
  16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  17
  18 #include "sysdep.h"
  19 #include "opcode/v850.h"
  20 #include <stdio.h>
  21 #include "opintl.h"
  22
  23 /* regular opcode */
  24 #define OP(x)           ((x & 0x3f) << 5)
  25 #define OP_MASK         OP (0x3f)
  26
  27 /* conditional branch opcode */
  28 #define BOP(x)          ((0x0b << 7) | (x & 0x0f))
  29 #define BOP_MASK        ((0x0f << 7) | 0x0f)
  30
  31 /* one-word opcodes */
  32 #define one(x)          ((unsigned int) (x))
  33
  34 /* two-word opcodes */
  35 #define two(x,y)        ((unsigned int) (x) | ((unsigned int) (y) << 16))
  36
  37 static long unsigned int insert_d9
  38   PARAMS ((long unsigned int, long int, const char **));
  39 static long unsigned int extract_d9
  40   PARAMS ((long unsigned int, int *));
  41 static long unsigned int insert_d22
  42   PARAMS ((long unsigned int, long int, const char **));
  43 static long unsigned int extract_d22
  44   PARAMS ((long unsigned int, int *));
  45 static long unsigned int insert_d16_15
  46   PARAMS ((long unsigned int, long int, const char **));
  47 static long unsigned int extract_d16_15
  48   PARAMS ((long unsigned int, int *));
  49 static long unsigned int insert_d8_7
  50   PARAMS ((long unsigned int, long int, const char **));
  51 static long unsigned int extract_d8_7 PARAMS ((long unsigned int, int *));
  52 static long unsigned int insert_d8_6
  53   PARAMS ((long unsigned int, long int, const char **));
  54 static long unsigned int extract_d8_6 PARAMS ((long unsigned int, int *));
  55 static long unsigned int insert_d5_4
  56   PARAMS ((long unsigned int, long int, const char **));
  57 static long unsigned int extract_d5_4 PARAMS ((long unsigned int, int *));
  58 static long unsigned int insert_d16_16
  59   PARAMS ((long unsigned int, long int, const char **));
  60 static long unsigned int extract_d16_16 PARAMS ((long unsigned int, int *));
  61 static long unsigned int insert_i9
  62   PARAMS ((long unsigned int, long int, const char **));
  63 static long unsigned int extract_i9 PARAMS ((long unsigned int, int *));
  64 static long unsigned int insert_u9
  65   PARAMS ((long unsigned int, long unsigned int, const char **));
  66 static long unsigned int extract_u9 PARAMS ((long unsigned int, int *));
  67 static long unsigned int insert_spe
  68   PARAMS ((long unsigned int, long unsigned int, const char **));
  69 static long unsigned int extract_spe PARAMS ((long unsigned int, int *));
  70 static long unsigned int insert_i5div
  71   PARAMS ((long unsigned int, long unsigned int, const char **));
  72 static long unsigned int extract_i5div PARAMS ((long unsigned int, int *));
  73
  74 \f
  75 /* The functions used to insert and extract complicated operands.  */
  76
  77 /* Note: There is a conspiracy between these functions and
  78    v850_insert_operand() in gas/config/tc-v850.c.  Error messages
  79    containing the string 'out of range' will be ignored unless a
  80    specific command line option is given to GAS.  */
  81
  82 static const char * not_valid    = N_ ("displacement value is not in range and is not aligned");
  83 static const char * out_of_range = N_ ("displacement value is out of range");
  84 static const char * not_aligned  = N_ ("displacement value is not aligned");
  85
  86 static const char * immediate_out_of_range = N_ ("immediate value is out of range");
  87
  88 static unsigned long
  89 insert_d9 (insn, value, errmsg)
  90      unsigned long insn;
  91      long          value;
  92      const char ** errmsg;
  93 {
  94   if (value > 0xff || value < -0x100)
  95     {
  96       if ((value % 2) != 0)
  97         * errmsg = _("branch value not in range and to odd offset");
  98       else
  99         * errmsg = _("branch value out of range");
 100     }
 101   else if ((value % 2) != 0)
 102     * errmsg = _("branch to odd offset");
 103
 104   return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
 105 }
 106
 107 static unsigned long
 108 extract_d9 (insn, invalid)
 109      unsigned long insn;
 110      int *         invalid ATTRIBUTE_UNUSED;
 111 {
 112   unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
 113
 114   if ((insn & 0x8000) != 0)
 115     ret -= 0x0200;
 116
 117   return ret;
 118 }
 119
 120 static unsigned long
 121 insert_d22 (insn, value, errmsg)
 122      unsigned long insn;
 123      long          value;
 124      const char ** errmsg;
 125 {
 126   if (value > 0x1fffff || value < -0x200000)
 127     {
 128       if ((value % 2) != 0)
 129         * errmsg = _("branch value not in range and to an odd offset");
 130       else
 131         * errmsg = _("branch value out of range");
 132     }
 133   else if ((value % 2) != 0)
 134     * errmsg = _("branch to odd offset");
 135
 136   return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16));
 137 }
 138
 139 static unsigned long
 140 extract_d22 (insn, invalid)
 141      unsigned long insn;
 142      int *         invalid ATTRIBUTE_UNUSED;
 143 {
 144   signed long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16);
 145
 146   return (unsigned long) ((ret << 10) >> 10);
 147 }
 148
 149 static unsigned long
 150 insert_d16_15 (insn, value, errmsg)
 151      unsigned long insn;
 152      long          value;
 153      const char ** errmsg;
 154 {
 155   if (value > 0x7fff || value < -0x8000)
 156     {
 157       if ((value % 2) != 0)
 158         * errmsg = _(not_valid);
 159       else
 160         * errmsg = _(out_of_range);
 161     }
 162   else if ((value % 2) != 0)
 163     * errmsg = _(not_aligned);
 164
 165   return insn | ((value & 0xfffe) << 16);
 166 }
 167
 168 static unsigned long
 169 extract_d16_15 (insn, invalid)
 170      unsigned long insn;
 171      int *         invalid ATTRIBUTE_UNUSED;
 172 {
 173   signed long ret = (insn & 0xfffe0000);
 174
 175   return ret >> 16;
 176 }
 177
 178 static unsigned long
 179 insert_d8_7 (insn, value, errmsg)
 180      unsigned long insn;
 181      long          value;
 182      const char ** errmsg;
 183 {
 184   if (value > 0xff || value < 0)
 185     {
 186       if ((value % 2) != 0)
 187         * errmsg = _(not_valid);
 188       else
 189         * errmsg = _(out_of_range);
 190     }
 191   else if ((value % 2) != 0)
 192     * errmsg = _(not_aligned);
 193
 194   value >>= 1;
 195
 196   return (insn | (value & 0x7f));
 197 }
 198
 199 static unsigned long
 200 extract_d8_7 (insn, invalid)
 201      unsigned long insn;
 202      int *         invalid ATTRIBUTE_UNUSED;
 203 {
 204   unsigned long ret = (insn & 0x7f);
 205
 206   return ret << 1;
 207 }
 208
 209 static unsigned long
 210 insert_d8_6 (insn, value, errmsg)
 211      unsigned long insn;
 212      long          value;
 213      const char ** errmsg;
 214 {
 215   if (value > 0xff || value < 0)
 216     {
 217       if ((value % 4) != 0)
 218         *errmsg = _(not_valid);
 219       else
 220         * errmsg = _(out_of_range);
 221     }
 222   else if ((value % 4) != 0)
 223     * errmsg = _(not_aligned);
 224
 225   value >>= 1;
 226
 227   return (insn | (value & 0x7e));
 228 }
 229
 230 static unsigned long
 231 extract_d8_6 (insn, invalid)
 232      unsigned long insn;
 233      int *         invalid ATTRIBUTE_UNUSED;
 234 {
 235   unsigned long ret = (insn & 0x7e);
 236
 237   return ret << 1;
 238 }
 239
 240 static unsigned long
 241 insert_d5_4 (insn, value, errmsg)
 242      unsigned long insn;
 243      long          value;
 244      const char ** errmsg;
 245 {
 246   if (value > 0x1f || value < 0)
 247     {
 248       if (value & 1)
 249         * errmsg = _(not_valid);
 250       else
 251         *errmsg = _(out_of_range);
 252     }
 253   else if (value & 1)
 254     * errmsg = _(not_aligned);
 255
 256   value >>= 1;
 257
 258   return (insn | (value & 0x0f));
 259 }
 260
 261 static unsigned long
 262 extract_d5_4 (insn, invalid)
 263      unsigned long insn;
 264      int *         invalid ATTRIBUTE_UNUSED;
 265 {
 266   unsigned long ret = (insn & 0x0f);
 267
 268   return ret << 1;
 269 }
 270
 271 static unsigned long
 272 insert_d16_16 (insn, value, errmsg)
 273      unsigned long insn;
 274      signed long   value;
 275      const char ** errmsg;
 276 {
 277   if (value > 0x7fff || value < -0x8000)
 278     * errmsg = _(out_of_range);
 279
 280   return (insn | ((value & 0xfffe) << 16) | ((value & 1) << 5));
 281 }
 282
 283 static unsigned long
 284 extract_d16_16 (insn, invalid)
 285      unsigned long insn;
 286      int *         invalid ATTRIBUTE_UNUSED;
 287 {
 288   signed long ret = insn & 0xfffe0000;
 289
 290   ret >>= 16;
 291
 292   ret |= ((insn & 0x20) >> 5);
 293
 294   return ret;
 295 }
 296
 297 static unsigned long
 298 insert_i9 (insn, value, errmsg)
 299      unsigned long insn;
 300      signed long   value;
 301      const char ** errmsg;
 302 {
 303   if (value > 0xff || value < -0x100)
 304     * errmsg = _(immediate_out_of_range);
 305
 306   return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
 307 }
 308
 309 static unsigned long
 310 extract_i9 (insn, invalid)
 311      unsigned long insn;
 312      int *         invalid ATTRIBUTE_UNUSED;
 313 {
 314   signed long ret = insn & 0x003c0000;
 315
 316   ret <<= 10;
 317   ret >>= 23;
 318
 319   ret |= (insn & 0x1f);
 320
 321   return ret;
 322 }
 323
 324 static unsigned long
 325 insert_u9 (insn, value, errmsg)
 326      unsigned long insn;
 327      unsigned long value;
 328      const char ** errmsg;
 329 {
 330   if (value > 0x1ff)
 331     * errmsg = _(immediate_out_of_range);
 332
 333   return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
 334 }
 335
 336 static unsigned long
 337 extract_u9 (insn, invalid)
 338      unsigned long insn;
 339      int *         invalid ATTRIBUTE_UNUSED;
 340 {
 341   unsigned long ret = insn & 0x003c0000;
 342
 343   ret >>= 13;
 344
 345   ret |= (insn & 0x1f);
 346
 347   return ret;
 348 }
 349
 350 static unsigned long
 351 insert_spe (insn, value, errmsg)
 352      unsigned long insn;
 353      unsigned long value;
 354      const char ** errmsg;
 355 {
 356   if (value != 3)
 357     * errmsg = _("invalid register for stack adjustment");
 358
 359   return insn & (~ 0x180000);
 360 }
 361
 362 static unsigned long
 363 extract_spe (insn, invalid)
 364      unsigned long insn ATTRIBUTE_UNUSED;
 365      int *         invalid ATTRIBUTE_UNUSED;
 366 {
 367   return 3;
 368 }
 369
 370 static unsigned long
 371 insert_i5div (insn, value, errmsg)
 372      unsigned long insn;
 373      unsigned long value;
 374      const char ** errmsg;
 375 {
 376   if (value > 0x1ff)
 377     {
 378       if (value & 1)
 379         * errmsg = _("immediate value not in range and not even");
 380       else
 381         * errmsg = _(immediate_out_of_range);
 382     }
 383   else if (value & 1)
 384     * errmsg = _("immediate value must be even");
 385
 386   value = 32 - value;
 387
 388   return insn | ((value & 0x1e) << 17);
 389 }
 390
 391 static unsigned long
 392 extract_i5div (insn, invalid)
 393      unsigned long insn;
 394      int *         invalid ATTRIBUTE_UNUSED;
 395 {
 396   unsigned long ret = insn & 0x3c0000;
 397
 398   ret >>= 17;
 399
 400   ret = 32 - ret;
 401
 402   return ret;
 403 }
 404
 405 \f
 406 /* Warning: code in gas/config/tc-v850.c examines the contents of this array.
 407    If you change any of the values here, be sure to look for side effects in
 408    that code. */
 409 const struct v850_operand v850_operands[] =
 410 {
 411 #define UNUSED  0
 412   { 0, 0, NULL, NULL, 0 },
 413
 414 /* The R1 field in a format 1, 6, 7, or 9 insn. */
 415 #define R1      (UNUSED + 1)
 416   { 5, 0, NULL, NULL, V850_OPERAND_REG },
 417
 418 /* As above, but register 0 is not allowed.  */
 419 #define R1_NOTR0 (R1 + 1)
 420   { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
 421
 422 /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
 423 #define R2      (R1_NOTR0 + 1)
 424   { 5, 11, NULL, NULL, V850_OPERAND_REG },
 425
 426 /* As above, but register 0 is not allowed.  */
 427 #define R2_NOTR0 (R2 + 1)
 428   { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
 429
 430 /* The imm5 field in a format 2 insn. */
 431 #define I5      (R2_NOTR0 + 1)
 432   { 5, 0, NULL, NULL, V850_OPERAND_SIGNED },
 433
 434 /* The unsigned imm5 field in a format 2 insn. */
 435 #define I5U     (I5 + 1)
 436   { 5, 0, NULL, NULL, 0 },
 437
 438 /* The imm16 field in a format 6 insn. */
 439 #define I16     (I5U + 1)
 440   { 16, 16, NULL, NULL, V850_OPERAND_SIGNED },
 441
 442 /* The signed disp7 field in a format 4 insn. */
 443 #define D7      (I16 + 1)
 444   { 7, 0, NULL, NULL, 0},
 445
 446 /* The disp16 field in a format 6 insn. */
 447 #define D16_15  (D7 + 1)
 448   { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED },
 449
 450 /* The 3 bit immediate field in format 8 insn.  */
 451 #define B3      (D16_15 + 1)
 452   { 3, 11, NULL, NULL, 0 },
 453
 454 /* The 4 bit condition code in a setf instruction */
 455 #define CCCC    (B3 + 1)
 456   { 4, 0, NULL, NULL, V850_OPERAND_CC },
 457
 458 /* The unsigned DISP8 field in a format 4 insn. */
 459 #define D8_7    (CCCC + 1)
 460   { 7, 0, insert_d8_7, extract_d8_7, 0 },
 461
 462 /* The unsigned DISP8 field in a format 4 insn. */
 463 #define D8_6    (D8_7 + 1)
 464   { 6, 1, insert_d8_6, extract_d8_6, 0 },
 465
 466 /* System register operands.  */
 467 #define SR1     (D8_6 + 1)
 468   { 5, 0, NULL, NULL, V850_OPERAND_SRG },
 469
 470 /* EP Register.  */
 471 #define EP      (SR1 + 1)
 472   { 0, 0, NULL, NULL, V850_OPERAND_EP },
 473
 474 /* The imm16 field (unsigned) in a format 6 insn. */
 475 #define I16U    (EP + 1)
 476   { 16, 16, NULL, NULL, 0},
 477
 478 /* The R2 field as a system register.  */
 479 #define SR2     (I16U + 1)
 480   { 5, 11, NULL, NULL, V850_OPERAND_SRG },
 481
 482 /* The disp16 field in a format 8 insn. */
 483 #define D16     (SR2 + 1)
 484   { 16, 16, NULL, NULL, V850_OPERAND_SIGNED },
 485
 486 /* The DISP9 field in a format 3 insn, relaxable. */
 487 #define D9_RELAX        (D16 + 1)
 488   { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP },
 489
 490 /* The DISP22 field in a format 4 insn, relaxable.
 491    This _must_ follow D9_RELAX; the assembler assumes that the longer
 492    version immediately follows the shorter version for relaxing.  */
 493 #define D22     (D9_RELAX + 1)
 494   { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP },
 495
 496 /* The signed disp4 field in a format 4 insn. */
 497 #define D4      (D22 + 1)
 498   { 4, 0, NULL, NULL, 0},
 499
 500 /* The unsigned disp5 field in a format 4 insn. */
 501 #define D5_4    (D4 + 1)
 502   { 4, 0, insert_d5_4, extract_d5_4, 0 },
 503
 504 /* The disp16 field in an format 7 unsigned byte load insn. */
 505 #define D16_16  (D5_4 + 1)
 506   { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 },
 507
 508 /* Third register in conditional moves. */
 509 #define R3      (D16_16 + 1)
 510   { 5, 27, NULL, NULL, V850_OPERAND_REG },
 511
 512 /* Condition code in conditional moves.  */
 513 #define MOVCC   (R3 + 1)
 514   { 4, 17, NULL, NULL, V850_OPERAND_CC },
 515
 516 /* The imm9 field in a multiply word. */
 517 #define I9      (MOVCC + 1)
 518   { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED },
 519
 520 /* The unsigned imm9 field in a multiply word. */
 521 #define U9      (I9 + 1)
 522   { 9, 0, insert_u9, extract_u9, 0 },
 523
 524 /* A list of registers in a prepare/dispose instruction.  */
 525 #define LIST12  (U9 + 1)
 526   { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP },
 527
 528 /* The IMM6 field in a call instruction. */
 529 #define I6      (LIST12 + 1)
 530   { 6, 0, NULL, NULL, 0 },
 531
 532 /* The 16 bit immediate following a 32 bit instruction.  */
 533 #define IMM16   (I6 + 1)
 534   { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 },
 535
 536 /* The 32 bit immediate following a 32 bit instruction.  */
 537 #define IMM32   (IMM16 + 1)
 538   { 0, 0, NULL, NULL, V850E_IMMEDIATE32 },
 539
 540 /* The imm5 field in a push/pop instruction. */
 541 #define IMM5    (IMM32 + 1)
 542   { 5, 1, NULL, NULL, 0 },
 543
 544 /* Reg2 in dispose instruction. */
 545 #define R2DISPOSE       (IMM5 + 1)
 546   { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
 547
 548 /* Stack pointer in prepare instruction. */
 549 #define SP      (R2DISPOSE + 1)
 550   { 2, 19, insert_spe, extract_spe, V850_OPERAND_REG },
 551
 552 /* The IMM5 field in a divide N step instruction. */
 553 #define I5DIV   (SP + 1)
 554   { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED },
 555
 556   /* The list of registers in a PUSHMH/POPMH instruction.  */
 557 #define LIST18_H (I5DIV + 1)
 558   { -1, 0xfff8000f, NULL, NULL, V850E_PUSH_POP },
 559
 560   /* The list of registers in a PUSHML/POPML instruction.  */
 561 #define LIST18_L (LIST18_H + 1)
 562   { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c */
 563 } ;
 564
 565 \f
 566 /* reg-reg instruction format (Format I) */
 567 #define IF1     {R1, R2}
 568
 569 /* imm-reg instruction format (Format II) */
 570 #define IF2     {I5, R2}
 571
 572 /* conditional branch instruction format (Format III) */
 573 #define IF3     {D9_RELAX}
 574
 575 /* 3 operand instruction (Format VI) */
 576 #define IF6     {I16, R1, R2}
 577
 578 /* 3 operand instruction (Format VI) */
 579 #define IF6U    {I16U, R1, R2}
 580
 581
 582 \f
 583 /* The opcode table.
 584
 585    The format of the opcode table is:
 586
 587    NAME         OPCODE                  MASK                   { OPERANDS }        MEMOP    PROCESSOR
 588
 589    NAME is the name of the instruction.
 590    OPCODE is the instruction opcode.
 591    MASK is the opcode mask; this is used to tell the disassembler
 592      which bits in the actual opcode must match OPCODE.
 593    OPERANDS is the list of operands.
 594    MEMOP specifies which operand (if any) is a memory operand.
 595    PROCESSORS specifies which CPU(s) support the opcode.
 596
 597    The disassembler reads the table in order and prints the first
 598    instruction which matches, so this table is sorted to put more
 599    specific instructions before more general instructions.  It is also
 600    sorted by major opcode.
 601
 602    The table is also sorted by name.  This is used by the assembler.
 603    When parsing an instruction the assembler finds the first occurance
 604    of the name of the instruciton in this table and then attempts to
 605    match the instruction's arguments with description of the operands
 606    associated with the entry it has just found in this table.  If the
 607    match fails the assembler looks at the next entry in this table.
 608    If that entry has the same name as the previous entry, then it
 609    tries to match the instruction against that entry and so on.  This
 610    is how the assembler copes with multiple, different formats of the
 611    same instruction.  */
 612
 613 const struct v850_opcode v850_opcodes[] =
 614 {
 615 { "breakpoint", 0xffff,                 0xffff,                 {UNUSED},               0, PROCESSOR_ALL },
 616
 617 { "jmp",        one (0x0060),           one (0xffe0),           {R1},                   1, PROCESSOR_ALL },
 618
 619 /* load/store instructions */
 620 { "sld.bu",     one (0x0300),           one (0x0780),           {D7,   EP,   R2_NOTR0}, 1, PROCESSOR_V850EA },
 621 { "sld.bu",     one (0x0060),           one (0x07f0),           {D4,   EP,   R2_NOTR0}, 1, PROCESSOR_V850E },
 622
 623 { "sld.hu",     one (0x0400),           one (0x0780),           {D8_7, EP,   R2_NOTR0}, 1, PROCESSOR_V850EA },
 624 { "sld.hu",     one (0x0070),           one (0x07f0),           {D5_4, EP,   R2_NOTR0}, 1, PROCESSOR_V850E },
 625
 626 { "sld.b",      one (0x0060),           one (0x07f0),           {D4,   EP,   R2},       1, PROCESSOR_V850EA },
 627 { "sld.b",      one (0x0300),           one (0x0780),           {D7,   EP,   R2},       1, PROCESSOR_V850E },
 628 { "sld.b",      one (0x0300),           one (0x0780),           {D7,   EP,   R2},       1, PROCESSOR_V850 },
 629
 630 { "sld.h",      one (0x0070),           one (0x07f0),           {D5_4, EP,   R2},       1, PROCESSOR_V850EA },
 631 { "sld.h",      one (0x0400),           one (0x0780),           {D8_7, EP,   R2},       1, PROCESSOR_V850E },
 632 { "sld.h",      one (0x0400),           one (0x0780),           {D8_7, EP,   R2},       1, PROCESSOR_V850 },
 633 { "sld.w",      one (0x0500),           one (0x0781),           {D8_6, EP,   R2},       1, PROCESSOR_ALL },
 634 { "sst.b",      one (0x0380),           one (0x0780),           {R2,   D7,   EP},       2, PROCESSOR_ALL },
 635 { "sst.h",      one (0x0480),           one (0x0780),           {R2,   D8_7, EP},       2, PROCESSOR_ALL },
 636 { "sst.w",      one (0x0501),           one (0x0781),           {R2,   D8_6, EP},       2, PROCESSOR_ALL },
 637
 638 { "pushml",     two (0x07e0, 0x0001),   two (0xfff0, 0x0007),   {LIST18_L},             0, PROCESSOR_V850EA },
 639 { "pushmh",     two (0x07e0, 0x0003),   two (0xfff0, 0x0007),   {LIST18_H},             0, PROCESSOR_V850EA },
 640 { "popml",      two (0x07f0, 0x0001),   two (0xfff0, 0x0007),   {LIST18_L},             0, PROCESSOR_V850EA },
 641 { "popmh",      two (0x07f0, 0x0003),   two (0xfff0, 0x0007),   {LIST18_H},             0, PROCESSOR_V850EA },
 642 { "prepare",    two (0x0780, 0x0003),   two (0xffc0, 0x001f),   {LIST12, IMM5, SP},     0, PROCESSOR_NOT_V850 },
 643 { "prepare",    two (0x0780, 0x000b),   two (0xffc0, 0x001f),   {LIST12, IMM5, IMM16},  0, PROCESSOR_NOT_V850 },
 644 { "prepare",    two (0x0780, 0x0013),   two (0xffc0, 0x001f),   {LIST12, IMM5, IMM16},  0, PROCESSOR_NOT_V850 },
 645 { "prepare",    two (0x0780, 0x001b),   two (0xffc0, 0x001f),   {LIST12, IMM5, IMM32},  0, PROCESSOR_NOT_V850 },
 646 { "prepare",    two (0x0780, 0x0001),   two (0xffc0, 0x001f),   {LIST12, IMM5},         0, PROCESSOR_NOT_V850 },
 647 { "dispose",    one (0x0640),           one (0xffc0),           {IMM5, LIST12, R2DISPOSE},0, PROCESSOR_NOT_V850 },
 648 { "dispose",    two (0x0640, 0x0000),   two (0xffc0, 0x001f),   {IMM5, LIST12},         0, PROCESSOR_NOT_V850 },
 649
 650 { "ld.b",       two (0x0700, 0x0000),   two (0x07e0, 0x0000),   {D16, R1, R2},          1, PROCESSOR_ALL },
 651 { "ld.h",       two (0x0720, 0x0000),   two (0x07e0, 0x0001),   {D16_15, R1, R2},       1, PROCESSOR_ALL },
 652 { "ld.w",       two (0x0720, 0x0001),   two (0x07e0, 0x0001),   {D16_15, R1, R2},       1, PROCESSOR_ALL },
 653 { "ld.bu",      two (0x0780, 0x0001),   two (0x07c0, 0x0001),   {D16_16, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 },
 654 { "ld.hu",      two (0x07e0, 0x0001),   two (0x07e0, 0x0001),   {D16_15, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 },
 655 { "st.b",       two (0x0740, 0x0000),   two (0x07e0, 0x0000),   {R2, D16, R1},          2, PROCESSOR_ALL },
 656 { "st.h",       two (0x0760, 0x0000),   two (0x07e0, 0x0001),   {R2, D16_15, R1},       2, PROCESSOR_ALL },
 657 { "st.w",       two (0x0760, 0x0001),   two (0x07e0, 0x0001),   {R2, D16_15, R1},       2, PROCESSOR_ALL },
 658
 659 /* byte swap/extend instructions */
 660 { "zxb",        one (0x0080),           one (0xffe0),           {R1_NOTR0},             0, PROCESSOR_NOT_V850 },
 661 { "zxh",        one (0x00c0),           one (0xffe0),           {R1_NOTR0},             0, PROCESSOR_NOT_V850 },
 662 { "sxb",        one (0x00a0),           one (0xffe0),           {R1_NOTR0},             0, PROCESSOR_NOT_V850 },
 663 { "sxh",        one (0x00e0),           one (0xffe0),           {R1_NOTR0},             0, PROCESSOR_NOT_V850 },
 664 { "bsh",        two (0x07e0, 0x0342),   two (0x07ff, 0x07ff),   {R2, R3},               0, PROCESSOR_NOT_V850 },
 665 { "bsw",        two (0x07e0, 0x0340),   two (0x07ff, 0x07ff),   {R2, R3},               0, PROCESSOR_NOT_V850 },
 666 { "hsw",        two (0x07e0, 0x0344),   two (0x07ff, 0x07ff),   {R2, R3},               0, PROCESSOR_NOT_V850 },
 667
 668 /* jump table instructions */
 669 { "switch",     one (0x0040),           one (0xffe0),           {R1},                   1, PROCESSOR_NOT_V850 },
 670 { "callt",      one (0x0200),           one (0xffc0),           {I6},                   0, PROCESSOR_NOT_V850 },
 671 { "ctret",      two (0x07e0, 0x0144),   two (0xffff, 0xffff),   {0},                    0, PROCESSOR_NOT_V850 },
 672
 673 /* arithmetic operation instructions */
 674 { "setf",       two (0x07e0, 0x0000),   two (0x07f0, 0xffff),   {CCCC, R2},             0, PROCESSOR_ALL },
 675 { "cmov",       two (0x07e0, 0x0320),   two (0x07e0, 0x07e1),   {MOVCC, R1, R2, R3},    0, PROCESSOR_NOT_V850 },
 676 { "cmov",       two (0x07e0, 0x0300),   two (0x07e0, 0x07e1),   {MOVCC, I5, R2, R3},    0, PROCESSOR_NOT_V850 },
 677
 678 { "mul",        two (0x07e0, 0x0220),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_NOT_V850 },
 679 { "mul",        two (0x07e0, 0x0240),   two (0x07e0, 0x07c3),   {I9, R2, R3},           0, PROCESSOR_NOT_V850 },
 680 { "mulu",       two (0x07e0, 0x0222),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_NOT_V850 },
 681 { "mulu",       two (0x07e0, 0x0242),   two (0x07e0, 0x07c3),   {U9, R2, R3},           0, PROCESSOR_NOT_V850 },
 682
 683 { "div",        two (0x07e0, 0x02c0),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_NOT_V850 },
 684 { "divu",       two (0x07e0, 0x02c2),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_NOT_V850 },
 685 { "divhu",      two (0x07e0, 0x0282),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_NOT_V850 },
 686 { "divh",       two (0x07e0, 0x0280),   two (0x07e0, 0x07ff),   {R1, R2, R3},           0, PROCESSOR_NOT_V850 },
 687 { "divh",       OP  (0x02),             OP_MASK,                {R1, R2_NOTR0},         0, PROCESSOR_ALL },
 688
 689 { "divhn",      two (0x07e0, 0x0280),   two (0x07e0, 0x07c3),   {I5DIV, R1, R2, R3},    0, PROCESSOR_V850EA },
 690 { "divhun",     two (0x07e0, 0x0282),   two (0x07e0, 0x07c3),   {I5DIV, R1, R2, R3},    0, PROCESSOR_V850EA },
 691 { "divn",       two (0x07e0, 0x02c0),   two (0x07e0, 0x07c3),   {I5DIV, R1, R2, R3},    0, PROCESSOR_V850EA },
 692 { "divun",      two (0x07e0, 0x02c2),   two (0x07e0, 0x07c3),   {I5DIV, R1, R2, R3},    0, PROCESSOR_V850EA },
 693 { "sdivhn",     two (0x07e0, 0x0180),   two (0x07e0, 0x07c3),   {I5DIV, R1, R2, R3},    0, PROCESSOR_V850EA },
 694 { "sdivhun",    two (0x07e0, 0x0182),   two (0x07e0, 0x07c3),   {I5DIV, R1, R2, R3},    0, PROCESSOR_V850EA },
 695 { "sdivn",      two (0x07e0, 0x01c0),   two (0x07e0, 0x07c3),   {I5DIV, R1, R2, R3},    0, PROCESSOR_V850EA },
 696 { "sdivun",     two (0x07e0, 0x01c2),   two (0x07e0, 0x07c3),   {I5DIV, R1, R2, R3},    0, PROCESSOR_V850EA },
 697
 698 { "nop",        one (0x00),             one (0xffff),           {0},                    0, PROCESSOR_ALL },
 699 { "mov",        OP  (0x10),             OP_MASK,                {I5, R2_NOTR0},         0, PROCESSOR_ALL },
 700 { "mov",        one (0x0620),           one (0xffe0),           {IMM32, R1_NOTR0},      0, PROCESSOR_NOT_V850 },
 701 { "mov",        OP  (0x00),             OP_MASK,                {R1, R2_NOTR0},         0, PROCESSOR_ALL },
 702 { "movea",      OP  (0x31),             OP_MASK,                {I16, R1, R2_NOTR0},    0, PROCESSOR_ALL },
 703 { "movhi",      OP  (0x32),             OP_MASK,                {I16U, R1, R2_NOTR0},   0, PROCESSOR_ALL },
 704 { "add",        OP  (0x0e),             OP_MASK,                IF1,                    0, PROCESSOR_ALL },
 705 { "add",        OP  (0x12),             OP_MASK,                IF2,                    0, PROCESSOR_ALL },
 706 { "addi",       OP  (0x30),             OP_MASK,                IF6,                    0, PROCESSOR_ALL },
 707 { "sub",        OP  (0x0d),             OP_MASK,                IF1,                    0, PROCESSOR_ALL },
 708 { "subr",       OP  (0x0c),             OP_MASK,                IF1,                    0, PROCESSOR_ALL },
 709 { "mulh",       OP  (0x17),             OP_MASK,                {I5, R2_NOTR0},         0, PROCESSOR_ALL },
 710 { "mulh",       OP  (0x07),             OP_MASK,                {R1, R2_NOTR0},         0, PROCESSOR_ALL },
 711 { "mulhi",      OP  (0x37),             OP_MASK,                {I16, R1, R2_NOTR0},    0, PROCESSOR_ALL },
 712 { "cmp",        OP  (0x0f),             OP_MASK,                IF1,                    0, PROCESSOR_ALL },
 713 { "cmp",        OP  (0x13),             OP_MASK,                IF2,                    0, PROCESSOR_ALL },
 714
 715 /* saturated operation instructions */
 716 { "satadd",     OP (0x11),              OP_MASK,                {I5, R2_NOTR0},         0, PROCESSOR_ALL },
 717 { "satadd",     OP (0x06),              OP_MASK,                {R1, R2_NOTR0},         0, PROCESSOR_ALL },
 718 { "satsub",     OP (0x05),              OP_MASK,                {R1, R2_NOTR0},         0, PROCESSOR_ALL },
 719 { "satsubi",    OP (0x33),              OP_MASK,                {I16, R1, R2_NOTR0},    0, PROCESSOR_ALL },
 720 { "satsubr",    OP (0x04),              OP_MASK,                {R1, R2_NOTR0},         0, PROCESSOR_ALL },
 721
 722 /* logical operation instructions */
 723 { "tst",        OP (0x0b),              OP_MASK,                IF1,                    0, PROCESSOR_ALL },
 724 { "or",         OP (0x08),              OP_MASK,                IF1,                    0, PROCESSOR_ALL },
 725 { "ori",        OP (0x34),              OP_MASK,                IF6U,                   0, PROCESSOR_ALL },
 726 { "and",        OP (0x0a),              OP_MASK,                IF1,                    0, PROCESSOR_ALL },
 727 { "andi",       OP (0x36),              OP_MASK,                IF6U,                   0, PROCESSOR_ALL },
 728 { "xor",        OP (0x09),              OP_MASK,                IF1,                    0, PROCESSOR_ALL },
 729 { "xori",       OP (0x35),              OP_MASK,                IF6U,                   0, PROCESSOR_ALL },
 730 { "not",        OP (0x01),              OP_MASK,                IF1,                    0, PROCESSOR_ALL },
 731 { "sar",        OP (0x15),              OP_MASK,                {I5U, R2},              0, PROCESSOR_ALL },
 732 { "sar",        two (0x07e0, 0x00a0),   two (0x07e0, 0xffff),   {R1,  R2},              0, PROCESSOR_ALL },
 733 { "shl",        OP  (0x16),             OP_MASK,                {I5U, R2},              0, PROCESSOR_ALL },
 734 { "shl",        two (0x07e0, 0x00c0),   two (0x07e0, 0xffff),   {R1,  R2},              0, PROCESSOR_ALL },
 735 { "shr",        OP  (0x14),             OP_MASK,                {I5U, R2},              0, PROCESSOR_ALL },
 736 { "shr",        two (0x07e0, 0x0080),   two (0x07e0, 0xffff),   {R1,  R2},              0, PROCESSOR_ALL },
 737 { "sasf",       two (0x07e0, 0x0200),   two (0x07f0, 0xffff),   {CCCC, R2},             0, PROCESSOR_NOT_V850 },
 738
 739 /* branch instructions */
 740         /* signed integer */
 741 { "bgt",        BOP (0xf),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 742 { "bge",        BOP (0xe),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 743 { "blt",        BOP (0x6),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 744 { "ble",        BOP (0x7),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 745         /* unsigned integer */
 746 { "bh",         BOP (0xb),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 747 { "bnh",        BOP (0x3),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 748 { "bl",         BOP (0x1),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 749 { "bnl",        BOP (0x9),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 750         /* common */
 751 { "be",         BOP (0x2),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 752 { "bne",        BOP (0xa),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 753         /* others */
 754 { "bv",         BOP (0x0),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 755 { "bnv",        BOP (0x8),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 756 { "bn",         BOP (0x4),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 757 { "bp",         BOP (0xc),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 758 { "bc",         BOP (0x1),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 759 { "bnc",        BOP (0x9),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 760 { "bz",         BOP (0x2),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 761 { "bnz",        BOP (0xa),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 762 { "br",         BOP (0x5),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 763 { "bsa",        BOP (0xd),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 764
 765 /* Branch macros.
 766
 767    We use the short form in the opcode/mask fields.  The assembler
 768    will twiddle bits as necessary if the long form is needed.  */
 769
 770         /* signed integer */
 771 { "jgt",        BOP (0xf),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 772 { "jge",        BOP (0xe),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 773 { "jlt",        BOP (0x6),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 774 { "jle",        BOP (0x7),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 775         /* unsigned integer */
 776 { "jh",         BOP (0xb),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 777 { "jnh",        BOP (0x3),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 778 { "jl",         BOP (0x1),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 779 { "jnl",        BOP (0x9),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 780         /* common */
 781 { "je",         BOP (0x2),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 782 { "jne",        BOP (0xa),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 783         /* others */
 784 { "jv",         BOP (0x0),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 785 { "jnv",        BOP (0x8),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 786 { "jn",         BOP (0x4),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 787 { "jp",         BOP (0xc),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 788 { "jc",         BOP (0x1),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 789 { "jnc",        BOP (0x9),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 790 { "jz",         BOP (0x2),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 791 { "jnz",        BOP (0xa),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 792 { "jsa",        BOP (0xd),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 793 { "jbr",        BOP (0x5),              BOP_MASK,               IF3,                    0, PROCESSOR_ALL },
 794
 795 { "jr",         one (0x0780),           two (0xffc0, 0x0001),   {D22},                  0, PROCESSOR_ALL },
 796 { "jarl",       one (0x0780),           two (0x07c0, 0x0001),   {D22, R2},              0, PROCESSOR_ALL},
 797
 798 /* bit manipulation instructions */
 799 { "set1",       two (0x07c0, 0x0000),   two (0xc7e0, 0x0000),   {B3, D16, R1},          2, PROCESSOR_ALL },
 800 { "set1",       two (0x07e0, 0x00e0),   two (0x07e0, 0xffff),   {R2, R1},               2, PROCESSOR_NOT_V850 },
 801 { "not1",       two (0x47c0, 0x0000),   two (0xc7e0, 0x0000),   {B3, D16, R1},          2, PROCESSOR_ALL },
 802 { "not1",       two (0x07e0, 0x00e2),   two (0x07e0, 0xffff),   {R2, R1},               2, PROCESSOR_NOT_V850 },
 803 { "clr1",       two (0x87c0, 0x0000),   two (0xc7e0, 0x0000),   {B3, D16, R1},          2, PROCESSOR_ALL },
 804 { "clr1",       two (0x07e0, 0x00e4),   two (0x07e0, 0xffff),   {R2, R1},               2, PROCESSOR_NOT_V850 },
 805 { "tst1",       two (0xc7c0, 0x0000),   two (0xc7e0, 0x0000),   {B3, D16, R1},          2, PROCESSOR_ALL },
 806 { "tst1",       two (0x07e0, 0x00e6),   two (0x07e0, 0xffff),   {R2, R1},               2, PROCESSOR_NOT_V850 },
 807
 808 /* special instructions */
 809 { "di",         two (0x07e0, 0x0160),   two (0xffff, 0xffff),   {0},                    0, PROCESSOR_ALL },
 810 { "ei",         two (0x87e0, 0x0160),   two (0xffff, 0xffff),   {0},                    0, PROCESSOR_ALL },
 811 { "halt",       two (0x07e0, 0x0120),   two (0xffff, 0xffff),   {0},                    0, PROCESSOR_ALL },
 812 { "reti",       two (0x07e0, 0x0140),   two (0xffff, 0xffff),   {0},                    0, PROCESSOR_ALL },
 813 { "trap",       two (0x07e0, 0x0100),   two (0xffe0, 0xffff),   {I5U},                  0, PROCESSOR_ALL },
 814 { "ldsr",       two (0x07e0, 0x0020),   two (0x07e0, 0xffff),   {R1, SR2},              0, PROCESSOR_ALL },
 815 { "stsr",       two (0x07e0, 0x0040),   two (0x07e0, 0xffff),   {SR1, R2},              0, PROCESSOR_ALL },
 816 { 0, 0, 0, {0}, 0, 0 },
 817
 818 } ;
 819
 820 const int v850_num_opcodes =
 821   sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
 822