sim/aarch64/ChangeLog

   1 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
   2
   3         * simulator.c (do_vec_MLA): Rewrite switch body.
   4
   5         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
   6         2.  Move test_false if inside loop.  Fix logic for computing result
   7         stored to vd.
   8
   9         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
  10         (do_vec_LDn_single, do_vec_STn_single): New.
  11         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
  12         loop over nregs using new var n.  Add n times size to address in loop.
  13         Add n to vd in loop.
  14         (do_vec_load_store): Add comment for instruction bit 24.  New var
  15         single to hold instruction bit 24.  Add new code to use single.  Move
  16         ldnr support inside single if statements.  Fix ldnr register counts
  17         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
  18
  19 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
  20
  21         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
  22
  23 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
  24
  25         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
  26         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
  27         case 3, call HALT_UNALLOC unconditionally.
  28         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
  29         i + 2.  Delete if on bias, change index to i + bias * X.
  30
  31 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
  32
  33         * simulator.c (do_vec_UZP): Rewrite.
  34
  35 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
  36
  37         * cpustate.c: Include math.h.
  38         (aarch64_set_FP_float): Use signbit to check for signed zero.
  39         (aarch64_set_FP_double): Likewise.
  40         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
  41         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
  42         args same size as third arg.
  43         (fmaxnm): Use isnan instead of fpclassify.
  44         (fminnm, dmaxnm, dminnm): Likewise.
  45         (do_vec_MLS): Reverse order of subtraction operands.
  46         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
  47         aarch64_get_FP_float to get source register contents.
  48         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
  49         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
  50         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
  51         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
  52         raise_exception calls.
  53
  54 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
  55
  56         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
  57         Add comment to document NaN issue.
  58         (set_flags_for_double_compare): Likewise.
  59
  60 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
  61
  62         * simulator.c (NEG, POS): Move before set_flags_for_add64.
  63         (set_flags_for_add64): Replace with a modified copy of
  64         set_flags_for_sub64.
  65
  66 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
  67
  68         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
  69         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
  70
  71 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
  72
  73         * simulator.c (fsturs): Switch use of rn and st variables.
  74         (fsturd, fsturq): Likewise
  75
  76 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
  77
  78         * interp.c: Include bfd.h.
  79         (symcount, symtab, aarch64_get_sym_value): Delete.
  80         (remove_useless_symbols): Change count type to long.
  81         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
  82         and symtab local variables.
  83         (sim_create_inferior): Delete storage.  Replace symbol code
  84         with a call to trace_load_symbols.
  85         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
  86         includes.
  87         (aarch64_get_heap_start): Change aarch64_get_sym_value to
  88         trace_sym_value.
  89         * memory.h: Delete bfd.h include.
  90         (mem_add_blk): Delete unused prototype.
  91         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
  92         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
  93         (aarch64_get_sym_value): Delete.
  94
  95 2016-08-12  Nick Clifton  <nickc@redhat.com>
  96
  97         * simulator.c (aarch64_step): Revert pervious delta.
  98         (aarch64_run): Call sim_events_tick after each
  99         instruction is simulated, and if necessary call
 100         sim_events_process.
 101         * simulator.h: Revert previous delta.
 102
 103 2016-08-11  Nick Clifton  <nickc@redhat.com>
 104
 105         * interp.c (sim_create_inferior): Allow for being called with a
 106         NULL abfd parameter.  If a bfd is provided, initialise the sim
 107         with that start address.
 108         * simulator.c (HALT_NYI): Just print out the numeric value of the
 109         instruction when not tracing.
 110         (aarch64_step): Change from static to global.
 111         * simulator.h: Add a prototype for aarch64_step().
 112
 113 2016-07-27  Alan Modra  <amodra@gmail.com>
 114
 115         * memory.c: Don't include libbfd.h.
 116
 117 2016-07-21  Nick Clifton  <nickc@redhat.com>
 118
 119         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 120
 121 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 122
 123         * cpustate.h: Include config.h.
 124         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 125         use anonymous structs to align members.
 126         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 127         endian_le2h_4 to read instruction from pc.
 128
 129 2016-05-06  Nick Clifton  <nickc@redhat.com>
 130
 131         * simulator.c (do_FMLA_by_element): New function.
 132         (do_vec_op2): Call it.
 133
 134 2016-04-27  Nick Clifton  <nickc@redhat.com>
 135
 136         * simulator.c: Add TRACE_DECODE statements to all emulation
 137         functions.
 138
 139 2016-03-30  Nick Clifton  <nickc@redhat.com>
 140
 141         * cpustate.c (aarch64_set_reg_s32): New function.
 142         (aarch64_set_reg_u32): New function.
 143         (aarch64_get_FP_half): Place half precision value into the correct
 144         slot of the union.
 145         (aarch64_set_FP_half): Likewise.
 146         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 147         aarch64_set_reg_u32.
 148         * memory.c (FETCH_FUNC): Cast the read value to the access type
 149         before converting it to the return type.  Rename to FETCH_FUNC64.
 150         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 151         accesses.  Use for 32-bit memory access functions.
 152         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 153         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 154         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 155         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 156         (ldrh32_abs): Store 32 bit value not 64-bits.
 157         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 158         (do_vec_MOV_immediate): Fix computation of val.
 159         (do_vec_MVNI): Likewise.
 160         (DO_VEC_WIDENING_MUL): New macro.
 161         (do_vec_mull): Use new macro.
 162         (do_vec_mul): Use new macro.
 163         (do_vec_MLA): Read values before writing.
 164         (do_vec_xtl): Likewise.
 165         (do_vec_SSHL): Select correct shift value.
 166         (do_vec_USHL): Likewise.
 167         (do_scalar_UCVTF): New function.
 168         (do_scalar_vec): Call new function.
 169         (store_pair_u64): Treat reads of SP as reads of XZR.
 170
 171 2016-03-29  Nick Clifton  <nickc@redhat.com>
 172
 173         * cpustate.c: Remove space after asterisk in function parameters.
 174         * decode.h (greg): Delete unused function.
 175         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 176         * simulator.c: Use INSTR macro in more places.
 177         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 178         Remove extraneous whitespace.
 179
 180 2016-03-23  Nick Clifton  <nickc@redhat.com>
 181
 182         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 183         register as a half precision floating point number.
 184         (aarch64_set_FP_half): New function.  Similar, but for setting
 185         a half precision register.
 186         (aarch64_get_thread_id): New function.  Returns the value of the
 187         CPU's TPIDR register.
 188         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 189         floating point control register.
 190         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 191         register.
 192         * cpustate.h: Add prototypes for new functions.
 193         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 194         * memory.c: Use unaligned core access functions for all memory
 195         reads and writes.
 196         * simulator.c (HALT_NYI): Generate an error message if tracing
 197         will not tell the user why the simulator is halting.
 198         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 199         (INSTR): New time-saver macro.
 200         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 201         offset.
 202         (fldrh_abs): New function.  Likewise for 16-bit values.
 203         (do_vec_SSHL): Allow for negative shift values.
 204         (do_vec_USHL): Likewise.
 205         (do_vec_SHL): Correct computation of shift amount.
 206         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 207         shifts and computation of shift value.
 208         (clz): New function.  Counts leading zero bits.
 209         (do_vec_CLZ): New function.  Implements CLZ (vector).
 210         (do_vec_MOV_element): Call do_vec_CLZ.
 211         (dexSimpleFPCondCompare): Implement.
 212         (do_FCVT_half_to_single): New function.  Implements one of the
 213         FCVT operations.
 214         (do_FCVT_half_to_double): New function.  Likewise.
 215         (do_FCVT_single_to_half): New function.  Likewise.
 216         (do_FCVT_double_to_half): New function.  Likewise.
 217         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 218         (do_scalar_SHL): Handle negative shifts.
 219         (do_scalar_shift): Handle SSHR.
 220         (do_scalar_USHL): New function.
 221         (do_double_add): Simplify to just performing a double precision
 222         add operation.  Move remaining code into...
 223         (do_scalar_vec): ... New function.
 224         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 225         functions.
 226         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 227         registers.
 228         (system_set): New function.
 229         (do_MSR_immediate): New function.  Stub for now.
 230         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 231         instruction.
 232         (do_SYS): New function.  Stub for now,
 233         (dexSystem): Call new functions.
 234
 235 2016-03-18  Nick Clifton  <nickc@redhat.com>
 236
 237         * cpustate.c: Remove spurious spaces from TRACE strings.
 238         Print hex equivalents of floats and doubles.
 239         Check element number against array size when accessing vector
 240         registers.
 241         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 242         element index.
 243         (SET_VEC_ELEMENT): Likewise.
 244         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 245
 246         * memory.c: Trace memory reads when --trace-memory is enabled.
 247         Remove float and double load and store functions.
 248         * memory.h (aarch64_get_mem_float): Delete prototype.
 249         (aarch64_get_mem_double): Likewise.
 250         (aarch64_set_mem_float): Likewise.
 251         (aarch64_set_mem_double): Likewise.
 252         * simulator (IS_SET): Always return either 0 or 1.
 253         (IS_CLEAR): Likewise.
 254         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 255         and doubles using 64-bit memory accesses.
 256         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 257         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 258         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 259         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 260         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 261         (do_vec_MUL_by_element): New function.
 262         (do_vec_op2): Call do_vec_MUL_by_element.
 263         (do_scalar_NEG): New function.
 264         (do_double_add): Call do_scalar_NEG.
 265
 266 2016-03-03  Nick Clifton  <nickc@redhat.com>
 267
 268         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 269         (CondCompare): Swap interpretation of bit 30.
 270         (DO_ADDP): Delete macro.
 271         (do_vec_ADDP): Copy source registers before starting to update
 272         destination register.
 273         (do_vec_FADDP): Likewise.
 274         (do_vec_load_store): Fix computation of sizeof_operation.
 275         (rbit64): Fix type of constant.
 276         (aarch64_step): When displaying insn value, display all 32 bits.
 277
 278 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 279
 280         * config.in, configure: Regenerate.
 281
 282 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 283
 284         * configure: Regenerate.
 285
 286 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 287
 288         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 289         * configure: Regenerate.
 290
 291 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 292
 293         * configure: Regenerate.
 294
 295 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 296
 297         * configure: Regenerate.
 298
 299 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 300
 301         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 302         * configure: Regenerate.
 303
 304 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 305
 306         * configure: Regenerate.
 307
 308 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 309
 310         * configure: Regenerate.
 311
 312 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 313
 314         * config.in, configure: Regenerate.
 315
 316 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 317
 318         * interp.c (sim_create_inferior): Mark argv and env const.
 319         (sim_open): Mark argv const.
 320
 321 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 322
 323         * interp.c: Delete dis-asm.h include.
 324         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 325         (sim_create_inferior): Delete disassemble init logic.
 326         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 327         (sim_open): Delete sim_add_option_table call.
 328         * memory.c (mem_error): Delete disas check.
 329         * simulator.c: Delete dis-asm.h include.
 330         (disas): Delete.
 331         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 332         (HALT_NYI): Likewise.
 333         (handle_halt): Delete disas call.
 334         (aarch64_step): Replace disas logic with TRACE_DISASM.
 335         * simulator.h: Delete dis-asm.h include.
 336         (aarch64_print_insn): Delete.
 337
 338 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 339
 340         * simulator.c (MAX, MIN): Delete.
 341         (do_vec_maxv): Change MAX to max and MIN to min.
 342         (do_vec_fminmaxV): Likewise.
 343
 344 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 345
 346         * simulator.c: Remove syscall.h include.
 347
 348 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 349
 350         * configure: Regenerate.
 351
 352 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 353
 354         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 355         * configure: Regenerate.
 356
 357 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 358
 359         * configure: Regenerate.
 360
 361 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 362
 363         * interp.c (sim_dis_read): Change private_data to application_data.
 364         (sim_create_inferior): Likewise.
 365
 366 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 367
 368         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 369
 370 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 371
 372         * config.in, configure: Regenerate.
 373
 374 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 375
 376         * interp.c (sim_create_inferior): Update comment and argv check.
 377
 378 2015-12-14  Nick Clifton  <nickc@redhat.com>
 379
 380         * simulator.c (system_get): New function.  Provides read
 381         access to the dczid system register.
 382         (do_mrs): New function - implements the MRS instruction.
 383         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 384         unimplemented system instructions.
 385
 386 2015-11-24  Nick Clifton  <nickc@redhat.com>
 387
 388         * configure.ac: New configure template.
 389         * aclocal.m4: Generate.
 390         * config.in: Generate.
 391         * configure: Generate.
 392         * cpustate.c: New file - functions for accessing AArch64 registers.
 393         * cpustate.h: New header.
 394         * decode.h: New header.
 395         * interp.c: New file - interface between GDB and simulator.
 396         * Makefile.in: New makefile template.
 397         * memory.c: New file - functions for simulating aarch64 memory
 398         accesses.
 399         * memory.h: New header.
 400         * sim-main.h: New header.
 401         * simulator.c: New file - aarch64 simulator functions.
 402         * simulator.h: New header.