sim/aarch64/ChangeLog

   1 2016-04-27  Nick Clifton  <nickc@redhat.com>
   2
   3         * simulator.c: Add TRACE_DECODE statements to all emulation
   4         functions.
   5
   6 2016-03-30  Nick Clifton  <nickc@redhat.com>
   7
   8         * cpustate.c (aarch64_set_reg_s32): New function.
   9         (aarch64_set_reg_u32): New function.
  10         (aarch64_get_FP_half): Place half precision value into the correct
  11         slot of the union.
  12         (aarch64_set_FP_half): Likewise.
  13         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
  14         aarch64_set_reg_u32.
  15         * memory.c (FETCH_FUNC): Cast the read value to the access type
  16         before converting it to the return type.  Rename to FETCH_FUNC64.
  17         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
  18         accesses.  Use for 32-bit memory access functions.
  19         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
  20         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
  21         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
  22         (ldrsh_scale_ext, ldrsw_abs): Likewise.
  23         (ldrh32_abs): Store 32 bit value not 64-bits.
  24         (ldrh32_wb, ldrh32_scale_ext): Likewise.
  25         (do_vec_MOV_immediate): Fix computation of val.
  26         (do_vec_MVNI): Likewise.
  27         (DO_VEC_WIDENING_MUL): New macro.
  28         (do_vec_mull): Use new macro.
  29         (do_vec_mul): Use new macro.
  30         (do_vec_MLA): Read values before writing.
  31         (do_vec_xtl): Likewise.
  32         (do_vec_SSHL): Select correct shift value.
  33         (do_vec_USHL): Likewise.
  34         (do_scalar_UCVTF): New function.
  35         (do_scalar_vec): Call new function.
  36         (store_pair_u64): Treat reads of SP as reads of XZR.
  37
  38 2016-03-29  Nick Clifton  <nickc@redhat.com>
  39
  40         * cpustate.c: Remove space after asterisk in function parameters.
  41         * decode.h (greg): Delete unused function.
  42         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
  43         * simulator.c: Use INSTR macro in more places.
  44         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
  45         Remove extraneous whitespace.
  46
  47 2016-03-23  Nick Clifton  <nickc@redhat.com>
  48
  49         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
  50         register as a half precision floating point number.
  51         (aarch64_set_FP_half): New function.  Similar, but for setting
  52         a half precision register.
  53         (aarch64_get_thread_id): New function.  Returns the value of the
  54         CPU's TPIDR register.
  55         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
  56         floating point control register.
  57         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
  58         register.
  59         * cpustate.h: Add prototypes for new functions.
  60         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
  61         * memory.c: Use unaligned core access functions for all memory
  62         reads and writes.
  63         * simulator.c (HALT_NYI): Generate an error message if tracing
  64         will not tell the user why the simulator is halting.
  65         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
  66         (INSTR): New time-saver macro.
  67         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
  68         offset.
  69         (fldrh_abs): New function.  Likewise for 16-bit values.
  70         (do_vec_SSHL): Allow for negative shift values.
  71         (do_vec_USHL): Likewise.
  72         (do_vec_SHL): Correct computation of shift amount.
  73         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
  74         shifts and computation of shift value.
  75         (clz): New function.  Counts leading zero bits.
  76         (do_vec_CLZ): New function.  Implements CLZ (vector).
  77         (do_vec_MOV_element): Call do_vec_CLZ.
  78         (dexSimpleFPCondCompare): Implement.
  79         (do_FCVT_half_to_single): New function.  Implements one of the
  80         FCVT operations.
  81         (do_FCVT_half_to_double): New function.  Likewise.
  82         (do_FCVT_single_to_half): New function.  Likewise.
  83         (do_FCVT_double_to_half): New function.  Likewise.
  84         (dexSimpleFPDataProc1Source): Call new FCVT functions.
  85         (do_scalar_SHL): Handle negative shifts.
  86         (do_scalar_shift): Handle SSHR.
  87         (do_scalar_USHL): New function.
  88         (do_double_add): Simplify to just performing a double precision
  89         add operation.  Move remaining code into...
  90         (do_scalar_vec): ... New function.
  91         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
  92         functions.
  93         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
  94         registers.
  95         (system_set): New function.
  96         (do_MSR_immediate): New function.  Stub for now.
  97         (do_MSR_reg): New function.  Likewise. Partially implements MSR
  98         instruction.
  99         (do_SYS): New function.  Stub for now,
 100         (dexSystem): Call new functions.
 101
 102 2016-03-18  Nick Clifton  <nickc@redhat.com>
 103
 104         * cpustate.c: Remove spurious spaces from TRACE strings.
 105         Print hex equivalents of floats and doubles.
 106         Check element number against array size when accessing vector
 107         registers.
 108         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 109         element index.
 110         (SET_VEC_ELEMENT): Likewise.
 111         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 112
 113         * memory.c: Trace memory reads when --trace-memory is enabled.
 114         Remove float and double load and store functions.
 115         * memory.h (aarch64_get_mem_float): Delete prototype.
 116         (aarch64_get_mem_double): Likewise.
 117         (aarch64_set_mem_float): Likewise.
 118         (aarch64_set_mem_double): Likewise.
 119         * simulator (IS_SET): Always return either 0 or 1.
 120         (IS_CLEAR): Likewise.
 121         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 122         and doubles using 64-bit memory accesses.
 123         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 124         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 125         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 126         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 127         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 128         (do_vec_MUL_by_element): New function.
 129         (do_vec_op2): Call do_vec_MUL_by_element.
 130         (do_scalar_NEG): New function.
 131         (do_double_add): Call do_scalar_NEG.
 132
 133 2016-03-03  Nick Clifton  <nickc@redhat.com>
 134
 135         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 136         (CondCompare): Swap interpretation of bit 30.
 137         (DO_ADDP): Delete macro.
 138         (do_vec_ADDP): Copy source registers before starting to update
 139         destination register.
 140         (do_vec_FADDP): Likewise.
 141         (do_vec_load_store): Fix computation of sizeof_operation.
 142         (rbit64): Fix type of constant.
 143         (aarch64_step): When displaying insn value, display all 32 bits.
 144
 145 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 146
 147         * config.in, configure: Regenerate.
 148
 149 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 150
 151         * configure: Regenerate.
 152
 153 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 154
 155         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 156         * configure: Regenerate.
 157
 158 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 159
 160         * configure: Regenerate.
 161
 162 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 163
 164         * configure: Regenerate.
 165
 166 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 167
 168         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 169         * configure: Regenerate.
 170
 171 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 172
 173         * configure: Regenerate.
 174
 175 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 176
 177         * configure: Regenerate.
 178
 179 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 180
 181         * config.in, configure: Regenerate.
 182
 183 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 184
 185         * interp.c (sim_create_inferior): Mark argv and env const.
 186         (sim_open): Mark argv const.
 187
 188 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 189
 190         * interp.c: Delete dis-asm.h include.
 191         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 192         (sim_create_inferior): Delete disassemble init logic.
 193         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 194         (sim_open): Delete sim_add_option_table call.
 195         * memory.c (mem_error): Delete disas check.
 196         * simulator.c: Delete dis-asm.h include.
 197         (disas): Delete.
 198         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 199         (HALT_NYI): Likewise.
 200         (handle_halt): Delete disas call.
 201         (aarch64_step): Replace disas logic with TRACE_DISASM.
 202         * simulator.h: Delete dis-asm.h include.
 203         (aarch64_print_insn): Delete.
 204
 205 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 206
 207         * simulator.c (MAX, MIN): Delete.
 208         (do_vec_maxv): Change MAX to max and MIN to min.
 209         (do_vec_fminmaxV): Likewise.
 210
 211 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 212
 213         * simulator.c: Remove syscall.h include.
 214
 215 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 216
 217         * configure: Regenerate.
 218
 219 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 220
 221         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 222         * configure: Regenerate.
 223
 224 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 225
 226         * configure: Regenerate.
 227
 228 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 229
 230         * interp.c (sim_dis_read): Change private_data to application_data.
 231         (sim_create_inferior): Likewise.
 232
 233 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 234
 235         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 236
 237 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 238
 239         * config.in, configure: Regenerate.
 240
 241 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 242
 243         * interp.c (sim_create_inferior): Update comment and argv check.
 244
 245 2015-12-14  Nick Clifton  <nickc@redhat.com>
 246
 247         * simulator.c (system_get): New function.  Provides read
 248         access to the dczid system register.
 249         (do_mrs): New function - implements the MRS instruction.
 250         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 251         unimplemented system instructions.
 252
 253 2015-11-24  Nick Clifton  <nickc@redhat.com>
 254
 255         * configure.ac: New configure template.
 256         * aclocal.m4: Generate.
 257         * config.in: Generate.
 258         * configure: Generate.
 259         * cpustate.c: New file - functions for accessing AArch64 registers.
 260         * cpustate.h: New header.
 261         * decode.h: New header.
 262         * interp.c: New file - interface between GDB and simulator.
 263         * Makefile.in: New makefile template.
 264         * memory.c: New file - functions for simulating aarch64 memory
 265         accesses.
 266         * memory.h: New header.
 267         * sim-main.h: New header.
 268         * simulator.c: New file - aarch64 simulator functions.
 269         * simulator.h: New header.