sim/aarch64/ChangeLog

   1 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
   2
   3         * configure: Regenerate.
   4
   5 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
   6
   7         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
   8         registers based on structure size.
   9         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
  10         (LD1_1): Replace with call to vec_load.
  11         (vec_store): Add new M argument.  Rewrite to iterate over registers
  12         based on structure size.
  13         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
  14         (ST1_1): Replace with call to vec_store.
  15
  16 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
  17
  18         * simulator.c (do_vec_FCVTL): New.
  19         (do_vec_op1): Call do_vec_FCVTL.
  20
  21         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
  22         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
  23         (do_scalar_vec): Add calls to new functions.
  24
  25 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
  26
  27         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
  28         flag check.
  29
  30 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
  31
  32         * simulator.c (mul64hi): Shift carry left by 32.
  33         (smulh): Change signum to negate.  If negate, invert result, and add
  34         carry bit if low part of multiply result is zero.
  35
  36 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
  37
  38         * simulator.c (do_vec_SMOV_into_scalar): New.
  39         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
  40         Rewritten.
  41         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
  42         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
  43         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
  44         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
  45
  46         * simulator.c (popcount): New.
  47         (do_vec_CNT): New.
  48         (do_vec_op1): Add do_vec_CNT call.
  49
  50 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
  51
  52         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
  53         with type set to input type size.
  54         (do_vec_xtl): Change bias from 3 to 4 for byte case.
  55
  56 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
  57
  58         * simulator.c (do_vec_MLA): Rewrite switch body.
  59
  60         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
  61         2.  Move test_false if inside loop.  Fix logic for computing result
  62         stored to vd.
  63
  64         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
  65         (do_vec_LDn_single, do_vec_STn_single): New.
  66         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
  67         loop over nregs using new var n.  Add n times size to address in loop.
  68         Add n to vd in loop.
  69         (do_vec_load_store): Add comment for instruction bit 24.  New var
  70         single to hold instruction bit 24.  Add new code to use single.  Move
  71         ldnr support inside single if statements.  Fix ldnr register counts
  72         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
  73
  74 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
  75
  76         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
  77
  78 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
  79
  80         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
  81         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
  82         case 3, call HALT_UNALLOC unconditionally.
  83         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
  84         i + 2.  Delete if on bias, change index to i + bias * X.
  85
  86 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
  87
  88         * simulator.c (do_vec_UZP): Rewrite.
  89
  90 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
  91
  92         * cpustate.c: Include math.h.
  93         (aarch64_set_FP_float): Use signbit to check for signed zero.
  94         (aarch64_set_FP_double): Likewise.
  95         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
  96         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
  97         args same size as third arg.
  98         (fmaxnm): Use isnan instead of fpclassify.
  99         (fminnm, dmaxnm, dminnm): Likewise.
 100         (do_vec_MLS): Reverse order of subtraction operands.
 101         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
 102         aarch64_get_FP_float to get source register contents.
 103         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 104         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 105         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 106         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 107         raise_exception calls.
 108
 109 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 110
 111         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 112         Add comment to document NaN issue.
 113         (set_flags_for_double_compare): Likewise.
 114
 115 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 116
 117         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 118         (set_flags_for_add64): Replace with a modified copy of
 119         set_flags_for_sub64.
 120
 121 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 122
 123         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 124         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 125
 126 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 127
 128         * simulator.c (fsturs): Switch use of rn and st variables.
 129         (fsturd, fsturq): Likewise
 130
 131 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 132
 133         * interp.c: Include bfd.h.
 134         (symcount, symtab, aarch64_get_sym_value): Delete.
 135         (remove_useless_symbols): Change count type to long.
 136         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 137         and symtab local variables.
 138         (sim_create_inferior): Delete storage.  Replace symbol code
 139         with a call to trace_load_symbols.
 140         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 141         includes.
 142         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 143         trace_sym_value.
 144         * memory.h: Delete bfd.h include.
 145         (mem_add_blk): Delete unused prototype.
 146         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 147         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 148         (aarch64_get_sym_value): Delete.
 149
 150 2016-08-12  Nick Clifton  <nickc@redhat.com>
 151
 152         * simulator.c (aarch64_step): Revert pervious delta.
 153         (aarch64_run): Call sim_events_tick after each
 154         instruction is simulated, and if necessary call
 155         sim_events_process.
 156         * simulator.h: Revert previous delta.
 157
 158 2016-08-11  Nick Clifton  <nickc@redhat.com>
 159
 160         * interp.c (sim_create_inferior): Allow for being called with a
 161         NULL abfd parameter.  If a bfd is provided, initialise the sim
 162         with that start address.
 163         * simulator.c (HALT_NYI): Just print out the numeric value of the
 164         instruction when not tracing.
 165         (aarch64_step): Change from static to global.
 166         * simulator.h: Add a prototype for aarch64_step().
 167
 168 2016-07-27  Alan Modra  <amodra@gmail.com>
 169
 170         * memory.c: Don't include libbfd.h.
 171
 172 2016-07-21  Nick Clifton  <nickc@redhat.com>
 173
 174         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 175
 176 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 177
 178         * cpustate.h: Include config.h.
 179         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 180         use anonymous structs to align members.
 181         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 182         endian_le2h_4 to read instruction from pc.
 183
 184 2016-05-06  Nick Clifton  <nickc@redhat.com>
 185
 186         * simulator.c (do_FMLA_by_element): New function.
 187         (do_vec_op2): Call it.
 188
 189 2016-04-27  Nick Clifton  <nickc@redhat.com>
 190
 191         * simulator.c: Add TRACE_DECODE statements to all emulation
 192         functions.
 193
 194 2016-03-30  Nick Clifton  <nickc@redhat.com>
 195
 196         * cpustate.c (aarch64_set_reg_s32): New function.
 197         (aarch64_set_reg_u32): New function.
 198         (aarch64_get_FP_half): Place half precision value into the correct
 199         slot of the union.
 200         (aarch64_set_FP_half): Likewise.
 201         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 202         aarch64_set_reg_u32.
 203         * memory.c (FETCH_FUNC): Cast the read value to the access type
 204         before converting it to the return type.  Rename to FETCH_FUNC64.
 205         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 206         accesses.  Use for 32-bit memory access functions.
 207         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 208         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 209         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 210         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 211         (ldrh32_abs): Store 32 bit value not 64-bits.
 212         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 213         (do_vec_MOV_immediate): Fix computation of val.
 214         (do_vec_MVNI): Likewise.
 215         (DO_VEC_WIDENING_MUL): New macro.
 216         (do_vec_mull): Use new macro.
 217         (do_vec_mul): Use new macro.
 218         (do_vec_MLA): Read values before writing.
 219         (do_vec_xtl): Likewise.
 220         (do_vec_SSHL): Select correct shift value.
 221         (do_vec_USHL): Likewise.
 222         (do_scalar_UCVTF): New function.
 223         (do_scalar_vec): Call new function.
 224         (store_pair_u64): Treat reads of SP as reads of XZR.
 225
 226 2016-03-29  Nick Clifton  <nickc@redhat.com>
 227
 228         * cpustate.c: Remove space after asterisk in function parameters.
 229         * decode.h (greg): Delete unused function.
 230         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 231         * simulator.c: Use INSTR macro in more places.
 232         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 233         Remove extraneous whitespace.
 234
 235 2016-03-23  Nick Clifton  <nickc@redhat.com>
 236
 237         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 238         register as a half precision floating point number.
 239         (aarch64_set_FP_half): New function.  Similar, but for setting
 240         a half precision register.
 241         (aarch64_get_thread_id): New function.  Returns the value of the
 242         CPU's TPIDR register.
 243         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 244         floating point control register.
 245         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 246         register.
 247         * cpustate.h: Add prototypes for new functions.
 248         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 249         * memory.c: Use unaligned core access functions for all memory
 250         reads and writes.
 251         * simulator.c (HALT_NYI): Generate an error message if tracing
 252         will not tell the user why the simulator is halting.
 253         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 254         (INSTR): New time-saver macro.
 255         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 256         offset.
 257         (fldrh_abs): New function.  Likewise for 16-bit values.
 258         (do_vec_SSHL): Allow for negative shift values.
 259         (do_vec_USHL): Likewise.
 260         (do_vec_SHL): Correct computation of shift amount.
 261         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 262         shifts and computation of shift value.
 263         (clz): New function.  Counts leading zero bits.
 264         (do_vec_CLZ): New function.  Implements CLZ (vector).
 265         (do_vec_MOV_element): Call do_vec_CLZ.
 266         (dexSimpleFPCondCompare): Implement.
 267         (do_FCVT_half_to_single): New function.  Implements one of the
 268         FCVT operations.
 269         (do_FCVT_half_to_double): New function.  Likewise.
 270         (do_FCVT_single_to_half): New function.  Likewise.
 271         (do_FCVT_double_to_half): New function.  Likewise.
 272         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 273         (do_scalar_SHL): Handle negative shifts.
 274         (do_scalar_shift): Handle SSHR.
 275         (do_scalar_USHL): New function.
 276         (do_double_add): Simplify to just performing a double precision
 277         add operation.  Move remaining code into...
 278         (do_scalar_vec): ... New function.
 279         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 280         functions.
 281         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 282         registers.
 283         (system_set): New function.
 284         (do_MSR_immediate): New function.  Stub for now.
 285         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 286         instruction.
 287         (do_SYS): New function.  Stub for now,
 288         (dexSystem): Call new functions.
 289
 290 2016-03-18  Nick Clifton  <nickc@redhat.com>
 291
 292         * cpustate.c: Remove spurious spaces from TRACE strings.
 293         Print hex equivalents of floats and doubles.
 294         Check element number against array size when accessing vector
 295         registers.
 296         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 297         element index.
 298         (SET_VEC_ELEMENT): Likewise.
 299         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 300
 301         * memory.c: Trace memory reads when --trace-memory is enabled.
 302         Remove float and double load and store functions.
 303         * memory.h (aarch64_get_mem_float): Delete prototype.
 304         (aarch64_get_mem_double): Likewise.
 305         (aarch64_set_mem_float): Likewise.
 306         (aarch64_set_mem_double): Likewise.
 307         * simulator (IS_SET): Always return either 0 or 1.
 308         (IS_CLEAR): Likewise.
 309         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 310         and doubles using 64-bit memory accesses.
 311         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 312         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 313         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 314         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 315         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 316         (do_vec_MUL_by_element): New function.
 317         (do_vec_op2): Call do_vec_MUL_by_element.
 318         (do_scalar_NEG): New function.
 319         (do_double_add): Call do_scalar_NEG.
 320
 321 2016-03-03  Nick Clifton  <nickc@redhat.com>
 322
 323         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 324         (CondCompare): Swap interpretation of bit 30.
 325         (DO_ADDP): Delete macro.
 326         (do_vec_ADDP): Copy source registers before starting to update
 327         destination register.
 328         (do_vec_FADDP): Likewise.
 329         (do_vec_load_store): Fix computation of sizeof_operation.
 330         (rbit64): Fix type of constant.
 331         (aarch64_step): When displaying insn value, display all 32 bits.
 332
 333 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 334
 335         * config.in, configure: Regenerate.
 336
 337 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 338
 339         * configure: Regenerate.
 340
 341 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 342
 343         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 344         * configure: Regenerate.
 345
 346 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 347
 348         * configure: Regenerate.
 349
 350 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 351
 352         * configure: Regenerate.
 353
 354 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 355
 356         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 357         * configure: Regenerate.
 358
 359 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 360
 361         * configure: Regenerate.
 362
 363 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 364
 365         * configure: Regenerate.
 366
 367 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 368
 369         * config.in, configure: Regenerate.
 370
 371 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 372
 373         * interp.c (sim_create_inferior): Mark argv and env const.
 374         (sim_open): Mark argv const.
 375
 376 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 377
 378         * interp.c: Delete dis-asm.h include.
 379         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 380         (sim_create_inferior): Delete disassemble init logic.
 381         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 382         (sim_open): Delete sim_add_option_table call.
 383         * memory.c (mem_error): Delete disas check.
 384         * simulator.c: Delete dis-asm.h include.
 385         (disas): Delete.
 386         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 387         (HALT_NYI): Likewise.
 388         (handle_halt): Delete disas call.
 389         (aarch64_step): Replace disas logic with TRACE_DISASM.
 390         * simulator.h: Delete dis-asm.h include.
 391         (aarch64_print_insn): Delete.
 392
 393 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 394
 395         * simulator.c (MAX, MIN): Delete.
 396         (do_vec_maxv): Change MAX to max and MIN to min.
 397         (do_vec_fminmaxV): Likewise.
 398
 399 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 400
 401         * simulator.c: Remove syscall.h include.
 402
 403 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 404
 405         * configure: Regenerate.
 406
 407 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 408
 409         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 410         * configure: Regenerate.
 411
 412 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 413
 414         * configure: Regenerate.
 415
 416 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 417
 418         * interp.c (sim_dis_read): Change private_data to application_data.
 419         (sim_create_inferior): Likewise.
 420
 421 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 422
 423         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 424
 425 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 426
 427         * config.in, configure: Regenerate.
 428
 429 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 430
 431         * interp.c (sim_create_inferior): Update comment and argv check.
 432
 433 2015-12-14  Nick Clifton  <nickc@redhat.com>
 434
 435         * simulator.c (system_get): New function.  Provides read
 436         access to the dczid system register.
 437         (do_mrs): New function - implements the MRS instruction.
 438         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 439         unimplemented system instructions.
 440
 441 2015-11-24  Nick Clifton  <nickc@redhat.com>
 442
 443         * configure.ac: New configure template.
 444         * aclocal.m4: Generate.
 445         * config.in: Generate.
 446         * configure: Generate.
 447         * cpustate.c: New file - functions for accessing AArch64 registers.
 448         * cpustate.h: New header.
 449         * decode.h: New header.
 450         * interp.c: New file - interface between GDB and simulator.
 451         * Makefile.in: New makefile template.
 452         * memory.c: New file - functions for simulating aarch64 memory
 453         accesses.
 454         * memory.h: New header.
 455         * sim-main.h: New header.
 456         * simulator.c: New file - aarch64 simulator functions.
 457         * simulator.h: New header.