sim/aarch64/ChangeLog

   1 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
   2
   3         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
   4         Add comment to document NaN issue.
   5         (set_flags_for_double_compare): Likewise.
   6
   7 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
   8
   9         * simulator.c (NEG, POS): Move before set_flags_for_add64.
  10         (set_flags_for_add64): Replace with a modified copy of
  11         set_flags_for_sub64.
  12
  13 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
  14
  15         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
  16         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
  17
  18 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
  19
  20         * simulator.c (fsturs): Switch use of rn and st variables.
  21         (fsturd, fsturq): Likewise
  22
  23 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
  24
  25         * interp.c: Include bfd.h.
  26         (symcount, symtab, aarch64_get_sym_value): Delete.
  27         (remove_useless_symbols): Change count type to long.
  28         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
  29         and symtab local variables.
  30         (sim_create_inferior): Delete storage.  Replace symbol code
  31         with a call to trace_load_symbols.
  32         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
  33         includes.
  34         (aarch64_get_heap_start): Change aarch64_get_sym_value to
  35         trace_sym_value.
  36         * memory.h: Delete bfd.h include.
  37         (mem_add_blk): Delete unused prototype.
  38         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
  39         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
  40         (aarch64_get_sym_value): Delete.
  41
  42 2016-08-12  Nick Clifton  <nickc@redhat.com>
  43
  44         * simulator.c (aarch64_step): Revert pervious delta.
  45         (aarch64_run): Call sim_events_tick after each
  46         instruction is simulated, and if necessary call
  47         sim_events_process.
  48         * simulator.h: Revert previous delta.
  49
  50 2016-08-11  Nick Clifton  <nickc@redhat.com>
  51
  52         * interp.c (sim_create_inferior): Allow for being called with a
  53         NULL abfd parameter.  If a bfd is provided, initialise the sim
  54         with that start address.
  55         * simulator.c (HALT_NYI): Just print out the numeric value of the
  56         instruction when not tracing.
  57         (aarch64_step): Change from static to global.
  58         * simulator.h: Add a prototype for aarch64_step().
  59
  60 2016-07-27  Alan Modra  <amodra@gmail.com>
  61
  62         * memory.c: Don't include libbfd.h.
  63
  64 2016-07-21  Nick Clifton  <nickc@redhat.com>
  65
  66         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
  67
  68 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
  69
  70         * cpustate.h: Include config.h.
  71         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
  72         use anonymous structs to align members.
  73         * simulator.c (aarch64_step): Use sim_core_read_buffer and
  74         endian_le2h_4 to read instruction from pc.
  75
  76 2016-05-06  Nick Clifton  <nickc@redhat.com>
  77
  78         * simulator.c (do_FMLA_by_element): New function.
  79         (do_vec_op2): Call it.
  80
  81 2016-04-27  Nick Clifton  <nickc@redhat.com>
  82
  83         * simulator.c: Add TRACE_DECODE statements to all emulation
  84         functions.
  85
  86 2016-03-30  Nick Clifton  <nickc@redhat.com>
  87
  88         * cpustate.c (aarch64_set_reg_s32): New function.
  89         (aarch64_set_reg_u32): New function.
  90         (aarch64_get_FP_half): Place half precision value into the correct
  91         slot of the union.
  92         (aarch64_set_FP_half): Likewise.
  93         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
  94         aarch64_set_reg_u32.
  95         * memory.c (FETCH_FUNC): Cast the read value to the access type
  96         before converting it to the return type.  Rename to FETCH_FUNC64.
  97         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
  98         accesses.  Use for 32-bit memory access functions.
  99         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 100         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 101         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 102         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 103         (ldrh32_abs): Store 32 bit value not 64-bits.
 104         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 105         (do_vec_MOV_immediate): Fix computation of val.
 106         (do_vec_MVNI): Likewise.
 107         (DO_VEC_WIDENING_MUL): New macro.
 108         (do_vec_mull): Use new macro.
 109         (do_vec_mul): Use new macro.
 110         (do_vec_MLA): Read values before writing.
 111         (do_vec_xtl): Likewise.
 112         (do_vec_SSHL): Select correct shift value.
 113         (do_vec_USHL): Likewise.
 114         (do_scalar_UCVTF): New function.
 115         (do_scalar_vec): Call new function.
 116         (store_pair_u64): Treat reads of SP as reads of XZR.
 117
 118 2016-03-29  Nick Clifton  <nickc@redhat.com>
 119
 120         * cpustate.c: Remove space after asterisk in function parameters.
 121         * decode.h (greg): Delete unused function.
 122         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 123         * simulator.c: Use INSTR macro in more places.
 124         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 125         Remove extraneous whitespace.
 126
 127 2016-03-23  Nick Clifton  <nickc@redhat.com>
 128
 129         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 130         register as a half precision floating point number.
 131         (aarch64_set_FP_half): New function.  Similar, but for setting
 132         a half precision register.
 133         (aarch64_get_thread_id): New function.  Returns the value of the
 134         CPU's TPIDR register.
 135         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 136         floating point control register.
 137         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 138         register.
 139         * cpustate.h: Add prototypes for new functions.
 140         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 141         * memory.c: Use unaligned core access functions for all memory
 142         reads and writes.
 143         * simulator.c (HALT_NYI): Generate an error message if tracing
 144         will not tell the user why the simulator is halting.
 145         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 146         (INSTR): New time-saver macro.
 147         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 148         offset.
 149         (fldrh_abs): New function.  Likewise for 16-bit values.
 150         (do_vec_SSHL): Allow for negative shift values.
 151         (do_vec_USHL): Likewise.
 152         (do_vec_SHL): Correct computation of shift amount.
 153         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 154         shifts and computation of shift value.
 155         (clz): New function.  Counts leading zero bits.
 156         (do_vec_CLZ): New function.  Implements CLZ (vector).
 157         (do_vec_MOV_element): Call do_vec_CLZ.
 158         (dexSimpleFPCondCompare): Implement.
 159         (do_FCVT_half_to_single): New function.  Implements one of the
 160         FCVT operations.
 161         (do_FCVT_half_to_double): New function.  Likewise.
 162         (do_FCVT_single_to_half): New function.  Likewise.
 163         (do_FCVT_double_to_half): New function.  Likewise.
 164         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 165         (do_scalar_SHL): Handle negative shifts.
 166         (do_scalar_shift): Handle SSHR.
 167         (do_scalar_USHL): New function.
 168         (do_double_add): Simplify to just performing a double precision
 169         add operation.  Move remaining code into...
 170         (do_scalar_vec): ... New function.
 171         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 172         functions.
 173         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 174         registers.
 175         (system_set): New function.
 176         (do_MSR_immediate): New function.  Stub for now.
 177         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 178         instruction.
 179         (do_SYS): New function.  Stub for now,
 180         (dexSystem): Call new functions.
 181
 182 2016-03-18  Nick Clifton  <nickc@redhat.com>
 183
 184         * cpustate.c: Remove spurious spaces from TRACE strings.
 185         Print hex equivalents of floats and doubles.
 186         Check element number against array size when accessing vector
 187         registers.
 188         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 189         element index.
 190         (SET_VEC_ELEMENT): Likewise.
 191         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 192
 193         * memory.c: Trace memory reads when --trace-memory is enabled.
 194         Remove float and double load and store functions.
 195         * memory.h (aarch64_get_mem_float): Delete prototype.
 196         (aarch64_get_mem_double): Likewise.
 197         (aarch64_set_mem_float): Likewise.
 198         (aarch64_set_mem_double): Likewise.
 199         * simulator (IS_SET): Always return either 0 or 1.
 200         (IS_CLEAR): Likewise.
 201         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 202         and doubles using 64-bit memory accesses.
 203         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 204         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 205         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 206         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 207         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 208         (do_vec_MUL_by_element): New function.
 209         (do_vec_op2): Call do_vec_MUL_by_element.
 210         (do_scalar_NEG): New function.
 211         (do_double_add): Call do_scalar_NEG.
 212
 213 2016-03-03  Nick Clifton  <nickc@redhat.com>
 214
 215         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 216         (CondCompare): Swap interpretation of bit 30.
 217         (DO_ADDP): Delete macro.
 218         (do_vec_ADDP): Copy source registers before starting to update
 219         destination register.
 220         (do_vec_FADDP): Likewise.
 221         (do_vec_load_store): Fix computation of sizeof_operation.
 222         (rbit64): Fix type of constant.
 223         (aarch64_step): When displaying insn value, display all 32 bits.
 224
 225 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 226
 227         * config.in, configure: Regenerate.
 228
 229 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 230
 231         * configure: Regenerate.
 232
 233 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 234
 235         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 236         * configure: Regenerate.
 237
 238 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 239
 240         * configure: Regenerate.
 241
 242 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 243
 244         * configure: Regenerate.
 245
 246 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 247
 248         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 249         * configure: Regenerate.
 250
 251 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 252
 253         * configure: Regenerate.
 254
 255 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 256
 257         * configure: Regenerate.
 258
 259 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 260
 261         * config.in, configure: Regenerate.
 262
 263 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 264
 265         * interp.c (sim_create_inferior): Mark argv and env const.
 266         (sim_open): Mark argv const.
 267
 268 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 269
 270         * interp.c: Delete dis-asm.h include.
 271         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 272         (sim_create_inferior): Delete disassemble init logic.
 273         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 274         (sim_open): Delete sim_add_option_table call.
 275         * memory.c (mem_error): Delete disas check.
 276         * simulator.c: Delete dis-asm.h include.
 277         (disas): Delete.
 278         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 279         (HALT_NYI): Likewise.
 280         (handle_halt): Delete disas call.
 281         (aarch64_step): Replace disas logic with TRACE_DISASM.
 282         * simulator.h: Delete dis-asm.h include.
 283         (aarch64_print_insn): Delete.
 284
 285 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 286
 287         * simulator.c (MAX, MIN): Delete.
 288         (do_vec_maxv): Change MAX to max and MIN to min.
 289         (do_vec_fminmaxV): Likewise.
 290
 291 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 292
 293         * simulator.c: Remove syscall.h include.
 294
 295 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 296
 297         * configure: Regenerate.
 298
 299 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 300
 301         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 302         * configure: Regenerate.
 303
 304 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 305
 306         * configure: Regenerate.
 307
 308 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 309
 310         * interp.c (sim_dis_read): Change private_data to application_data.
 311         (sim_create_inferior): Likewise.
 312
 313 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 314
 315         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 316
 317 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 318
 319         * config.in, configure: Regenerate.
 320
 321 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 322
 323         * interp.c (sim_create_inferior): Update comment and argv check.
 324
 325 2015-12-14  Nick Clifton  <nickc@redhat.com>
 326
 327         * simulator.c (system_get): New function.  Provides read
 328         access to the dczid system register.
 329         (do_mrs): New function - implements the MRS instruction.
 330         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 331         unimplemented system instructions.
 332
 333 2015-11-24  Nick Clifton  <nickc@redhat.com>
 334
 335         * configure.ac: New configure template.
 336         * aclocal.m4: Generate.
 337         * config.in: Generate.
 338         * configure: Generate.
 339         * cpustate.c: New file - functions for accessing AArch64 registers.
 340         * cpustate.h: New header.
 341         * decode.h: New header.
 342         * interp.c: New file - interface between GDB and simulator.
 343         * Makefile.in: New makefile template.
 344         * memory.c: New file - functions for simulating aarch64 memory
 345         accesses.
 346         * memory.h: New header.
 347         * sim-main.h: New header.
 348         * simulator.c: New file - aarch64 simulator functions.
 349         * simulator.h: New header.