sim/aarch64/ChangeLog

   1 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
   2
   3         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
   4         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
   5         (do_scalar_vec): Add calls to new functions.
   6
   7 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
   8
   9         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
  10         flag check.
  11
  12 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
  13
  14         * simulator.c (mul64hi): Shift carry left by 32.
  15         (smulh): Change signum to negate.  If negate, invert result, and add
  16         carry bit if low part of multiply result is zero.
  17
  18 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
  19
  20         * simulator.c (do_vec_SMOV_into_scalar): New.
  21         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
  22         Rewritten.
  23         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
  24         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
  25         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
  26         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
  27
  28         * simulator.c (popcount): New.
  29         (do_vec_CNT): New.
  30         (do_vec_op1): Add do_vec_CNT call.
  31
  32 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
  33
  34         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
  35         with type set to input type size.
  36         (do_vec_xtl): Change bias from 3 to 4 for byte case.
  37
  38 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
  39
  40         * simulator.c (do_vec_MLA): Rewrite switch body.
  41
  42         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
  43         2.  Move test_false if inside loop.  Fix logic for computing result
  44         stored to vd.
  45
  46         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
  47         (do_vec_LDn_single, do_vec_STn_single): New.
  48         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
  49         loop over nregs using new var n.  Add n times size to address in loop.
  50         Add n to vd in loop.
  51         (do_vec_load_store): Add comment for instruction bit 24.  New var
  52         single to hold instruction bit 24.  Add new code to use single.  Move
  53         ldnr support inside single if statements.  Fix ldnr register counts
  54         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
  55
  56 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
  57
  58         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
  59
  60 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
  61
  62         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
  63         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
  64         case 3, call HALT_UNALLOC unconditionally.
  65         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
  66         i + 2.  Delete if on bias, change index to i + bias * X.
  67
  68 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
  69
  70         * simulator.c (do_vec_UZP): Rewrite.
  71
  72 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
  73
  74         * cpustate.c: Include math.h.
  75         (aarch64_set_FP_float): Use signbit to check for signed zero.
  76         (aarch64_set_FP_double): Likewise.
  77         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
  78         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
  79         args same size as third arg.
  80         (fmaxnm): Use isnan instead of fpclassify.
  81         (fminnm, dmaxnm, dminnm): Likewise.
  82         (do_vec_MLS): Reverse order of subtraction operands.
  83         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
  84         aarch64_get_FP_float to get source register contents.
  85         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
  86         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
  87         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
  88         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
  89         raise_exception calls.
  90
  91 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
  92
  93         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
  94         Add comment to document NaN issue.
  95         (set_flags_for_double_compare): Likewise.
  96
  97 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
  98
  99         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 100         (set_flags_for_add64): Replace with a modified copy of
 101         set_flags_for_sub64.
 102
 103 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 104
 105         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 106         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 107
 108 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 109
 110         * simulator.c (fsturs): Switch use of rn and st variables.
 111         (fsturd, fsturq): Likewise
 112
 113 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 114
 115         * interp.c: Include bfd.h.
 116         (symcount, symtab, aarch64_get_sym_value): Delete.
 117         (remove_useless_symbols): Change count type to long.
 118         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 119         and symtab local variables.
 120         (sim_create_inferior): Delete storage.  Replace symbol code
 121         with a call to trace_load_symbols.
 122         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 123         includes.
 124         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 125         trace_sym_value.
 126         * memory.h: Delete bfd.h include.
 127         (mem_add_blk): Delete unused prototype.
 128         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 129         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 130         (aarch64_get_sym_value): Delete.
 131
 132 2016-08-12  Nick Clifton  <nickc@redhat.com>
 133
 134         * simulator.c (aarch64_step): Revert pervious delta.
 135         (aarch64_run): Call sim_events_tick after each
 136         instruction is simulated, and if necessary call
 137         sim_events_process.
 138         * simulator.h: Revert previous delta.
 139
 140 2016-08-11  Nick Clifton  <nickc@redhat.com>
 141
 142         * interp.c (sim_create_inferior): Allow for being called with a
 143         NULL abfd parameter.  If a bfd is provided, initialise the sim
 144         with that start address.
 145         * simulator.c (HALT_NYI): Just print out the numeric value of the
 146         instruction when not tracing.
 147         (aarch64_step): Change from static to global.
 148         * simulator.h: Add a prototype for aarch64_step().
 149
 150 2016-07-27  Alan Modra  <amodra@gmail.com>
 151
 152         * memory.c: Don't include libbfd.h.
 153
 154 2016-07-21  Nick Clifton  <nickc@redhat.com>
 155
 156         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 157
 158 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 159
 160         * cpustate.h: Include config.h.
 161         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 162         use anonymous structs to align members.
 163         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 164         endian_le2h_4 to read instruction from pc.
 165
 166 2016-05-06  Nick Clifton  <nickc@redhat.com>
 167
 168         * simulator.c (do_FMLA_by_element): New function.
 169         (do_vec_op2): Call it.
 170
 171 2016-04-27  Nick Clifton  <nickc@redhat.com>
 172
 173         * simulator.c: Add TRACE_DECODE statements to all emulation
 174         functions.
 175
 176 2016-03-30  Nick Clifton  <nickc@redhat.com>
 177
 178         * cpustate.c (aarch64_set_reg_s32): New function.
 179         (aarch64_set_reg_u32): New function.
 180         (aarch64_get_FP_half): Place half precision value into the correct
 181         slot of the union.
 182         (aarch64_set_FP_half): Likewise.
 183         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 184         aarch64_set_reg_u32.
 185         * memory.c (FETCH_FUNC): Cast the read value to the access type
 186         before converting it to the return type.  Rename to FETCH_FUNC64.
 187         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 188         accesses.  Use for 32-bit memory access functions.
 189         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 190         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 191         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 192         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 193         (ldrh32_abs): Store 32 bit value not 64-bits.
 194         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 195         (do_vec_MOV_immediate): Fix computation of val.
 196         (do_vec_MVNI): Likewise.
 197         (DO_VEC_WIDENING_MUL): New macro.
 198         (do_vec_mull): Use new macro.
 199         (do_vec_mul): Use new macro.
 200         (do_vec_MLA): Read values before writing.
 201         (do_vec_xtl): Likewise.
 202         (do_vec_SSHL): Select correct shift value.
 203         (do_vec_USHL): Likewise.
 204         (do_scalar_UCVTF): New function.
 205         (do_scalar_vec): Call new function.
 206         (store_pair_u64): Treat reads of SP as reads of XZR.
 207
 208 2016-03-29  Nick Clifton  <nickc@redhat.com>
 209
 210         * cpustate.c: Remove space after asterisk in function parameters.
 211         * decode.h (greg): Delete unused function.
 212         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 213         * simulator.c: Use INSTR macro in more places.
 214         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 215         Remove extraneous whitespace.
 216
 217 2016-03-23  Nick Clifton  <nickc@redhat.com>
 218
 219         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 220         register as a half precision floating point number.
 221         (aarch64_set_FP_half): New function.  Similar, but for setting
 222         a half precision register.
 223         (aarch64_get_thread_id): New function.  Returns the value of the
 224         CPU's TPIDR register.
 225         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 226         floating point control register.
 227         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 228         register.
 229         * cpustate.h: Add prototypes for new functions.
 230         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 231         * memory.c: Use unaligned core access functions for all memory
 232         reads and writes.
 233         * simulator.c (HALT_NYI): Generate an error message if tracing
 234         will not tell the user why the simulator is halting.
 235         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 236         (INSTR): New time-saver macro.
 237         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 238         offset.
 239         (fldrh_abs): New function.  Likewise for 16-bit values.
 240         (do_vec_SSHL): Allow for negative shift values.
 241         (do_vec_USHL): Likewise.
 242         (do_vec_SHL): Correct computation of shift amount.
 243         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 244         shifts and computation of shift value.
 245         (clz): New function.  Counts leading zero bits.
 246         (do_vec_CLZ): New function.  Implements CLZ (vector).
 247         (do_vec_MOV_element): Call do_vec_CLZ.
 248         (dexSimpleFPCondCompare): Implement.
 249         (do_FCVT_half_to_single): New function.  Implements one of the
 250         FCVT operations.
 251         (do_FCVT_half_to_double): New function.  Likewise.
 252         (do_FCVT_single_to_half): New function.  Likewise.
 253         (do_FCVT_double_to_half): New function.  Likewise.
 254         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 255         (do_scalar_SHL): Handle negative shifts.
 256         (do_scalar_shift): Handle SSHR.
 257         (do_scalar_USHL): New function.
 258         (do_double_add): Simplify to just performing a double precision
 259         add operation.  Move remaining code into...
 260         (do_scalar_vec): ... New function.
 261         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 262         functions.
 263         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 264         registers.
 265         (system_set): New function.
 266         (do_MSR_immediate): New function.  Stub for now.
 267         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 268         instruction.
 269         (do_SYS): New function.  Stub for now,
 270         (dexSystem): Call new functions.
 271
 272 2016-03-18  Nick Clifton  <nickc@redhat.com>
 273
 274         * cpustate.c: Remove spurious spaces from TRACE strings.
 275         Print hex equivalents of floats and doubles.
 276         Check element number against array size when accessing vector
 277         registers.
 278         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 279         element index.
 280         (SET_VEC_ELEMENT): Likewise.
 281         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 282
 283         * memory.c: Trace memory reads when --trace-memory is enabled.
 284         Remove float and double load and store functions.
 285         * memory.h (aarch64_get_mem_float): Delete prototype.
 286         (aarch64_get_mem_double): Likewise.
 287         (aarch64_set_mem_float): Likewise.
 288         (aarch64_set_mem_double): Likewise.
 289         * simulator (IS_SET): Always return either 0 or 1.
 290         (IS_CLEAR): Likewise.
 291         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 292         and doubles using 64-bit memory accesses.
 293         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 294         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 295         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 296         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 297         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 298         (do_vec_MUL_by_element): New function.
 299         (do_vec_op2): Call do_vec_MUL_by_element.
 300         (do_scalar_NEG): New function.
 301         (do_double_add): Call do_scalar_NEG.
 302
 303 2016-03-03  Nick Clifton  <nickc@redhat.com>
 304
 305         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 306         (CondCompare): Swap interpretation of bit 30.
 307         (DO_ADDP): Delete macro.
 308         (do_vec_ADDP): Copy source registers before starting to update
 309         destination register.
 310         (do_vec_FADDP): Likewise.
 311         (do_vec_load_store): Fix computation of sizeof_operation.
 312         (rbit64): Fix type of constant.
 313         (aarch64_step): When displaying insn value, display all 32 bits.
 314
 315 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 316
 317         * config.in, configure: Regenerate.
 318
 319 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 320
 321         * configure: Regenerate.
 322
 323 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 324
 325         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 326         * configure: Regenerate.
 327
 328 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 329
 330         * configure: Regenerate.
 331
 332 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 333
 334         * configure: Regenerate.
 335
 336 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 337
 338         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 339         * configure: Regenerate.
 340
 341 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 342
 343         * configure: Regenerate.
 344
 345 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 346
 347         * configure: Regenerate.
 348
 349 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 350
 351         * config.in, configure: Regenerate.
 352
 353 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 354
 355         * interp.c (sim_create_inferior): Mark argv and env const.
 356         (sim_open): Mark argv const.
 357
 358 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 359
 360         * interp.c: Delete dis-asm.h include.
 361         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 362         (sim_create_inferior): Delete disassemble init logic.
 363         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 364         (sim_open): Delete sim_add_option_table call.
 365         * memory.c (mem_error): Delete disas check.
 366         * simulator.c: Delete dis-asm.h include.
 367         (disas): Delete.
 368         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 369         (HALT_NYI): Likewise.
 370         (handle_halt): Delete disas call.
 371         (aarch64_step): Replace disas logic with TRACE_DISASM.
 372         * simulator.h: Delete dis-asm.h include.
 373         (aarch64_print_insn): Delete.
 374
 375 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 376
 377         * simulator.c (MAX, MIN): Delete.
 378         (do_vec_maxv): Change MAX to max and MIN to min.
 379         (do_vec_fminmaxV): Likewise.
 380
 381 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 382
 383         * simulator.c: Remove syscall.h include.
 384
 385 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 386
 387         * configure: Regenerate.
 388
 389 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 390
 391         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 392         * configure: Regenerate.
 393
 394 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 395
 396         * configure: Regenerate.
 397
 398 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 399
 400         * interp.c (sim_dis_read): Change private_data to application_data.
 401         (sim_create_inferior): Likewise.
 402
 403 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 404
 405         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 406
 407 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 408
 409         * config.in, configure: Regenerate.
 410
 411 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 412
 413         * interp.c (sim_create_inferior): Update comment and argv check.
 414
 415 2015-12-14  Nick Clifton  <nickc@redhat.com>
 416
 417         * simulator.c (system_get): New function.  Provides read
 418         access to the dczid system register.
 419         (do_mrs): New function - implements the MRS instruction.
 420         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 421         unimplemented system instructions.
 422
 423 2015-11-24  Nick Clifton  <nickc@redhat.com>
 424
 425         * configure.ac: New configure template.
 426         * aclocal.m4: Generate.
 427         * config.in: Generate.
 428         * configure: Generate.
 429         * cpustate.c: New file - functions for accessing AArch64 registers.
 430         * cpustate.h: New header.
 431         * decode.h: New header.
 432         * interp.c: New file - interface between GDB and simulator.
 433         * Makefile.in: New makefile template.
 434         * memory.c: New file - functions for simulating aarch64 memory
 435         accesses.
 436         * memory.h: New header.
 437         * sim-main.h: New header.
 438         * simulator.c: New file - aarch64 simulator functions.
 439         * simulator.h: New header.