sim/aarch64/ChangeLog

   1 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
   2
   3         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
   4         registers based on structure size.
   5         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
   6         (LD1_1): Replace with call to vec_load.
   7         (vec_store): Add new M argument.  Rewrite to iterate over registers
   8         based on structure size.
   9         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
  10         (ST1_1): Replace with call to vec_store.
  11
  12 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
  13
  14         * simulator.c (do_vec_FCVTL): New.
  15         (do_vec_op1): Call do_vec_FCVTL.
  16
  17         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
  18         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
  19         (do_scalar_vec): Add calls to new functions.
  20
  21 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
  22
  23         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
  24         flag check.
  25
  26 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
  27
  28         * simulator.c (mul64hi): Shift carry left by 32.
  29         (smulh): Change signum to negate.  If negate, invert result, and add
  30         carry bit if low part of multiply result is zero.
  31
  32 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
  33
  34         * simulator.c (do_vec_SMOV_into_scalar): New.
  35         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
  36         Rewritten.
  37         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
  38         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
  39         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
  40         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
  41
  42         * simulator.c (popcount): New.
  43         (do_vec_CNT): New.
  44         (do_vec_op1): Add do_vec_CNT call.
  45
  46 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
  47
  48         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
  49         with type set to input type size.
  50         (do_vec_xtl): Change bias from 3 to 4 for byte case.
  51
  52 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
  53
  54         * simulator.c (do_vec_MLA): Rewrite switch body.
  55
  56         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
  57         2.  Move test_false if inside loop.  Fix logic for computing result
  58         stored to vd.
  59
  60         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
  61         (do_vec_LDn_single, do_vec_STn_single): New.
  62         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
  63         loop over nregs using new var n.  Add n times size to address in loop.
  64         Add n to vd in loop.
  65         (do_vec_load_store): Add comment for instruction bit 24.  New var
  66         single to hold instruction bit 24.  Add new code to use single.  Move
  67         ldnr support inside single if statements.  Fix ldnr register counts
  68         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
  69
  70 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
  71
  72         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
  73
  74 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
  75
  76         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
  77         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
  78         case 3, call HALT_UNALLOC unconditionally.
  79         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
  80         i + 2.  Delete if on bias, change index to i + bias * X.
  81
  82 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
  83
  84         * simulator.c (do_vec_UZP): Rewrite.
  85
  86 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
  87
  88         * cpustate.c: Include math.h.
  89         (aarch64_set_FP_float): Use signbit to check for signed zero.
  90         (aarch64_set_FP_double): Likewise.
  91         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
  92         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
  93         args same size as third arg.
  94         (fmaxnm): Use isnan instead of fpclassify.
  95         (fminnm, dmaxnm, dminnm): Likewise.
  96         (do_vec_MLS): Reverse order of subtraction operands.
  97         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
  98         aarch64_get_FP_float to get source register contents.
  99         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 100         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 101         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 102         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 103         raise_exception calls.
 104
 105 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 106
 107         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 108         Add comment to document NaN issue.
 109         (set_flags_for_double_compare): Likewise.
 110
 111 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 112
 113         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 114         (set_flags_for_add64): Replace with a modified copy of
 115         set_flags_for_sub64.
 116
 117 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 118
 119         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 120         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 121
 122 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 123
 124         * simulator.c (fsturs): Switch use of rn and st variables.
 125         (fsturd, fsturq): Likewise
 126
 127 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 128
 129         * interp.c: Include bfd.h.
 130         (symcount, symtab, aarch64_get_sym_value): Delete.
 131         (remove_useless_symbols): Change count type to long.
 132         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 133         and symtab local variables.
 134         (sim_create_inferior): Delete storage.  Replace symbol code
 135         with a call to trace_load_symbols.
 136         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 137         includes.
 138         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 139         trace_sym_value.
 140         * memory.h: Delete bfd.h include.
 141         (mem_add_blk): Delete unused prototype.
 142         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 143         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 144         (aarch64_get_sym_value): Delete.
 145
 146 2016-08-12  Nick Clifton  <nickc@redhat.com>
 147
 148         * simulator.c (aarch64_step): Revert pervious delta.
 149         (aarch64_run): Call sim_events_tick after each
 150         instruction is simulated, and if necessary call
 151         sim_events_process.
 152         * simulator.h: Revert previous delta.
 153
 154 2016-08-11  Nick Clifton  <nickc@redhat.com>
 155
 156         * interp.c (sim_create_inferior): Allow for being called with a
 157         NULL abfd parameter.  If a bfd is provided, initialise the sim
 158         with that start address.
 159         * simulator.c (HALT_NYI): Just print out the numeric value of the
 160         instruction when not tracing.
 161         (aarch64_step): Change from static to global.
 162         * simulator.h: Add a prototype for aarch64_step().
 163
 164 2016-07-27  Alan Modra  <amodra@gmail.com>
 165
 166         * memory.c: Don't include libbfd.h.
 167
 168 2016-07-21  Nick Clifton  <nickc@redhat.com>
 169
 170         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 171
 172 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 173
 174         * cpustate.h: Include config.h.
 175         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 176         use anonymous structs to align members.
 177         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 178         endian_le2h_4 to read instruction from pc.
 179
 180 2016-05-06  Nick Clifton  <nickc@redhat.com>
 181
 182         * simulator.c (do_FMLA_by_element): New function.
 183         (do_vec_op2): Call it.
 184
 185 2016-04-27  Nick Clifton  <nickc@redhat.com>
 186
 187         * simulator.c: Add TRACE_DECODE statements to all emulation
 188         functions.
 189
 190 2016-03-30  Nick Clifton  <nickc@redhat.com>
 191
 192         * cpustate.c (aarch64_set_reg_s32): New function.
 193         (aarch64_set_reg_u32): New function.
 194         (aarch64_get_FP_half): Place half precision value into the correct
 195         slot of the union.
 196         (aarch64_set_FP_half): Likewise.
 197         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 198         aarch64_set_reg_u32.
 199         * memory.c (FETCH_FUNC): Cast the read value to the access type
 200         before converting it to the return type.  Rename to FETCH_FUNC64.
 201         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 202         accesses.  Use for 32-bit memory access functions.
 203         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 204         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 205         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 206         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 207         (ldrh32_abs): Store 32 bit value not 64-bits.
 208         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 209         (do_vec_MOV_immediate): Fix computation of val.
 210         (do_vec_MVNI): Likewise.
 211         (DO_VEC_WIDENING_MUL): New macro.
 212         (do_vec_mull): Use new macro.
 213         (do_vec_mul): Use new macro.
 214         (do_vec_MLA): Read values before writing.
 215         (do_vec_xtl): Likewise.
 216         (do_vec_SSHL): Select correct shift value.
 217         (do_vec_USHL): Likewise.
 218         (do_scalar_UCVTF): New function.
 219         (do_scalar_vec): Call new function.
 220         (store_pair_u64): Treat reads of SP as reads of XZR.
 221
 222 2016-03-29  Nick Clifton  <nickc@redhat.com>
 223
 224         * cpustate.c: Remove space after asterisk in function parameters.
 225         * decode.h (greg): Delete unused function.
 226         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 227         * simulator.c: Use INSTR macro in more places.
 228         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 229         Remove extraneous whitespace.
 230
 231 2016-03-23  Nick Clifton  <nickc@redhat.com>
 232
 233         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 234         register as a half precision floating point number.
 235         (aarch64_set_FP_half): New function.  Similar, but for setting
 236         a half precision register.
 237         (aarch64_get_thread_id): New function.  Returns the value of the
 238         CPU's TPIDR register.
 239         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 240         floating point control register.
 241         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 242         register.
 243         * cpustate.h: Add prototypes for new functions.
 244         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 245         * memory.c: Use unaligned core access functions for all memory
 246         reads and writes.
 247         * simulator.c (HALT_NYI): Generate an error message if tracing
 248         will not tell the user why the simulator is halting.
 249         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 250         (INSTR): New time-saver macro.
 251         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 252         offset.
 253         (fldrh_abs): New function.  Likewise for 16-bit values.
 254         (do_vec_SSHL): Allow for negative shift values.
 255         (do_vec_USHL): Likewise.
 256         (do_vec_SHL): Correct computation of shift amount.
 257         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 258         shifts and computation of shift value.
 259         (clz): New function.  Counts leading zero bits.
 260         (do_vec_CLZ): New function.  Implements CLZ (vector).
 261         (do_vec_MOV_element): Call do_vec_CLZ.
 262         (dexSimpleFPCondCompare): Implement.
 263         (do_FCVT_half_to_single): New function.  Implements one of the
 264         FCVT operations.
 265         (do_FCVT_half_to_double): New function.  Likewise.
 266         (do_FCVT_single_to_half): New function.  Likewise.
 267         (do_FCVT_double_to_half): New function.  Likewise.
 268         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 269         (do_scalar_SHL): Handle negative shifts.
 270         (do_scalar_shift): Handle SSHR.
 271         (do_scalar_USHL): New function.
 272         (do_double_add): Simplify to just performing a double precision
 273         add operation.  Move remaining code into...
 274         (do_scalar_vec): ... New function.
 275         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 276         functions.
 277         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 278         registers.
 279         (system_set): New function.
 280         (do_MSR_immediate): New function.  Stub for now.
 281         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 282         instruction.
 283         (do_SYS): New function.  Stub for now,
 284         (dexSystem): Call new functions.
 285
 286 2016-03-18  Nick Clifton  <nickc@redhat.com>
 287
 288         * cpustate.c: Remove spurious spaces from TRACE strings.
 289         Print hex equivalents of floats and doubles.
 290         Check element number against array size when accessing vector
 291         registers.
 292         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 293         element index.
 294         (SET_VEC_ELEMENT): Likewise.
 295         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 296
 297         * memory.c: Trace memory reads when --trace-memory is enabled.
 298         Remove float and double load and store functions.
 299         * memory.h (aarch64_get_mem_float): Delete prototype.
 300         (aarch64_get_mem_double): Likewise.
 301         (aarch64_set_mem_float): Likewise.
 302         (aarch64_set_mem_double): Likewise.
 303         * simulator (IS_SET): Always return either 0 or 1.
 304         (IS_CLEAR): Likewise.
 305         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 306         and doubles using 64-bit memory accesses.
 307         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 308         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 309         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 310         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 311         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 312         (do_vec_MUL_by_element): New function.
 313         (do_vec_op2): Call do_vec_MUL_by_element.
 314         (do_scalar_NEG): New function.
 315         (do_double_add): Call do_scalar_NEG.
 316
 317 2016-03-03  Nick Clifton  <nickc@redhat.com>
 318
 319         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 320         (CondCompare): Swap interpretation of bit 30.
 321         (DO_ADDP): Delete macro.
 322         (do_vec_ADDP): Copy source registers before starting to update
 323         destination register.
 324         (do_vec_FADDP): Likewise.
 325         (do_vec_load_store): Fix computation of sizeof_operation.
 326         (rbit64): Fix type of constant.
 327         (aarch64_step): When displaying insn value, display all 32 bits.
 328
 329 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 330
 331         * config.in, configure: Regenerate.
 332
 333 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 334
 335         * configure: Regenerate.
 336
 337 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 338
 339         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 340         * configure: Regenerate.
 341
 342 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 343
 344         * configure: Regenerate.
 345
 346 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 347
 348         * configure: Regenerate.
 349
 350 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 351
 352         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 353         * configure: Regenerate.
 354
 355 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 356
 357         * configure: Regenerate.
 358
 359 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 360
 361         * configure: Regenerate.
 362
 363 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 364
 365         * config.in, configure: Regenerate.
 366
 367 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 368
 369         * interp.c (sim_create_inferior): Mark argv and env const.
 370         (sim_open): Mark argv const.
 371
 372 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 373
 374         * interp.c: Delete dis-asm.h include.
 375         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 376         (sim_create_inferior): Delete disassemble init logic.
 377         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 378         (sim_open): Delete sim_add_option_table call.
 379         * memory.c (mem_error): Delete disas check.
 380         * simulator.c: Delete dis-asm.h include.
 381         (disas): Delete.
 382         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 383         (HALT_NYI): Likewise.
 384         (handle_halt): Delete disas call.
 385         (aarch64_step): Replace disas logic with TRACE_DISASM.
 386         * simulator.h: Delete dis-asm.h include.
 387         (aarch64_print_insn): Delete.
 388
 389 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 390
 391         * simulator.c (MAX, MIN): Delete.
 392         (do_vec_maxv): Change MAX to max and MIN to min.
 393         (do_vec_fminmaxV): Likewise.
 394
 395 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 396
 397         * simulator.c: Remove syscall.h include.
 398
 399 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 400
 401         * configure: Regenerate.
 402
 403 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 404
 405         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 406         * configure: Regenerate.
 407
 408 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 409
 410         * configure: Regenerate.
 411
 412 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 413
 414         * interp.c (sim_dis_read): Change private_data to application_data.
 415         (sim_create_inferior): Likewise.
 416
 417 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 418
 419         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 420
 421 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 422
 423         * config.in, configure: Regenerate.
 424
 425 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 426
 427         * interp.c (sim_create_inferior): Update comment and argv check.
 428
 429 2015-12-14  Nick Clifton  <nickc@redhat.com>
 430
 431         * simulator.c (system_get): New function.  Provides read
 432         access to the dczid system register.
 433         (do_mrs): New function - implements the MRS instruction.
 434         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 435         unimplemented system instructions.
 436
 437 2015-11-24  Nick Clifton  <nickc@redhat.com>
 438
 439         * configure.ac: New configure template.
 440         * aclocal.m4: Generate.
 441         * config.in: Generate.
 442         * configure: Generate.
 443         * cpustate.c: New file - functions for accessing AArch64 registers.
 444         * cpustate.h: New header.
 445         * decode.h: New header.
 446         * interp.c: New file - interface between GDB and simulator.
 447         * Makefile.in: New makefile template.
 448         * memory.c: New file - functions for simulating aarch64 memory
 449         accesses.
 450         * memory.h: New header.
 451         * sim-main.h: New header.
 452         * simulator.c: New file - aarch64 simulator functions.
 453         * simulator.h: New header.