sim/aarch64/ChangeLog

   1 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
   2
   3         * simulator.c (do_vec_SMOV_into_scalar): New.
   4         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
   5         Rewritten.
   6         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
   7         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
   8         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
   9         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
  10
  11         * simulator.c (popcount): New.
  12         (do_vec_CNT): New.
  13         (do_vec_op1): Add do_vec_CNT call.
  14
  15 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
  16
  17         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
  18         with type set to input type size.
  19         (do_vec_xtl): Change bias from 3 to 4 for byte case.
  20
  21 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
  22
  23         * simulator.c (do_vec_MLA): Rewrite switch body.
  24
  25         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
  26         2.  Move test_false if inside loop.  Fix logic for computing result
  27         stored to vd.
  28
  29         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
  30         (do_vec_LDn_single, do_vec_STn_single): New.
  31         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
  32         loop over nregs using new var n.  Add n times size to address in loop.
  33         Add n to vd in loop.
  34         (do_vec_load_store): Add comment for instruction bit 24.  New var
  35         single to hold instruction bit 24.  Add new code to use single.  Move
  36         ldnr support inside single if statements.  Fix ldnr register counts
  37         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
  38
  39 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
  40
  41         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
  42
  43 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
  44
  45         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
  46         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
  47         case 3, call HALT_UNALLOC unconditionally.
  48         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
  49         i + 2.  Delete if on bias, change index to i + bias * X.
  50
  51 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
  52
  53         * simulator.c (do_vec_UZP): Rewrite.
  54
  55 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
  56
  57         * cpustate.c: Include math.h.
  58         (aarch64_set_FP_float): Use signbit to check for signed zero.
  59         (aarch64_set_FP_double): Likewise.
  60         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
  61         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
  62         args same size as third arg.
  63         (fmaxnm): Use isnan instead of fpclassify.
  64         (fminnm, dmaxnm, dminnm): Likewise.
  65         (do_vec_MLS): Reverse order of subtraction operands.
  66         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
  67         aarch64_get_FP_float to get source register contents.
  68         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
  69         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
  70         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
  71         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
  72         raise_exception calls.
  73
  74 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
  75
  76         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
  77         Add comment to document NaN issue.
  78         (set_flags_for_double_compare): Likewise.
  79
  80 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
  81
  82         * simulator.c (NEG, POS): Move before set_flags_for_add64.
  83         (set_flags_for_add64): Replace with a modified copy of
  84         set_flags_for_sub64.
  85
  86 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
  87
  88         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
  89         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
  90
  91 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
  92
  93         * simulator.c (fsturs): Switch use of rn and st variables.
  94         (fsturd, fsturq): Likewise
  95
  96 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
  97
  98         * interp.c: Include bfd.h.
  99         (symcount, symtab, aarch64_get_sym_value): Delete.
 100         (remove_useless_symbols): Change count type to long.
 101         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 102         and symtab local variables.
 103         (sim_create_inferior): Delete storage.  Replace symbol code
 104         with a call to trace_load_symbols.
 105         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 106         includes.
 107         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 108         trace_sym_value.
 109         * memory.h: Delete bfd.h include.
 110         (mem_add_blk): Delete unused prototype.
 111         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 112         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 113         (aarch64_get_sym_value): Delete.
 114
 115 2016-08-12  Nick Clifton  <nickc@redhat.com>
 116
 117         * simulator.c (aarch64_step): Revert pervious delta.
 118         (aarch64_run): Call sim_events_tick after each
 119         instruction is simulated, and if necessary call
 120         sim_events_process.
 121         * simulator.h: Revert previous delta.
 122
 123 2016-08-11  Nick Clifton  <nickc@redhat.com>
 124
 125         * interp.c (sim_create_inferior): Allow for being called with a
 126         NULL abfd parameter.  If a bfd is provided, initialise the sim
 127         with that start address.
 128         * simulator.c (HALT_NYI): Just print out the numeric value of the
 129         instruction when not tracing.
 130         (aarch64_step): Change from static to global.
 131         * simulator.h: Add a prototype for aarch64_step().
 132
 133 2016-07-27  Alan Modra  <amodra@gmail.com>
 134
 135         * memory.c: Don't include libbfd.h.
 136
 137 2016-07-21  Nick Clifton  <nickc@redhat.com>
 138
 139         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 140
 141 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 142
 143         * cpustate.h: Include config.h.
 144         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 145         use anonymous structs to align members.
 146         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 147         endian_le2h_4 to read instruction from pc.
 148
 149 2016-05-06  Nick Clifton  <nickc@redhat.com>
 150
 151         * simulator.c (do_FMLA_by_element): New function.
 152         (do_vec_op2): Call it.
 153
 154 2016-04-27  Nick Clifton  <nickc@redhat.com>
 155
 156         * simulator.c: Add TRACE_DECODE statements to all emulation
 157         functions.
 158
 159 2016-03-30  Nick Clifton  <nickc@redhat.com>
 160
 161         * cpustate.c (aarch64_set_reg_s32): New function.
 162         (aarch64_set_reg_u32): New function.
 163         (aarch64_get_FP_half): Place half precision value into the correct
 164         slot of the union.
 165         (aarch64_set_FP_half): Likewise.
 166         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 167         aarch64_set_reg_u32.
 168         * memory.c (FETCH_FUNC): Cast the read value to the access type
 169         before converting it to the return type.  Rename to FETCH_FUNC64.
 170         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 171         accesses.  Use for 32-bit memory access functions.
 172         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 173         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 174         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 175         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 176         (ldrh32_abs): Store 32 bit value not 64-bits.
 177         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 178         (do_vec_MOV_immediate): Fix computation of val.
 179         (do_vec_MVNI): Likewise.
 180         (DO_VEC_WIDENING_MUL): New macro.
 181         (do_vec_mull): Use new macro.
 182         (do_vec_mul): Use new macro.
 183         (do_vec_MLA): Read values before writing.
 184         (do_vec_xtl): Likewise.
 185         (do_vec_SSHL): Select correct shift value.
 186         (do_vec_USHL): Likewise.
 187         (do_scalar_UCVTF): New function.
 188         (do_scalar_vec): Call new function.
 189         (store_pair_u64): Treat reads of SP as reads of XZR.
 190
 191 2016-03-29  Nick Clifton  <nickc@redhat.com>
 192
 193         * cpustate.c: Remove space after asterisk in function parameters.
 194         * decode.h (greg): Delete unused function.
 195         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 196         * simulator.c: Use INSTR macro in more places.
 197         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 198         Remove extraneous whitespace.
 199
 200 2016-03-23  Nick Clifton  <nickc@redhat.com>
 201
 202         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 203         register as a half precision floating point number.
 204         (aarch64_set_FP_half): New function.  Similar, but for setting
 205         a half precision register.
 206         (aarch64_get_thread_id): New function.  Returns the value of the
 207         CPU's TPIDR register.
 208         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 209         floating point control register.
 210         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 211         register.
 212         * cpustate.h: Add prototypes for new functions.
 213         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 214         * memory.c: Use unaligned core access functions for all memory
 215         reads and writes.
 216         * simulator.c (HALT_NYI): Generate an error message if tracing
 217         will not tell the user why the simulator is halting.
 218         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 219         (INSTR): New time-saver macro.
 220         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 221         offset.
 222         (fldrh_abs): New function.  Likewise for 16-bit values.
 223         (do_vec_SSHL): Allow for negative shift values.
 224         (do_vec_USHL): Likewise.
 225         (do_vec_SHL): Correct computation of shift amount.
 226         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 227         shifts and computation of shift value.
 228         (clz): New function.  Counts leading zero bits.
 229         (do_vec_CLZ): New function.  Implements CLZ (vector).
 230         (do_vec_MOV_element): Call do_vec_CLZ.
 231         (dexSimpleFPCondCompare): Implement.
 232         (do_FCVT_half_to_single): New function.  Implements one of the
 233         FCVT operations.
 234         (do_FCVT_half_to_double): New function.  Likewise.
 235         (do_FCVT_single_to_half): New function.  Likewise.
 236         (do_FCVT_double_to_half): New function.  Likewise.
 237         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 238         (do_scalar_SHL): Handle negative shifts.
 239         (do_scalar_shift): Handle SSHR.
 240         (do_scalar_USHL): New function.
 241         (do_double_add): Simplify to just performing a double precision
 242         add operation.  Move remaining code into...
 243         (do_scalar_vec): ... New function.
 244         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 245         functions.
 246         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 247         registers.
 248         (system_set): New function.
 249         (do_MSR_immediate): New function.  Stub for now.
 250         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 251         instruction.
 252         (do_SYS): New function.  Stub for now,
 253         (dexSystem): Call new functions.
 254
 255 2016-03-18  Nick Clifton  <nickc@redhat.com>
 256
 257         * cpustate.c: Remove spurious spaces from TRACE strings.
 258         Print hex equivalents of floats and doubles.
 259         Check element number against array size when accessing vector
 260         registers.
 261         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 262         element index.
 263         (SET_VEC_ELEMENT): Likewise.
 264         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 265
 266         * memory.c: Trace memory reads when --trace-memory is enabled.
 267         Remove float and double load and store functions.
 268         * memory.h (aarch64_get_mem_float): Delete prototype.
 269         (aarch64_get_mem_double): Likewise.
 270         (aarch64_set_mem_float): Likewise.
 271         (aarch64_set_mem_double): Likewise.
 272         * simulator (IS_SET): Always return either 0 or 1.
 273         (IS_CLEAR): Likewise.
 274         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 275         and doubles using 64-bit memory accesses.
 276         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 277         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 278         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 279         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 280         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 281         (do_vec_MUL_by_element): New function.
 282         (do_vec_op2): Call do_vec_MUL_by_element.
 283         (do_scalar_NEG): New function.
 284         (do_double_add): Call do_scalar_NEG.
 285
 286 2016-03-03  Nick Clifton  <nickc@redhat.com>
 287
 288         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 289         (CondCompare): Swap interpretation of bit 30.
 290         (DO_ADDP): Delete macro.
 291         (do_vec_ADDP): Copy source registers before starting to update
 292         destination register.
 293         (do_vec_FADDP): Likewise.
 294         (do_vec_load_store): Fix computation of sizeof_operation.
 295         (rbit64): Fix type of constant.
 296         (aarch64_step): When displaying insn value, display all 32 bits.
 297
 298 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 299
 300         * config.in, configure: Regenerate.
 301
 302 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 303
 304         * configure: Regenerate.
 305
 306 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 307
 308         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 309         * configure: Regenerate.
 310
 311 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 312
 313         * configure: Regenerate.
 314
 315 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 316
 317         * configure: Regenerate.
 318
 319 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 320
 321         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 322         * configure: Regenerate.
 323
 324 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 325
 326         * configure: Regenerate.
 327
 328 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 329
 330         * configure: Regenerate.
 331
 332 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 333
 334         * config.in, configure: Regenerate.
 335
 336 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 337
 338         * interp.c (sim_create_inferior): Mark argv and env const.
 339         (sim_open): Mark argv const.
 340
 341 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 342
 343         * interp.c: Delete dis-asm.h include.
 344         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 345         (sim_create_inferior): Delete disassemble init logic.
 346         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 347         (sim_open): Delete sim_add_option_table call.
 348         * memory.c (mem_error): Delete disas check.
 349         * simulator.c: Delete dis-asm.h include.
 350         (disas): Delete.
 351         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 352         (HALT_NYI): Likewise.
 353         (handle_halt): Delete disas call.
 354         (aarch64_step): Replace disas logic with TRACE_DISASM.
 355         * simulator.h: Delete dis-asm.h include.
 356         (aarch64_print_insn): Delete.
 357
 358 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 359
 360         * simulator.c (MAX, MIN): Delete.
 361         (do_vec_maxv): Change MAX to max and MIN to min.
 362         (do_vec_fminmaxV): Likewise.
 363
 364 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 365
 366         * simulator.c: Remove syscall.h include.
 367
 368 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 369
 370         * configure: Regenerate.
 371
 372 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 373
 374         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 375         * configure: Regenerate.
 376
 377 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 378
 379         * configure: Regenerate.
 380
 381 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 382
 383         * interp.c (sim_dis_read): Change private_data to application_data.
 384         (sim_create_inferior): Likewise.
 385
 386 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 387
 388         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 389
 390 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 391
 392         * config.in, configure: Regenerate.
 393
 394 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 395
 396         * interp.c (sim_create_inferior): Update comment and argv check.
 397
 398 2015-12-14  Nick Clifton  <nickc@redhat.com>
 399
 400         * simulator.c (system_get): New function.  Provides read
 401         access to the dczid system register.
 402         (do_mrs): New function - implements the MRS instruction.
 403         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 404         unimplemented system instructions.
 405
 406 2015-11-24  Nick Clifton  <nickc@redhat.com>
 407
 408         * configure.ac: New configure template.
 409         * aclocal.m4: Generate.
 410         * config.in: Generate.
 411         * configure: Generate.
 412         * cpustate.c: New file - functions for accessing AArch64 registers.
 413         * cpustate.h: New header.
 414         * decode.h: New header.
 415         * interp.c: New file - interface between GDB and simulator.
 416         * Makefile.in: New makefile template.
 417         * memory.c: New file - functions for simulating aarch64 memory
 418         accesses.
 419         * memory.h: New header.
 420         * sim-main.h: New header.
 421         * simulator.c: New file - aarch64 simulator functions.
 422         * simulator.h: New header.