sim/aarch64/ChangeLog

   1 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
   2
   3         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
   4         (do_vec_LDn_single, do_vec_STn_single): New.
   5         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
   6         loop over nregs using new var n.  Add n times size to address in loop.
   7         Add n to vd in loop.
   8         (do_vec_load_store): Add comment for instruction bit 24.  New var
   9         single to hold instruction bit 24.  Add new code to use single.  Move
  10         ldnr support inside single if statements.  Fix ldnr register counts
  11         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
  12
  13 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
  14
  15         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
  16
  17 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
  18
  19         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
  20         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
  21         case 3, call HALT_UNALLOC unconditionally.
  22         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
  23         i + 2.  Delete if on bias, change index to i + bias * X.
  24
  25 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
  26
  27         * simulator.c (do_vec_UZP): Rewrite.
  28
  29 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
  30
  31         * cpustate.c: Include math.h.
  32         (aarch64_set_FP_float): Use signbit to check for signed zero.
  33         (aarch64_set_FP_double): Likewise.
  34         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
  35         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
  36         args same size as third arg.
  37         (fmaxnm): Use isnan instead of fpclassify.
  38         (fminnm, dmaxnm, dminnm): Likewise.
  39         (do_vec_MLS): Reverse order of subtraction operands.
  40         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
  41         aarch64_get_FP_float to get source register contents.
  42         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
  43         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
  44         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
  45         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
  46         raise_exception calls.
  47
  48 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
  49
  50         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
  51         Add comment to document NaN issue.
  52         (set_flags_for_double_compare): Likewise.
  53
  54 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
  55
  56         * simulator.c (NEG, POS): Move before set_flags_for_add64.
  57         (set_flags_for_add64): Replace with a modified copy of
  58         set_flags_for_sub64.
  59
  60 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
  61
  62         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
  63         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
  64
  65 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
  66
  67         * simulator.c (fsturs): Switch use of rn and st variables.
  68         (fsturd, fsturq): Likewise
  69
  70 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
  71
  72         * interp.c: Include bfd.h.
  73         (symcount, symtab, aarch64_get_sym_value): Delete.
  74         (remove_useless_symbols): Change count type to long.
  75         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
  76         and symtab local variables.
  77         (sim_create_inferior): Delete storage.  Replace symbol code
  78         with a call to trace_load_symbols.
  79         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
  80         includes.
  81         (aarch64_get_heap_start): Change aarch64_get_sym_value to
  82         trace_sym_value.
  83         * memory.h: Delete bfd.h include.
  84         (mem_add_blk): Delete unused prototype.
  85         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
  86         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
  87         (aarch64_get_sym_value): Delete.
  88
  89 2016-08-12  Nick Clifton  <nickc@redhat.com>
  90
  91         * simulator.c (aarch64_step): Revert pervious delta.
  92         (aarch64_run): Call sim_events_tick after each
  93         instruction is simulated, and if necessary call
  94         sim_events_process.
  95         * simulator.h: Revert previous delta.
  96
  97 2016-08-11  Nick Clifton  <nickc@redhat.com>
  98
  99         * interp.c (sim_create_inferior): Allow for being called with a
 100         NULL abfd parameter.  If a bfd is provided, initialise the sim
 101         with that start address.
 102         * simulator.c (HALT_NYI): Just print out the numeric value of the
 103         instruction when not tracing.
 104         (aarch64_step): Change from static to global.
 105         * simulator.h: Add a prototype for aarch64_step().
 106
 107 2016-07-27  Alan Modra  <amodra@gmail.com>
 108
 109         * memory.c: Don't include libbfd.h.
 110
 111 2016-07-21  Nick Clifton  <nickc@redhat.com>
 112
 113         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 114
 115 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 116
 117         * cpustate.h: Include config.h.
 118         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 119         use anonymous structs to align members.
 120         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 121         endian_le2h_4 to read instruction from pc.
 122
 123 2016-05-06  Nick Clifton  <nickc@redhat.com>
 124
 125         * simulator.c (do_FMLA_by_element): New function.
 126         (do_vec_op2): Call it.
 127
 128 2016-04-27  Nick Clifton  <nickc@redhat.com>
 129
 130         * simulator.c: Add TRACE_DECODE statements to all emulation
 131         functions.
 132
 133 2016-03-30  Nick Clifton  <nickc@redhat.com>
 134
 135         * cpustate.c (aarch64_set_reg_s32): New function.
 136         (aarch64_set_reg_u32): New function.
 137         (aarch64_get_FP_half): Place half precision value into the correct
 138         slot of the union.
 139         (aarch64_set_FP_half): Likewise.
 140         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 141         aarch64_set_reg_u32.
 142         * memory.c (FETCH_FUNC): Cast the read value to the access type
 143         before converting it to the return type.  Rename to FETCH_FUNC64.
 144         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 145         accesses.  Use for 32-bit memory access functions.
 146         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 147         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 148         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 149         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 150         (ldrh32_abs): Store 32 bit value not 64-bits.
 151         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 152         (do_vec_MOV_immediate): Fix computation of val.
 153         (do_vec_MVNI): Likewise.
 154         (DO_VEC_WIDENING_MUL): New macro.
 155         (do_vec_mull): Use new macro.
 156         (do_vec_mul): Use new macro.
 157         (do_vec_MLA): Read values before writing.
 158         (do_vec_xtl): Likewise.
 159         (do_vec_SSHL): Select correct shift value.
 160         (do_vec_USHL): Likewise.
 161         (do_scalar_UCVTF): New function.
 162         (do_scalar_vec): Call new function.
 163         (store_pair_u64): Treat reads of SP as reads of XZR.
 164
 165 2016-03-29  Nick Clifton  <nickc@redhat.com>
 166
 167         * cpustate.c: Remove space after asterisk in function parameters.
 168         * decode.h (greg): Delete unused function.
 169         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 170         * simulator.c: Use INSTR macro in more places.
 171         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 172         Remove extraneous whitespace.
 173
 174 2016-03-23  Nick Clifton  <nickc@redhat.com>
 175
 176         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 177         register as a half precision floating point number.
 178         (aarch64_set_FP_half): New function.  Similar, but for setting
 179         a half precision register.
 180         (aarch64_get_thread_id): New function.  Returns the value of the
 181         CPU's TPIDR register.
 182         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 183         floating point control register.
 184         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 185         register.
 186         * cpustate.h: Add prototypes for new functions.
 187         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 188         * memory.c: Use unaligned core access functions for all memory
 189         reads and writes.
 190         * simulator.c (HALT_NYI): Generate an error message if tracing
 191         will not tell the user why the simulator is halting.
 192         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 193         (INSTR): New time-saver macro.
 194         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 195         offset.
 196         (fldrh_abs): New function.  Likewise for 16-bit values.
 197         (do_vec_SSHL): Allow for negative shift values.
 198         (do_vec_USHL): Likewise.
 199         (do_vec_SHL): Correct computation of shift amount.
 200         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 201         shifts and computation of shift value.
 202         (clz): New function.  Counts leading zero bits.
 203         (do_vec_CLZ): New function.  Implements CLZ (vector).
 204         (do_vec_MOV_element): Call do_vec_CLZ.
 205         (dexSimpleFPCondCompare): Implement.
 206         (do_FCVT_half_to_single): New function.  Implements one of the
 207         FCVT operations.
 208         (do_FCVT_half_to_double): New function.  Likewise.
 209         (do_FCVT_single_to_half): New function.  Likewise.
 210         (do_FCVT_double_to_half): New function.  Likewise.
 211         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 212         (do_scalar_SHL): Handle negative shifts.
 213         (do_scalar_shift): Handle SSHR.
 214         (do_scalar_USHL): New function.
 215         (do_double_add): Simplify to just performing a double precision
 216         add operation.  Move remaining code into...
 217         (do_scalar_vec): ... New function.
 218         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 219         functions.
 220         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 221         registers.
 222         (system_set): New function.
 223         (do_MSR_immediate): New function.  Stub for now.
 224         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 225         instruction.
 226         (do_SYS): New function.  Stub for now,
 227         (dexSystem): Call new functions.
 228
 229 2016-03-18  Nick Clifton  <nickc@redhat.com>
 230
 231         * cpustate.c: Remove spurious spaces from TRACE strings.
 232         Print hex equivalents of floats and doubles.
 233         Check element number against array size when accessing vector
 234         registers.
 235         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 236         element index.
 237         (SET_VEC_ELEMENT): Likewise.
 238         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 239
 240         * memory.c: Trace memory reads when --trace-memory is enabled.
 241         Remove float and double load and store functions.
 242         * memory.h (aarch64_get_mem_float): Delete prototype.
 243         (aarch64_get_mem_double): Likewise.
 244         (aarch64_set_mem_float): Likewise.
 245         (aarch64_set_mem_double): Likewise.
 246         * simulator (IS_SET): Always return either 0 or 1.
 247         (IS_CLEAR): Likewise.
 248         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 249         and doubles using 64-bit memory accesses.
 250         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 251         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 252         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 253         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 254         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 255         (do_vec_MUL_by_element): New function.
 256         (do_vec_op2): Call do_vec_MUL_by_element.
 257         (do_scalar_NEG): New function.
 258         (do_double_add): Call do_scalar_NEG.
 259
 260 2016-03-03  Nick Clifton  <nickc@redhat.com>
 261
 262         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 263         (CondCompare): Swap interpretation of bit 30.
 264         (DO_ADDP): Delete macro.
 265         (do_vec_ADDP): Copy source registers before starting to update
 266         destination register.
 267         (do_vec_FADDP): Likewise.
 268         (do_vec_load_store): Fix computation of sizeof_operation.
 269         (rbit64): Fix type of constant.
 270         (aarch64_step): When displaying insn value, display all 32 bits.
 271
 272 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 273
 274         * config.in, configure: Regenerate.
 275
 276 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 277
 278         * configure: Regenerate.
 279
 280 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 281
 282         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 283         * configure: Regenerate.
 284
 285 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 286
 287         * configure: Regenerate.
 288
 289 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 290
 291         * configure: Regenerate.
 292
 293 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 294
 295         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 296         * configure: Regenerate.
 297
 298 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 299
 300         * configure: Regenerate.
 301
 302 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 303
 304         * configure: Regenerate.
 305
 306 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 307
 308         * config.in, configure: Regenerate.
 309
 310 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 311
 312         * interp.c (sim_create_inferior): Mark argv and env const.
 313         (sim_open): Mark argv const.
 314
 315 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 316
 317         * interp.c: Delete dis-asm.h include.
 318         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 319         (sim_create_inferior): Delete disassemble init logic.
 320         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 321         (sim_open): Delete sim_add_option_table call.
 322         * memory.c (mem_error): Delete disas check.
 323         * simulator.c: Delete dis-asm.h include.
 324         (disas): Delete.
 325         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 326         (HALT_NYI): Likewise.
 327         (handle_halt): Delete disas call.
 328         (aarch64_step): Replace disas logic with TRACE_DISASM.
 329         * simulator.h: Delete dis-asm.h include.
 330         (aarch64_print_insn): Delete.
 331
 332 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 333
 334         * simulator.c (MAX, MIN): Delete.
 335         (do_vec_maxv): Change MAX to max and MIN to min.
 336         (do_vec_fminmaxV): Likewise.
 337
 338 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 339
 340         * simulator.c: Remove syscall.h include.
 341
 342 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 343
 344         * configure: Regenerate.
 345
 346 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 347
 348         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 349         * configure: Regenerate.
 350
 351 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 352
 353         * configure: Regenerate.
 354
 355 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 356
 357         * interp.c (sim_dis_read): Change private_data to application_data.
 358         (sim_create_inferior): Likewise.
 359
 360 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 361
 362         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 363
 364 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 365
 366         * config.in, configure: Regenerate.
 367
 368 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 369
 370         * interp.c (sim_create_inferior): Update comment and argv check.
 371
 372 2015-12-14  Nick Clifton  <nickc@redhat.com>
 373
 374         * simulator.c (system_get): New function.  Provides read
 375         access to the dczid system register.
 376         (do_mrs): New function - implements the MRS instruction.
 377         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 378         unimplemented system instructions.
 379
 380 2015-11-24  Nick Clifton  <nickc@redhat.com>
 381
 382         * configure.ac: New configure template.
 383         * aclocal.m4: Generate.
 384         * config.in: Generate.
 385         * configure: Generate.
 386         * cpustate.c: New file - functions for accessing AArch64 registers.
 387         * cpustate.h: New header.
 388         * decode.h: New header.
 389         * interp.c: New file - interface between GDB and simulator.
 390         * Makefile.in: New makefile template.
 391         * memory.c: New file - functions for simulating aarch64 memory
 392         accesses.
 393         * memory.h: New header.
 394         * sim-main.h: New header.
 395         * simulator.c: New file - aarch64 simulator functions.
 396         * simulator.h: New header.