sim/aarch64/ChangeLog

   1 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
   2
   3         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
   4         flag check.
   5
   6 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
   7
   8         * simulator.c (mul64hi): Shift carry left by 32.
   9         (smulh): Change signum to negate.  If negate, invert result, and add
  10         carry bit if low part of multiply result is zero.
  11
  12 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
  13
  14         * simulator.c (do_vec_SMOV_into_scalar): New.
  15         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
  16         Rewritten.
  17         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
  18         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
  19         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
  20         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
  21
  22         * simulator.c (popcount): New.
  23         (do_vec_CNT): New.
  24         (do_vec_op1): Add do_vec_CNT call.
  25
  26 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
  27
  28         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
  29         with type set to input type size.
  30         (do_vec_xtl): Change bias from 3 to 4 for byte case.
  31
  32 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
  33
  34         * simulator.c (do_vec_MLA): Rewrite switch body.
  35
  36         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
  37         2.  Move test_false if inside loop.  Fix logic for computing result
  38         stored to vd.
  39
  40         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
  41         (do_vec_LDn_single, do_vec_STn_single): New.
  42         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
  43         loop over nregs using new var n.  Add n times size to address in loop.
  44         Add n to vd in loop.
  45         (do_vec_load_store): Add comment for instruction bit 24.  New var
  46         single to hold instruction bit 24.  Add new code to use single.  Move
  47         ldnr support inside single if statements.  Fix ldnr register counts
  48         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
  49
  50 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
  51
  52         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
  53
  54 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
  55
  56         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
  57         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
  58         case 3, call HALT_UNALLOC unconditionally.
  59         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
  60         i + 2.  Delete if on bias, change index to i + bias * X.
  61
  62 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
  63
  64         * simulator.c (do_vec_UZP): Rewrite.
  65
  66 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
  67
  68         * cpustate.c: Include math.h.
  69         (aarch64_set_FP_float): Use signbit to check for signed zero.
  70         (aarch64_set_FP_double): Likewise.
  71         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
  72         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
  73         args same size as third arg.
  74         (fmaxnm): Use isnan instead of fpclassify.
  75         (fminnm, dmaxnm, dminnm): Likewise.
  76         (do_vec_MLS): Reverse order of subtraction operands.
  77         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
  78         aarch64_get_FP_float to get source register contents.
  79         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
  80         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
  81         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
  82         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
  83         raise_exception calls.
  84
  85 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
  86
  87         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
  88         Add comment to document NaN issue.
  89         (set_flags_for_double_compare): Likewise.
  90
  91 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
  92
  93         * simulator.c (NEG, POS): Move before set_flags_for_add64.
  94         (set_flags_for_add64): Replace with a modified copy of
  95         set_flags_for_sub64.
  96
  97 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
  98
  99         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 100         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 101
 102 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 103
 104         * simulator.c (fsturs): Switch use of rn and st variables.
 105         (fsturd, fsturq): Likewise
 106
 107 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 108
 109         * interp.c: Include bfd.h.
 110         (symcount, symtab, aarch64_get_sym_value): Delete.
 111         (remove_useless_symbols): Change count type to long.
 112         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 113         and symtab local variables.
 114         (sim_create_inferior): Delete storage.  Replace symbol code
 115         with a call to trace_load_symbols.
 116         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 117         includes.
 118         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 119         trace_sym_value.
 120         * memory.h: Delete bfd.h include.
 121         (mem_add_blk): Delete unused prototype.
 122         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 123         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 124         (aarch64_get_sym_value): Delete.
 125
 126 2016-08-12  Nick Clifton  <nickc@redhat.com>
 127
 128         * simulator.c (aarch64_step): Revert pervious delta.
 129         (aarch64_run): Call sim_events_tick after each
 130         instruction is simulated, and if necessary call
 131         sim_events_process.
 132         * simulator.h: Revert previous delta.
 133
 134 2016-08-11  Nick Clifton  <nickc@redhat.com>
 135
 136         * interp.c (sim_create_inferior): Allow for being called with a
 137         NULL abfd parameter.  If a bfd is provided, initialise the sim
 138         with that start address.
 139         * simulator.c (HALT_NYI): Just print out the numeric value of the
 140         instruction when not tracing.
 141         (aarch64_step): Change from static to global.
 142         * simulator.h: Add a prototype for aarch64_step().
 143
 144 2016-07-27  Alan Modra  <amodra@gmail.com>
 145
 146         * memory.c: Don't include libbfd.h.
 147
 148 2016-07-21  Nick Clifton  <nickc@redhat.com>
 149
 150         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 151
 152 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 153
 154         * cpustate.h: Include config.h.
 155         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 156         use anonymous structs to align members.
 157         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 158         endian_le2h_4 to read instruction from pc.
 159
 160 2016-05-06  Nick Clifton  <nickc@redhat.com>
 161
 162         * simulator.c (do_FMLA_by_element): New function.
 163         (do_vec_op2): Call it.
 164
 165 2016-04-27  Nick Clifton  <nickc@redhat.com>
 166
 167         * simulator.c: Add TRACE_DECODE statements to all emulation
 168         functions.
 169
 170 2016-03-30  Nick Clifton  <nickc@redhat.com>
 171
 172         * cpustate.c (aarch64_set_reg_s32): New function.
 173         (aarch64_set_reg_u32): New function.
 174         (aarch64_get_FP_half): Place half precision value into the correct
 175         slot of the union.
 176         (aarch64_set_FP_half): Likewise.
 177         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 178         aarch64_set_reg_u32.
 179         * memory.c (FETCH_FUNC): Cast the read value to the access type
 180         before converting it to the return type.  Rename to FETCH_FUNC64.
 181         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 182         accesses.  Use for 32-bit memory access functions.
 183         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 184         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 185         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 186         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 187         (ldrh32_abs): Store 32 bit value not 64-bits.
 188         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 189         (do_vec_MOV_immediate): Fix computation of val.
 190         (do_vec_MVNI): Likewise.
 191         (DO_VEC_WIDENING_MUL): New macro.
 192         (do_vec_mull): Use new macro.
 193         (do_vec_mul): Use new macro.
 194         (do_vec_MLA): Read values before writing.
 195         (do_vec_xtl): Likewise.
 196         (do_vec_SSHL): Select correct shift value.
 197         (do_vec_USHL): Likewise.
 198         (do_scalar_UCVTF): New function.
 199         (do_scalar_vec): Call new function.
 200         (store_pair_u64): Treat reads of SP as reads of XZR.
 201
 202 2016-03-29  Nick Clifton  <nickc@redhat.com>
 203
 204         * cpustate.c: Remove space after asterisk in function parameters.
 205         * decode.h (greg): Delete unused function.
 206         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 207         * simulator.c: Use INSTR macro in more places.
 208         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 209         Remove extraneous whitespace.
 210
 211 2016-03-23  Nick Clifton  <nickc@redhat.com>
 212
 213         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 214         register as a half precision floating point number.
 215         (aarch64_set_FP_half): New function.  Similar, but for setting
 216         a half precision register.
 217         (aarch64_get_thread_id): New function.  Returns the value of the
 218         CPU's TPIDR register.
 219         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 220         floating point control register.
 221         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 222         register.
 223         * cpustate.h: Add prototypes for new functions.
 224         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 225         * memory.c: Use unaligned core access functions for all memory
 226         reads and writes.
 227         * simulator.c (HALT_NYI): Generate an error message if tracing
 228         will not tell the user why the simulator is halting.
 229         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 230         (INSTR): New time-saver macro.
 231         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 232         offset.
 233         (fldrh_abs): New function.  Likewise for 16-bit values.
 234         (do_vec_SSHL): Allow for negative shift values.
 235         (do_vec_USHL): Likewise.
 236         (do_vec_SHL): Correct computation of shift amount.
 237         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 238         shifts and computation of shift value.
 239         (clz): New function.  Counts leading zero bits.
 240         (do_vec_CLZ): New function.  Implements CLZ (vector).
 241         (do_vec_MOV_element): Call do_vec_CLZ.
 242         (dexSimpleFPCondCompare): Implement.
 243         (do_FCVT_half_to_single): New function.  Implements one of the
 244         FCVT operations.
 245         (do_FCVT_half_to_double): New function.  Likewise.
 246         (do_FCVT_single_to_half): New function.  Likewise.
 247         (do_FCVT_double_to_half): New function.  Likewise.
 248         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 249         (do_scalar_SHL): Handle negative shifts.
 250         (do_scalar_shift): Handle SSHR.
 251         (do_scalar_USHL): New function.
 252         (do_double_add): Simplify to just performing a double precision
 253         add operation.  Move remaining code into...
 254         (do_scalar_vec): ... New function.
 255         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 256         functions.
 257         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 258         registers.
 259         (system_set): New function.
 260         (do_MSR_immediate): New function.  Stub for now.
 261         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 262         instruction.
 263         (do_SYS): New function.  Stub for now,
 264         (dexSystem): Call new functions.
 265
 266 2016-03-18  Nick Clifton  <nickc@redhat.com>
 267
 268         * cpustate.c: Remove spurious spaces from TRACE strings.
 269         Print hex equivalents of floats and doubles.
 270         Check element number against array size when accessing vector
 271         registers.
 272         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 273         element index.
 274         (SET_VEC_ELEMENT): Likewise.
 275         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 276
 277         * memory.c: Trace memory reads when --trace-memory is enabled.
 278         Remove float and double load and store functions.
 279         * memory.h (aarch64_get_mem_float): Delete prototype.
 280         (aarch64_get_mem_double): Likewise.
 281         (aarch64_set_mem_float): Likewise.
 282         (aarch64_set_mem_double): Likewise.
 283         * simulator (IS_SET): Always return either 0 or 1.
 284         (IS_CLEAR): Likewise.
 285         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 286         and doubles using 64-bit memory accesses.
 287         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 288         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 289         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 290         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 291         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 292         (do_vec_MUL_by_element): New function.
 293         (do_vec_op2): Call do_vec_MUL_by_element.
 294         (do_scalar_NEG): New function.
 295         (do_double_add): Call do_scalar_NEG.
 296
 297 2016-03-03  Nick Clifton  <nickc@redhat.com>
 298
 299         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 300         (CondCompare): Swap interpretation of bit 30.
 301         (DO_ADDP): Delete macro.
 302         (do_vec_ADDP): Copy source registers before starting to update
 303         destination register.
 304         (do_vec_FADDP): Likewise.
 305         (do_vec_load_store): Fix computation of sizeof_operation.
 306         (rbit64): Fix type of constant.
 307         (aarch64_step): When displaying insn value, display all 32 bits.
 308
 309 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 310
 311         * config.in, configure: Regenerate.
 312
 313 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 314
 315         * configure: Regenerate.
 316
 317 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 318
 319         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 320         * configure: Regenerate.
 321
 322 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 323
 324         * configure: Regenerate.
 325
 326 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 327
 328         * configure: Regenerate.
 329
 330 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 331
 332         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 333         * configure: Regenerate.
 334
 335 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 336
 337         * configure: Regenerate.
 338
 339 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 340
 341         * configure: Regenerate.
 342
 343 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 344
 345         * config.in, configure: Regenerate.
 346
 347 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 348
 349         * interp.c (sim_create_inferior): Mark argv and env const.
 350         (sim_open): Mark argv const.
 351
 352 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 353
 354         * interp.c: Delete dis-asm.h include.
 355         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 356         (sim_create_inferior): Delete disassemble init logic.
 357         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 358         (sim_open): Delete sim_add_option_table call.
 359         * memory.c (mem_error): Delete disas check.
 360         * simulator.c: Delete dis-asm.h include.
 361         (disas): Delete.
 362         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 363         (HALT_NYI): Likewise.
 364         (handle_halt): Delete disas call.
 365         (aarch64_step): Replace disas logic with TRACE_DISASM.
 366         * simulator.h: Delete dis-asm.h include.
 367         (aarch64_print_insn): Delete.
 368
 369 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 370
 371         * simulator.c (MAX, MIN): Delete.
 372         (do_vec_maxv): Change MAX to max and MIN to min.
 373         (do_vec_fminmaxV): Likewise.
 374
 375 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 376
 377         * simulator.c: Remove syscall.h include.
 378
 379 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 380
 381         * configure: Regenerate.
 382
 383 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 384
 385         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 386         * configure: Regenerate.
 387
 388 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 389
 390         * configure: Regenerate.
 391
 392 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 393
 394         * interp.c (sim_dis_read): Change private_data to application_data.
 395         (sim_create_inferior): Likewise.
 396
 397 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 398
 399         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 400
 401 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 402
 403         * config.in, configure: Regenerate.
 404
 405 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 406
 407         * interp.c (sim_create_inferior): Update comment and argv check.
 408
 409 2015-12-14  Nick Clifton  <nickc@redhat.com>
 410
 411         * simulator.c (system_get): New function.  Provides read
 412         access to the dczid system register.
 413         (do_mrs): New function - implements the MRS instruction.
 414         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 415         unimplemented system instructions.
 416
 417 2015-11-24  Nick Clifton  <nickc@redhat.com>
 418
 419         * configure.ac: New configure template.
 420         * aclocal.m4: Generate.
 421         * config.in: Generate.
 422         * configure: Generate.
 423         * cpustate.c: New file - functions for accessing AArch64 registers.
 424         * cpustate.h: New header.
 425         * decode.h: New header.
 426         * interp.c: New file - interface between GDB and simulator.
 427         * Makefile.in: New makefile template.
 428         * memory.c: New file - functions for simulating aarch64 memory
 429         accesses.
 430         * memory.h: New header.
 431         * sim-main.h: New header.
 432         * simulator.c: New file - aarch64 simulator functions.
 433         * simulator.h: New header.