1 /* cpustate.h -- Prototypes for AArch64 simulator functions.
3 Copyright (C) 2015-2016 Free Software Foundation, Inc.
5 Contributed by Red Hat.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "simulator.h"
28 /* Some operands are allowed to access the stack pointer (reg 31).
29 For others a read from r31 always returns 0, and a write to r31 is ignored. */
30 #define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg))
33 aarch64_set_reg_u64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
, uint64_t val
)
35 if (reg
== R31
&& ! r31_is_sp
)
37 TRACE_REGISTER (cpu
, "GR[31] NOT CHANGED!");
41 if (val
!= cpu
->gr
[reg
].u64
)
43 "GR[%2d] changes from %16" PRIx64
" to %16" PRIx64
,
44 reg
, cpu
->gr
[reg
].u64
, val
);
46 cpu
->gr
[reg
].u64
= val
;
50 aarch64_set_reg_s64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
, int64_t val
)
52 if (reg
== R31
&& ! r31_is_sp
)
54 TRACE_REGISTER (cpu
, "GR[31] NOT CHANGED!");
58 if (val
!= cpu
->gr
[reg
].s64
)
60 "GR[%2d] changes from %16" PRIx64
" to %16" PRIx64
,
61 reg
, cpu
->gr
[reg
].s64
, val
);
63 cpu
->gr
[reg
].s64
= val
;
67 aarch64_get_reg_u64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
69 return cpu
->gr
[reg_num(reg
)].u64
;
73 aarch64_get_reg_s64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
75 return cpu
->gr
[reg_num(reg
)].s64
;
79 aarch64_get_reg_u32 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
81 return cpu
->gr
[reg_num(reg
)].u32
;
85 aarch64_get_reg_s32 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
87 return cpu
->gr
[reg_num(reg
)].s32
;
91 aarch64_set_reg_s32 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
, int32_t val
)
93 if (reg
== R31
&& ! r31_is_sp
)
95 TRACE_REGISTER (cpu
, "GR[31] NOT CHANGED!");
99 if (val
!= cpu
->gr
[reg
].s32
)
100 TRACE_REGISTER (cpu
, "GR[%2d] changes from %8x to %8x",
101 reg
, cpu
->gr
[reg
].s32
, val
);
103 /* The ARM ARM states that (C1.2.4):
104 When the data size is 32 bits, the lower 32 bits of the
105 register are used and the upper 32 bits are ignored on
106 a read and cleared to zero on a write.
107 We simulate this by first clearing the whole 64-bits and
108 then writing to the 32-bit value in the GRegister union. */
109 cpu
->gr
[reg
].s64
= 0;
110 cpu
->gr
[reg
].s32
= val
;
114 aarch64_set_reg_u32 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
, uint32_t val
)
116 if (reg
== R31
&& ! r31_is_sp
)
118 TRACE_REGISTER (cpu
, "GR[31] NOT CHANGED!");
122 if (val
!= cpu
->gr
[reg
].u32
)
123 TRACE_REGISTER (cpu
, "GR[%2d] changes from %8x to %8x",
124 reg
, cpu
->gr
[reg
].u32
, val
);
126 cpu
->gr
[reg
].u64
= 0;
127 cpu
->gr
[reg
].u32
= val
;
131 aarch64_get_reg_u16 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
133 return cpu
->gr
[reg_num(reg
)].u16
;
137 aarch64_get_reg_s16 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
139 return cpu
->gr
[reg_num(reg
)].s16
;
143 aarch64_get_reg_u8 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
145 return cpu
->gr
[reg_num(reg
)].u8
;
149 aarch64_get_reg_s8 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
151 return cpu
->gr
[reg_num(reg
)].s8
;
155 aarch64_get_PC (sim_cpu
*cpu
)
161 aarch64_get_next_PC (sim_cpu
*cpu
)
167 aarch64_set_next_PC (sim_cpu
*cpu
, uint64_t next
)
169 if (next
!= cpu
->nextpc
+ 4)
171 "NextPC changes from %16" PRIx64
" to %16" PRIx64
,
178 aarch64_set_next_PC_by_offset (sim_cpu
*cpu
, int64_t offset
)
180 if (cpu
->pc
+ offset
!= cpu
->nextpc
+ 4)
182 "NextPC changes from %16" PRIx64
" to %16" PRIx64
,
183 cpu
->nextpc
, cpu
->pc
+ offset
);
185 cpu
->nextpc
= cpu
->pc
+ offset
;
188 /* Install nextpc as current pc. */
190 aarch64_update_PC (sim_cpu
*cpu
)
192 cpu
->pc
= cpu
->nextpc
;
193 /* Rezero the register we hand out when asked for ZR just in case it
194 was used as the destination for a write by the previous
196 cpu
->gr
[32].u64
= 0UL;
199 /* This instruction can be used to save the next PC to LR
200 just before installing a branch PC. */
202 aarch64_save_LR (sim_cpu
*cpu
)
204 if (cpu
->gr
[LR
].u64
!= cpu
->nextpc
)
206 "LR changes from %16" PRIx64
" to %16" PRIx64
,
207 cpu
->gr
[LR
].u64
, cpu
->nextpc
);
209 cpu
->gr
[LR
].u64
= cpu
->nextpc
;
213 decode_cpsr (FlagMask flags
)
215 switch (flags
& CPSR_ALL_FLAGS
)
218 case 0: return "----";
219 case 1: return "---V";
220 case 2: return "--C-";
221 case 3: return "--CV";
222 case 4: return "-Z--";
223 case 5: return "-Z-V";
224 case 6: return "-ZC-";
225 case 7: return "-ZCV";
226 case 8: return "N---";
227 case 9: return "N--V";
228 case 10: return "N-C-";
229 case 11: return "N-CV";
230 case 12: return "NZ--";
231 case 13: return "NZ-V";
232 case 14: return "NZC-";
233 case 15: return "NZCV";
237 /* Retrieve the CPSR register as an int. */
239 aarch64_get_CPSR (sim_cpu
*cpu
)
244 /* Set the CPSR register as an int. */
246 aarch64_set_CPSR (sim_cpu
*cpu
, uint32_t new_flags
)
248 if (TRACE_REGISTER_P (cpu
))
250 if (cpu
->CPSR
!= new_flags
)
252 "CPSR changes from %s to %s",
253 decode_cpsr (cpu
->CPSR
), decode_cpsr (new_flags
));
256 "CPSR stays at %s", decode_cpsr (cpu
->CPSR
));
259 cpu
->CPSR
= new_flags
& CPSR_ALL_FLAGS
;
262 /* Read a specific subset of the CPSR as a bit pattern. */
264 aarch64_get_CPSR_bits (sim_cpu
*cpu
, FlagMask mask
)
266 return cpu
->CPSR
& mask
;
269 /* Assign a specific subset of the CPSR as a bit pattern. */
271 aarch64_set_CPSR_bits (sim_cpu
*cpu
, uint32_t mask
, uint32_t value
)
273 uint32_t old_flags
= cpu
->CPSR
;
275 mask
&= CPSR_ALL_FLAGS
;
277 cpu
->CPSR
|= (value
& mask
);
279 if (old_flags
!= cpu
->CPSR
)
281 "CPSR changes from %s to %s",
282 decode_cpsr (old_flags
), decode_cpsr (cpu
->CPSR
));
285 /* Test the value of a single CPSR returned as non-zero or zero. */
287 aarch64_test_CPSR_bit (sim_cpu
*cpu
, FlagMask bit
)
289 return cpu
->CPSR
& bit
;
292 /* Set a single flag in the CPSR. */
294 aarch64_set_CPSR_bit (sim_cpu
*cpu
, FlagMask bit
)
296 uint32_t old_flags
= cpu
->CPSR
;
298 cpu
->CPSR
|= (bit
& CPSR_ALL_FLAGS
);
300 if (old_flags
!= cpu
->CPSR
)
302 "CPSR changes from %s to %s",
303 decode_cpsr (old_flags
), decode_cpsr (cpu
->CPSR
));
306 /* Clear a single flag in the CPSR. */
308 aarch64_clear_CPSR_bit (sim_cpu
*cpu
, FlagMask bit
)
310 uint32_t old_flags
= cpu
->CPSR
;
312 cpu
->CPSR
&= ~(bit
& CPSR_ALL_FLAGS
);
314 if (old_flags
!= cpu
->CPSR
)
316 "CPSR changes from %s to %s",
317 decode_cpsr (old_flags
), decode_cpsr (cpu
->CPSR
));
321 aarch64_get_FP_half (sim_cpu
*cpu
, VReg reg
)
330 u
.h
[1] = cpu
->fr
[reg
].h
[0];
336 aarch64_get_FP_float (sim_cpu
*cpu
, VReg reg
)
338 return cpu
->fr
[reg
].s
;
342 aarch64_get_FP_double (sim_cpu
*cpu
, VReg reg
)
344 return cpu
->fr
[reg
].d
;
348 aarch64_get_FP_long_double (sim_cpu
*cpu
, VReg reg
, FRegister
*a
)
350 a
->v
[0] = cpu
->fr
[reg
].v
[0];
351 a
->v
[1] = cpu
->fr
[reg
].v
[1];
355 aarch64_set_FP_half (sim_cpu
*cpu
, VReg reg
, float val
)
364 cpu
->fr
[reg
].h
[0] = u
.h
[1];
365 cpu
->fr
[reg
].h
[1] = 0;
370 aarch64_set_FP_float (sim_cpu
*cpu
, VReg reg
, float val
)
372 if (val
!= cpu
->fr
[reg
].s
)
378 "FR[%d].s changes from %f to %f [hex: %0lx]",
379 reg
, cpu
->fr
[reg
].s
, val
, v
.v
[0]);
382 cpu
->fr
[reg
].s
= val
;
386 aarch64_set_FP_double (sim_cpu
*cpu
, VReg reg
, double val
)
388 if (val
!= cpu
->fr
[reg
].d
)
394 "FR[%d].d changes from %f to %f [hex: %0lx]",
395 reg
, cpu
->fr
[reg
].d
, val
, v
.v
[0]);
397 cpu
->fr
[reg
].d
= val
;
401 aarch64_set_FP_long_double (sim_cpu
*cpu
, VReg reg
, FRegister a
)
403 if (cpu
->fr
[reg
].v
[0] != a
.v
[0]
404 || cpu
->fr
[reg
].v
[1] != a
.v
[1])
406 "FR[%d].q changes from [%0lx %0lx] to [%0lx %0lx] ",
408 cpu
->fr
[reg
].v
[0], cpu
->fr
[reg
].v
[1],
411 cpu
->fr
[reg
].v
[0] = a
.v
[0];
412 cpu
->fr
[reg
].v
[1] = a
.v
[1];
415 #define GET_VEC_ELEMENT(REG, ELEMENT, FIELD) \
418 if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
420 TRACE_REGISTER (cpu, \
421 "Internal SIM error: invalid element number: %d ",\
423 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
424 sim_stopped, SIM_SIGBUS); \
426 return cpu->fr[REG].FIELD [ELEMENT]; \
431 aarch64_get_vec_u64 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
433 GET_VEC_ELEMENT (reg
, element
, v
);
437 aarch64_get_vec_u32 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
439 GET_VEC_ELEMENT (reg
, element
, w
);
443 aarch64_get_vec_u16 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
445 GET_VEC_ELEMENT (reg
, element
, h
);
449 aarch64_get_vec_u8 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
451 GET_VEC_ELEMENT (reg
, element
, b
);
455 aarch64_get_vec_s64 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
457 GET_VEC_ELEMENT (reg
, element
, V
);
461 aarch64_get_vec_s32 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
463 GET_VEC_ELEMENT (reg
, element
, W
);
467 aarch64_get_vec_s16 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
469 GET_VEC_ELEMENT (reg
, element
, H
);
473 aarch64_get_vec_s8 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
475 GET_VEC_ELEMENT (reg
, element
, B
);
479 aarch64_get_vec_float (sim_cpu
*cpu
, VReg reg
, unsigned element
)
481 GET_VEC_ELEMENT (reg
, element
, S
);
485 aarch64_get_vec_double (sim_cpu
*cpu
, VReg reg
, unsigned element
)
487 GET_VEC_ELEMENT (reg
, element
, D
);
491 #define SET_VEC_ELEMENT(REG, ELEMENT, VAL, FIELD, PRINTER) \
494 if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
496 TRACE_REGISTER (cpu, \
497 "Internal SIM error: invalid element number: %d ",\
499 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
500 sim_stopped, SIM_SIGBUS); \
502 if (VAL != cpu->fr[REG].FIELD [ELEMENT]) \
503 TRACE_REGISTER (cpu, \
504 "VR[%2d]." #FIELD " [%d] changes from " PRINTER \
505 " to " PRINTER , REG, \
506 ELEMENT, cpu->fr[REG].FIELD [ELEMENT], VAL); \
508 cpu->fr[REG].FIELD [ELEMENT] = VAL; \
513 aarch64_set_vec_u64 (sim_cpu
*cpu
, VReg reg
, unsigned element
, uint64_t val
)
515 SET_VEC_ELEMENT (reg
, element
, val
, v
, "%16lx");
519 aarch64_set_vec_u32 (sim_cpu
*cpu
, VReg reg
, unsigned element
, uint32_t val
)
521 SET_VEC_ELEMENT (reg
, element
, val
, w
, "%8x");
525 aarch64_set_vec_u16 (sim_cpu
*cpu
, VReg reg
, unsigned element
, uint16_t val
)
527 SET_VEC_ELEMENT (reg
, element
, val
, h
, "%4x");
531 aarch64_set_vec_u8 (sim_cpu
*cpu
, VReg reg
, unsigned element
, uint8_t val
)
533 SET_VEC_ELEMENT (reg
, element
, val
, b
, "%x");
537 aarch64_set_vec_s64 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int64_t val
)
539 SET_VEC_ELEMENT (reg
, element
, val
, V
, "%16lx");
543 aarch64_set_vec_s32 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int32_t val
)
545 SET_VEC_ELEMENT (reg
, element
, val
, W
, "%8x");
549 aarch64_set_vec_s16 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int16_t val
)
551 SET_VEC_ELEMENT (reg
, element
, val
, H
, "%4x");
555 aarch64_set_vec_s8 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int8_t val
)
557 SET_VEC_ELEMENT (reg
, element
, val
, B
, "%x");
561 aarch64_set_vec_float (sim_cpu
*cpu
, VReg reg
, unsigned element
, float val
)
563 SET_VEC_ELEMENT (reg
, element
, val
, S
, "%f");
567 aarch64_set_vec_double (sim_cpu
*cpu
, VReg reg
, unsigned element
, double val
)
569 SET_VEC_ELEMENT (reg
, element
, val
, D
, "%f");
573 aarch64_set_FPSR (sim_cpu
*cpu
, uint32_t value
)
575 if (cpu
->FPSR
!= value
)
577 "FPSR changes from %x to %x", cpu
->FPSR
, value
);
579 cpu
->FPSR
= value
& FPSR_ALL_FPSRS
;
583 aarch64_get_FPSR (sim_cpu
*cpu
)
589 aarch64_set_FPSR_bits (sim_cpu
*cpu
, uint32_t mask
, uint32_t value
)
591 uint32_t old_FPSR
= cpu
->FPSR
;
593 mask
&= FPSR_ALL_FPSRS
;
595 cpu
->FPSR
|= (value
& mask
);
597 if (cpu
->FPSR
!= old_FPSR
)
599 "FPSR changes from %x to %x", old_FPSR
, cpu
->FPSR
);
603 aarch64_get_FPSR_bits (sim_cpu
*cpu
, uint32_t mask
)
605 mask
&= FPSR_ALL_FPSRS
;
606 return cpu
->FPSR
& mask
;
610 aarch64_test_FPSR_bit (sim_cpu
*cpu
, FPSRMask flag
)
612 return cpu
->FPSR
& flag
;
616 aarch64_get_thread_id (sim_cpu
*cpu
)
622 aarch64_get_FPCR (sim_cpu
*cpu
)
628 aarch64_set_FPCR (sim_cpu
*cpu
, uint32_t val
)
630 if (cpu
->FPCR
!= val
)
632 "FPCR changes from %x to %x", cpu
->FPCR
, val
);
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