1 /* cpustate.h -- Prototypes for AArch64 simulator functions.
3 Copyright (C) 2015-2016 Free Software Foundation, Inc.
5 Contributed by Red Hat.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "simulator.h"
28 /* Some operands are allowed to access the stack pointer (reg 31).
29 For others a read from r31 always returns 0, and a write to r31 is ignored. */
30 #define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg))
33 aarch64_set_reg_u64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
, uint64_t val
)
35 if (reg
== R31
&& ! r31_is_sp
)
37 TRACE_REGISTER (cpu
, "GR[31] NOT CHANGED!");
41 if (val
!= cpu
->gr
[reg
].u64
)
43 "GR[%2d] changes from %16" PRIx64
" to %16" PRIx64
,
44 reg
, cpu
->gr
[reg
].u64
, val
);
46 cpu
->gr
[reg
].u64
= val
;
50 aarch64_set_reg_s64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
, int64_t val
)
52 if (reg
== R31
&& ! r31_is_sp
)
54 TRACE_REGISTER (cpu
, "GR[31] NOT CHANGED!");
58 if (val
!= cpu
->gr
[reg
].s64
)
60 "GR[%2d] changes from %16" PRIx64
" to %16" PRIx64
,
61 reg
, cpu
->gr
[reg
].s64
, val
);
63 cpu
->gr
[reg
].s64
= val
;
67 aarch64_get_reg_u64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
69 return cpu
->gr
[reg_num(reg
)].u64
;
73 aarch64_get_reg_s64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
75 return cpu
->gr
[reg_num(reg
)].s64
;
79 aarch64_get_reg_u32 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
81 return cpu
->gr
[reg_num(reg
)].u32
;
85 aarch64_get_reg_s32 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
87 return cpu
->gr
[reg_num(reg
)].s32
;
91 aarch64_get_reg_u16 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
93 return cpu
->gr
[reg_num(reg
)].u16
;
97 aarch64_get_reg_s16 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
99 return cpu
->gr
[reg_num(reg
)].s16
;
103 aarch64_get_reg_u8 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
105 return cpu
->gr
[reg_num(reg
)].u8
;
109 aarch64_get_reg_s8 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
111 return cpu
->gr
[reg_num(reg
)].s8
;
115 aarch64_get_PC (sim_cpu
*cpu
)
121 aarch64_get_next_PC (sim_cpu
*cpu
)
127 aarch64_set_next_PC (sim_cpu
*cpu
, uint64_t next
)
129 if (next
!= cpu
->nextpc
+ 4)
131 "NextPC changes from %16" PRIx64
" to %16" PRIx64
,
138 aarch64_set_next_PC_by_offset (sim_cpu
*cpu
, int64_t offset
)
140 if (cpu
->pc
+ offset
!= cpu
->nextpc
+ 4)
142 "NextPC changes from %16" PRIx64
" to %16" PRIx64
,
143 cpu
->nextpc
, cpu
->pc
+ offset
);
145 cpu
->nextpc
= cpu
->pc
+ offset
;
148 /* Install nextpc as current pc. */
150 aarch64_update_PC (sim_cpu
*cpu
)
152 cpu
->pc
= cpu
->nextpc
;
153 /* Rezero the register we hand out when asked for ZR just in case it
154 was used as the destination for a write by the previous
156 cpu
->gr
[32].u64
= 0UL;
159 /* This instruction can be used to save the next PC to LR
160 just before installing a branch PC. */
162 aarch64_save_LR (sim_cpu
*cpu
)
164 if (cpu
->gr
[LR
].u64
!= cpu
->nextpc
)
166 "LR changes from %16" PRIx64
" to %16" PRIx64
,
167 cpu
->gr
[LR
].u64
, cpu
->nextpc
);
169 cpu
->gr
[LR
].u64
= cpu
->nextpc
;
173 decode_cpsr (FlagMask flags
)
175 switch (flags
& CPSR_ALL_FLAGS
)
178 case 0: return "----";
179 case 1: return "---V";
180 case 2: return "--C-";
181 case 3: return "--CV";
182 case 4: return "-Z--";
183 case 5: return "-Z-V";
184 case 6: return "-ZC-";
185 case 7: return "-ZCV";
186 case 8: return "N---";
187 case 9: return "N--V";
188 case 10: return "N-C-";
189 case 11: return "N-CV";
190 case 12: return "NZ--";
191 case 13: return "NZ-V";
192 case 14: return "NZC-";
193 case 15: return "NZCV";
197 /* Retrieve the CPSR register as an int. */
199 aarch64_get_CPSR (sim_cpu
*cpu
)
204 /* Set the CPSR register as an int. */
206 aarch64_set_CPSR (sim_cpu
*cpu
, uint32_t new_flags
)
208 if (TRACE_REGISTER_P (cpu
))
210 if (cpu
->CPSR
!= new_flags
)
212 "CPSR changes from %s to %s",
213 decode_cpsr (cpu
->CPSR
), decode_cpsr (new_flags
));
216 "CPSR stays at %s", decode_cpsr (cpu
->CPSR
));
219 cpu
->CPSR
= new_flags
& CPSR_ALL_FLAGS
;
222 /* Read a specific subset of the CPSR as a bit pattern. */
224 aarch64_get_CPSR_bits (sim_cpu
*cpu
, FlagMask mask
)
226 return cpu
->CPSR
& mask
;
229 /* Assign a specific subset of the CPSR as a bit pattern. */
231 aarch64_set_CPSR_bits (sim_cpu
*cpu
, uint32_t mask
, uint32_t value
)
233 uint32_t old_flags
= cpu
->CPSR
;
235 mask
&= CPSR_ALL_FLAGS
;
237 cpu
->CPSR
|= (value
& mask
);
239 if (old_flags
!= cpu
->CPSR
)
241 "CPSR changes from %s to %s",
242 decode_cpsr (old_flags
), decode_cpsr (cpu
->CPSR
));
245 /* Test the value of a single CPSR returned as non-zero or zero. */
247 aarch64_test_CPSR_bit (sim_cpu
*cpu
, FlagMask bit
)
249 return cpu
->CPSR
& bit
;
252 /* Set a single flag in the CPSR. */
254 aarch64_set_CPSR_bit (sim_cpu
*cpu
, FlagMask bit
)
256 uint32_t old_flags
= cpu
->CPSR
;
258 cpu
->CPSR
|= (bit
& CPSR_ALL_FLAGS
);
260 if (old_flags
!= cpu
->CPSR
)
262 "CPSR changes from %s to %s",
263 decode_cpsr (old_flags
), decode_cpsr (cpu
->CPSR
));
266 /* Clear a single flag in the CPSR. */
268 aarch64_clear_CPSR_bit (sim_cpu
*cpu
, FlagMask bit
)
270 uint32_t old_flags
= cpu
->CPSR
;
272 cpu
->CPSR
&= ~(bit
& CPSR_ALL_FLAGS
);
274 if (old_flags
!= cpu
->CPSR
)
276 "CPSR changes from %s to %s",
277 decode_cpsr (old_flags
), decode_cpsr (cpu
->CPSR
));
281 aarch64_get_FP_half (sim_cpu
*cpu
, VReg reg
)
289 u
.h
[0] = cpu
->fr
[reg
].h
[0];
296 aarch64_get_FP_float (sim_cpu
*cpu
, VReg reg
)
298 return cpu
->fr
[reg
].s
;
302 aarch64_get_FP_double (sim_cpu
*cpu
, VReg reg
)
304 return cpu
->fr
[reg
].d
;
308 aarch64_get_FP_long_double (sim_cpu
*cpu
, VReg reg
, FRegister
*a
)
310 a
->v
[0] = cpu
->fr
[reg
].v
[0];
311 a
->v
[1] = cpu
->fr
[reg
].v
[1];
315 aarch64_set_FP_half (sim_cpu
*cpu
, VReg reg
, float val
)
324 cpu
->fr
[reg
].h
[0] = u
.h
[0];
325 cpu
->fr
[reg
].h
[1] = 0;
330 aarch64_set_FP_float (sim_cpu
*cpu
, VReg reg
, float val
)
332 if (val
!= cpu
->fr
[reg
].s
)
338 "FR[%d].s changes from %f to %f [hex: %0lx]",
339 reg
, cpu
->fr
[reg
].s
, val
, v
.v
[0]);
342 cpu
->fr
[reg
].s
= val
;
346 aarch64_set_FP_double (sim_cpu
*cpu
, VReg reg
, double val
)
348 if (val
!= cpu
->fr
[reg
].d
)
354 "FR[%d].d changes from %f to %f [hex: %0lx]",
355 reg
, cpu
->fr
[reg
].d
, val
, v
.v
[0]);
357 cpu
->fr
[reg
].d
= val
;
361 aarch64_set_FP_long_double (sim_cpu
*cpu
, VReg reg
, FRegister a
)
363 if (cpu
->fr
[reg
].v
[0] != a
.v
[0]
364 || cpu
->fr
[reg
].v
[1] != a
.v
[1])
366 "FR[%d].q changes from [%0lx %0lx] to [%0lx %0lx] ",
368 cpu
->fr
[reg
].v
[0], cpu
->fr
[reg
].v
[1],
371 cpu
->fr
[reg
].v
[0] = a
.v
[0];
372 cpu
->fr
[reg
].v
[1] = a
.v
[1];
375 #define GET_VEC_ELEMENT(REG, ELEMENT, FIELD) \
378 if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
380 TRACE_REGISTER (cpu, \
381 "Internal SIM error: invalid element number: %d ",\
383 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
384 sim_stopped, SIM_SIGBUS); \
386 return cpu->fr[REG].FIELD [ELEMENT]; \
391 aarch64_get_vec_u64 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
393 GET_VEC_ELEMENT (reg
, element
, v
);
397 aarch64_get_vec_u32 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
399 GET_VEC_ELEMENT (reg
, element
, w
);
403 aarch64_get_vec_u16 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
405 GET_VEC_ELEMENT (reg
, element
, h
);
409 aarch64_get_vec_u8 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
411 GET_VEC_ELEMENT (reg
, element
, b
);
415 aarch64_get_vec_s64 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
417 GET_VEC_ELEMENT (reg
, element
, V
);
421 aarch64_get_vec_s32 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
423 GET_VEC_ELEMENT (reg
, element
, W
);
427 aarch64_get_vec_s16 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
429 GET_VEC_ELEMENT (reg
, element
, H
);
433 aarch64_get_vec_s8 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
435 GET_VEC_ELEMENT (reg
, element
, B
);
439 aarch64_get_vec_float (sim_cpu
*cpu
, VReg reg
, unsigned element
)
441 GET_VEC_ELEMENT (reg
, element
, S
);
445 aarch64_get_vec_double (sim_cpu
*cpu
, VReg reg
, unsigned element
)
447 GET_VEC_ELEMENT (reg
, element
, D
);
451 #define SET_VEC_ELEMENT(REG, ELEMENT, VAL, FIELD, PRINTER) \
454 if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
456 TRACE_REGISTER (cpu, \
457 "Internal SIM error: invalid element number: %d ",\
459 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
460 sim_stopped, SIM_SIGBUS); \
462 if (VAL != cpu->fr[REG].FIELD [ELEMENT]) \
463 TRACE_REGISTER (cpu, \
464 "VR[%2d]." #FIELD " [%d] changes from " PRINTER \
465 " to " PRINTER , REG, \
466 ELEMENT, cpu->fr[REG].FIELD [ELEMENT], VAL); \
468 cpu->fr[REG].FIELD [ELEMENT] = VAL; \
473 aarch64_set_vec_u64 (sim_cpu
* cpu
, VReg reg
, unsigned element
, uint64_t val
)
475 SET_VEC_ELEMENT (reg
, element
, val
, v
, "%16lx");
479 aarch64_set_vec_u32 (sim_cpu
* cpu
, VReg reg
, unsigned element
, uint32_t val
)
481 SET_VEC_ELEMENT (reg
, element
, val
, w
, "%8x");
485 aarch64_set_vec_u16 (sim_cpu
* cpu
, VReg reg
, unsigned element
, uint16_t val
)
487 SET_VEC_ELEMENT (reg
, element
, val
, h
, "%4x");
491 aarch64_set_vec_u8 (sim_cpu
* cpu
, VReg reg
, unsigned element
, uint8_t val
)
493 SET_VEC_ELEMENT (reg
, element
, val
, b
, "%x");
497 aarch64_set_vec_s64 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int64_t val
)
499 SET_VEC_ELEMENT (reg
, element
, val
, V
, "%16lx");
503 aarch64_set_vec_s32 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int32_t val
)
505 SET_VEC_ELEMENT (reg
, element
, val
, W
, "%8x");
509 aarch64_set_vec_s16 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int16_t val
)
511 SET_VEC_ELEMENT (reg
, element
, val
, H
, "%4x");
515 aarch64_set_vec_s8 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int8_t val
)
517 SET_VEC_ELEMENT (reg
, element
, val
, B
, "%x");
521 aarch64_set_vec_float (sim_cpu
*cpu
, VReg reg
, unsigned element
, float val
)
523 SET_VEC_ELEMENT (reg
, element
, val
, S
, "%f");
527 aarch64_set_vec_double (sim_cpu
*cpu
, VReg reg
, unsigned element
, double val
)
529 SET_VEC_ELEMENT (reg
, element
, val
, D
, "%f");
533 aarch64_set_FPSR (sim_cpu
*cpu
, uint32_t value
)
535 if (cpu
->FPSR
!= value
)
537 "FPSR changes from %x to %x", cpu
->FPSR
, value
);
539 cpu
->FPSR
= value
& FPSR_ALL_FPSRS
;
543 aarch64_get_FPSR (sim_cpu
*cpu
)
549 aarch64_set_FPSR_bits (sim_cpu
*cpu
, uint32_t mask
, uint32_t value
)
551 uint32_t old_FPSR
= cpu
->FPSR
;
553 mask
&= FPSR_ALL_FPSRS
;
555 cpu
->FPSR
|= (value
& mask
);
557 if (cpu
->FPSR
!= old_FPSR
)
559 "FPSR changes from %x to %x", old_FPSR
, cpu
->FPSR
);
563 aarch64_get_FPSR_bits (sim_cpu
*cpu
, uint32_t mask
)
565 mask
&= FPSR_ALL_FPSRS
;
566 return cpu
->FPSR
& mask
;
570 aarch64_test_FPSR_bit (sim_cpu
*cpu
, FPSRMask flag
)
572 return cpu
->FPSR
& flag
;
576 aarch64_get_thread_id (sim_cpu
* cpu
)
582 aarch64_get_FPCR (sim_cpu
* cpu
)
588 aarch64_set_FPCR (sim_cpu
* cpu
, uint32_t val
)
590 if (cpu
->FPCR
!= val
)
592 "FPCR changes from %x to %x", cpu
->FPCR
, val
);
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