sim/arm/armcopro.c

   1 /*  armcopro.c -- co-processor interface:  ARM6 Instruction Emulator.
   2     Copyright (C) 1994, 2000 Advanced RISC Machines Ltd.
   3
   4     This program is free software; you can redistribute it and/or modify
   5     it under the terms of the GNU General Public License as published by
   6     the Free Software Foundation; either version 2 of the License, or
   7     (at your option) any later version.
   8
   9     This program is distributed in the hope that it will be useful,
  10     but WITHOUT ANY WARRANTY; without even the implied warranty of
  11     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12     GNU General Public License for more details.
  13
  14     You should have received a copy of the GNU General Public License
  15     along with this program; if not, write to the Free Software
  16     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  17
  18 #include "armdefs.h"
  19 #include "armemu.h"
  20 #include "ansidecl.h"
  21
  22 extern unsigned ARMul_CoProInit (ARMul_State * state);
  23 extern void ARMul_CoProExit (ARMul_State * state);
  24 extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
  25                                ARMul_CPInits * init, ARMul_CPExits * exit,
  26                                ARMul_LDCs * ldc, ARMul_STCs * stc,
  27                                ARMul_MRCs * mrc, ARMul_MCRs * mcr,
  28                                ARMul_CDPs * cdp,
  29                                ARMul_CPReads * read, ARMul_CPWrites * write);
  30 extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
  31
  32
  33 /***************************************************************************\
  34 *                            Dummy Co-processors                            *
  35 \***************************************************************************/
  36
  37 static unsigned NoCoPro3R (ARMul_State * state, unsigned, ARMword);
  38 static unsigned NoCoPro4R (ARMul_State * state, unsigned, ARMword, ARMword);
  39 static unsigned NoCoPro4W (ARMul_State * state, unsigned, ARMword, ARMword *);
  40
  41 /***************************************************************************\
  42 *                Define Co-Processor instruction handlers here              *
  43 \***************************************************************************/
  44
  45 /* Here's ARMulator's MMU definition.  A few things to note:
  46 1) it has eight registers, but only two are defined.
  47 2) you can only access its registers with MCR and MRC.
  48 3) MMU Register 0 (ID) returns 0x41440110
  49 4) Register 1 only has 4 bits defined.  Bits 0 to 3 are unused, bit 4
  50 controls 32/26 bit program space, bit 5 controls 32/26 bit data space,
  51 bit 6 controls late abort timimg and bit 7 controls big/little endian.
  52 */
  53
  54 static ARMword MMUReg[8];
  55
  56 static unsigned
  57 MMUInit (ARMul_State * state)
  58 {
  59   MMUReg[1] = state->prog32Sig << 4 |
  60     state->data32Sig << 5 | state->lateabtSig << 6 | state->bigendSig << 7;
  61   ARMul_ConsolePrint (state, ", MMU present");
  62   return (TRUE);
  63 }
  64
  65 static unsigned
  66 MMUMRC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value)
  67 {
  68   int reg = BITS (16, 19) & 7;
  69
  70   if (reg == 0)
  71     *value = 0x41440110;
  72   else
  73     *value = MMUReg[reg];
  74   return (ARMul_DONE);
  75 }
  76
  77 static unsigned
  78 MMUMCR (ARMul_State * state, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value)
  79 {
  80   int reg = BITS (16, 19) & 7;
  81
  82   MMUReg[reg] = value;
  83
  84   if (reg == 1)
  85     {
  86       ARMword p,d,l,b;
  87
  88       p = state->prog32Sig;
  89       d = state->data32Sig;
  90       l = state->lateabtSig;
  91       b = state->bigendSig;
  92
  93       state->prog32Sig = value >> 4 & 1;
  94       state->data32Sig = value >> 5 & 1;
  95       state->lateabtSig = value >> 6 & 1;
  96       state->bigendSig = value >> 7 & 1;
  97
  98       if (p != state->prog32Sig
  99           || d != state->data32Sig
 100           || l != state->lateabtSig
 101           || b != state->bigendSig)
 102         state->Emulate = CHANGEMODE;    /* Force ARMulator to notice these now.  */
 103     }
 104
 105   return ARMul_DONE;
 106 }
 107
 108
 109 static unsigned
 110 MMURead (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword * value)
 111 {
 112   if (reg == 0)
 113     *value = 0x41440110;
 114   else if (reg < 8)
 115     *value = MMUReg[reg];
 116   return (TRUE);
 117 }
 118
 119 static unsigned
 120 MMUWrite (ARMul_State * state, unsigned reg, ARMword value)
 121 {
 122   if (reg < 8)
 123     MMUReg[reg] = value;
 124
 125   if (reg == 1)
 126     {
 127       ARMword p,d,l,b;
 128
 129       p = state->prog32Sig;
 130       d = state->data32Sig;
 131       l = state->lateabtSig;
 132       b = state->bigendSig;
 133
 134       state->prog32Sig = value >> 4 & 1;
 135       state->data32Sig = value >> 5 & 1;
 136       state->lateabtSig = value >> 6 & 1;
 137       state->bigendSig = value >> 7 & 1;
 138
 139
 140       if (p != state->prog32Sig
 141           || d != state->data32Sig
 142           || l != state->lateabtSig
 143           || b != state->bigendSig)
 144         state->Emulate = CHANGEMODE;    /* Force ARMulator to notice these now.  */
 145     }
 146
 147   return TRUE;
 148 }
 149
 150
 151 /* What follows is the Validation Suite Coprocessor.  It uses two
 152 co-processor numbers (4 and 5) and has the follwing functionality.
 153 Sixteen registers.  Both co-processor nuimbers can be used in an MCR and
 154 MRC to access these registers.  CP 4 can LDC and STC to and from the
 155 registers.  CP 4 and CP 5 CDP 0 will busy wait for the number of cycles
 156 specified by a CP register.  CP 5 CDP 1 issues a FIQ after a number of
 157 cycles (specified in a CP register), CDP 2 issues an IRQW in the same
 158 way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5 stores a 32
 159 bit time value in a CP register (actually it's the total number of N, S,
 160 I, C and F cyles) */
 161
 162 static ARMword ValReg[16];
 163
 164 static unsigned
 165 ValLDC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type, ARMword instr, ARMword data)
 166 {
 167   static unsigned words;
 168
 169   if (type != ARMul_DATA)
 170     {
 171       words = 0;
 172       return (ARMul_DONE);
 173     }
 174   if (BIT (22))
 175     {                           /* it's a long access, get two words */
 176       ValReg[BITS (12, 15)] = data;
 177       if (words++ == 4)
 178         return (ARMul_DONE);
 179       else
 180         return (ARMul_INC);
 181     }
 182   else
 183     {                           /* get just one word */
 184       ValReg[BITS (12, 15)] = data;
 185       return (ARMul_DONE);
 186     }
 187 }
 188
 189 static unsigned
 190 ValSTC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type, ARMword instr, ARMword * data)
 191 {
 192   static unsigned words;
 193
 194   if (type != ARMul_DATA)
 195     {
 196       words = 0;
 197       return (ARMul_DONE);
 198     }
 199   if (BIT (22))
 200     {                           /* it's a long access, get two words */
 201       *data = ValReg[BITS (12, 15)];
 202       if (words++ == 4)
 203         return (ARMul_DONE);
 204       else
 205         return (ARMul_INC);
 206     }
 207   else
 208     {                           /* get just one word */
 209       *data = ValReg[BITS (12, 15)];
 210       return (ARMul_DONE);
 211     }
 212 }
 213
 214 static unsigned
 215 ValMRC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value)
 216 {
 217   *value = ValReg[BITS (16, 19)];
 218   return (ARMul_DONE);
 219 }
 220
 221 static unsigned
 222 ValMCR (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value)
 223 {
 224   ValReg[BITS (16, 19)] = value;
 225   return (ARMul_DONE);
 226 }
 227
 228 static unsigned
 229 ValCDP (ARMul_State * state, unsigned type, ARMword instr)
 230 {
 231   static unsigned long finish = 0;
 232   ARMword howlong;
 233
 234   howlong = ValReg[BITS (0, 3)];
 235   if (BITS (20, 23) == 0)
 236     {
 237       if (type == ARMul_FIRST)
 238         {                       /* First cycle of a busy wait */
 239           finish = ARMul_Time (state) + howlong;
 240           if (howlong == 0)
 241             return (ARMul_DONE);
 242           else
 243             return (ARMul_BUSY);
 244         }
 245       else if (type == ARMul_BUSY)
 246         {
 247           if (ARMul_Time (state) >= finish)
 248             return (ARMul_DONE);
 249           else
 250             return (ARMul_BUSY);
 251         }
 252     }
 253   return (ARMul_CANT);
 254 }
 255
 256 static unsigned
 257 DoAFIQ (ARMul_State * state)
 258 {
 259   state->NfiqSig = LOW;
 260   state->Exception++;
 261   return (0);
 262 }
 263
 264 static unsigned
 265 DoAIRQ (ARMul_State * state)
 266 {
 267   state->NirqSig = LOW;
 268   state->Exception++;
 269   return (0);
 270 }
 271
 272 static unsigned
 273 IntCDP (ARMul_State * state, unsigned type, ARMword instr)
 274 {
 275   static unsigned long finish;
 276   ARMword howlong;
 277
 278   howlong = ValReg[BITS (0, 3)];
 279   switch ((int) BITS (20, 23))
 280     {
 281     case 0:
 282       if (type == ARMul_FIRST)
 283         {                       /* First cycle of a busy wait */
 284           finish = ARMul_Time (state) + howlong;
 285           if (howlong == 0)
 286             return (ARMul_DONE);
 287           else
 288             return (ARMul_BUSY);
 289         }
 290       else if (type == ARMul_BUSY)
 291         {
 292           if (ARMul_Time (state) >= finish)
 293             return (ARMul_DONE);
 294           else
 295             return (ARMul_BUSY);
 296         }
 297       return (ARMul_DONE);
 298     case 1:
 299       if (howlong == 0)
 300         ARMul_Abort (state, ARMul_FIQV);
 301       else
 302         ARMul_ScheduleEvent (state, howlong, DoAFIQ);
 303       return (ARMul_DONE);
 304     case 2:
 305       if (howlong == 0)
 306         ARMul_Abort (state, ARMul_IRQV);
 307       else
 308         ARMul_ScheduleEvent (state, howlong, DoAIRQ);
 309       return (ARMul_DONE);
 310     case 3:
 311       state->NfiqSig = HIGH;
 312       state->Exception--;
 313       return (ARMul_DONE);
 314     case 4:
 315       state->NirqSig = HIGH;
 316       state->Exception--;
 317       return (ARMul_DONE);
 318     case 5:
 319       ValReg[BITS (0, 3)] = ARMul_Time (state);
 320       return (ARMul_DONE);
 321     }
 322   return (ARMul_CANT);
 323 }
 324
 325 /***************************************************************************\
 326 *         Install co-processor instruction handlers in this routine         *
 327 \***************************************************************************/
 328
 329 unsigned
 330 ARMul_CoProInit (ARMul_State * state)
 331 {
 332   register unsigned i;
 333
 334   for (i = 0; i < 16; i++)      /* initialise tham all first */
 335     ARMul_CoProDetach (state, i);
 336
 337   /* Install CoPro Instruction handlers here
 338      The format is
 339      ARMul_CoProAttach(state, CP Number, Init routine, Exit routine
 340      LDC routine, STC routine, MRC routine, MCR routine,
 341      CDP routine, Read Reg routine, Write Reg routine) ;
 342    */
 343
 344   ARMul_CoProAttach (state, 4, NULL, NULL,
 345                      ValLDC, ValSTC, ValMRC, ValMCR, ValCDP, NULL, NULL);
 346
 347   ARMul_CoProAttach (state, 5, NULL, NULL,
 348                      NULL, NULL, ValMRC, ValMCR, IntCDP, NULL, NULL);
 349
 350   ARMul_CoProAttach (state, 15, MMUInit, NULL,
 351                      NULL, NULL, MMUMRC, MMUMCR, NULL, MMURead, MMUWrite);
 352
 353
 354   /* No handlers below here */
 355
 356   for (i = 0; i < 16; i++)      /* Call all the initialisation routines */
 357     if (state->CPInit[i])
 358       (state->CPInit[i]) (state);
 359   return (TRUE);
 360 }
 361
 362 /***************************************************************************\
 363 *         Install co-processor finalisation routines in this routine        *
 364 \***************************************************************************/
 365
 366 void
 367 ARMul_CoProExit (ARMul_State * state)
 368 {
 369   register unsigned i;
 370
 371   for (i = 0; i < 16; i++)
 372     if (state->CPExit[i])
 373       (state->CPExit[i]) (state);
 374   for (i = 0; i < 16; i++)      /* Detach all handlers */
 375     ARMul_CoProDetach (state, i);
 376 }
 377
 378 /***************************************************************************\
 379 *              Routines to hook Co-processors into ARMulator                 *
 380 \***************************************************************************/
 381
 382 void
 383 ARMul_CoProAttach (ARMul_State * state, unsigned number,
 384                    ARMul_CPInits * init, ARMul_CPExits * exit,
 385                    ARMul_LDCs * ldc, ARMul_STCs * stc,
 386                    ARMul_MRCs * mrc, ARMul_MCRs * mcr, ARMul_CDPs * cdp,
 387                    ARMul_CPReads * read, ARMul_CPWrites * write)
 388 {
 389   if (init != NULL)
 390     state->CPInit[number] = init;
 391   if (exit != NULL)
 392     state->CPExit[number] = exit;
 393   if (ldc != NULL)
 394     state->LDC[number] = ldc;
 395   if (stc != NULL)
 396     state->STC[number] = stc;
 397   if (mrc != NULL)
 398     state->MRC[number] = mrc;
 399   if (mcr != NULL)
 400     state->MCR[number] = mcr;
 401   if (cdp != NULL)
 402     state->CDP[number] = cdp;
 403   if (read != NULL)
 404     state->CPRead[number] = read;
 405   if (write != NULL)
 406     state->CPWrite[number] = write;
 407 }
 408
 409 void
 410 ARMul_CoProDetach (ARMul_State * state, unsigned number)
 411 {
 412   ARMul_CoProAttach (state, number, NULL, NULL,
 413                      NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
 414                      NoCoPro3R, NULL, NULL);
 415   state->CPInit[number] = NULL;
 416   state->CPExit[number] = NULL;
 417   state->CPRead[number] = NULL;
 418   state->CPWrite[number] = NULL;
 419 }
 420
 421 /***************************************************************************\
 422 *         There is no CoPro around, so Undefined Instruction trap           *
 423 \***************************************************************************/
 424
 425 static unsigned
 426 NoCoPro3R (ARMul_State * state ATTRIBUTE_UNUSED,
 427            unsigned a ATTRIBUTE_UNUSED,
 428            ARMword b ATTRIBUTE_UNUSED)
 429 {
 430   return (ARMul_CANT);
 431 }
 432
 433 static unsigned
 434 NoCoPro4R (
 435            ARMul_State * state ATTRIBUTE_UNUSED,
 436            unsigned a ATTRIBUTE_UNUSED,
 437            ARMword b ATTRIBUTE_UNUSED,
 438            ARMword c ATTRIBUTE_UNUSED)
 439 {
 440   return (ARMul_CANT);
 441 }
 442
 443 static unsigned
 444 NoCoPro4W (
 445            ARMul_State * state ATTRIBUTE_UNUSED,
 446            unsigned a ATTRIBUTE_UNUSED,
 447            ARMword b ATTRIBUTE_UNUSED,
 448            ARMword * c ATTRIBUTE_UNUSED)
 449 {
 450   return (ARMul_CANT);
 451 }