1 /* armcopro.c -- co-processor interface: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20 extern unsigned ARMul_CoProInit(ARMul_State
*state
) ;
21 extern void ARMul_CoProExit(ARMul_State
*state
) ;
22 extern void ARMul_CoProAttach(ARMul_State
*state
, unsigned number
,
23 ARMul_CPInits
*init
, ARMul_CPExits
*exit
,
24 ARMul_LDCs
*ldc
, ARMul_STCs
*stc
,
25 ARMul_MRCs
*mrc
, ARMul_MCRs
*mcr
,
27 ARMul_CPReads
*read
, ARMul_CPWrites
*write
) ;
28 extern void ARMul_CoProDetach(ARMul_State
*state
, unsigned number
) ;
31 /***************************************************************************\
32 * Dummy Co-processors *
33 \***************************************************************************/
35 static unsigned NoCoPro3R(ARMul_State
*state
,unsigned,ARMword
) ;
36 static unsigned NoCoPro4R(ARMul_State
*state
,unsigned,ARMword
,ARMword
) ;
37 static unsigned NoCoPro4W(ARMul_State
*state
,unsigned,ARMword
,ARMword
*) ;
39 /***************************************************************************\
40 * Define Co-Processor instruction handlers here *
41 \***************************************************************************/
43 /* Here's ARMulator's MMU definition. A few things to note:
44 1) it has eight registers, but only two are defined.
45 2) you can only access its registers with MCR and MRC.
46 3) MMU Register 0 (ID) returns 0x41440110
47 4) Register 1 only has 4 bits defined. Bits 0 to 3 are unused, bit 4
48 controls 32/26 bit program space, bit 5 controls 32/26 bit data space,
49 bit 6 controls late abort timimg and bit 7 controls big/little endian.
52 static ARMword MMUReg
[8] ;
54 static unsigned MMUInit(ARMul_State
*state
)
55 {MMUReg
[1] = state
->prog32Sig
<< 4 |
56 state
->data32Sig
<< 5 |
57 state
->lateabtSig
<< 6 |
58 state
->bigendSig
<< 7 ;
59 ARMul_ConsolePrint (state
, ", MMU present") ;
63 static unsigned MMUMRC(ARMul_State
*state
, unsigned type
, ARMword instr
,ARMword
*value
)
64 {int reg
= BITS(16,19) & 7 ;
69 *value
= MMUReg
[reg
] ;
73 static unsigned MMUMCR(ARMul_State
*state
, unsigned type
, ARMword instr
, ARMword value
)
74 {int reg
= BITS(16,19) & 7 ;
78 state
->prog32Sig
= value
>> 4 & 1 ;
79 state
->data32Sig
= value
>> 5 & 1 ;
80 state
->lateabtSig
= value
>> 6 & 1 ;
81 state
->bigendSig
= value
>> 7 & 1 ;
82 state
->Emulate
= TRUE
; /* force ARMulator to notice these now !*/
88 static unsigned MMURead(ARMul_State
*state
, unsigned reg
, ARMword
*value
)
92 *value
= MMUReg
[reg
] ;
96 static unsigned MMUWrite(ARMul_State
*state
, unsigned reg
, ARMword value
)
100 state
->prog32Sig
= value
>> 4 & 1 ;
101 state
->data32Sig
= value
>> 5 & 1 ;
102 state
->lateabtSig
= value
>> 6 & 1 ;
103 state
->bigendSig
= value
>> 7 & 1 ;
104 state
->Emulate
= TRUE
; /* force ARMulator to notice these now !*/
110 /* What follows is the Validation Suite Coprocessor. It uses two
111 co-processor numbers (4 and 5) and has the follwing functionality.
112 Sixteen registers. Both co-processor nuimbers can be used in an MCR and
113 MRC to access these registers. CP 4 can LDC and STC to and from the
114 registers. CP 4 and CP 5 CDP 0 will busy wait for the number of cycles
115 specified by a CP register. CP 5 CDP 1 issues a FIQ after a number of
116 cycles (specified in a CP register), CDP 2 issues an IRQW in the same
117 way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5 stores a 32
118 bit time value in a CP register (actually it's the total number of N, S,
121 static ARMword ValReg
[16] ;
123 static unsigned ValLDC(ARMul_State
*state
, unsigned type
,
124 ARMword instr
, ARMword data
)
125 {static unsigned words
;
127 if (type
!= ARMul_DATA
) {
131 if (BIT(22)) { /* it's a long access, get two words */
132 ValReg
[BITS(12,15)] = data
;
138 else { /* get just one word */
139 ValReg
[BITS(12,15)] = data
;
144 static unsigned ValSTC(ARMul_State
*state
, unsigned type
,
145 ARMword instr
, ARMword
*data
)
146 {static unsigned words
;
148 if (type
!= ARMul_DATA
) {
152 if (BIT(22)) { /* it's a long access, get two words */
153 *data
= ValReg
[BITS(12,15)] ;
159 else { /* get just one word */
160 *data
= ValReg
[BITS(12,15)] ;
165 static unsigned ValMRC(ARMul_State
*state
, unsigned type
, ARMword instr
,ARMword
*value
)
167 *value
= ValReg
[BITS(16,19)] ;
171 static unsigned ValMCR(ARMul_State
*state
, unsigned type
, ARMword instr
, ARMword value
)
173 ValReg
[BITS(16,19)] = value
;
177 static unsigned ValCDP(ARMul_State
*state
, unsigned type
, ARMword instr
)
179 static unsigned long finish
= 0 ;
182 howlong
= ValReg
[BITS(0,3)] ;
183 if (BITS(20,23)==0) {
184 if (type
== ARMul_FIRST
) { /* First cycle of a busy wait */
185 finish
= ARMul_Time(state
) + howlong
;
191 else if (type
== ARMul_BUSY
) {
192 if (ARMul_Time(state
) >= finish
)
201 static unsigned DoAFIQ(ARMul_State
*state
)
202 {state
->NfiqSig
= LOW
;
207 static unsigned DoAIRQ(ARMul_State
*state
)
208 {state
->NirqSig
= LOW
;
213 static unsigned IntCDP(ARMul_State
*state
, unsigned type
, ARMword instr
)
214 {static unsigned long finish
;
217 howlong
= ValReg
[BITS(0,3)] ;
218 switch((int)BITS(20,23)) {
219 case 0 : if (type
== ARMul_FIRST
) { /* First cycle of a busy wait */
220 finish
= ARMul_Time(state
) + howlong
;
226 else if (type
== ARMul_BUSY
) {
227 if (ARMul_Time(state
) >= finish
)
233 case 1 : if (howlong
== 0)
234 ARMul_Abort(state
,ARMul_FIQV
) ;
236 ARMul_ScheduleEvent(state
,howlong
,DoAFIQ
) ;
238 case 2 : if (howlong
== 0)
239 ARMul_Abort(state
,ARMul_IRQV
) ;
241 ARMul_ScheduleEvent(state
,howlong
,DoAIRQ
) ;
243 case 3 : state
->NfiqSig
= HIGH
;
246 case 4 : state
->NirqSig
= HIGH
;
249 case 5 : ValReg
[BITS(0,3)] = ARMul_Time(state
) ;
255 /***************************************************************************\
256 * Install co-processor instruction handlers in this routine *
257 \***************************************************************************/
259 unsigned ARMul_CoProInit(ARMul_State
*state
)
260 {register unsigned i
;
262 for (i
= 0 ; i
< 16 ; i
++) /* initialise tham all first */
263 ARMul_CoProDetach(state
, i
) ;
265 /* Install CoPro Instruction handlers here
267 ARMul_CoProAttach(state, CP Number, Init routine, Exit routine
268 LDC routine, STC routine, MRC routine, MCR routine,
269 CDP routine, Read Reg routine, Write Reg routine) ;
272 ARMul_CoProAttach(state
, 4, NULL
, NULL
,
273 ValLDC
, ValSTC
, ValMRC
, ValMCR
,
274 ValCDP
, NULL
, NULL
) ;
276 ARMul_CoProAttach(state
, 5, NULL
, NULL
,
277 NULL
, NULL
, ValMRC
, ValMCR
,
278 IntCDP
, NULL
, NULL
) ;
280 ARMul_CoProAttach(state
, 15, MMUInit
, NULL
,
281 NULL
, NULL
, MMUMRC
, MMUMCR
,
282 NULL
, MMURead
, MMUWrite
) ;
285 /* No handlers below here */
287 for (i
= 0 ; i
< 16 ; i
++) /* Call all the initialisation routines */
288 if (state
->CPInit
[i
])
289 (state
->CPInit
[i
])(state
) ;
293 /***************************************************************************\
294 * Install co-processor finalisation routines in this routine *
295 \***************************************************************************/
297 void ARMul_CoProExit(ARMul_State
*state
)
298 {register unsigned i
;
300 for (i
= 0 ; i
< 16 ; i
++)
301 if (state
->CPExit
[i
])
302 (state
->CPExit
[i
])(state
) ;
303 for (i
= 0 ; i
< 16 ; i
++) /* Detach all handlers */
304 ARMul_CoProDetach(state
, i
) ;
307 /***************************************************************************\
308 * Routines to hook Co-processors into ARMulator *
309 \***************************************************************************/
311 void ARMul_CoProAttach(ARMul_State
*state
, unsigned number
,
312 ARMul_CPInits
*init
, ARMul_CPExits
*exit
,
313 ARMul_LDCs
*ldc
, ARMul_STCs
*stc
,
314 ARMul_MRCs
*mrc
, ARMul_MCRs
*mcr
, ARMul_CDPs
*cdp
,
315 ARMul_CPReads
*read
, ARMul_CPWrites
*write
)
317 state
->CPInit
[number
] = init
;
319 state
->CPExit
[number
] = exit
;
321 state
->LDC
[number
] = ldc
;
323 state
->STC
[number
] = stc
;
325 state
->MRC
[number
] = mrc
;
327 state
->MCR
[number
] = mcr
;
329 state
->CDP
[number
] = cdp
;
331 state
->CPRead
[number
] = read
;
333 state
->CPWrite
[number
] = write
;
336 void ARMul_CoProDetach(ARMul_State
*state
, unsigned number
)
337 {ARMul_CoProAttach(state
, number
, NULL
, NULL
,
338 NoCoPro4R
, NoCoPro4W
, NoCoPro4W
, NoCoPro4R
,
339 NoCoPro3R
, NULL
, NULL
) ;
340 state
->CPInit
[number
] = NULL
;
341 state
->CPExit
[number
] = NULL
;
342 state
->CPRead
[number
] = NULL
;
343 state
->CPWrite
[number
] = NULL
;
346 /***************************************************************************\
347 * There is no CoPro around, so Undefined Instruction trap *
348 \***************************************************************************/
350 static unsigned NoCoPro3R(ARMul_State
*state
,unsigned a
,ARMword b
)
351 {return(ARMul_CANT
) ;}
353 static unsigned NoCoPro4R(ARMul_State
*state
, unsigned a
,ARMword b
,ARMword c
)
354 {return(ARMul_CANT
) ;}
356 static unsigned NoCoPro4W(ARMul_State
*state
, unsigned a
,ARMword b
,ARMword
*c
)
357 {return(ARMul_CANT
) ;}
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