1 /* armcopro.c -- co-processor interface: ARM6 Instruction Emulator.
2 Copyright (C) 1994, 2000 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 extern unsigned ARMul_CoProInit (ARMul_State
* state
);
22 extern void ARMul_CoProExit (ARMul_State
* state
);
23 extern void ARMul_CoProAttach (ARMul_State
* state
, unsigned number
,
24 ARMul_CPInits
* init
, ARMul_CPExits
* exit
,
25 ARMul_LDCs
* ldc
, ARMul_STCs
* stc
,
26 ARMul_MRCs
* mrc
, ARMul_MCRs
* mcr
,
28 ARMul_CPReads
* read
, ARMul_CPWrites
* write
);
29 extern void ARMul_CoProDetach (ARMul_State
* state
, unsigned number
);
32 /***************************************************************************\
33 * Dummy Co-processors *
34 \***************************************************************************/
36 static unsigned NoCoPro3R (ARMul_State
* state
, unsigned, ARMword
);
37 static unsigned NoCoPro4R (ARMul_State
* state
, unsigned, ARMword
, ARMword
);
38 static unsigned NoCoPro4W (ARMul_State
* state
, unsigned, ARMword
, ARMword
*);
40 /***************************************************************************\
41 * Define Co-Processor instruction handlers here *
42 \***************************************************************************/
44 /* Here's ARMulator's MMU definition. A few things to note:
45 1) it has eight registers, but only two are defined.
46 2) you can only access its registers with MCR and MRC.
47 3) MMU Register 0 (ID) returns 0x41440110
48 4) Register 1 only has 4 bits defined. Bits 0 to 3 are unused, bit 4
49 controls 32/26 bit program space, bit 5 controls 32/26 bit data space,
50 bit 6 controls late abort timimg and bit 7 controls big/little endian.
53 static ARMword MMUReg
[8];
56 MMUInit (ARMul_State
* state
)
58 MMUReg
[1] = state
->prog32Sig
<< 4 |
59 state
->data32Sig
<< 5 | state
->lateabtSig
<< 6 | state
->bigendSig
<< 7;
60 ARMul_ConsolePrint (state
, ", MMU present");
65 MMUMRC (ARMul_State
* state ATTRIBUTE_UNUSED
, unsigned type ATTRIBUTE_UNUSED
, ARMword instr
, ARMword
* value
)
67 int reg
= BITS (16, 19) & 7;
77 MMUMCR (ARMul_State
* state
, unsigned type ATTRIBUTE_UNUSED
, ARMword instr
, ARMword value
)
79 int reg
= BITS (16, 19) & 7;
84 state
->prog32Sig
= value
>> 4 & 1;
85 state
->data32Sig
= value
>> 5 & 1;
86 state
->lateabtSig
= value
>> 6 & 1;
87 state
->bigendSig
= value
>> 7 & 1;
88 state
->Emulate
= TRUE
; /* force ARMulator to notice these now ! */
95 MMURead (ARMul_State
* state ATTRIBUTE_UNUSED
, unsigned reg
, ARMword
* value
)
100 *value
= MMUReg
[reg
];
105 MMUWrite (ARMul_State
* state
, unsigned reg
, ARMword value
)
111 state
->prog32Sig
= value
>> 4 & 1;
112 state
->data32Sig
= value
>> 5 & 1;
113 state
->lateabtSig
= value
>> 6 & 1;
114 state
->bigendSig
= value
>> 7 & 1;
115 state
->Emulate
= TRUE
; /* force ARMulator to notice these now ! */
121 /* What follows is the Validation Suite Coprocessor. It uses two
122 co-processor numbers (4 and 5) and has the follwing functionality.
123 Sixteen registers. Both co-processor nuimbers can be used in an MCR and
124 MRC to access these registers. CP 4 can LDC and STC to and from the
125 registers. CP 4 and CP 5 CDP 0 will busy wait for the number of cycles
126 specified by a CP register. CP 5 CDP 1 issues a FIQ after a number of
127 cycles (specified in a CP register), CDP 2 issues an IRQW in the same
128 way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5 stores a 32
129 bit time value in a CP register (actually it's the total number of N, S,
132 static ARMword ValReg
[16];
135 ValLDC (ARMul_State
* state ATTRIBUTE_UNUSED
, unsigned type
, ARMword instr
, ARMword data
)
137 static unsigned words
;
139 if (type
!= ARMul_DATA
)
145 { /* it's a long access, get two words */
146 ValReg
[BITS (12, 15)] = data
;
153 { /* get just one word */
154 ValReg
[BITS (12, 15)] = data
;
160 ValSTC (ARMul_State
* state ATTRIBUTE_UNUSED
, unsigned type
, ARMword instr
, ARMword
* data
)
162 static unsigned words
;
164 if (type
!= ARMul_DATA
)
170 { /* it's a long access, get two words */
171 *data
= ValReg
[BITS (12, 15)];
178 { /* get just one word */
179 *data
= ValReg
[BITS (12, 15)];
185 ValMRC (ARMul_State
* state ATTRIBUTE_UNUSED
, unsigned type ATTRIBUTE_UNUSED
, ARMword instr
, ARMword
* value
)
187 *value
= ValReg
[BITS (16, 19)];
192 ValMCR (ARMul_State
* state ATTRIBUTE_UNUSED
, unsigned type ATTRIBUTE_UNUSED
, ARMword instr
, ARMword value
)
194 ValReg
[BITS (16, 19)] = value
;
199 ValCDP (ARMul_State
* state
, unsigned type
, ARMword instr
)
201 static unsigned long finish
= 0;
204 howlong
= ValReg
[BITS (0, 3)];
205 if (BITS (20, 23) == 0)
207 if (type
== ARMul_FIRST
)
208 { /* First cycle of a busy wait */
209 finish
= ARMul_Time (state
) + howlong
;
215 else if (type
== ARMul_BUSY
)
217 if (ARMul_Time (state
) >= finish
)
227 DoAFIQ (ARMul_State
* state
)
229 state
->NfiqSig
= LOW
;
235 DoAIRQ (ARMul_State
* state
)
237 state
->NirqSig
= LOW
;
243 IntCDP (ARMul_State
* state
, unsigned type
, ARMword instr
)
245 static unsigned long finish
;
248 howlong
= ValReg
[BITS (0, 3)];
249 switch ((int) BITS (20, 23))
252 if (type
== ARMul_FIRST
)
253 { /* First cycle of a busy wait */
254 finish
= ARMul_Time (state
) + howlong
;
260 else if (type
== ARMul_BUSY
)
262 if (ARMul_Time (state
) >= finish
)
270 ARMul_Abort (state
, ARMul_FIQV
);
272 ARMul_ScheduleEvent (state
, howlong
, DoAFIQ
);
276 ARMul_Abort (state
, ARMul_IRQV
);
278 ARMul_ScheduleEvent (state
, howlong
, DoAIRQ
);
281 state
->NfiqSig
= HIGH
;
285 state
->NirqSig
= HIGH
;
289 ValReg
[BITS (0, 3)] = ARMul_Time (state
);
295 /***************************************************************************\
296 * Install co-processor instruction handlers in this routine *
297 \***************************************************************************/
300 ARMul_CoProInit (ARMul_State
* state
)
304 for (i
= 0; i
< 16; i
++) /* initialise tham all first */
305 ARMul_CoProDetach (state
, i
);
307 /* Install CoPro Instruction handlers here
309 ARMul_CoProAttach(state, CP Number, Init routine, Exit routine
310 LDC routine, STC routine, MRC routine, MCR routine,
311 CDP routine, Read Reg routine, Write Reg routine) ;
314 ARMul_CoProAttach (state
, 4, NULL
, NULL
,
315 ValLDC
, ValSTC
, ValMRC
, ValMCR
, ValCDP
, NULL
, NULL
);
317 ARMul_CoProAttach (state
, 5, NULL
, NULL
,
318 NULL
, NULL
, ValMRC
, ValMCR
, IntCDP
, NULL
, NULL
);
320 ARMul_CoProAttach (state
, 15, MMUInit
, NULL
,
321 NULL
, NULL
, MMUMRC
, MMUMCR
, NULL
, MMURead
, MMUWrite
);
324 /* No handlers below here */
326 for (i
= 0; i
< 16; i
++) /* Call all the initialisation routines */
327 if (state
->CPInit
[i
])
328 (state
->CPInit
[i
]) (state
);
332 /***************************************************************************\
333 * Install co-processor finalisation routines in this routine *
334 \***************************************************************************/
337 ARMul_CoProExit (ARMul_State
* state
)
341 for (i
= 0; i
< 16; i
++)
342 if (state
->CPExit
[i
])
343 (state
->CPExit
[i
]) (state
);
344 for (i
= 0; i
< 16; i
++) /* Detach all handlers */
345 ARMul_CoProDetach (state
, i
);
348 /***************************************************************************\
349 * Routines to hook Co-processors into ARMulator *
350 \***************************************************************************/
353 ARMul_CoProAttach (ARMul_State
* state
, unsigned number
,
354 ARMul_CPInits
* init
, ARMul_CPExits
* exit
,
355 ARMul_LDCs
* ldc
, ARMul_STCs
* stc
,
356 ARMul_MRCs
* mrc
, ARMul_MCRs
* mcr
, ARMul_CDPs
* cdp
,
357 ARMul_CPReads
* read
, ARMul_CPWrites
* write
)
360 state
->CPInit
[number
] = init
;
362 state
->CPExit
[number
] = exit
;
364 state
->LDC
[number
] = ldc
;
366 state
->STC
[number
] = stc
;
368 state
->MRC
[number
] = mrc
;
370 state
->MCR
[number
] = mcr
;
372 state
->CDP
[number
] = cdp
;
374 state
->CPRead
[number
] = read
;
376 state
->CPWrite
[number
] = write
;
380 ARMul_CoProDetach (ARMul_State
* state
, unsigned number
)
382 ARMul_CoProAttach (state
, number
, NULL
, NULL
,
383 NoCoPro4R
, NoCoPro4W
, NoCoPro4W
, NoCoPro4R
,
384 NoCoPro3R
, NULL
, NULL
);
385 state
->CPInit
[number
] = NULL
;
386 state
->CPExit
[number
] = NULL
;
387 state
->CPRead
[number
] = NULL
;
388 state
->CPWrite
[number
] = NULL
;
391 /***************************************************************************\
392 * There is no CoPro around, so Undefined Instruction trap *
393 \***************************************************************************/
396 NoCoPro3R (ARMul_State
* state ATTRIBUTE_UNUSED
,
397 unsigned a ATTRIBUTE_UNUSED
,
398 ARMword b ATTRIBUTE_UNUSED
)
405 ARMul_State
* state ATTRIBUTE_UNUSED
,
406 unsigned a ATTRIBUTE_UNUSED
,
407 ARMword b ATTRIBUTE_UNUSED
,
408 ARMword c ATTRIBUTE_UNUSED
)
415 ARMul_State
* state ATTRIBUTE_UNUSED
,
416 unsigned a ATTRIBUTE_UNUSED
,
417 ARMword b ATTRIBUTE_UNUSED
,
418 ARMword
* c ATTRIBUTE_UNUSED
)