sim/arm/armdefs.h

   1 /*  armdefs.h -- ARMulator common definitions:  ARM6 Instruction Emulator.
   2     Copyright (C) 1994 Advanced RISC Machines Ltd.
   3
   4     This program is free software; you can redistribute it and/or modify
   5     it under the terms of the GNU General Public License as published by
   6     the Free Software Foundation; either version 2 of the License, or
   7     (at your option) any later version.
   8
   9     This program is distributed in the hope that it will be useful,
  10     but WITHOUT ANY WARRANTY; without even the implied warranty of
  11     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12     GNU General Public License for more details.
  13
  14     You should have received a copy of the GNU General Public License
  15     along with this program; if not, write to the Free Software
  16     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  17
  18 #include <stdio.h>
  19 #include <stdlib.h>
  20
  21 #define FALSE 0
  22 #define TRUE 1
  23 #define LOW 0
  24 #define HIGH 1
  25 #define LOWHIGH 1
  26 #define HIGHLOW 2
  27
  28 #ifndef __STDC__
  29 typedef char *VoidStar;
  30 #endif
  31
  32 typedef unsigned long ARMword;  /* must be 32 bits wide */
  33 typedef unsigned long long ARMdword;    /* Must be at least 64 bits wide.  */
  34 typedef struct ARMul_State ARMul_State;
  35
  36 typedef unsigned ARMul_CPInits (ARMul_State * state);
  37 typedef unsigned ARMul_CPExits (ARMul_State * state);
  38 typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type,
  39                              ARMword instr, ARMword value);
  40 typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type,
  41                              ARMword instr, ARMword * value);
  42 typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type,
  43                              ARMword instr, ARMword * value);
  44 typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type,
  45                              ARMword instr, ARMword value);
  46 typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type,
  47                              ARMword instr);
  48 typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
  49                                 ARMword * value);
  50 typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
  51                                  ARMword value);
  52
  53 struct ARMul_State
  54 {
  55   ARMword Emulate;              /* to start and stop emulation */
  56   unsigned EndCondition;        /* reason for stopping */
  57   unsigned ErrorCode;           /* type of illegal instruction */
  58   ARMword Reg[16];              /* the current register file */
  59   ARMword RegBank[7][16];       /* all the registers */
  60   /* 40 bit accumulator.  We always keep this 64 bits wide,
  61      and move only 40 bits out of it in an MRA insn.  */
  62   ARMdword Accumulator;
  63   ARMword Cpsr;                 /* the current psr */
  64   ARMword Spsr[7];              /* the exception psr's */
  65   ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags;  /* dummy flags for speed */
  66   ARMword SFlag;
  67 #ifdef MODET
  68   ARMword TFlag;                /* Thumb state */
  69 #endif
  70   ARMword Bank;                 /* the current register bank */
  71   ARMword Mode;                 /* the current mode */
  72   ARMword instr, pc, temp;      /* saved register state */
  73   ARMword loaded, decoded;      /* saved pipeline state */
  74   unsigned long NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles;     /* emulated cycles used */
  75   unsigned long NumInstrs;      /* the number of instructions executed */
  76   unsigned NextInstr;
  77   unsigned VectorCatch;         /* caught exception mask */
  78   unsigned CallDebug;           /* set to call the debugger */
  79   unsigned CanWatch;            /* set by memory interface if its willing to suffer the
  80                                    overhead of checking for watchpoints on each memory
  81                                    access */
  82   unsigned MemReadDebug, MemWriteDebug;
  83   unsigned long StopHandle;
  84
  85   unsigned char *MemDataPtr;    /* admin data */
  86   unsigned char *MemInPtr;      /* the Data In bus */
  87   unsigned char *MemOutPtr;     /* the Data Out bus (which you may not need */
  88   unsigned char *MemSparePtr;   /* extra space */
  89   ARMword MemSize;
  90
  91   unsigned char *OSptr;         /* OS Handle */
  92   char *CommandLine;            /* Command Line from ARMsd */
  93
  94   ARMul_CPInits *CPInit[16];    /* coprocessor initialisers */
  95   ARMul_CPExits *CPExit[16];    /* coprocessor finalisers */
  96   ARMul_LDCs *LDC[16];          /* LDC instruction */
  97   ARMul_STCs *STC[16];          /* STC instruction */
  98   ARMul_MRCs *MRC[16];          /* MRC instruction */
  99   ARMul_MCRs *MCR[16];          /* MCR instruction */
 100   ARMul_CDPs *CDP[16];          /* CDP instruction */
 101   ARMul_CPReads *CPRead[16];    /* Read CP register */
 102   ARMul_CPWrites *CPWrite[16];  /* Write CP register */
 103   unsigned char *CPData[16];    /* Coprocessor data */
 104   unsigned char const *CPRegWords[16];  /* map of coprocessor register sizes */
 105   unsigned long LastTime;       /* Value of last call to ARMul_Time() */
 106   ARMword CP14R0_CCD;           /* used to count 64 clock cycles with CP14 R0 bit
 107                                    3 set */
 108
 109   unsigned EventSet;            /* the number of events in the queue */
 110   unsigned long Now;            /* time to the nearest cycle */
 111   struct EventNode **EventPtr;  /* the event list */
 112
 113   unsigned Exception;           /* enable the next four values */
 114   unsigned Debug;               /* show instructions as they are executed */
 115   unsigned NresetSig;           /* reset the processor */
 116   unsigned NfiqSig;
 117   unsigned NirqSig;
 118
 119   unsigned abortSig;
 120   unsigned NtransSig;
 121   unsigned bigendSig;
 122   unsigned prog32Sig;
 123   unsigned data32Sig;
 124   unsigned lateabtSig;
 125   ARMword Vector;               /* synthesize aborts in cycle modes */
 126   ARMword Aborted;              /* sticky flag for aborts */
 127   ARMword Reseted;              /* sticky flag for Reset */
 128   ARMword Inted, LastInted;     /* sticky flags for interrupts */
 129   ARMword Base;                 /* extra hand for base writeback */
 130   ARMword AbortAddr;            /* to keep track of Prefetch aborts */
 131
 132   const struct Dbg_HostosInterface *hostif;
 133
 134   unsigned is_v4;               /* Are we emulating a v4 architecture (or higher) ?  */
 135   unsigned is_v5;               /* Are we emulating a v5 architecture ?  */
 136   unsigned is_v5e;              /* Are we emulating a v5e architecture ?  */
 137   unsigned is_XScale;           /* Are we emulating an XScale architecture ?  */
 138   unsigned verbose;             /* Print various messages like the banner */
 139 };
 140
 141 #define ResetPin NresetSig
 142 #define FIQPin NfiqSig
 143 #define IRQPin NirqSig
 144 #define AbortPin abortSig
 145 #define TransPin NtransSig
 146 #define BigEndPin bigendSig
 147 #define Prog32Pin prog32Sig
 148 #define Data32Pin data32Sig
 149 #define LateAbortPin lateabtSig
 150
 151 /***************************************************************************\
 152 *                        Properties of ARM we know about                    *
 153 \***************************************************************************/
 154
 155 /* The bitflags */
 156 #define ARM_Fix26_Prop   0x01
 157 #define ARM_Nexec_Prop   0x02
 158 #define ARM_Debug_Prop   0x10
 159 #define ARM_Isync_Prop   ARM_Debug_Prop
 160 #define ARM_Lock_Prop    0x20
 161 #define ARM_v4_Prop      0x40
 162 #define ARM_v5_Prop      0x80
 163 #define ARM_v5e_Prop     0x100
 164 #define ARM_XScale_Prop  0x200
 165
 166 /***************************************************************************\
 167 *                   Macros to extract instruction fields                    *
 168 \***************************************************************************/
 169
 170 #define BIT(n) ( (ARMword)(instr>>(n))&1)       /* bit n of instruction */
 171 #define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) )      /* bits m to n of instr */
 172 #define TOPBITS(n) (instr >> (n))       /* bits 31 to n of instr */
 173
 174 /***************************************************************************\
 175 *                      The hardware vector addresses                        *
 176 \***************************************************************************/
 177
 178 #define ARMResetV 0L
 179 #define ARMUndefinedInstrV 4L
 180 #define ARMSWIV 8L
 181 #define ARMPrefetchAbortV 12L
 182 #define ARMDataAbortV 16L
 183 #define ARMAddrExceptnV 20L
 184 #define ARMIRQV 24L
 185 #define ARMFIQV 28L
 186 #define ARMErrorV 32L           /* This is an offset, not an address ! */
 187
 188 #define ARMul_ResetV ARMResetV
 189 #define ARMul_UndefinedInstrV ARMUndefinedInstrV
 190 #define ARMul_SWIV ARMSWIV
 191 #define ARMul_PrefetchAbortV ARMPrefetchAbortV
 192 #define ARMul_DataAbortV ARMDataAbortV
 193 #define ARMul_AddrExceptnV ARMAddrExceptnV
 194 #define ARMul_IRQV ARMIRQV
 195 #define ARMul_FIQV ARMFIQV
 196
 197 /***************************************************************************\
 198 *                          Mode and Bank Constants                          *
 199 \***************************************************************************/
 200
 201 #define USER26MODE   0L
 202 #define FIQ26MODE    1L
 203 #define IRQ26MODE    2L
 204 #define SVC26MODE    3L
 205 #define USER32MODE  16L
 206 #define FIQ32MODE   17L
 207 #define IRQ32MODE   18L
 208 #define SVC32MODE   19L
 209 #define ABORT32MODE 23L
 210 #define UNDEF32MODE 27L
 211 #define SYSTEMMODE  31L
 212
 213 #define ARM32BITMODE (state->Mode > 3)
 214 #define ARM26BITMODE (state->Mode <= 3)
 215 #define ARMMODE (state->Mode)
 216 #define ARMul_MODEBITS 0x1fL
 217 #define ARMul_MODE32BIT ARM32BITMODE
 218 #define ARMul_MODE26BIT ARM26BITMODE
 219
 220 #define USERBANK 0
 221 #define FIQBANK 1
 222 #define IRQBANK 2
 223 #define SVCBANK 3
 224 #define ABORTBANK 4
 225 #define UNDEFBANK 5
 226 #define DUMMYBANK 6
 227 #define SYSTEMBANK USERBANK
 228
 229 #define BANK_CAN_ACCESS_SPSR(bank)  \
 230   ((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK)
 231
 232 /***************************************************************************\
 233 *                  Definitons of things in the emulator                     *
 234 \***************************************************************************/
 235
 236 extern void ARMul_EmulateInit (void);
 237 extern ARMul_State *ARMul_NewState (void);
 238 extern void ARMul_Reset (ARMul_State * state);
 239 extern ARMword ARMul_DoProg (ARMul_State * state);
 240 extern ARMword ARMul_DoInstr (ARMul_State * state);
 241
 242 /***************************************************************************\
 243 *                Definitons of things for event handling                    *
 244 \***************************************************************************/
 245
 246 extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
 247                                  unsigned (*func) ());
 248 extern void ARMul_EnvokeEvent (ARMul_State * state);
 249 extern unsigned long ARMul_Time (ARMul_State * state);
 250
 251 /***************************************************************************\
 252 *                          Useful support routines                          *
 253 \***************************************************************************/
 254
 255 extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode,
 256                              unsigned reg);
 257 extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
 258                           ARMword value);
 259 extern ARMword ARMul_GetPC (ARMul_State * state);
 260 extern ARMword ARMul_GetNextPC (ARMul_State * state);
 261 extern void ARMul_SetPC (ARMul_State * state, ARMword value);
 262 extern ARMword ARMul_GetR15 (ARMul_State * state);
 263 extern void ARMul_SetR15 (ARMul_State * state, ARMword value);
 264
 265 extern ARMword ARMul_GetCPSR (ARMul_State * state);
 266 extern void ARMul_SetCPSR (ARMul_State * state, ARMword value);
 267 extern ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode);
 268 extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);
 269
 270 /***************************************************************************\
 271 *                  Definitons of things to handle aborts                    *
 272 \***************************************************************************/
 273
 274 extern void ARMul_Abort (ARMul_State * state, ARMword address);
 275 #define ARMul_ABORTWORD 0xefffffff      /* SWI -1 */
 276 #define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
 277                                         state->AbortAddr = (address & ~3L)
 278 #define ARMul_DATAABORT(address) state->abortSig = HIGH ; \
 279                                  state->Aborted = ARMul_DataAbortV ;
 280 #define ARMul_CLEARABORT state->abortSig = LOW
 281
 282 /***************************************************************************\
 283 *              Definitons of things in the memory interface                 *
 284 \***************************************************************************/
 285
 286 extern unsigned ARMul_MemoryInit (ARMul_State * state,
 287                                   unsigned long initmemsize);
 288 extern void ARMul_MemoryExit (ARMul_State * state);
 289
 290 extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address,
 291                                  ARMword isize);
 292 extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address,
 293                                  ARMword isize);
 294 extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address,
 295                                   ARMword isize);
 296
 297 extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address);
 298 extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address);
 299 extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address);
 300 extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address);
 301
 302 extern void ARMul_StoreWordS (ARMul_State * state, ARMword address,
 303                               ARMword data);
 304 extern void ARMul_StoreWordN (ARMul_State * state, ARMword address,
 305                               ARMword data);
 306 extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address,
 307                                  ARMword data);
 308 extern void ARMul_StoreByte (ARMul_State * state, ARMword address,
 309                              ARMword data);
 310
 311 extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address,
 312                                ARMword data);
 313 extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address,
 314                                ARMword data);
 315
 316 extern void ARMul_Icycles (ARMul_State * state, unsigned number,
 317                            ARMword address);
 318 extern void ARMul_Ccycles (ARMul_State * state, unsigned number,
 319                            ARMword address);
 320
 321 extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address);
 322 extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address);
 323 extern ARMword ARMul_SafeReadByte (ARMul_State * state, ARMword address);
 324 extern void ARMul_WriteWord (ARMul_State * state, ARMword address,
 325                              ARMword data);
 326 extern void ARMul_WriteByte (ARMul_State * state, ARMword address,
 327                              ARMword data);
 328 extern void ARMul_SafeWriteByte (ARMul_State * state, ARMword address,
 329                              ARMword data);
 330
 331 extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
 332                                 ARMword, ARMword, ARMword, ARMword, ARMword,
 333                                 ARMword, ARMword, ARMword);
 334
 335 /***************************************************************************\
 336 *            Definitons of things in the co-processor interface             *
 337 \***************************************************************************/
 338
 339 #define ARMul_FIRST 0
 340 #define ARMul_TRANSFER 1
 341 #define ARMul_BUSY 2
 342 #define ARMul_DATA 3
 343 #define ARMul_INTERRUPT 4
 344 #define ARMul_DONE 0
 345 #define ARMul_CANT 1
 346 #define ARMul_INC 3
 347
 348 #define ARMul_CP13_R0_FIQ       0x1
 349 #define ARMul_CP13_R0_IRQ       0x2
 350 #define ARMul_CP13_R8_PMUS      0x1
 351
 352 #define ARMul_CP14_R0_ENABLE    0x0001
 353 #define ARMul_CP14_R0_CLKRST    0x0004
 354 #define ARMul_CP14_R0_CCD       0x0008
 355 #define ARMul_CP14_R0_INTEN0    0x0010
 356 #define ARMul_CP14_R0_INTEN1    0x0020
 357 #define ARMul_CP14_R0_INTEN2    0x0040
 358 #define ARMul_CP14_R0_FLAG0     0x0100
 359 #define ARMul_CP14_R0_FLAG1     0x0200
 360 #define ARMul_CP14_R0_FLAG2     0x0400
 361 #define ARMul_CP14_R10_MOE_IB   0x0004
 362 #define ARMul_CP14_R10_MOE_DB   0x0008
 363 #define ARMul_CP14_R10_MOE_BT   0x000c
 364 #define ARMul_CP15_R1_ENDIAN    0x0080
 365 #define ARMul_CP15_R1_ALIGN     0x0002
 366 #define ARMul_CP15_R5_X         0x0400
 367 #define ARMul_CP15_R5_ST_ALIGN  0x0001
 368 #define ARMul_CP15_R5_IMPRE     0x0406
 369 #define ARMul_CP15_R5_MMU_EXCPT 0x0400
 370 #define ARMul_CP15_DBCON_M      0x0100
 371 #define ARMul_CP15_DBCON_E1     0x000c
 372 #define ARMul_CP15_DBCON_E0     0x0003
 373
 374 extern unsigned ARMul_CoProInit (ARMul_State * state);
 375 extern void ARMul_CoProExit (ARMul_State * state);
 376 extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
 377                                ARMul_CPInits * init, ARMul_CPExits * exit,
 378                                ARMul_LDCs * ldc, ARMul_STCs * stc,
 379                                ARMul_MRCs * mrc, ARMul_MCRs * mcr,
 380                                ARMul_CDPs * cdp,
 381                                ARMul_CPReads * read, ARMul_CPWrites * write);
 382 extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
 383 extern void XScale_check_memacc (ARMul_State * state, ARMword * address,
 384                                  int store);
 385 extern void XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far);
 386 extern int XScale_debug_moe (ARMul_State * state, int moe);
 387
 388 /***************************************************************************\
 389 *               Definitons of things in the host environment                *
 390 \***************************************************************************/
 391
 392 extern unsigned ARMul_OSInit (ARMul_State * state);
 393 extern void ARMul_OSExit (ARMul_State * state);
 394 extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number);
 395 extern ARMword ARMul_OSLastErrorP (ARMul_State * state);
 396
 397 extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr);
 398 extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector,
 399                                    ARMword pc);
 400 extern int rdi_log;
 401
 402 /***************************************************************************\
 403 *                            Host-dependent stuff                           *
 404 \***************************************************************************/
 405
 406 #ifdef macintosh
 407 pascal void SpinCursor (short increment);       /* copied from CursorCtl.h */
 408 # define HOURGLASS           SpinCursor( 1 )
 409 # define HOURGLASS_RATE      1023       /* 2^n - 1 */
 410 #endif
 411
 412 extern void ARMul_UndefInstr      (ARMul_State *, ARMword);
 413 extern void ARMul_FixCPSR         (ARMul_State *, ARMword, ARMword);
 414 extern void ARMul_FixSPSR         (ARMul_State *, ARMword, ARMword);
 415 extern void ARMul_ConsolePrint    (ARMul_State *, const char *, ...);
 416 extern void ARMul_SelectProcessor (ARMul_State *, unsigned);