1 /* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20 /***************************************************************************\
21 * Condition code values *
22 \***************************************************************************/
41 /***************************************************************************\
43 \***************************************************************************/
50 /***************************************************************************\
51 * Macros to twiddle the status flags and mode *
52 \***************************************************************************/
54 #define NBIT ((unsigned)1L << 31)
55 #define ZBIT (1L << 30)
56 #define CBIT (1L << 29)
57 #define VBIT (1L << 28)
58 #define SBIT (1L << 27)
59 #define IBIT (1L << 7)
60 #define FBIT (1L << 6)
61 #define IFBITS (3L << 6)
62 #define R15IBIT (1L << 27)
63 #define R15FBIT (1L << 26)
64 #define R15IFBITS (3L << 26)
66 #define POS(i) ( (~(i)) >> 31 )
67 #define NEG(i) ( (i) >> 31 )
69 #ifdef MODET /* Thumb support */
70 /* ??? This bit is actually in the low order bit of the PC in the hardware.
71 It isn't clear if the simulator needs to model that or not. */
72 #define TBIT (1L << 5)
73 #define TFLAG state->TFlag
74 #define SETT state->TFlag = 1
75 #define CLEART state->TFlag = 0
76 #define ASSIGNT(res) state->TFlag = res
77 #define INSN_SIZE (TFLAG ? 2 : 4)
82 #define NFLAG state->NFlag
83 #define SETN state->NFlag = 1
84 #define CLEARN state->NFlag = 0
85 #define ASSIGNN(res) state->NFlag = res
87 #define ZFLAG state->ZFlag
88 #define SETZ state->ZFlag = 1
89 #define CLEARZ state->ZFlag = 0
90 #define ASSIGNZ(res) state->ZFlag = res
92 #define CFLAG state->CFlag
93 #define SETC state->CFlag = 1
94 #define CLEARC state->CFlag = 0
95 #define ASSIGNC(res) state->CFlag = res
97 #define VFLAG state->VFlag
98 #define SETV state->VFlag = 1
99 #define CLEARV state->VFlag = 0
100 #define ASSIGNV(res) state->VFlag = res
102 #define SFLAG state->SFlag
103 #define SETS state->SFlag = 1
104 #define CLEARS state->SFlag = 0
105 #define ASSIGNS(res) state->SFlag = res
107 #define IFLAG (state->IFFlags >> 1)
108 #define FFLAG (state->IFFlags & 1)
109 #define IFFLAGS state->IFFlags
110 #define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
111 #define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
113 #define PSR_FBITS (0xff000000L)
114 #define PSR_SBITS (0x00ff0000L)
115 #define PSR_XBITS (0x0000ff00L)
116 #define PSR_CBITS (0x000000ffL)
118 #if defined MODE32 || defined MODET
119 #define CCBITS (0xf8000000L)
121 #define CCBITS (0xf0000000L)
124 #define INTBITS (0xc0L)
126 #if defined MODET && defined MODE32
127 #define PCBITS (0xffffffffL)
129 #define PCBITS (0xfffffffcL)
132 #define MODEBITS (0x1fL)
133 #define R15INTBITS (3L << 26)
135 #if defined MODET && defined MODE32
136 #define R15PCBITS (0x03ffffffL)
138 #define R15PCBITS (0x03fffffcL)
141 #define R15PCMODEBITS (0x03ffffffL)
142 #define R15MODEBITS (0x3L)
145 #define PCMASK PCBITS
146 #define PCWRAP(pc) (pc)
148 #define PCMASK R15PCBITS
149 #define PCWRAP(pc) ((pc) & R15PCBITS)
152 #define PC (state->Reg[15] & PCMASK)
153 #define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
154 #define R15INT (state->Reg[15] & R15INTBITS)
155 #define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
156 #define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
157 #define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
158 #define R15PC (state->Reg[15] & R15PCBITS)
159 #define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
160 #define R15MODE (state->Reg[15] & R15MODEBITS)
162 #define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (SFLAG << 27))
163 #define EINT (IFFLAGS << 6)
164 #define ER15INT (IFFLAGS << 26)
165 #define EMODE (state->Mode)
168 #define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
170 #define CPSR (ECC | EINT | EMODE)
176 #define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
179 #define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
180 #define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS)
181 #define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS)
182 #define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS)
183 #define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS)
184 #define SETR15PSR(s) if (state->Mode == USER26MODE) { \
185 state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE ; \
186 ASSIGNN((state->Reg[15] & NBIT) != 0) ; \
187 ASSIGNZ((state->Reg[15] & ZBIT) != 0) ; \
188 ASSIGNC((state->Reg[15] & CBIT) != 0) ; \
189 ASSIGNV((state->Reg[15] & VBIT) != 0) ; \
192 state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)) ; \
193 ARMul_R15Altered (state) ; \
195 #define SETABORT(i,m,d) do { \
196 int SETABORT_mode = (m); \
197 ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
198 ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \
199 | (i) | SETABORT_mode)); \
200 state->Reg[14] = temp - (d); \
205 #define LEGALADDR 0x03ffffff
206 #define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
207 #define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
210 #define INTERNALABORT(address) if (address < VECTORS) \
211 state->Aborted = ARMul_DataAbortV ; \
213 state->Aborted = ARMul_AddrExceptnV ;
216 #define TAKEABORT ARMul_Abort(state,ARMul_DataAbortV)
218 #define TAKEABORT if (state->Aborted == ARMul_AddrExceptnV) \
219 ARMul_Abort(state,ARMul_AddrExceptnV) ; \
221 ARMul_Abort(state,ARMul_DataAbortV)
223 #define CPTAKEABORT if (!state->Aborted) \
224 ARMul_Abort(state,ARMul_UndefinedInstrV) ; \
225 else if (state->Aborted == ARMul_AddrExceptnV) \
226 ARMul_Abort(state,ARMul_AddrExceptnV) ; \
228 ARMul_Abort(state,ARMul_DataAbortV)
231 /***************************************************************************\
232 * Different ways to start the next instruction *
233 \***************************************************************************/
238 #define PCINCEDNONSEQ 3
242 #define NORMALCYCLE state->NextInstr = 0
243 #define BUSUSEDN state->NextInstr |= 1 /* The next fetch will be an N cycle. */
244 #define BUSUSEDINCPCS \
247 if (! state->is_v4) \
249 state->Reg[15] += isize ; /* A standard PC inc and an S cycle. */ \
250 state->NextInstr = (state->NextInstr & 0xff) | 2; \
254 #define BUSUSEDINCPCN \
261 state->Reg[15] += isize ; /* A standard PC inc and an N cycle. */ \
262 state->NextInstr |= 3; \
266 #define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \
267 state->NextInstr |= 2
268 #define FLUSHPIPE state->NextInstr |= PRIMEPIPE
270 /***************************************************************************\
271 * Cycle based emulation *
272 \***************************************************************************/
274 #define OUTPUTCP(i,a,b)
281 /***************************************************************************\
282 * States of the cycle based state machine *
283 \***************************************************************************/
286 /***************************************************************************\
287 * Macros to extract parts of instructions *
288 \***************************************************************************/
290 #define DESTReg (BITS(12,15))
291 #define LHSReg (BITS(16,19))
292 #define RHSReg (BITS(0,3))
294 #define DEST (state->Reg[DESTReg])
298 #define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
300 #define LHS (state->Reg[LHSReg])
303 #define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]) )
306 #define MULDESTReg (BITS(16,19))
307 #define MULLHSReg (BITS(0,3))
308 #define MULRHSReg (BITS(8,11))
309 #define MULACCReg (BITS(12,15))
311 #define DPImmRHS (ARMul_ImmedTable[BITS(0,11)])
312 #define DPSImmRHS temp = BITS(0,11) ; \
313 rhs = ARMul_ImmedTable[temp] ; \
314 if (temp > 255) /* there was a shift */ \
318 #define DPRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
319 : GetDPRegRHS(state, instr))
320 #define DPSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
321 : GetDPSRegRHS(state, instr))
323 #define DPRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
324 : GetDPRegRHS(state, instr))
325 #define DPSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
326 : GetDPSRegRHS(state, instr))
329 #define LSBase state->Reg[LHSReg]
330 #define LSImmRHS (BITS(0,11))
333 #define LSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
334 : GetLSRegRHS(state, instr))
336 #define LSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
337 : GetLSRegRHS(state, instr))
340 #define LSMNumRegs ((ARMword)ARMul_BitList[BITS(0,7)] + \
341 (ARMword)ARMul_BitList[BITS(8,15)] )
342 #define LSMBaseFirst ((LHSReg == 0 && BIT(0)) || \
343 (BIT(LHSReg) && BITS(0,LHSReg-1) == 0))
345 #define SWAPSRC (state->Reg[RHSReg])
347 #define LSCOff (BITS(0,7) << 2)
348 #define CPNum BITS(8,11)
350 /***************************************************************************\
351 * Macro to rotate n right by b bits *
352 \***************************************************************************/
354 #define ROTATER(n,b) (((n)>>(b))|((n)<<(32-(b))))
356 /***************************************************************************\
357 * Macros to store results of instructions *
358 \***************************************************************************/
360 #define WRITEDEST(d) if (DESTReg==15) \
361 WriteR15(state, d) ; \
365 #define WRITESDEST(d) if (DESTReg == 15) \
366 WriteSR15(state, d) ; \
369 ARMul_NegZero(state, d) ; \
372 #define WRITEDESTB(d) if (DESTReg == 15) \
373 WriteR15Branch(state, d) ; \
377 #define BYTETOBUS(data) ((data & 0xff) | \
378 ((data & 0xff) << 8) | \
379 ((data & 0xff) << 16) | \
380 ((data & 0xff) << 24))
381 #define BUSTOBYTE(address,data) \
382 if (state->bigendSig) \
383 temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff ; \
385 temp = (data >> ((address & 3) << 3)) & 0xff
387 #define LOADMULT(instr,address,wb) LoadMult(state,instr,address,wb)
388 #define LOADSMULT(instr,address,wb) LoadSMult(state,instr,address,wb)
389 #define STOREMULT(instr,address,wb) StoreMult(state,instr,address,wb)
390 #define STORESMULT(instr,address,wb) StoreSMult(state,instr,address,wb)
392 #define POSBRANCH ((instr & 0x7fffff) << 2)
393 #define NEGBRANCH ((0xff000000 |(instr & 0xffffff)) << 2)
396 /***************************************************************************\
397 * Values for Emulate *
398 \***************************************************************************/
400 #define STOP 0 /* stop */
401 #define CHANGEMODE 1 /* change mode */
402 #define ONCE 2 /* execute just one interation */
403 #define RUN 3 /* continuous execution */
405 /***************************************************************************\
406 * Stuff that is shared across modes *
407 \***************************************************************************/
409 extern ARMword
ARMul_Emulate26 (ARMul_State
* state
);
410 extern ARMword
ARMul_Emulate32 (ARMul_State
* state
);
411 extern unsigned ARMul_MultTable
[]; /* Number of I cycles for a mult */
412 extern ARMword ARMul_ImmedTable
[]; /* immediate DP LHS values */
413 extern char ARMul_BitList
[]; /* number of bits in a byte table */
414 extern void ARMul_Abort26 (ARMul_State
* state
, ARMword
);
415 extern void ARMul_Abort32 (ARMul_State
* state
, ARMword
);
416 extern unsigned ARMul_NthReg (ARMword instr
, unsigned number
);
417 extern void ARMul_MSRCpsr (ARMul_State
* state
, ARMword instr
, ARMword rhs
);
418 extern void ARMul_NegZero (ARMul_State
* state
, ARMword result
);
419 extern void ARMul_AddCarry (ARMul_State
* state
, ARMword a
, ARMword b
,
421 extern int AddOverflow (ARMword a
, ARMword b
, ARMword result
);
422 extern int SubOverflow (ARMword a
, ARMword b
, ARMword result
);
423 extern void ARMul_AddOverflow (ARMul_State
* state
, ARMword a
, ARMword b
,
425 extern void ARMul_SubCarry (ARMul_State
* state
, ARMword a
, ARMword b
,
427 extern void ARMul_SubOverflow (ARMul_State
* state
, ARMword a
, ARMword b
,
429 extern void ARMul_CPSRAltered (ARMul_State
* state
);
430 extern void ARMul_R15Altered (ARMul_State
* state
);
431 extern ARMword
ARMul_SwitchMode (ARMul_State
* state
, ARMword oldmode
,
433 extern unsigned ARMul_NthReg (ARMword instr
, unsigned number
);
434 extern void ARMul_LDC (ARMul_State
* state
, ARMword instr
, ARMword address
);
435 extern void ARMul_STC (ARMul_State
* state
, ARMword instr
, ARMword address
);
436 extern void ARMul_MCR (ARMul_State
* state
, ARMword instr
, ARMword source
);
437 extern ARMword
ARMul_MRC (ARMul_State
* state
, ARMword instr
);
438 extern void ARMul_CDP (ARMul_State
* state
, ARMword instr
);
439 extern unsigned IntPending (ARMul_State
* state
);
440 extern ARMword
ARMul_Align (ARMul_State
* state
, ARMword address
,
442 #define EVENTLISTSIZE 1024L
448 t_undefined
, /* undefined Thumb instruction */
449 t_decoded
, /* instruction decoded to ARM equivalent */
450 t_branch
/* Thumb branch (already processed) */
454 extern tdstate
ARMul_ThumbDecode (ARMul_State
* state
, ARMword pc
,
455 ARMword tinstr
, ARMword
* ainstr
);
457 /***************************************************************************\
458 * Macros to scrutinize instructions *
459 \***************************************************************************/
466 #define UNDEF_MULPCDest
467 #define UNDEF_MULDestEQOp1
469 #define UNDEF_LSRBaseEQOffWb
470 #define UNDEF_LSRBaseEQDestWb
471 #define UNDEF_LSRPCBaseWb
472 #define UNDEF_LSRPCOffWb
473 #define UNDEF_LSMNoRegs
474 #define UNDEF_LSMPCBase
475 #define UNDEF_LSMUserBankWb
476 #define UNDEF_LSMBaseInListWb
478 #define UNDEF_CoProHS
480 #define UNDEF_LSCPCBaseWb
481 #define UNDEF_UndefNotBounced
482 #define UNDEF_ShortInt
483 #define UNDEF_IllegalMode
484 #define UNDEF_Prog32SigChange
485 #define UNDEF_Data32SigChange
487 /* Coprocessor support functions. */
488 extern unsigned ARMul_CoProInit (ARMul_State
*);
489 extern void ARMul_CoProExit (ARMul_State
*);
490 extern void ARMul_CoProAttach (ARMul_State
*, unsigned, ARMul_CPInits
*, ARMul_CPExits
*,
491 ARMul_LDCs
*, ARMul_STCs
*, ARMul_MRCs
*, ARMul_MCRs
*,
492 ARMul_CDPs
*, ARMul_CPReads
*, ARMul_CPWrites
*);
493 extern void ARMul_CoProDetach (ARMul_State
*, unsigned);
494 extern void write_cp15_reg (unsigned, unsigned, unsigned, ARMword
);
495 extern void write_cp14_reg (unsigned, ARMword
);
496 extern ARMword
read_cp14_reg (unsigned);
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