5e832f2e668afc17cb72eef13688eb8c27c900f0
1 /* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20 /***************************************************************************\
21 * Condition code values *
22 \***************************************************************************/
41 /***************************************************************************\
43 \***************************************************************************/
50 /***************************************************************************\
51 * Macros to twiddle the status flags and mode *
52 \***************************************************************************/
54 #define NBIT ((unsigned)1L << 31)
55 #define ZBIT (1L << 30)
56 #define CBIT (1L << 29)
57 #define VBIT (1L << 28)
58 #define IBIT (1L << 7)
59 #define FBIT (1L << 6)
60 #define IFBITS (3L << 6)
61 #define R15IBIT (1L << 27)
62 #define R15FBIT (1L << 26)
63 #define R15IFBITS (3L << 26)
65 #define POS(i) ( (~(i)) >> 31 )
66 #define NEG(i) ( (i) >> 31 )
68 #ifdef MODET /* Thumb support */
69 /* ??? This bit is actually in the low order bit of the PC in the hardware.
70 It isn't clear if the simulator needs to model that or not. */
71 #define TBIT (1L << 5)
72 #define TFLAG state->TFlag
73 #define SETT state->TFlag = 1
74 #define CLEART state->TFlag = 0
75 #define ASSIGNT(res) state->TFlag = res
78 #define NFLAG state->NFlag
79 #define SETN state->NFlag = 1
80 #define CLEARN state->NFlag = 0
81 #define ASSIGNN(res) state->NFlag = res
83 #define ZFLAG state->ZFlag
84 #define SETZ state->ZFlag = 1
85 #define CLEARZ state->ZFlag = 0
86 #define ASSIGNZ(res) state->ZFlag = res
88 #define CFLAG state->CFlag
89 #define SETC state->CFlag = 1
90 #define CLEARC state->CFlag = 0
91 #define ASSIGNC(res) state->CFlag = res
93 #define VFLAG state->VFlag
94 #define SETV state->VFlag = 1
95 #define CLEARV state->VFlag = 0
96 #define ASSIGNV(res) state->VFlag = res
99 #define IFLAG (state->IFFlags >> 1)
100 #define FFLAG (state->IFFlags & 1)
101 #define IFFLAGS state->IFFlags
102 #define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
103 #define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
105 #define PSR_FBITS (0xff000000L)
106 #define PSR_SBITS (0x00ff0000L)
107 #define PSR_XBITS (0x0000ff00L)
108 #define PSR_CBITS (0x000000ffL)
110 #define CCBITS (0xf0000000L)
111 #define INTBITS (0xc0L)
113 #if defined MODET && defined MODE32
114 #define PCBITS (0xffffffffL)
116 #define PCBITS (0xfffffffcL)
119 #define MODEBITS (0x1fL)
120 #define R15INTBITS (3L << 26)
122 #if defined MODET && defined MODE32
123 #define R15PCBITS (0x03ffffffL)
125 #define R15PCBITS (0x03fffffcL)
128 #define R15PCMODEBITS (0x03ffffffL)
129 #define R15MODEBITS (0x3L)
132 #define PCMASK PCBITS
133 #define PCWRAP(pc) (pc)
135 #define PCMASK R15PCBITS
136 #define PCWRAP(pc) ((pc) & R15PCBITS)
139 #define PC (state->Reg[15] & PCMASK)
140 #define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
141 #define R15INT (state->Reg[15] & R15INTBITS)
142 #define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
143 #define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
144 #define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
145 #define R15PC (state->Reg[15] & R15PCBITS)
146 #define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
147 #define R15MODE (state->Reg[15] & R15MODEBITS)
149 #define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28))
150 #define EINT (IFFLAGS << 6)
151 #define ER15INT (IFFLAGS << 26)
152 #define EMODE (state->Mode)
155 #define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
157 #define CPSR (ECC | EINT | EMODE)
163 #define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
166 #define GETSPSR(bank) bank>0?state->Spsr[bank]:ECC | EINT | EMODE ;
167 #define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS)
168 #define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS)
169 #define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS)
170 #define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS)
171 #define SETR15PSR(s) if (state->Mode == USER26MODE) { \
172 state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE ; \
173 ASSIGNN((state->Reg[15] & NBIT) != 0) ; \
174 ASSIGNZ((state->Reg[15] & ZBIT) != 0) ; \
175 ASSIGNC((state->Reg[15] & CBIT) != 0) ; \
176 ASSIGNV((state->Reg[15] & VBIT) != 0) ; \
179 state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)) ; \
180 ARMul_R15Altered (state) ; \
182 #define SETABORT(i,m) state->Cpsr = ECC | EINT | (i) | (m)
186 #define LEGALADDR 0x03ffffff
187 #define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
188 #define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
191 #define INTERNALABORT(address) if (address < VECTORS) \
192 state->Aborted = ARMul_DataAbortV ; \
194 state->Aborted = ARMul_AddrExceptnV ;
197 #define TAKEABORT ARMul_Abort(state,ARMul_DataAbortV)
199 #define TAKEABORT if (state->Aborted == ARMul_AddrExceptnV) \
200 ARMul_Abort(state,ARMul_AddrExceptnV) ; \
202 ARMul_Abort(state,ARMul_DataAbortV)
204 #define CPTAKEABORT if (!state->Aborted) \
205 ARMul_Abort(state,ARMul_UndefinedInstrV) ; \
206 else if (state->Aborted == ARMul_AddrExceptnV) \
207 ARMul_Abort(state,ARMul_AddrExceptnV) ; \
209 ARMul_Abort(state,ARMul_DataAbortV)
212 /***************************************************************************\
213 * Different ways to start the next instruction *
214 \***************************************************************************/
219 #define PCINCEDNONSEQ 3
223 #define NORMALCYCLE state->NextInstr = 0
224 #define BUSUSEDN state->NextInstr |= 1 /* the next fetch will be an N cycle */
225 #define BUSUSEDINCPCS state->Reg[15] += isize ; /* a standard PC inc and an S cycle */ \
226 state->NextInstr = (state->NextInstr & 0xff) | 2
227 #define BUSUSEDINCPCN state->Reg[15] += isize ; /* a standard PC inc and an N cycle */ \
228 state->NextInstr |= 3
229 #define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \
230 state->NextInstr |= 2
231 #define FLUSHPIPE state->NextInstr |= PRIMEPIPE
233 /***************************************************************************\
234 * Cycle based emulation *
235 \***************************************************************************/
237 #define OUTPUTCP(i,a,b)
244 /***************************************************************************\
245 * States of the cycle based state machine *
246 \***************************************************************************/
249 /***************************************************************************\
250 * Macros to extract parts of instructions *
251 \***************************************************************************/
253 #define DESTReg (BITS(12,15))
254 #define LHSReg (BITS(16,19))
255 #define RHSReg (BITS(0,3))
257 #define DEST (state->Reg[DESTReg])
261 #define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
263 #define LHS (state->Reg[LHSReg])
266 #define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]) )
269 #define MULDESTReg (BITS(16,19))
270 #define MULLHSReg (BITS(0,3))
271 #define MULRHSReg (BITS(8,11))
272 #define MULACCReg (BITS(12,15))
274 #define DPImmRHS (ARMul_ImmedTable[BITS(0,11)])
275 #define DPSImmRHS temp = BITS(0,11) ; \
276 rhs = ARMul_ImmedTable[temp] ; \
277 if (temp > 255) /* there was a shift */ \
281 #define DPRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
282 : GetDPRegRHS(state, instr))
283 #define DPSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
284 : GetDPSRegRHS(state, instr))
286 #define DPRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
287 : GetDPRegRHS(state, instr))
288 #define DPSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
289 : GetDPSRegRHS(state, instr))
292 #define LSBase state->Reg[LHSReg]
293 #define LSImmRHS (BITS(0,11))
296 #define LSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
297 : GetLSRegRHS(state, instr))
299 #define LSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
300 : GetLSRegRHS(state, instr))
303 #define LSMNumRegs ((ARMword)ARMul_BitList[BITS(0,7)] + \
304 (ARMword)ARMul_BitList[BITS(8,15)] )
305 #define LSMBaseFirst ((LHSReg == 0 && BIT(0)) || \
306 (BIT(LHSReg) && BITS(0,LHSReg-1) == 0))
308 #define SWAPSRC (state->Reg[RHSReg])
310 #define LSCOff (BITS(0,7) << 2)
311 #define CPNum BITS(8,11)
313 /***************************************************************************\
314 * Macro to rotate n right by b bits *
315 \***************************************************************************/
317 #define ROTATER(n,b) (((n)>>(b))|((n)<<(32-(b))))
319 /***************************************************************************\
320 * Macros to store results of instructions *
321 \***************************************************************************/
323 #define WRITEDEST(d) if (DESTReg==15) \
324 WriteR15(state, d) ; \
328 #define WRITESDEST(d) if (DESTReg == 15) \
329 WriteSR15(state, d) ; \
332 ARMul_NegZero(state, d) ; \
335 #define BYTETOBUS(data) ((data & 0xff) | \
336 ((data & 0xff) << 8) | \
337 ((data & 0xff) << 16) | \
338 ((data & 0xff) << 24))
339 #define BUSTOBYTE(address,data) \
340 if (state->bigendSig) \
341 temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff ; \
343 temp = (data >> ((address & 3) << 3)) & 0xff
345 #define LOADMULT(instr,address,wb) LoadMult(state,instr,address,wb)
346 #define LOADSMULT(instr,address,wb) LoadSMult(state,instr,address,wb)
347 #define STOREMULT(instr,address,wb) StoreMult(state,instr,address,wb)
348 #define STORESMULT(instr,address,wb) StoreSMult(state,instr,address,wb)
350 #define POSBRANCH ((instr & 0x7fffff) << 2)
351 #define NEGBRANCH (0xfc000000 | ((instr & 0xffffff) << 2))
353 /***************************************************************************\
354 * Values for Emulate *
355 \***************************************************************************/
357 #define STOP 0 /* stop */
358 #define CHANGEMODE 1 /* change mode */
359 #define ONCE 2 /* execute just one interation */
360 #define RUN 3 /* continuous execution */
362 /***************************************************************************\
363 * Stuff that is shared across modes *
364 \***************************************************************************/
366 extern ARMword
ARMul_Emulate26 (ARMul_State
* state
);
367 extern ARMword
ARMul_Emulate32 (ARMul_State
* state
);
368 extern unsigned ARMul_MultTable
[]; /* Number of I cycles for a mult */
369 extern ARMword ARMul_ImmedTable
[]; /* immediate DP LHS values */
370 extern char ARMul_BitList
[]; /* number of bits in a byte table */
371 extern void ARMul_Abort26 (ARMul_State
* state
, ARMword
);
372 extern void ARMul_Abort32 (ARMul_State
* state
, ARMword
);
373 extern unsigned ARMul_NthReg (ARMword instr
, unsigned number
);
374 extern void ARMul_MSRCpsr (ARMul_State
* state
, ARMword instr
, ARMword rhs
);
375 extern void ARMul_NegZero (ARMul_State
* state
, ARMword result
);
376 extern void ARMul_AddCarry (ARMul_State
* state
, ARMword a
, ARMword b
,
378 extern int AddOverflow (ARMword a
, ARMword b
, ARMword result
);
379 extern int SubOverflow (ARMword a
, ARMword b
, ARMword result
);
380 extern void ARMul_AddOverflow (ARMul_State
* state
, ARMword a
, ARMword b
,
382 extern void ARMul_SubCarry (ARMul_State
* state
, ARMword a
, ARMword b
,
384 extern void ARMul_SubOverflow (ARMul_State
* state
, ARMword a
, ARMword b
,
386 extern void ARMul_CPSRAltered (ARMul_State
* state
);
387 extern void ARMul_R15Altered (ARMul_State
* state
);
388 extern ARMword
ARMul_SwitchMode (ARMul_State
* state
, ARMword oldmode
,
390 extern unsigned ARMul_NthReg (ARMword instr
, unsigned number
);
391 extern void ARMul_LDC (ARMul_State
* state
, ARMword instr
, ARMword address
);
392 extern void ARMul_STC (ARMul_State
* state
, ARMword instr
, ARMword address
);
393 extern void ARMul_MCR (ARMul_State
* state
, ARMword instr
, ARMword source
);
394 extern ARMword
ARMul_MRC (ARMul_State
* state
, ARMword instr
);
395 extern void ARMul_CDP (ARMul_State
* state
, ARMword instr
);
396 extern unsigned IntPending (ARMul_State
* state
);
397 extern ARMword
ARMul_Align (ARMul_State
* state
, ARMword address
,
399 #define EVENTLISTSIZE 1024L
405 t_undefined
, /* undefined Thumb instruction */
406 t_decoded
, /* instruction decoded to ARM equivalent */
407 t_branch
/* Thumb branch (already processed) */
411 extern tdstate
ARMul_ThumbDecode (ARMul_State
* state
, ARMword pc
,
412 ARMword tinstr
, ARMword
* ainstr
);
414 /***************************************************************************\
415 * Macros to scrutinize instructions *
416 \***************************************************************************/
423 #define UNDEF_MULPCDest
424 #define UNDEF_MULDestEQOp1
426 #define UNDEF_LSRBaseEQOffWb
427 #define UNDEF_LSRBaseEQDestWb
428 #define UNDEF_LSRPCBaseWb
429 #define UNDEF_LSRPCOffWb
430 #define UNDEF_LSMNoRegs
431 #define UNDEF_LSMPCBase
432 #define UNDEF_LSMUserBankWb
433 #define UNDEF_LSMBaseInListWb
435 #define UNDEF_CoProHS
437 #define UNDEF_LSCPCBaseWb
438 #define UNDEF_UndefNotBounced
439 #define UNDEF_ShortInt
440 #define UNDEF_IllegalMode
441 #define UNDEF_Prog32SigChange
442 #define UNDEF_Data32SigChange
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