81ecd523d176299f777056fd90c4d2ecb523e1fd
1 /* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20 /***************************************************************************\
21 * Condition code values *
22 \***************************************************************************/
41 /***************************************************************************\
43 \***************************************************************************/
50 /***************************************************************************\
51 * Macros to twiddle the status flags and mode *
52 \***************************************************************************/
54 #define NBIT ((unsigned)1L << 31)
55 #define ZBIT (1L << 30)
56 #define CBIT (1L << 29)
57 #define VBIT (1L << 28)
58 #define IBIT (1L << 7)
59 #define FBIT (1L << 6)
60 #define IFBITS (3L << 6)
61 #define R15IBIT (1L << 27)
62 #define R15FBIT (1L << 26)
63 #define R15IFBITS (3L << 26)
65 #define POS(i) ( (~(i)) >> 31 )
66 #define NEG(i) ( (i) >> 31 )
68 #ifdef MODET /* Thumb support */
69 /* ??? This bit is actually in the low order bit of the PC in the hardware.
70 It isn't clear if the simulator needs to model that or not. */
71 #define TBIT (1L << 5)
72 #define TFLAG state->TFlag
73 #define SETT state->TFlag = 1
74 #define CLEART state->TFlag = 0
75 #define ASSIGNT(res) state->TFlag = res
76 #define INSN_SIZE (TFLAG ? 2 : 4)
81 #define NFLAG state->NFlag
82 #define SETN state->NFlag = 1
83 #define CLEARN state->NFlag = 0
84 #define ASSIGNN(res) state->NFlag = res
86 #define ZFLAG state->ZFlag
87 #define SETZ state->ZFlag = 1
88 #define CLEARZ state->ZFlag = 0
89 #define ASSIGNZ(res) state->ZFlag = res
91 #define CFLAG state->CFlag
92 #define SETC state->CFlag = 1
93 #define CLEARC state->CFlag = 0
94 #define ASSIGNC(res) state->CFlag = res
96 #define VFLAG state->VFlag
97 #define SETV state->VFlag = 1
98 #define CLEARV state->VFlag = 0
99 #define ASSIGNV(res) state->VFlag = res
102 #define IFLAG (state->IFFlags >> 1)
103 #define FFLAG (state->IFFlags & 1)
104 #define IFFLAGS state->IFFlags
105 #define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
106 #define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
108 #define PSR_FBITS (0xff000000L)
109 #define PSR_SBITS (0x00ff0000L)
110 #define PSR_XBITS (0x0000ff00L)
111 #define PSR_CBITS (0x000000ffL)
113 #define CCBITS (0xf0000000L)
114 #define INTBITS (0xc0L)
116 #if defined MODET && defined MODE32
117 #define PCBITS (0xffffffffL)
119 #define PCBITS (0xfffffffcL)
122 #define MODEBITS (0x1fL)
123 #define R15INTBITS (3L << 26)
125 #if defined MODET && defined MODE32
126 #define R15PCBITS (0x03ffffffL)
128 #define R15PCBITS (0x03fffffcL)
131 #define R15PCMODEBITS (0x03ffffffL)
132 #define R15MODEBITS (0x3L)
135 #define PCMASK PCBITS
136 #define PCWRAP(pc) (pc)
138 #define PCMASK R15PCBITS
139 #define PCWRAP(pc) ((pc) & R15PCBITS)
142 #define PC (state->Reg[15] & PCMASK)
143 #define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
144 #define R15INT (state->Reg[15] & R15INTBITS)
145 #define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
146 #define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
147 #define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
148 #define R15PC (state->Reg[15] & R15PCBITS)
149 #define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
150 #define R15MODE (state->Reg[15] & R15MODEBITS)
152 #define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28))
153 #define EINT (IFFLAGS << 6)
154 #define ER15INT (IFFLAGS << 26)
155 #define EMODE (state->Mode)
158 #define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
160 #define CPSR (ECC | EINT | EMODE)
166 #define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
169 #define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
170 #define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS)
171 #define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS)
172 #define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS)
173 #define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS)
174 #define SETR15PSR(s) if (state->Mode == USER26MODE) { \
175 state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE ; \
176 ASSIGNN((state->Reg[15] & NBIT) != 0) ; \
177 ASSIGNZ((state->Reg[15] & ZBIT) != 0) ; \
178 ASSIGNC((state->Reg[15] & CBIT) != 0) ; \
179 ASSIGNV((state->Reg[15] & VBIT) != 0) ; \
182 state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)) ; \
183 ARMul_R15Altered (state) ; \
185 #define SETABORT(i,m,d) do { \
186 int SETABORT_mode = (m); \
187 ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
188 ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \
189 | (i) | SETABORT_mode)); \
190 state->Reg[14] = temp - (d); \
195 #define LEGALADDR 0x03ffffff
196 #define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
197 #define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
200 #define INTERNALABORT(address) if (address < VECTORS) \
201 state->Aborted = ARMul_DataAbortV ; \
203 state->Aborted = ARMul_AddrExceptnV ;
206 #define TAKEABORT ARMul_Abort(state,ARMul_DataAbortV)
208 #define TAKEABORT if (state->Aborted == ARMul_AddrExceptnV) \
209 ARMul_Abort(state,ARMul_AddrExceptnV) ; \
211 ARMul_Abort(state,ARMul_DataAbortV)
213 #define CPTAKEABORT if (!state->Aborted) \
214 ARMul_Abort(state,ARMul_UndefinedInstrV) ; \
215 else if (state->Aborted == ARMul_AddrExceptnV) \
216 ARMul_Abort(state,ARMul_AddrExceptnV) ; \
218 ARMul_Abort(state,ARMul_DataAbortV)
221 /***************************************************************************\
222 * Different ways to start the next instruction *
223 \***************************************************************************/
228 #define PCINCEDNONSEQ 3
232 #define NORMALCYCLE state->NextInstr = 0
233 #define BUSUSEDN state->NextInstr |= 1 /* The next fetch will be an N cycle. */
234 #define BUSUSEDINCPCS \
237 if (! state->is_v4) \
239 state->Reg[15] += isize ; /* A standard PC inc and an S cycle. */ \
240 state->NextInstr = (state->NextInstr & 0xff) | 2; \
244 #define BUSUSEDINCPCN \
251 state->Reg[15] += isize ; /* A standard PC inc and an N cycle. */ \
252 state->NextInstr |= 3; \
256 #define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \
257 state->NextInstr |= 2
258 #define FLUSHPIPE state->NextInstr |= PRIMEPIPE
260 /***************************************************************************\
261 * Cycle based emulation *
262 \***************************************************************************/
264 #define OUTPUTCP(i,a,b)
271 /***************************************************************************\
272 * States of the cycle based state machine *
273 \***************************************************************************/
276 /***************************************************************************\
277 * Macros to extract parts of instructions *
278 \***************************************************************************/
280 #define DESTReg (BITS(12,15))
281 #define LHSReg (BITS(16,19))
282 #define RHSReg (BITS(0,3))
284 #define DEST (state->Reg[DESTReg])
288 #define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
290 #define LHS (state->Reg[LHSReg])
293 #define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]) )
296 #define MULDESTReg (BITS(16,19))
297 #define MULLHSReg (BITS(0,3))
298 #define MULRHSReg (BITS(8,11))
299 #define MULACCReg (BITS(12,15))
301 #define DPImmRHS (ARMul_ImmedTable[BITS(0,11)])
302 #define DPSImmRHS temp = BITS(0,11) ; \
303 rhs = ARMul_ImmedTable[temp] ; \
304 if (temp > 255) /* there was a shift */ \
308 #define DPRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
309 : GetDPRegRHS(state, instr))
310 #define DPSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
311 : GetDPSRegRHS(state, instr))
313 #define DPRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
314 : GetDPRegRHS(state, instr))
315 #define DPSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
316 : GetDPSRegRHS(state, instr))
319 #define LSBase state->Reg[LHSReg]
320 #define LSImmRHS (BITS(0,11))
323 #define LSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
324 : GetLSRegRHS(state, instr))
326 #define LSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
327 : GetLSRegRHS(state, instr))
330 #define LSMNumRegs ((ARMword)ARMul_BitList[BITS(0,7)] + \
331 (ARMword)ARMul_BitList[BITS(8,15)] )
332 #define LSMBaseFirst ((LHSReg == 0 && BIT(0)) || \
333 (BIT(LHSReg) && BITS(0,LHSReg-1) == 0))
335 #define SWAPSRC (state->Reg[RHSReg])
337 #define LSCOff (BITS(0,7) << 2)
338 #define CPNum BITS(8,11)
340 /***************************************************************************\
341 * Macro to rotate n right by b bits *
342 \***************************************************************************/
344 #define ROTATER(n,b) (((n)>>(b))|((n)<<(32-(b))))
346 /***************************************************************************\
347 * Macros to store results of instructions *
348 \***************************************************************************/
350 #define WRITEDEST(d) if (DESTReg==15) \
351 WriteR15(state, d) ; \
355 #define WRITESDEST(d) if (DESTReg == 15) \
356 WriteSR15(state, d) ; \
359 ARMul_NegZero(state, d) ; \
362 #define WRITEDESTB(d) if (DESTReg == 15) \
363 WriteR15Branch(state, d) ; \
367 #define BYTETOBUS(data) ((data & 0xff) | \
368 ((data & 0xff) << 8) | \
369 ((data & 0xff) << 16) | \
370 ((data & 0xff) << 24))
371 #define BUSTOBYTE(address,data) \
372 if (state->bigendSig) \
373 temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff ; \
375 temp = (data >> ((address & 3) << 3)) & 0xff
377 #define LOADMULT(instr,address,wb) LoadMult(state,instr,address,wb)
378 #define LOADSMULT(instr,address,wb) LoadSMult(state,instr,address,wb)
379 #define STOREMULT(instr,address,wb) StoreMult(state,instr,address,wb)
380 #define STORESMULT(instr,address,wb) StoreSMult(state,instr,address,wb)
382 #define POSBRANCH ((instr & 0x7fffff) << 2)
383 #define NEGBRANCH (0xfc000000 | ((instr & 0xffffff) << 2))
385 /***************************************************************************\
386 * Values for Emulate *
387 \***************************************************************************/
389 #define STOP 0 /* stop */
390 #define CHANGEMODE 1 /* change mode */
391 #define ONCE 2 /* execute just one interation */
392 #define RUN 3 /* continuous execution */
394 /***************************************************************************\
395 * Stuff that is shared across modes *
396 \***************************************************************************/
398 extern ARMword
ARMul_Emulate26 (ARMul_State
* state
);
399 extern ARMword
ARMul_Emulate32 (ARMul_State
* state
);
400 extern unsigned ARMul_MultTable
[]; /* Number of I cycles for a mult */
401 extern ARMword ARMul_ImmedTable
[]; /* immediate DP LHS values */
402 extern char ARMul_BitList
[]; /* number of bits in a byte table */
403 extern void ARMul_Abort26 (ARMul_State
* state
, ARMword
);
404 extern void ARMul_Abort32 (ARMul_State
* state
, ARMword
);
405 extern unsigned ARMul_NthReg (ARMword instr
, unsigned number
);
406 extern void ARMul_MSRCpsr (ARMul_State
* state
, ARMword instr
, ARMword rhs
);
407 extern void ARMul_NegZero (ARMul_State
* state
, ARMword result
);
408 extern void ARMul_AddCarry (ARMul_State
* state
, ARMword a
, ARMword b
,
410 extern int AddOverflow (ARMword a
, ARMword b
, ARMword result
);
411 extern int SubOverflow (ARMword a
, ARMword b
, ARMword result
);
412 extern void ARMul_AddOverflow (ARMul_State
* state
, ARMword a
, ARMword b
,
414 extern void ARMul_SubCarry (ARMul_State
* state
, ARMword a
, ARMword b
,
416 extern void ARMul_SubOverflow (ARMul_State
* state
, ARMword a
, ARMword b
,
418 extern void ARMul_CPSRAltered (ARMul_State
* state
);
419 extern void ARMul_R15Altered (ARMul_State
* state
);
420 extern ARMword
ARMul_SwitchMode (ARMul_State
* state
, ARMword oldmode
,
422 extern unsigned ARMul_NthReg (ARMword instr
, unsigned number
);
423 extern void ARMul_LDC (ARMul_State
* state
, ARMword instr
, ARMword address
);
424 extern void ARMul_STC (ARMul_State
* state
, ARMword instr
, ARMword address
);
425 extern void ARMul_MCR (ARMul_State
* state
, ARMword instr
, ARMword source
);
426 extern ARMword
ARMul_MRC (ARMul_State
* state
, ARMword instr
);
427 extern void ARMul_CDP (ARMul_State
* state
, ARMword instr
);
428 extern unsigned IntPending (ARMul_State
* state
);
429 extern ARMword
ARMul_Align (ARMul_State
* state
, ARMword address
,
431 #define EVENTLISTSIZE 1024L
437 t_undefined
, /* undefined Thumb instruction */
438 t_decoded
, /* instruction decoded to ARM equivalent */
439 t_branch
/* Thumb branch (already processed) */
443 extern tdstate
ARMul_ThumbDecode (ARMul_State
* state
, ARMword pc
,
444 ARMword tinstr
, ARMword
* ainstr
);
446 /***************************************************************************\
447 * Macros to scrutinize instructions *
448 \***************************************************************************/
455 #define UNDEF_MULPCDest
456 #define UNDEF_MULDestEQOp1
458 #define UNDEF_LSRBaseEQOffWb
459 #define UNDEF_LSRBaseEQDestWb
460 #define UNDEF_LSRPCBaseWb
461 #define UNDEF_LSRPCOffWb
462 #define UNDEF_LSMNoRegs
463 #define UNDEF_LSMPCBase
464 #define UNDEF_LSMUserBankWb
465 #define UNDEF_LSMBaseInListWb
467 #define UNDEF_CoProHS
469 #define UNDEF_LSCPCBaseWb
470 #define UNDEF_UndefNotBounced
471 #define UNDEF_ShortInt
472 #define UNDEF_IllegalMode
473 #define UNDEF_Prog32SigChange
474 #define UNDEF_Data32SigChange
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