sim/arm/arminit.c

   1 /*  arminit.c -- ARMulator initialization:  ARM6 Instruction Emulator.
   2     Copyright (C) 1994 Advanced RISC Machines Ltd.
   3
   4     This program is free software; you can redistribute it and/or modify
   5     it under the terms of the GNU General Public License as published by
   6     the Free Software Foundation; either version 2 of the License, or
   7     (at your option) any later version.
   8
   9     This program is distributed in the hope that it will be useful,
  10     but WITHOUT ANY WARRANTY; without even the implied warranty of
  11     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12     GNU General Public License for more details.
  13
  14     You should have received a copy of the GNU General Public License
  15     along with this program; if not, write to the Free Software
  16     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  17
  18 #include "armdefs.h"
  19 #include "armemu.h"
  20
  21 /***************************************************************************\
  22 *                 Definitions for the emulator architecture                 *
  23 \***************************************************************************/
  24
  25 void ARMul_EmulateInit (void);
  26 ARMul_State *ARMul_NewState (void);
  27 void ARMul_Reset (ARMul_State * state);
  28 ARMword ARMul_DoCycle (ARMul_State * state);
  29 unsigned ARMul_DoCoPro (ARMul_State * state);
  30 ARMword ARMul_DoProg (ARMul_State * state);
  31 ARMword ARMul_DoInstr (ARMul_State * state);
  32 void ARMul_Abort (ARMul_State * state, ARMword address);
  33
  34 unsigned ARMul_MultTable[32] =
  35   { 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9,
  36   10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16
  37 };
  38 ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */
  39 char ARMul_BitList[256];        /* number of bits in a byte table */
  40
  41 /***************************************************************************\
  42 *         Call this routine once to set up the emulator's tables.           *
  43 \***************************************************************************/
  44
  45 void
  46 ARMul_EmulateInit (void)
  47 {
  48   unsigned long i, j;
  49
  50   for (i = 0; i < 4096; i++)
  51     {                           /* the values of 12 bit dp rhs's */
  52       ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL);
  53     }
  54
  55   for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */
  56   for (j = 1; j < 256; j <<= 1)
  57     for (i = 0; i < 256; i++)
  58       if ((i & j) > 0)
  59         ARMul_BitList[i]++;
  60
  61   for (i = 0; i < 256; i++)
  62     ARMul_BitList[i] *= 4;      /* you always need 4 times these values */
  63
  64 }
  65
  66 /***************************************************************************\
  67 *            Returns a new instantiation of the ARMulator's state           *
  68 \***************************************************************************/
  69
  70 ARMul_State *
  71 ARMul_NewState (void)
  72 {
  73   ARMul_State *state;
  74   unsigned i, j;
  75
  76   state = (ARMul_State *) malloc (sizeof (ARMul_State));
  77   memset (state, 0, sizeof (ARMul_State));
  78
  79   state->Emulate = RUN;
  80   for (i = 0; i < 16; i++)
  81     {
  82       state->Reg[i] = 0;
  83       for (j = 0; j < 7; j++)
  84         state->RegBank[j][i] = 0;
  85     }
  86   for (i = 0; i < 7; i++)
  87     state->Spsr[i] = 0;
  88
  89   state->Mode = USER26MODE;
  90
  91   state->CallDebug = FALSE;
  92   state->Debug = FALSE;
  93   state->VectorCatch = 0;
  94   state->Aborted = FALSE;
  95   state->Reseted = FALSE;
  96   state->Inted = 3;
  97   state->LastInted = 3;
  98
  99   state->MemDataPtr = NULL;
 100   state->MemInPtr = NULL;
 101   state->MemOutPtr = NULL;
 102   state->MemSparePtr = NULL;
 103   state->MemSize = 0;
 104
 105   state->OSptr = NULL;
 106   state->CommandLine = NULL;
 107
 108   state->EventSet = 0;
 109   state->Now = 0;
 110   state->EventPtr = (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE *
 111                                                   sizeof (struct EventNode
 112                                                           *));
 113   for (i = 0; i < EVENTLISTSIZE; i++)
 114     *(state->EventPtr + i) = NULL;
 115
 116 #ifdef ARM61
 117   state->prog32Sig = LOW;
 118   state->data32Sig = LOW;
 119 #else
 120   state->prog32Sig = HIGH;
 121   state->data32Sig = HIGH;
 122 #endif
 123
 124   state->lateabtSig = LOW;
 125   state->bigendSig = LOW;
 126
 127   state->is_StrongARM = LOW;
 128
 129   ARMul_Reset (state);
 130   return (state);
 131 }
 132
 133 /***************************************************************************\
 134 *       Call this routine to set ARMulator to model a certain processor     *
 135 \***************************************************************************/
 136
 137 void
 138 ARMul_SelectProcessor (ARMul_State * state, unsigned processor)
 139 {
 140   if (processor & ARM_Fix26_Prop)
 141     {
 142       state->prog32Sig = LOW;
 143       state->data32Sig = LOW;
 144     }
 145   else
 146     {
 147       state->prog32Sig = HIGH;
 148       state->data32Sig = HIGH;
 149     }
 150
 151   state->lateabtSig = LOW;
 152
 153   state->is_StrongARM = (processor & ARM_Strong_Prop) ? HIGH : LOW;
 154 }
 155
 156 /***************************************************************************\
 157 * Call this routine to set up the initial machine state (or perform a RESET *
 158 \***************************************************************************/
 159
 160 void
 161 ARMul_Reset (ARMul_State * state)
 162 {
 163   state->NextInstr = 0;
 164
 165   if (state->prog32Sig)
 166     {
 167       state->Reg[15] = 0;
 168       state->Cpsr = INTBITS | SVC32MODE;
 169       state->Mode = SVC32MODE;
 170     }
 171   else
 172     {
 173       state->Reg[15] = R15INTBITS | SVC26MODE;
 174       state->Cpsr = INTBITS | SVC26MODE;
 175       state->Mode = SVC26MODE;
 176     }
 177
 178   ARMul_CPSRAltered (state);
 179   state->Bank = SVCBANK;
 180
 181   FLUSHPIPE;
 182
 183   state->EndCondition = 0;
 184   state->ErrorCode = 0;
 185
 186   state->Exception = FALSE;
 187   state->NresetSig = HIGH;
 188   state->NfiqSig = HIGH;
 189   state->NirqSig = HIGH;
 190   state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
 191   state->abortSig = LOW;
 192   state->AbortAddr = 1;
 193
 194   state->NumInstrs = 0;
 195   state->NumNcycles = 0;
 196   state->NumScycles = 0;
 197   state->NumIcycles = 0;
 198   state->NumCcycles = 0;
 199   state->NumFcycles = 0;
 200 #ifdef ASIM
 201   (void) ARMul_MemoryInit ();
 202   ARMul_OSInit (state);
 203 #endif
 204 }
 205
 206
 207 /***************************************************************************\
 208 * Emulate the execution of an entire program.  Start the correct emulator   *
 209 * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the   *
 210 * address of the last instruction that is executed.                         *
 211 \***************************************************************************/
 212
 213 ARMword
 214 ARMul_DoProg (ARMul_State * state)
 215 {
 216   ARMword pc = 0;
 217
 218   state->Emulate = RUN;
 219   while (state->Emulate != STOP)
 220     {
 221       state->Emulate = RUN;
 222       if (state->prog32Sig && ARMul_MODE32BIT)
 223         pc = ARMul_Emulate32 (state);
 224       else
 225         pc = ARMul_Emulate26 (state);
 226     }
 227   return (pc);
 228 }
 229
 230 /***************************************************************************\
 231 * Emulate the execution of one instruction.  Start the correct emulator     *
 232 * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the   *
 233 * address of the instruction that is executed.                              *
 234 \***************************************************************************/
 235
 236 ARMword
 237 ARMul_DoInstr (ARMul_State * state)
 238 {
 239   ARMword pc = 0;
 240
 241   state->Emulate = ONCE;
 242   if (state->prog32Sig && ARMul_MODE32BIT)
 243     pc = ARMul_Emulate32 (state);
 244   else
 245     pc = ARMul_Emulate26 (state);
 246
 247   return (pc);
 248 }
 249
 250 /***************************************************************************\
 251 * This routine causes an Abort to occur, including selecting the correct    *
 252 * mode, register bank, and the saving of registers.  Call with the          *
 253 * appropriate vector's memory address (0,4,8 ....)                          *
 254 \***************************************************************************/
 255
 256 void
 257 ARMul_Abort (ARMul_State * state, ARMword vector)
 258 {
 259   ARMword temp;
 260   int isize = INSN_SIZE;
 261
 262   state->Aborted = FALSE;
 263
 264   if (ARMul_OSException (state, vector, ARMul_GetPC (state)))
 265     return;
 266
 267   if (state->prog32Sig)
 268     if (ARMul_MODE26BIT)
 269       temp = R15PC;
 270     else
 271       temp = state->Reg[15];
 272   else
 273     temp = R15PC | ECC | ER15INT | EMODE;
 274
 275   switch (vector)
 276     {
 277     case ARMul_ResetV:          /* RESET */
 278       SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE, 0);
 279       break;
 280     case ARMul_UndefinedInstrV: /* Undefined Instruction */
 281       SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE, isize);
 282       break;
 283     case ARMul_SWIV:            /* Software Interrupt */
 284       SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, isize);
 285       break;
 286     case ARMul_PrefetchAbortV:  /* Prefetch Abort */
 287       state->AbortAddr = 1;
 288       SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, isize);
 289       break;
 290     case ARMul_DataAbortV:      /* Data Abort */
 291       SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, isize);
 292       break;
 293     case ARMul_AddrExceptnV:    /* Address Exception */
 294       SETABORT (IBIT, SVC26MODE, isize);
 295       break;
 296     case ARMul_IRQV:            /* IRQ */
 297       SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, isize);
 298       break;
 299     case ARMul_FIQV:            /* FIQ */
 300       SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, isize);
 301       break;
 302     }
 303   if (ARMul_MODE32BIT)
 304     ARMul_SetR15 (state, vector);
 305   else
 306     ARMul_SetR15 (state, R15CCINTMODE | vector);
 307 }