1 /* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 3 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, see <http://www.gnu.org/licenses/>. */
23 /***************************************************************************\
24 * Definitions for the emulator architecture *
25 \***************************************************************************/
27 void ARMul_EmulateInit (void);
28 ARMul_State
*ARMul_NewState (void);
29 void ARMul_Reset (ARMul_State
* state
);
30 ARMword
ARMul_DoCycle (ARMul_State
* state
);
31 unsigned ARMul_DoCoPro (ARMul_State
* state
);
32 ARMword
ARMul_DoProg (ARMul_State
* state
);
33 ARMword
ARMul_DoInstr (ARMul_State
* state
);
34 void ARMul_Abort (ARMul_State
* state
, ARMword address
);
36 unsigned ARMul_MultTable
[32] =
37 { 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9,
38 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16
40 ARMword ARMul_ImmedTable
[4096]; /* immediate DP LHS values */
41 char ARMul_BitList
[256]; /* number of bits in a byte table */
43 /***************************************************************************\
44 * Call this routine once to set up the emulator's tables. *
45 \***************************************************************************/
48 ARMul_EmulateInit (void)
52 for (i
= 0; i
< 4096; i
++)
53 { /* the values of 12 bit dp rhs's */
54 ARMul_ImmedTable
[i
] = ROTATER (i
& 0xffL
, (i
>> 7L) & 0x1eL
);
57 for (i
= 0; i
< 256; ARMul_BitList
[i
++] = 0); /* how many bits in LSM */
58 for (j
= 1; j
< 256; j
<<= 1)
59 for (i
= 0; i
< 256; i
++)
63 for (i
= 0; i
< 256; i
++)
64 ARMul_BitList
[i
] *= 4; /* you always need 4 times these values */
68 /***************************************************************************\
69 * Returns a new instantiation of the ARMulator's state *
70 \***************************************************************************/
78 state
= (ARMul_State
*) malloc (sizeof (ARMul_State
));
79 memset (state
, 0, sizeof (ARMul_State
));
82 for (i
= 0; i
< 16; i
++)
85 for (j
= 0; j
< 7; j
++)
86 state
->RegBank
[j
][i
] = 0;
88 for (i
= 0; i
< 7; i
++)
91 /* state->Mode = USER26MODE; */
92 state
->Mode
= USER32MODE
;
94 state
->CallDebug
= FALSE
;
96 state
->VectorCatch
= 0;
97 state
->Aborted
= FALSE
;
98 state
->Reseted
= FALSE
;
100 state
->LastInted
= 3;
102 state
->MemDataPtr
= NULL
;
103 state
->MemInPtr
= NULL
;
104 state
->MemOutPtr
= NULL
;
105 state
->MemSparePtr
= NULL
;
109 state
->CommandLine
= NULL
;
111 state
->CP14R0_CCD
= -1;
116 state
->EventPtr
= (struct EventNode
**) malloc ((unsigned) EVENTLISTSIZE
*
117 sizeof (struct EventNode
119 for (i
= 0; i
< EVENTLISTSIZE
; i
++)
120 *(state
->EventPtr
+ i
) = NULL
;
122 state
->prog32Sig
= HIGH
;
123 state
->data32Sig
= HIGH
;
125 state
->lateabtSig
= LOW
;
126 state
->bigendSig
= LOW
;
131 state
->is_XScale
= LOW
;
132 state
->is_iWMMXt
= LOW
;
140 /***************************************************************************\
141 Call this routine to set ARMulator to model certain processor properities
142 \***************************************************************************/
145 ARMul_SelectProcessor (ARMul_State
* state
, unsigned properties
)
147 if (properties
& ARM_Fix26_Prop
)
149 state
->prog32Sig
= LOW
;
150 state
->data32Sig
= LOW
;
154 state
->prog32Sig
= HIGH
;
155 state
->data32Sig
= HIGH
;
158 state
->lateabtSig
= LOW
;
160 state
->is_v4
= (properties
& (ARM_v4_Prop
| ARM_v5_Prop
)) ? HIGH
: LOW
;
161 state
->is_v5
= (properties
& ARM_v5_Prop
) ? HIGH
: LOW
;
162 state
->is_v5e
= (properties
& ARM_v5e_Prop
) ? HIGH
: LOW
;
163 state
->is_XScale
= (properties
& ARM_XScale_Prop
) ? HIGH
: LOW
;
164 state
->is_iWMMXt
= (properties
& ARM_iWMMXt_Prop
) ? HIGH
: LOW
;
165 state
->is_ep9312
= (properties
& ARM_ep9312_Prop
) ? HIGH
: LOW
;
166 state
->is_v6
= (properties
& ARM_v6_Prop
) ? HIGH
: LOW
;
168 /* Only initialse the coprocessor support once we
169 know what kind of chip we are dealing with. */
170 ARMul_CoProInit (state
);
173 /***************************************************************************\
174 * Call this routine to set up the initial machine state (or perform a RESET *
175 \***************************************************************************/
178 ARMul_Reset (ARMul_State
* state
)
180 state
->NextInstr
= 0;
182 if (state
->prog32Sig
)
185 state
->Cpsr
= INTBITS
| SVC32MODE
;
186 state
->Mode
= SVC32MODE
;
190 state
->Reg
[15] = R15INTBITS
| SVC26MODE
;
191 state
->Cpsr
= INTBITS
| SVC26MODE
;
192 state
->Mode
= SVC26MODE
;
195 ARMul_CPSRAltered (state
);
196 state
->Bank
= SVCBANK
;
200 state
->EndCondition
= 0;
202 state
->Exception
= FALSE
;
203 state
->NresetSig
= HIGH
;
204 state
->NfiqSig
= HIGH
;
205 state
->NirqSig
= HIGH
;
206 state
->NtransSig
= (state
->Mode
& 3) ? HIGH
: LOW
;
207 state
->abortSig
= LOW
;
208 state
->AbortAddr
= 1;
210 state
->NumInstrs
= 0;
211 state
->NumNcycles
= 0;
212 state
->NumScycles
= 0;
213 state
->NumIcycles
= 0;
214 state
->NumCcycles
= 0;
215 state
->NumFcycles
= 0;
217 (void) ARMul_MemoryInit ();
218 ARMul_OSInit (state
);
223 /***************************************************************************\
224 * Emulate the execution of an entire program. Start the correct emulator *
225 * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
226 * address of the last instruction that is executed. *
227 \***************************************************************************/
230 ARMul_DoProg (ARMul_State
* state
)
234 state
->Emulate
= RUN
;
235 while (state
->Emulate
!= STOP
)
237 state
->Emulate
= RUN
;
238 if (state
->prog32Sig
&& ARMul_MODE32BIT
)
239 pc
= ARMul_Emulate32 (state
);
241 pc
= ARMul_Emulate26 (state
);
246 /***************************************************************************\
247 * Emulate the execution of one instruction. Start the correct emulator *
248 * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
249 * address of the instruction that is executed. *
250 \***************************************************************************/
253 ARMul_DoInstr (ARMul_State
* state
)
257 state
->Emulate
= ONCE
;
258 if (state
->prog32Sig
&& ARMul_MODE32BIT
)
259 pc
= ARMul_Emulate32 (state
);
261 pc
= ARMul_Emulate26 (state
);
266 /***************************************************************************\
267 * This routine causes an Abort to occur, including selecting the correct *
268 * mode, register bank, and the saving of registers. Call with the *
269 * appropriate vector's memory address (0,4,8 ....) *
270 \***************************************************************************/
273 ARMul_Abort (ARMul_State
* state
, ARMword vector
)
276 int isize
= INSN_SIZE
;
277 int esize
= (TFLAG
? 0 : 4);
278 int e2size
= (TFLAG
? -4 : 0);
280 state
->Aborted
= FALSE
;
282 if (state
->prog32Sig
)
286 temp
= state
->Reg
[15];
288 temp
= R15PC
| ECC
| ER15INT
| EMODE
;
292 case ARMul_ResetV
: /* RESET */
293 SETABORT (INTBITS
, state
->prog32Sig
? SVC32MODE
: SVC26MODE
, 0);
295 case ARMul_UndefinedInstrV
: /* Undefined Instruction */
296 SETABORT (IBIT
, state
->prog32Sig
? UNDEF32MODE
: SVC26MODE
, isize
);
298 case ARMul_SWIV
: /* Software Interrupt */
299 SETABORT (IBIT
, state
->prog32Sig
? SVC32MODE
: SVC26MODE
, isize
);
301 case ARMul_PrefetchAbortV
: /* Prefetch Abort */
302 state
->AbortAddr
= 1;
303 SETABORT (IBIT
, state
->prog32Sig
? ABORT32MODE
: SVC26MODE
, esize
);
305 case ARMul_DataAbortV
: /* Data Abort */
306 SETABORT (IBIT
, state
->prog32Sig
? ABORT32MODE
: SVC26MODE
, e2size
);
308 case ARMul_AddrExceptnV
: /* Address Exception */
309 SETABORT (IBIT
, SVC26MODE
, isize
);
311 case ARMul_IRQV
: /* IRQ */
312 if ( ! state
->is_XScale
313 || ! state
->CPRead
[13] (state
, 0, & temp
)
314 || (temp
& ARMul_CP13_R0_IRQ
))
315 SETABORT (IBIT
, state
->prog32Sig
? IRQ32MODE
: IRQ26MODE
, esize
);
317 case ARMul_FIQV
: /* FIQ */
318 if ( ! state
->is_XScale
319 || ! state
->CPRead
[13] (state
, 0, & temp
)
320 || (temp
& ARMul_CP13_R0_FIQ
))
321 SETABORT (INTBITS
, state
->prog32Sig
? FIQ32MODE
: FIQ26MODE
, esize
);
325 ARMul_SetR15 (state
, vector
);
327 ARMul_SetR15 (state
, R15CCINTMODE
| vector
);
329 if (ARMul_ReadWord (state
, ARMul_GetPC (state
)) == 0)
331 /* No vector has been installed. Rather than simulating whatever
332 random bits might happen to be at address 0x20 onwards we elect
336 case ARMul_ResetV
: state
->EndCondition
= RDIError_Reset
; break;
337 case ARMul_UndefinedInstrV
: state
->EndCondition
= RDIError_UndefinedInstruction
; break;
338 case ARMul_SWIV
: state
->EndCondition
= RDIError_SoftwareInterrupt
; break;
339 case ARMul_PrefetchAbortV
: state
->EndCondition
= RDIError_PrefetchAbort
; break;
340 case ARMul_DataAbortV
: state
->EndCondition
= RDIError_DataAbort
; break;
341 case ARMul_AddrExceptnV
: state
->EndCondition
= RDIError_AddressException
; break;
342 case ARMul_IRQV
: state
->EndCondition
= RDIError_IRQ
; break;
343 case ARMul_FIQV
: state
->EndCondition
= RDIError_FIQ
; break;
346 state
->Emulate
= FALSE
;