1 /* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 /***************************************************************************\
22 * Definitions for the emulator architecture *
23 \***************************************************************************/
25 void ARMul_EmulateInit (void);
26 ARMul_State
*ARMul_NewState (void);
27 void ARMul_Reset (ARMul_State
* state
);
28 ARMword
ARMul_DoCycle (ARMul_State
* state
);
29 unsigned ARMul_DoCoPro (ARMul_State
* state
);
30 ARMword
ARMul_DoProg (ARMul_State
* state
);
31 ARMword
ARMul_DoInstr (ARMul_State
* state
);
32 void ARMul_Abort (ARMul_State
* state
, ARMword address
);
34 unsigned ARMul_MultTable
[32] =
35 { 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9,
36 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16
38 ARMword ARMul_ImmedTable
[4096]; /* immediate DP LHS values */
39 char ARMul_BitList
[256]; /* number of bits in a byte table */
41 /***************************************************************************\
42 * Call this routine once to set up the emulator's tables. *
43 \***************************************************************************/
46 ARMul_EmulateInit (void)
50 for (i
= 0; i
< 4096; i
++)
51 { /* the values of 12 bit dp rhs's */
52 ARMul_ImmedTable
[i
] = ROTATER (i
& 0xffL
, (i
>> 7L) & 0x1eL
);
55 for (i
= 0; i
< 256; ARMul_BitList
[i
++] = 0); /* how many bits in LSM */
56 for (j
= 1; j
< 256; j
<<= 1)
57 for (i
= 0; i
< 256; i
++)
61 for (i
= 0; i
< 256; i
++)
62 ARMul_BitList
[i
] *= 4; /* you always need 4 times these values */
66 /***************************************************************************\
67 * Returns a new instantiation of the ARMulator's state *
68 \***************************************************************************/
76 state
= (ARMul_State
*) malloc (sizeof (ARMul_State
));
77 memset (state
, 0, sizeof (ARMul_State
));
80 for (i
= 0; i
< 16; i
++)
83 for (j
= 0; j
< 7; j
++)
84 state
->RegBank
[j
][i
] = 0;
86 for (i
= 0; i
< 7; i
++)
90 state
->CallDebug
= FALSE
;
92 state
->VectorCatch
= 0;
93 state
->Aborted
= FALSE
;
94 state
->Reseted
= FALSE
;
98 state
->MemDataPtr
= NULL
;
99 state
->MemInPtr
= NULL
;
100 state
->MemOutPtr
= NULL
;
101 state
->MemSparePtr
= NULL
;
105 state
->CommandLine
= NULL
;
109 state
->EventPtr
= (struct EventNode
**) malloc ((unsigned) EVENTLISTSIZE
*
110 sizeof (struct EventNode
112 for (i
= 0; i
< EVENTLISTSIZE
; i
++)
113 *(state
->EventPtr
+ i
) = NULL
;
116 state
->prog32Sig
= LOW
;
117 state
->data32Sig
= LOW
;
119 state
->prog32Sig
= HIGH
;
120 state
->data32Sig
= HIGH
;
123 state
->lateabtSig
= LOW
;
124 state
->bigendSig
= LOW
;
130 /***************************************************************************\
131 * Call this routine to set ARMulator to model a certain processor *
132 \***************************************************************************/
135 ARMul_SelectProcessor (ARMul_State
* state
, unsigned processor
)
137 if (processor
& ARM_Fix26_Prop
)
139 state
->prog32Sig
= LOW
;
140 state
->data32Sig
= LOW
;
144 state
->prog32Sig
= HIGH
;
145 state
->data32Sig
= HIGH
;
148 state
->lateabtSig
= LOW
;
151 /***************************************************************************\
152 * Call this routine to set up the initial machine state (or perform a RESET *
153 \***************************************************************************/
156 ARMul_Reset (ARMul_State
* state
)
158 state
->NextInstr
= 0;
159 if (state
->prog32Sig
)
162 state
->Cpsr
= INTBITS
| SVC32MODE
;
166 state
->Reg
[15] = R15INTBITS
| SVC26MODE
;
167 state
->Cpsr
= INTBITS
| SVC26MODE
;
169 ARMul_CPSRAltered (state
);
170 state
->Bank
= SVCBANK
;
173 state
->EndCondition
= 0;
174 state
->ErrorCode
= 0;
176 state
->Exception
= FALSE
;
177 state
->NresetSig
= HIGH
;
178 state
->NfiqSig
= HIGH
;
179 state
->NirqSig
= HIGH
;
180 state
->NtransSig
= (state
->Mode
& 3) ? HIGH
: LOW
;
181 state
->abortSig
= LOW
;
182 state
->AbortAddr
= 1;
184 state
->NumInstrs
= 0;
185 state
->NumNcycles
= 0;
186 state
->NumScycles
= 0;
187 state
->NumIcycles
= 0;
188 state
->NumCcycles
= 0;
189 state
->NumFcycles
= 0;
191 (void) ARMul_MemoryInit ();
192 ARMul_OSInit (state
);
197 /***************************************************************************\
198 * Emulate the execution of an entire program. Start the correct emulator *
199 * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
200 * address of the last instruction that is executed. *
201 \***************************************************************************/
204 ARMul_DoProg (ARMul_State
* state
)
208 state
->Emulate
= RUN
;
209 while (state
->Emulate
!= STOP
)
211 state
->Emulate
= RUN
;
212 if (state
->prog32Sig
&& ARMul_MODE32BIT
)
213 pc
= ARMul_Emulate32 (state
);
215 pc
= ARMul_Emulate26 (state
);
220 /***************************************************************************\
221 * Emulate the execution of one instruction. Start the correct emulator *
222 * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
223 * address of the instruction that is executed. *
224 \***************************************************************************/
227 ARMul_DoInstr (ARMul_State
* state
)
231 state
->Emulate
= ONCE
;
232 if (state
->prog32Sig
&& ARMul_MODE32BIT
)
233 pc
= ARMul_Emulate32 (state
);
235 pc
= ARMul_Emulate26 (state
);
240 /***************************************************************************\
241 * This routine causes an Abort to occur, including selecting the correct *
242 * mode, register bank, and the saving of registers. Call with the *
243 * appropriate vector's memory address (0,4,8 ....) *
244 \***************************************************************************/
247 ARMul_Abort (ARMul_State
* state
, ARMword vector
)
251 state
->Aborted
= FALSE
;
253 if (ARMul_OSException (state
, vector
, ARMul_GetPC (state
)))
256 if (state
->prog32Sig
)
260 temp
= state
->Reg
[15];
262 temp
= R15PC
| ECC
| ER15INT
| EMODE
;
266 case ARMul_ResetV
: /* RESET */
267 state
->Spsr
[SVCBANK
] = CPSR
;
268 SETABORT (INTBITS
, state
->prog32Sig
? SVC32MODE
: SVC26MODE
);
269 ARMul_CPSRAltered (state
);
270 state
->Reg
[14] = temp
;
272 case ARMul_UndefinedInstrV
: /* Undefined Instruction */
273 state
->Spsr
[state
->prog32Sig
? UNDEFBANK
: SVCBANK
] = CPSR
;
274 SETABORT (IBIT
, state
->prog32Sig
? UNDEF32MODE
: SVC26MODE
);
275 ARMul_CPSRAltered (state
);
276 state
->Reg
[14] = temp
- 4;
278 case ARMul_SWIV
: /* Software Interrupt */
279 state
->Spsr
[SVCBANK
] = CPSR
;
280 SETABORT (IBIT
, state
->prog32Sig
? SVC32MODE
: SVC26MODE
);
281 ARMul_CPSRAltered (state
);
282 state
->Reg
[14] = temp
- 4;
284 case ARMul_PrefetchAbortV
: /* Prefetch Abort */
285 state
->AbortAddr
= 1;
286 state
->Spsr
[state
->prog32Sig
? ABORTBANK
: SVCBANK
] = CPSR
;
287 SETABORT (IBIT
, state
->prog32Sig
? ABORT32MODE
: SVC26MODE
);
288 ARMul_CPSRAltered (state
);
289 state
->Reg
[14] = temp
- 4;
291 case ARMul_DataAbortV
: /* Data Abort */
292 state
->Spsr
[state
->prog32Sig
? ABORTBANK
: SVCBANK
] = CPSR
;
293 SETABORT (IBIT
, state
->prog32Sig
? ABORT32MODE
: SVC26MODE
);
294 ARMul_CPSRAltered (state
);
295 state
->Reg
[14] = temp
- 4; /* the PC must have been incremented */
297 case ARMul_AddrExceptnV
: /* Address Exception */
298 state
->Spsr
[SVCBANK
] = CPSR
;
299 SETABORT (IBIT
, SVC26MODE
);
300 ARMul_CPSRAltered (state
);
301 state
->Reg
[14] = temp
- 4;
303 case ARMul_IRQV
: /* IRQ */
304 state
->Spsr
[IRQBANK
] = CPSR
;
305 SETABORT (IBIT
, state
->prog32Sig
? IRQ32MODE
: IRQ26MODE
);
306 ARMul_CPSRAltered (state
);
307 state
->Reg
[14] = temp
- 4;
309 case ARMul_FIQV
: /* FIQ */
310 state
->Spsr
[FIQBANK
] = CPSR
;
311 SETABORT (INTBITS
, state
->prog32Sig
? FIQ32MODE
: FIQ26MODE
);
312 ARMul_CPSRAltered (state
);
313 state
->Reg
[14] = temp
- 4;
317 ARMul_SetR15 (state
, vector
);
319 ARMul_SetR15 (state
, R15CCINTMODE
| vector
);
This page took 0.03896 seconds and 5 git commands to generate.