1 /* run front end support for arm
2 Copyright (C) 1995-2016 Free Software Foundation, Inc.
4 This file is part of ARM SIM.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19 /* This file provides the interface between the simulator and
20 run.c and gdb (when the simulator is linked with gdb).
21 All simulator interaction should go through this file. */
29 #include "gdb/callback.h"
30 #include "gdb/remote-sim.h"
32 #include "sim-options.h"
36 #include "gdb/sim-arm.h"
37 #include "gdb/signals.h"
38 #include "libiberty.h"
41 /* TODO: This should get pulled from the SIM_DESC. */
42 host_callback
*sim_callback
;
44 /* TODO: This should get merged into sim_cpu. */
45 struct ARMul_State
*state
;
47 /* Memory size in bytes. */
48 /* TODO: Memory should be converted to the common memory module. */
49 static int mem_size
= (1 << 21);
55 /* TODO: Tracing should be converted to common tracing module. */
60 static struct disassemble_info info
;
61 static char opbuf
[1000];
64 op_printf (char *buf
, char *fmt
, ...)
70 ret
= vsprintf (opbuf
+ strlen (opbuf
), fmt
, ap
);
76 sim_dis_read (bfd_vma memaddr ATTRIBUTE_UNUSED
,
79 struct disassemble_info
* info
)
81 ARMword val
= (ARMword
) *((ARMword
*) info
->application_data
);
85 * ptr
++ = val
& 0xFF;
92 print_insn (ARMword instr
)
97 info
.application_data
= & instr
;
98 size
= print_insn_little_arm (0, & info
);
99 fprintf (stderr
, " %*s\n", size
, opbuf
);
102 /* Cirrus DSP registers.
104 We need to define these registers outside of maverick.c because
105 maverick.c might not be linked in unless --target=arm9e-* in which
106 case wrapper.c will not compile because it tries to access Cirrus
107 registers. This should all go away once we get the Cirrus and ARM
108 Coprocessor to coexist in armcopro.c-- aldyh. */
125 union maverick_acc_regs
127 long double ld
; /* Acc registers are 72-bits. */
130 struct maverick_regs DSPregs
[16];
131 union maverick_acc_regs DSPacc
[4];
141 ARMul_EmulateInit ();
142 state
= ARMul_NewState ();
143 state
->bigendSig
= (CURRENT_TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? HIGH
: LOW
);
144 ARMul_MemoryInit (state
, mem_size
);
145 ARMul_OSInit (state
);
152 ARMul_ConsolePrint (ARMul_State
* state
,
160 va_start (ap
, format
);
161 vprintf (format
, ap
);
167 sim_write (SIM_DESC sd ATTRIBUTE_UNUSED
,
169 const unsigned char * buffer
,
176 for (i
= 0; i
< size
; i
++)
177 ARMul_SafeWriteByte (state
, addr
+ i
, buffer
[i
]);
183 sim_read (SIM_DESC sd ATTRIBUTE_UNUSED
,
185 unsigned char * buffer
,
192 for (i
= 0; i
< size
; i
++)
193 buffer
[i
] = ARMul_SafeReadByte (state
, addr
+ i
);
199 sim_stop (SIM_DESC sd ATTRIBUTE_UNUSED
)
201 state
->Emulate
= STOP
;
207 sim_resume (SIM_DESC sd ATTRIBUTE_UNUSED
,
209 int siggnal ATTRIBUTE_UNUSED
)
211 state
->EndCondition
= 0;
216 state
->Reg
[15] = ARMul_DoInstr (state
);
217 if (state
->EndCondition
== 0)
218 state
->EndCondition
= RDIError_BreakpointReached
;
222 state
->NextInstr
= RESUME
; /* treat as PC change */
223 state
->Reg
[15] = ARMul_DoProg (state
);
230 sim_create_inferior (SIM_DESC sd ATTRIBUTE_UNUSED
,
243 ARMul_SetPC (state
, bfd_get_start_address (abfd
));
244 mach
= bfd_get_mach (abfd
);
248 ARMul_SetPC (state
, 0); /* ??? */
253 if (abfd
!= NULL
&& (bfd_get_start_address (abfd
) & 1))
260 (*sim_callback
->printf_filtered
)
262 "Unknown machine type '%d'; please update sim_create_inferior.\n",
267 /* We wouldn't set the machine type with earlier toolchains, so we
268 explicitly select a processor capable of supporting all ARMs in
270 ARMul_SelectProcessor (state
, ARM_v5_Prop
| ARM_v5e_Prop
| ARM_v6_Prop
);
273 case bfd_mach_arm_XScale
:
274 ARMul_SelectProcessor (state
, ARM_v5_Prop
| ARM_v5e_Prop
| ARM_XScale_Prop
| ARM_v6_Prop
);
277 case bfd_mach_arm_iWMMXt2
:
278 case bfd_mach_arm_iWMMXt
:
280 extern int SWI_vector_installed
;
283 if (! SWI_vector_installed
)
285 /* Intialise the hardware vectors to zero. */
286 if (! SWI_vector_installed
)
287 for (i
= ARMul_ResetV
; i
<= ARMFIQV
; i
+= 4)
288 ARMul_WriteWord (state
, i
, 0);
290 /* ARM_WriteWord will have detected the write to the SWI vector,
291 but we want SWI_vector_installed to remain at 0 so that thumb
292 mode breakpoints will work. */
293 SWI_vector_installed
= 0;
296 ARMul_SelectProcessor (state
, ARM_v5_Prop
| ARM_v5e_Prop
| ARM_XScale_Prop
| ARM_iWMMXt_Prop
);
299 case bfd_mach_arm_ep9312
:
300 ARMul_SelectProcessor (state
, ARM_v4_Prop
| ARM_ep9312_Prop
);
304 if (bfd_family_coff (abfd
))
306 /* This is a special case in order to support COFF based ARM toolchains.
307 The COFF header does not have enough room to store all the different
308 kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
309 to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5
310 machine type here, we assume it could be any of the above architectures
311 and so select the most feature-full. */
312 ARMul_SelectProcessor (state
, ARM_v5_Prop
| ARM_v5e_Prop
| ARM_XScale_Prop
);
315 /* Otherwise drop through. */
317 case bfd_mach_arm_5T
:
318 ARMul_SelectProcessor (state
, ARM_v5_Prop
);
321 case bfd_mach_arm_5TE
:
322 ARMul_SelectProcessor (state
, ARM_v5_Prop
| ARM_v5e_Prop
);
326 case bfd_mach_arm_4T
:
327 ARMul_SelectProcessor (state
, ARM_v4_Prop
);
331 case bfd_mach_arm_3M
:
332 ARMul_SelectProcessor (state
, ARM_Lock_Prop
);
336 case bfd_mach_arm_2a
:
337 ARMul_SelectProcessor (state
, ARM_Fix26_Prop
);
341 memset (& info
, 0, sizeof (info
));
342 INIT_DISASSEMBLE_INFO (info
, stdout
, op_printf
);
343 info
.read_memory_func
= sim_dis_read
;
344 info
.arch
= bfd_get_arch (abfd
);
345 info
.mach
= bfd_get_mach (abfd
);
346 info
.endian_code
= BFD_ENDIAN_LITTLE
;
348 info
.arch
= bfd_arch_arm
;
349 disassemble_init_for_target (& info
);
353 /* Set up the command line by laboriously stringing together
354 the environment carefully picked apart by our caller. */
356 /* Free any old stuff. */
357 if (state
->CommandLine
!= NULL
)
359 free (state
->CommandLine
);
360 state
->CommandLine
= NULL
;
363 /* See how much we need. */
364 for (arg
= argv
; *arg
!= NULL
; arg
++)
365 argvlen
+= strlen (*arg
) + 1;
368 state
->CommandLine
= malloc (argvlen
+ 1);
369 if (state
->CommandLine
!= NULL
)
372 state
->CommandLine
[0] = '\0';
374 for (arg
= argv
; *arg
!= NULL
; arg
++)
376 strcat (state
->CommandLine
, *arg
);
377 strcat (state
->CommandLine
, " ");
384 /* Now see if there's a MEMSIZE spec in the environment. */
387 if (strncmp (*env
, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
391 /* Set up memory limit. */
393 strtoul (*env
+ sizeof ("MEMSIZE=") - 1, &end_of_num
, 0);
403 frommem (struct ARMul_State
*state
, unsigned char *memory
)
405 if (state
->bigendSig
== HIGH
)
406 return (memory
[0] << 24) | (memory
[1] << 16)
407 | (memory
[2] << 8) | (memory
[3] << 0);
409 return (memory
[3] << 24) | (memory
[2] << 16)
410 | (memory
[1] << 8) | (memory
[0] << 0);
414 tomem (struct ARMul_State
*state
,
415 unsigned char *memory
,
418 if (state
->bigendSig
== HIGH
)
420 memory
[0] = val
>> 24;
421 memory
[1] = val
>> 16;
422 memory
[2] = val
>> 8;
423 memory
[3] = val
>> 0;
427 memory
[3] = val
>> 24;
428 memory
[2] = val
>> 16;
429 memory
[1] = val
>> 8;
430 memory
[0] = val
>> 0;
435 arm_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
439 switch ((enum sim_arm_regs
) rn
)
441 case SIM_ARM_R0_REGNUM
:
442 case SIM_ARM_R1_REGNUM
:
443 case SIM_ARM_R2_REGNUM
:
444 case SIM_ARM_R3_REGNUM
:
445 case SIM_ARM_R4_REGNUM
:
446 case SIM_ARM_R5_REGNUM
:
447 case SIM_ARM_R6_REGNUM
:
448 case SIM_ARM_R7_REGNUM
:
449 case SIM_ARM_R8_REGNUM
:
450 case SIM_ARM_R9_REGNUM
:
451 case SIM_ARM_R10_REGNUM
:
452 case SIM_ARM_R11_REGNUM
:
453 case SIM_ARM_R12_REGNUM
:
454 case SIM_ARM_R13_REGNUM
:
455 case SIM_ARM_R14_REGNUM
:
456 case SIM_ARM_R15_REGNUM
: /* PC */
457 case SIM_ARM_FP0_REGNUM
:
458 case SIM_ARM_FP1_REGNUM
:
459 case SIM_ARM_FP2_REGNUM
:
460 case SIM_ARM_FP3_REGNUM
:
461 case SIM_ARM_FP4_REGNUM
:
462 case SIM_ARM_FP5_REGNUM
:
463 case SIM_ARM_FP6_REGNUM
:
464 case SIM_ARM_FP7_REGNUM
:
465 case SIM_ARM_FPS_REGNUM
:
466 ARMul_SetReg (state
, state
->Mode
, rn
, frommem (state
, memory
));
469 case SIM_ARM_PS_REGNUM
:
470 state
->Cpsr
= frommem (state
, memory
);
471 ARMul_CPSRAltered (state
);
474 case SIM_ARM_MAVERIC_COP0R0_REGNUM
:
475 case SIM_ARM_MAVERIC_COP0R1_REGNUM
:
476 case SIM_ARM_MAVERIC_COP0R2_REGNUM
:
477 case SIM_ARM_MAVERIC_COP0R3_REGNUM
:
478 case SIM_ARM_MAVERIC_COP0R4_REGNUM
:
479 case SIM_ARM_MAVERIC_COP0R5_REGNUM
:
480 case SIM_ARM_MAVERIC_COP0R6_REGNUM
:
481 case SIM_ARM_MAVERIC_COP0R7_REGNUM
:
482 case SIM_ARM_MAVERIC_COP0R8_REGNUM
:
483 case SIM_ARM_MAVERIC_COP0R9_REGNUM
:
484 case SIM_ARM_MAVERIC_COP0R10_REGNUM
:
485 case SIM_ARM_MAVERIC_COP0R11_REGNUM
:
486 case SIM_ARM_MAVERIC_COP0R12_REGNUM
:
487 case SIM_ARM_MAVERIC_COP0R13_REGNUM
:
488 case SIM_ARM_MAVERIC_COP0R14_REGNUM
:
489 case SIM_ARM_MAVERIC_COP0R15_REGNUM
:
490 memcpy (& DSPregs
[rn
- SIM_ARM_MAVERIC_COP0R0_REGNUM
],
491 memory
, sizeof (struct maverick_regs
));
492 return sizeof (struct maverick_regs
);
494 case SIM_ARM_MAVERIC_DSPSC_REGNUM
:
495 memcpy (&DSPsc
, memory
, sizeof DSPsc
);
498 case SIM_ARM_IWMMXT_COP0R0_REGNUM
:
499 case SIM_ARM_IWMMXT_COP0R1_REGNUM
:
500 case SIM_ARM_IWMMXT_COP0R2_REGNUM
:
501 case SIM_ARM_IWMMXT_COP0R3_REGNUM
:
502 case SIM_ARM_IWMMXT_COP0R4_REGNUM
:
503 case SIM_ARM_IWMMXT_COP0R5_REGNUM
:
504 case SIM_ARM_IWMMXT_COP0R6_REGNUM
:
505 case SIM_ARM_IWMMXT_COP0R7_REGNUM
:
506 case SIM_ARM_IWMMXT_COP0R8_REGNUM
:
507 case SIM_ARM_IWMMXT_COP0R9_REGNUM
:
508 case SIM_ARM_IWMMXT_COP0R10_REGNUM
:
509 case SIM_ARM_IWMMXT_COP0R11_REGNUM
:
510 case SIM_ARM_IWMMXT_COP0R12_REGNUM
:
511 case SIM_ARM_IWMMXT_COP0R13_REGNUM
:
512 case SIM_ARM_IWMMXT_COP0R14_REGNUM
:
513 case SIM_ARM_IWMMXT_COP0R15_REGNUM
:
514 case SIM_ARM_IWMMXT_COP1R0_REGNUM
:
515 case SIM_ARM_IWMMXT_COP1R1_REGNUM
:
516 case SIM_ARM_IWMMXT_COP1R2_REGNUM
:
517 case SIM_ARM_IWMMXT_COP1R3_REGNUM
:
518 case SIM_ARM_IWMMXT_COP1R4_REGNUM
:
519 case SIM_ARM_IWMMXT_COP1R5_REGNUM
:
520 case SIM_ARM_IWMMXT_COP1R6_REGNUM
:
521 case SIM_ARM_IWMMXT_COP1R7_REGNUM
:
522 case SIM_ARM_IWMMXT_COP1R8_REGNUM
:
523 case SIM_ARM_IWMMXT_COP1R9_REGNUM
:
524 case SIM_ARM_IWMMXT_COP1R10_REGNUM
:
525 case SIM_ARM_IWMMXT_COP1R11_REGNUM
:
526 case SIM_ARM_IWMMXT_COP1R12_REGNUM
:
527 case SIM_ARM_IWMMXT_COP1R13_REGNUM
:
528 case SIM_ARM_IWMMXT_COP1R14_REGNUM
:
529 case SIM_ARM_IWMMXT_COP1R15_REGNUM
:
530 return Store_Iwmmxt_Register (rn
- SIM_ARM_IWMMXT_COP0R0_REGNUM
, memory
);
540 arm_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
547 switch ((enum sim_arm_regs
) rn
)
549 case SIM_ARM_R0_REGNUM
:
550 case SIM_ARM_R1_REGNUM
:
551 case SIM_ARM_R2_REGNUM
:
552 case SIM_ARM_R3_REGNUM
:
553 case SIM_ARM_R4_REGNUM
:
554 case SIM_ARM_R5_REGNUM
:
555 case SIM_ARM_R6_REGNUM
:
556 case SIM_ARM_R7_REGNUM
:
557 case SIM_ARM_R8_REGNUM
:
558 case SIM_ARM_R9_REGNUM
:
559 case SIM_ARM_R10_REGNUM
:
560 case SIM_ARM_R11_REGNUM
:
561 case SIM_ARM_R12_REGNUM
:
562 case SIM_ARM_R13_REGNUM
:
563 case SIM_ARM_R14_REGNUM
:
564 case SIM_ARM_R15_REGNUM
: /* PC */
565 regval
= ARMul_GetReg (state
, state
->Mode
, rn
);
568 case SIM_ARM_FP0_REGNUM
:
569 case SIM_ARM_FP1_REGNUM
:
570 case SIM_ARM_FP2_REGNUM
:
571 case SIM_ARM_FP3_REGNUM
:
572 case SIM_ARM_FP4_REGNUM
:
573 case SIM_ARM_FP5_REGNUM
:
574 case SIM_ARM_FP6_REGNUM
:
575 case SIM_ARM_FP7_REGNUM
:
576 case SIM_ARM_FPS_REGNUM
:
577 memset (memory
, 0, length
);
580 case SIM_ARM_PS_REGNUM
:
581 regval
= ARMul_GetCPSR (state
);
584 case SIM_ARM_MAVERIC_COP0R0_REGNUM
:
585 case SIM_ARM_MAVERIC_COP0R1_REGNUM
:
586 case SIM_ARM_MAVERIC_COP0R2_REGNUM
:
587 case SIM_ARM_MAVERIC_COP0R3_REGNUM
:
588 case SIM_ARM_MAVERIC_COP0R4_REGNUM
:
589 case SIM_ARM_MAVERIC_COP0R5_REGNUM
:
590 case SIM_ARM_MAVERIC_COP0R6_REGNUM
:
591 case SIM_ARM_MAVERIC_COP0R7_REGNUM
:
592 case SIM_ARM_MAVERIC_COP0R8_REGNUM
:
593 case SIM_ARM_MAVERIC_COP0R9_REGNUM
:
594 case SIM_ARM_MAVERIC_COP0R10_REGNUM
:
595 case SIM_ARM_MAVERIC_COP0R11_REGNUM
:
596 case SIM_ARM_MAVERIC_COP0R12_REGNUM
:
597 case SIM_ARM_MAVERIC_COP0R13_REGNUM
:
598 case SIM_ARM_MAVERIC_COP0R14_REGNUM
:
599 case SIM_ARM_MAVERIC_COP0R15_REGNUM
:
600 memcpy (memory
, & DSPregs
[rn
- SIM_ARM_MAVERIC_COP0R0_REGNUM
],
601 sizeof (struct maverick_regs
));
602 return sizeof (struct maverick_regs
);
604 case SIM_ARM_MAVERIC_DSPSC_REGNUM
:
605 memcpy (memory
, & DSPsc
, sizeof DSPsc
);
608 case SIM_ARM_IWMMXT_COP0R0_REGNUM
:
609 case SIM_ARM_IWMMXT_COP0R1_REGNUM
:
610 case SIM_ARM_IWMMXT_COP0R2_REGNUM
:
611 case SIM_ARM_IWMMXT_COP0R3_REGNUM
:
612 case SIM_ARM_IWMMXT_COP0R4_REGNUM
:
613 case SIM_ARM_IWMMXT_COP0R5_REGNUM
:
614 case SIM_ARM_IWMMXT_COP0R6_REGNUM
:
615 case SIM_ARM_IWMMXT_COP0R7_REGNUM
:
616 case SIM_ARM_IWMMXT_COP0R8_REGNUM
:
617 case SIM_ARM_IWMMXT_COP0R9_REGNUM
:
618 case SIM_ARM_IWMMXT_COP0R10_REGNUM
:
619 case SIM_ARM_IWMMXT_COP0R11_REGNUM
:
620 case SIM_ARM_IWMMXT_COP0R12_REGNUM
:
621 case SIM_ARM_IWMMXT_COP0R13_REGNUM
:
622 case SIM_ARM_IWMMXT_COP0R14_REGNUM
:
623 case SIM_ARM_IWMMXT_COP0R15_REGNUM
:
624 case SIM_ARM_IWMMXT_COP1R0_REGNUM
:
625 case SIM_ARM_IWMMXT_COP1R1_REGNUM
:
626 case SIM_ARM_IWMMXT_COP1R2_REGNUM
:
627 case SIM_ARM_IWMMXT_COP1R3_REGNUM
:
628 case SIM_ARM_IWMMXT_COP1R4_REGNUM
:
629 case SIM_ARM_IWMMXT_COP1R5_REGNUM
:
630 case SIM_ARM_IWMMXT_COP1R6_REGNUM
:
631 case SIM_ARM_IWMMXT_COP1R7_REGNUM
:
632 case SIM_ARM_IWMMXT_COP1R8_REGNUM
:
633 case SIM_ARM_IWMMXT_COP1R9_REGNUM
:
634 case SIM_ARM_IWMMXT_COP1R10_REGNUM
:
635 case SIM_ARM_IWMMXT_COP1R11_REGNUM
:
636 case SIM_ARM_IWMMXT_COP1R12_REGNUM
:
637 case SIM_ARM_IWMMXT_COP1R13_REGNUM
:
638 case SIM_ARM_IWMMXT_COP1R14_REGNUM
:
639 case SIM_ARM_IWMMXT_COP1R15_REGNUM
:
640 return Fetch_Iwmmxt_Register (rn
- SIM_ARM_IWMMXT_COP0R0_REGNUM
, memory
);
648 tomem (state
, memory
, regval
);
661 unsigned int swi_mask
;
664 #define SWI_SWITCH "--swi-support"
666 static swi_options options
[] =
669 { "demon", SWI_MASK_DEMON
},
670 { "angel", SWI_MASK_ANGEL
},
671 { "redboot", SWI_MASK_REDBOOT
},
674 { "DEMON", SWI_MASK_DEMON
},
675 { "ANGEL", SWI_MASK_ANGEL
},
676 { "REDBOOT", SWI_MASK_REDBOOT
},
682 sim_target_parse_command_line (int argc
, char ** argv
)
686 for (i
= 1; i
< argc
; i
++)
688 char * ptr
= argv
[i
];
691 if ((ptr
== NULL
) || (* ptr
!= '-'))
694 if (strcmp (ptr
, "-t") == 0)
700 if (strcmp (ptr
, "-z") == 0)
702 /* Remove this option from the argv array. */
703 for (arg
= i
; arg
< argc
; arg
++)
704 argv
[arg
] = argv
[arg
+ 1];
711 if (strcmp (ptr
, "-d") == 0)
713 /* Remove this option from the argv array. */
714 for (arg
= i
; arg
< argc
; arg
++)
715 argv
[arg
] = argv
[arg
+ 1];
722 if (strncmp (ptr
, SWI_SWITCH
, sizeof SWI_SWITCH
- 1) != 0)
725 if (ptr
[sizeof SWI_SWITCH
- 1] == 0)
727 /* Remove this option from the argv array. */
728 for (arg
= i
; arg
< argc
; arg
++)
729 argv
[arg
] = argv
[arg
+ 1];
735 ptr
+= sizeof SWI_SWITCH
;
743 for (i
= sizeof options
/ sizeof options
[0]; i
--;)
744 if (strncmp (ptr
, options
[i
].swi_option
,
745 strlen (options
[i
].swi_option
)) == 0)
747 swi_mask
|= options
[i
].swi_mask
;
748 ptr
+= strlen (options
[i
].swi_option
);
761 fprintf (stderr
, "Ignoring swi options: %s\n", ptr
);
763 /* Remove this option from the argv array. */
764 for (arg
= i
; arg
< argc
; arg
++)
765 argv
[arg
] = argv
[arg
+ 1];
773 sim_target_parse_arg_array (char ** argv
)
777 for (i
= 0; argv
[i
]; i
++)
780 sim_target_parse_command_line (i
, argv
);
784 arm_pc_get (sim_cpu
*cpu
)
790 arm_pc_set (sim_cpu
*cpu
, sim_cia pc
)
792 ARMul_SetPC (state
, pc
);
796 free_state (SIM_DESC sd
)
798 if (STATE_MODULES (sd
) != NULL
)
799 sim_module_uninstall (sd
);
800 sim_cpu_free_all (sd
);
805 sim_open (SIM_OPEN_KIND kind
,
811 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
812 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
814 /* The cpu data is kept in a separately allocated chunk of memory. */
815 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
821 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
827 /* getopt will print the error message so we just have to exit if this fails.
828 FIXME: Hmmm... in the case of gdb we need getopt to call
830 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
836 /* Check for/establish the a reference program image. */
837 if (sim_analyze_program (sd
,
838 (STATE_PROG_ARGV (sd
) != NULL
839 ? *STATE_PROG_ARGV (sd
)
840 : NULL
), abfd
) != SIM_RC_OK
)
846 /* Configure/verify the target byte order and other runtime
847 configuration options. */
848 if (sim_config (sd
) != SIM_RC_OK
)
850 sim_module_uninstall (sd
);
854 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
856 /* Uninstall the modules to avoid memory leaks,
857 file descriptor leaks, etc. */
858 sim_module_uninstall (sd
);
862 /* CPU specific initialization. */
863 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
865 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
867 CPU_REG_FETCH (cpu
) = arm_reg_fetch
;
868 CPU_REG_STORE (cpu
) = arm_reg_store
;
869 CPU_PC_FETCH (cpu
) = arm_pc_get
;
870 CPU_PC_STORE (cpu
) = arm_pc_set
;
875 sim_target_parse_arg_array (argv
);
881 /* Scan for memory-size switches. */
882 for (i
= 0; (argv
[i
] != NULL
) && (argv
[i
][0] != 0); i
++)
883 if (argv
[i
][0] == '-' && argv
[i
][1] == 'm')
885 if (argv
[i
][2] != '\0')
886 mem_size
= atoi (&argv
[i
][2]);
887 else if (argv
[i
+ 1] != NULL
)
889 mem_size
= atoi (argv
[i
+ 1]);
894 sim_callback
->printf_filtered (sim_callback
,
895 "Missing argument to -m option\n");
905 sim_stop_reason (SIM_DESC sd ATTRIBUTE_UNUSED
,
906 enum sim_stop
*reason
,
911 *reason
= sim_stopped
;
912 *sigrc
= GDB_SIGNAL_INT
;
914 else if (state
->EndCondition
== 0)
916 *reason
= sim_exited
;
917 *sigrc
= state
->Reg
[0] & 255;
921 *reason
= sim_stopped
;
922 if (state
->EndCondition
== RDIError_BreakpointReached
)
923 *sigrc
= GDB_SIGNAL_TRAP
;
924 else if ( state
->EndCondition
== RDIError_DataAbort
925 || state
->EndCondition
== RDIError_AddressException
)
926 *sigrc
= GDB_SIGNAL_BUS
;