sim/arm/wrapper.c

   1 /* run front end support for arm
   2    Copyright (C) 1995-2015 Free Software Foundation, Inc.
   3
   4    This file is part of ARM SIM.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 /* This file provides the interface between the simulator and
  20    run.c and gdb (when the simulator is linked with gdb).
  21    All simulator interaction should go through this file.  */
  22
  23 #include "config.h"
  24 #include <stdio.h>
  25 #include <stdarg.h>
  26 #include <string.h>
  27 #include <bfd.h>
  28 #include <signal.h>
  29 #include "gdb/callback.h"
  30 #include "gdb/remote-sim.h"
  31 #include "armdefs.h"
  32 #include "armemu.h"
  33 #include "dbg_rdi.h"
  34 #include "ansidecl.h"
  35 #include "sim-utils.h"
  36 #include "run-sim.h"
  37 #include "gdb/sim-arm.h"
  38 #include "gdb/signals.h"
  39 #include "libiberty.h"
  40 #include "iwmmxt.h"
  41
  42 host_callback *sim_callback;
  43
  44 static struct ARMul_State *state;
  45
  46 /* Who is using the simulator.  */
  47 static SIM_OPEN_KIND sim_kind;
  48
  49 /* argv[0] */
  50 static char *myname;
  51
  52 /* Memory size in bytes.  */
  53 static int mem_size = (1 << 21);
  54
  55 /* Non-zero to set big endian mode.  */
  56 static int big_endian;
  57
  58 int stop_simulator;
  59
  60 #include "dis-asm.h"
  61
  62 int trace = 0;
  63 int disas = 0;
  64 int trace_funcs = 0;
  65
  66 static struct disassemble_info  info;
  67 static char opbuf[1000];
  68
  69 static int
  70 op_printf (char *buf, char *fmt, ...)
  71 {
  72   int ret;
  73   va_list ap;
  74
  75   va_start (ap, fmt);
  76   ret = vsprintf (opbuf + strlen (opbuf), fmt, ap);
  77   va_end (ap);
  78   return ret;
  79 }
  80
  81 static int
  82 sim_dis_read (bfd_vma                     memaddr ATTRIBUTE_UNUSED,
  83               bfd_byte *                  ptr,
  84               unsigned int                length,
  85               struct disassemble_info *   info)
  86 {
  87   ARMword val = (ARMword) *((ARMword *) info->application_data);
  88
  89   while (length--)
  90     {
  91       * ptr ++ = val & 0xFF;
  92       val >>= 8;
  93     }
  94   return 0;
  95 }
  96
  97 void
  98 print_insn (ARMword instr)
  99 {
 100   int size;
 101
 102   opbuf[0] = 0;
 103   info.application_data = & instr;
 104   size = print_insn_little_arm (0, & info);
 105   fprintf (stderr, " %*s\n", size, opbuf);
 106 }
 107
 108 /* Cirrus DSP registers.
 109
 110    We need to define these registers outside of maverick.c because
 111    maverick.c might not be linked in unless --target=arm9e-* in which
 112    case wrapper.c will not compile because it tries to access Cirrus
 113    registers.  This should all go away once we get the Cirrus and ARM
 114    Coprocessor to coexist in armcopro.c-- aldyh.  */
 115
 116 struct maverick_regs
 117 {
 118   union
 119   {
 120     int i;
 121     float f;
 122   } upper;
 123
 124   union
 125   {
 126     int i;
 127     float f;
 128   } lower;
 129 };
 130
 131 union maverick_acc_regs
 132 {
 133   long double ld;               /* Acc registers are 72-bits.  */
 134 };
 135
 136 struct maverick_regs     DSPregs[16];
 137 union maverick_acc_regs  DSPacc[4];
 138 ARMword DSPsc;
 139
 140 static void
 141 init (void)
 142 {
 143   static int done;
 144
 145   if (!done)
 146     {
 147       ARMul_EmulateInit ();
 148       state = ARMul_NewState ();
 149       state->bigendSig = (big_endian ? HIGH : LOW);
 150       ARMul_MemoryInit (state, mem_size);
 151       ARMul_OSInit (state);
 152       state->verbose = 0;
 153       done = 1;
 154     }
 155 }
 156
 157 /* Set the memory size to SIZE bytes.
 158    Must be called before initializing simulator.  */
 159 /* FIXME: Rename to sim_set_mem_size.  */
 160
 161 void
 162 sim_size (int size)
 163 {
 164   mem_size = size;
 165 }
 166
 167 void
 168 ARMul_ConsolePrint (ARMul_State * state,
 169                     const char * format,
 170                     ...)
 171 {
 172   va_list ap;
 173
 174   if (state->verbose)
 175     {
 176       va_start (ap, format);
 177       vprintf (format, ap);
 178       va_end (ap);
 179     }
 180 }
 181
 182 ARMword
 183 ARMul_Debug (ARMul_State * state ATTRIBUTE_UNUSED,
 184              ARMword       pc    ATTRIBUTE_UNUSED,
 185              ARMword       instr ATTRIBUTE_UNUSED)
 186 {
 187   return 0;
 188 }
 189
 190 int
 191 sim_write (SIM_DESC sd ATTRIBUTE_UNUSED,
 192            SIM_ADDR addr,
 193            const unsigned char * buffer,
 194            int size)
 195 {
 196   int i;
 197
 198   init ();
 199
 200   for (i = 0; i < size; i++)
 201     ARMul_SafeWriteByte (state, addr + i, buffer[i]);
 202
 203   return size;
 204 }
 205
 206 int
 207 sim_read (SIM_DESC sd ATTRIBUTE_UNUSED,
 208           SIM_ADDR addr,
 209           unsigned char * buffer,
 210           int size)
 211 {
 212   int i;
 213
 214   init ();
 215
 216   for (i = 0; i < size; i++)
 217     buffer[i] = ARMul_SafeReadByte (state, addr + i);
 218
 219   return size;
 220 }
 221
 222 int
 223 sim_trace (SIM_DESC sd ATTRIBUTE_UNUSED)
 224 {
 225   trace = 1;
 226   sim_resume (sd, 0, 0);
 227   return 1;
 228 }
 229
 230 int
 231 sim_stop (SIM_DESC sd ATTRIBUTE_UNUSED)
 232 {
 233   state->Emulate = STOP;
 234   stop_simulator = 1;
 235   return 1;
 236 }
 237
 238 void
 239 sim_resume (SIM_DESC sd ATTRIBUTE_UNUSED,
 240             int step,
 241             int siggnal ATTRIBUTE_UNUSED)
 242 {
 243   state->EndCondition = 0;
 244   stop_simulator = 0;
 245
 246   if (step)
 247     {
 248       state->Reg[15] = ARMul_DoInstr (state);
 249       if (state->EndCondition == 0)
 250         state->EndCondition = RDIError_BreakpointReached;
 251     }
 252   else
 253     {
 254       state->NextInstr = RESUME;        /* treat as PC change */
 255       state->Reg[15] = ARMul_DoProg (state);
 256     }
 257
 258   FLUSHPIPE;
 259 }
 260
 261 SIM_RC
 262 sim_create_inferior (SIM_DESC sd ATTRIBUTE_UNUSED,
 263                      struct bfd * abfd,
 264                      char ** argv,
 265                      char ** env)
 266 {
 267   int argvlen = 0;
 268   int mach;
 269   char **arg;
 270
 271   init ();
 272
 273   if (abfd != NULL)
 274     {
 275       ARMul_SetPC (state, bfd_get_start_address (abfd));
 276       mach = bfd_get_mach (abfd);
 277     }
 278   else
 279     {
 280       ARMul_SetPC (state, 0);   /* ??? */
 281       mach = 0;
 282     }
 283
 284   switch (mach)
 285     {
 286     default:
 287       (*sim_callback->printf_filtered)
 288         (sim_callback,
 289          "Unknown machine type '%d'; please update sim_create_inferior.\n",
 290          mach);
 291       /* fall through */
 292
 293     case 0:
 294       /* We wouldn't set the machine type with earlier toolchains, so we
 295          explicitly select a processor capable of supporting all ARMs in
 296          32bit mode.  */
 297       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_v6_Prop);
 298       break;
 299
 300     case bfd_mach_arm_XScale:
 301       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop);
 302       break;
 303
 304     case bfd_mach_arm_iWMMXt2:
 305     case bfd_mach_arm_iWMMXt:
 306       {
 307         extern int SWI_vector_installed;
 308         ARMword i;
 309
 310         if (! SWI_vector_installed)
 311           {
 312             /* Intialise the hardware vectors to zero.  */
 313             if (! SWI_vector_installed)
 314               for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
 315                 ARMul_WriteWord (state, i, 0);
 316
 317             /* ARM_WriteWord will have detected the write to the SWI vector,
 318                but we want SWI_vector_installed to remain at 0 so that thumb
 319                mode breakpoints will work.  */
 320             SWI_vector_installed = 0;
 321           }
 322       }
 323       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop);
 324       break;
 325
 326     case bfd_mach_arm_ep9312:
 327       ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
 328       break;
 329
 330     case bfd_mach_arm_5:
 331       if (bfd_family_coff (abfd))
 332         {
 333           /* This is a special case in order to support COFF based ARM toolchains.
 334              The COFF header does not have enough room to store all the different
 335              kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
 336              to v5.  (See coff_set_flags() in bdf/coffcode.h).  So if we see a v5
 337              machine type here, we assume it could be any of the above architectures
 338              and so select the most feature-full.  */
 339           ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
 340           break;
 341         }
 342       /* Otherwise drop through.  */
 343
 344     case bfd_mach_arm_5T:
 345       ARMul_SelectProcessor (state, ARM_v5_Prop);
 346       break;
 347
 348     case bfd_mach_arm_5TE:
 349       ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
 350       break;
 351
 352     case bfd_mach_arm_4:
 353     case bfd_mach_arm_4T:
 354       ARMul_SelectProcessor (state, ARM_v4_Prop);
 355       break;
 356
 357     case bfd_mach_arm_3:
 358     case bfd_mach_arm_3M:
 359       ARMul_SelectProcessor (state, ARM_Lock_Prop);
 360       break;
 361
 362     case bfd_mach_arm_2:
 363     case bfd_mach_arm_2a:
 364       ARMul_SelectProcessor (state, ARM_Fix26_Prop);
 365       break;
 366     }
 367
 368   if (   mach != bfd_mach_arm_3
 369       && mach != bfd_mach_arm_3M
 370       && mach != bfd_mach_arm_2
 371       && mach != bfd_mach_arm_2a)
 372     {
 373       /* Reset mode to ARM.  A gdb user may rerun a program that had entered
 374          THUMB mode from the start and cause the ARM-mode startup code to be
 375          executed in THUMB mode.  */
 376       ARMul_SetCPSR (state, SVC32MODE);
 377     }
 378
 379   memset (& info, 0, sizeof (info));
 380   INIT_DISASSEMBLE_INFO (info, stdout, op_printf);
 381   info.read_memory_func = sim_dis_read;
 382   info.arch = bfd_get_arch (abfd);
 383   info.mach = bfd_get_mach (abfd);
 384   info.endian_code = BFD_ENDIAN_LITTLE;
 385   if (info.mach == 0)
 386     info.arch = bfd_arch_arm;
 387   disassemble_init_for_target (& info);
 388
 389   if (argv != NULL)
 390     {
 391       /* Set up the command line by laboriously stringing together
 392          the environment carefully picked apart by our caller.  */
 393
 394       /* Free any old stuff.  */
 395       if (state->CommandLine != NULL)
 396         {
 397           free (state->CommandLine);
 398           state->CommandLine = NULL;
 399         }
 400
 401       /* See how much we need.  */
 402       for (arg = argv; *arg != NULL; arg++)
 403         argvlen += strlen (*arg) + 1;
 404
 405       /* Allocate it.  */
 406       state->CommandLine = malloc (argvlen + 1);
 407       if (state->CommandLine != NULL)
 408         {
 409           arg = argv;
 410           state->CommandLine[0] = '\0';
 411
 412           for (arg = argv; *arg != NULL; arg++)
 413             {
 414               strcat (state->CommandLine, *arg);
 415               strcat (state->CommandLine, " ");
 416             }
 417         }
 418     }
 419
 420   if (env != NULL)
 421     {
 422       /* Now see if there's a MEMSIZE spec in the environment.  */
 423       while (*env)
 424         {
 425           if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
 426             {
 427               char *end_of_num;
 428
 429               /* Set up memory limit.  */
 430               state->MemSize =
 431                 strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0);
 432             }
 433           env++;
 434         }
 435     }
 436
 437   return SIM_RC_OK;
 438 }
 439
 440 void
 441 sim_info (SIM_DESC sd ATTRIBUTE_UNUSED,
 442           int verbose ATTRIBUTE_UNUSED)
 443 {
 444 }
 445
 446 static int
 447 frommem (struct ARMul_State *state, unsigned char *memory)
 448 {
 449   if (state->bigendSig == HIGH)
 450     return (memory[0] << 24) | (memory[1] << 16)
 451       | (memory[2] << 8) | (memory[3] << 0);
 452   else
 453     return (memory[3] << 24) | (memory[2] << 16)
 454       | (memory[1] << 8) | (memory[0] << 0);
 455 }
 456
 457 static void
 458 tomem (struct ARMul_State *state,
 459        unsigned char *memory,
 460        int val)
 461 {
 462   if (state->bigendSig == HIGH)
 463     {
 464       memory[0] = val >> 24;
 465       memory[1] = val >> 16;
 466       memory[2] = val >> 8;
 467       memory[3] = val >> 0;
 468     }
 469   else
 470     {
 471       memory[3] = val >> 24;
 472       memory[2] = val >> 16;
 473       memory[1] = val >> 8;
 474       memory[0] = val >> 0;
 475     }
 476 }
 477
 478 int
 479 sim_store_register (SIM_DESC sd ATTRIBUTE_UNUSED,
 480                     int rn,
 481                     unsigned char *memory,
 482                     int length)
 483 {
 484   init ();
 485
 486   switch ((enum sim_arm_regs) rn)
 487     {
 488     case SIM_ARM_R0_REGNUM:
 489     case SIM_ARM_R1_REGNUM:
 490     case SIM_ARM_R2_REGNUM:
 491     case SIM_ARM_R3_REGNUM:
 492     case SIM_ARM_R4_REGNUM:
 493     case SIM_ARM_R5_REGNUM:
 494     case SIM_ARM_R6_REGNUM:
 495     case SIM_ARM_R7_REGNUM:
 496     case SIM_ARM_R8_REGNUM:
 497     case SIM_ARM_R9_REGNUM:
 498     case SIM_ARM_R10_REGNUM:
 499     case SIM_ARM_R11_REGNUM:
 500     case SIM_ARM_R12_REGNUM:
 501     case SIM_ARM_R13_REGNUM:
 502     case SIM_ARM_R14_REGNUM:
 503     case SIM_ARM_R15_REGNUM: /* PC */
 504     case SIM_ARM_FP0_REGNUM:
 505     case SIM_ARM_FP1_REGNUM:
 506     case SIM_ARM_FP2_REGNUM:
 507     case SIM_ARM_FP3_REGNUM:
 508     case SIM_ARM_FP4_REGNUM:
 509     case SIM_ARM_FP5_REGNUM:
 510     case SIM_ARM_FP6_REGNUM:
 511     case SIM_ARM_FP7_REGNUM:
 512     case SIM_ARM_FPS_REGNUM:
 513       ARMul_SetReg (state, state->Mode, rn, frommem (state, memory));
 514       break;
 515
 516     case SIM_ARM_PS_REGNUM:
 517       state->Cpsr = frommem (state, memory);
 518       ARMul_CPSRAltered (state);
 519       break;
 520
 521     case SIM_ARM_MAVERIC_COP0R0_REGNUM:
 522     case SIM_ARM_MAVERIC_COP0R1_REGNUM:
 523     case SIM_ARM_MAVERIC_COP0R2_REGNUM:
 524     case SIM_ARM_MAVERIC_COP0R3_REGNUM:
 525     case SIM_ARM_MAVERIC_COP0R4_REGNUM:
 526     case SIM_ARM_MAVERIC_COP0R5_REGNUM:
 527     case SIM_ARM_MAVERIC_COP0R6_REGNUM:
 528     case SIM_ARM_MAVERIC_COP0R7_REGNUM:
 529     case SIM_ARM_MAVERIC_COP0R8_REGNUM:
 530     case SIM_ARM_MAVERIC_COP0R9_REGNUM:
 531     case SIM_ARM_MAVERIC_COP0R10_REGNUM:
 532     case SIM_ARM_MAVERIC_COP0R11_REGNUM:
 533     case SIM_ARM_MAVERIC_COP0R12_REGNUM:
 534     case SIM_ARM_MAVERIC_COP0R13_REGNUM:
 535     case SIM_ARM_MAVERIC_COP0R14_REGNUM:
 536     case SIM_ARM_MAVERIC_COP0R15_REGNUM:
 537       memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
 538               memory, sizeof (struct maverick_regs));
 539       return sizeof (struct maverick_regs);
 540
 541     case SIM_ARM_MAVERIC_DSPSC_REGNUM:
 542       memcpy (&DSPsc, memory, sizeof DSPsc);
 543       return sizeof DSPsc;
 544
 545     case SIM_ARM_IWMMXT_COP0R0_REGNUM:
 546     case SIM_ARM_IWMMXT_COP0R1_REGNUM:
 547     case SIM_ARM_IWMMXT_COP0R2_REGNUM:
 548     case SIM_ARM_IWMMXT_COP0R3_REGNUM:
 549     case SIM_ARM_IWMMXT_COP0R4_REGNUM:
 550     case SIM_ARM_IWMMXT_COP0R5_REGNUM:
 551     case SIM_ARM_IWMMXT_COP0R6_REGNUM:
 552     case SIM_ARM_IWMMXT_COP0R7_REGNUM:
 553     case SIM_ARM_IWMMXT_COP0R8_REGNUM:
 554     case SIM_ARM_IWMMXT_COP0R9_REGNUM:
 555     case SIM_ARM_IWMMXT_COP0R10_REGNUM:
 556     case SIM_ARM_IWMMXT_COP0R11_REGNUM:
 557     case SIM_ARM_IWMMXT_COP0R12_REGNUM:
 558     case SIM_ARM_IWMMXT_COP0R13_REGNUM:
 559     case SIM_ARM_IWMMXT_COP0R14_REGNUM:
 560     case SIM_ARM_IWMMXT_COP0R15_REGNUM:
 561     case SIM_ARM_IWMMXT_COP1R0_REGNUM:
 562     case SIM_ARM_IWMMXT_COP1R1_REGNUM:
 563     case SIM_ARM_IWMMXT_COP1R2_REGNUM:
 564     case SIM_ARM_IWMMXT_COP1R3_REGNUM:
 565     case SIM_ARM_IWMMXT_COP1R4_REGNUM:
 566     case SIM_ARM_IWMMXT_COP1R5_REGNUM:
 567     case SIM_ARM_IWMMXT_COP1R6_REGNUM:
 568     case SIM_ARM_IWMMXT_COP1R7_REGNUM:
 569     case SIM_ARM_IWMMXT_COP1R8_REGNUM:
 570     case SIM_ARM_IWMMXT_COP1R9_REGNUM:
 571     case SIM_ARM_IWMMXT_COP1R10_REGNUM:
 572     case SIM_ARM_IWMMXT_COP1R11_REGNUM:
 573     case SIM_ARM_IWMMXT_COP1R12_REGNUM:
 574     case SIM_ARM_IWMMXT_COP1R13_REGNUM:
 575     case SIM_ARM_IWMMXT_COP1R14_REGNUM:
 576     case SIM_ARM_IWMMXT_COP1R15_REGNUM:
 577       return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
 578
 579     default:
 580       return 0;
 581     }
 582
 583   return length;
 584 }
 585
 586 int
 587 sim_fetch_register (SIM_DESC sd ATTRIBUTE_UNUSED,
 588                     int rn,
 589                     unsigned char *memory,
 590                     int length)
 591 {
 592   ARMword regval;
 593   int len = length;
 594
 595   init ();
 596
 597   switch ((enum sim_arm_regs) rn)
 598     {
 599     case SIM_ARM_R0_REGNUM:
 600     case SIM_ARM_R1_REGNUM:
 601     case SIM_ARM_R2_REGNUM:
 602     case SIM_ARM_R3_REGNUM:
 603     case SIM_ARM_R4_REGNUM:
 604     case SIM_ARM_R5_REGNUM:
 605     case SIM_ARM_R6_REGNUM:
 606     case SIM_ARM_R7_REGNUM:
 607     case SIM_ARM_R8_REGNUM:
 608     case SIM_ARM_R9_REGNUM:
 609     case SIM_ARM_R10_REGNUM:
 610     case SIM_ARM_R11_REGNUM:
 611     case SIM_ARM_R12_REGNUM:
 612     case SIM_ARM_R13_REGNUM:
 613     case SIM_ARM_R14_REGNUM:
 614     case SIM_ARM_R15_REGNUM: /* PC */
 615       regval = ARMul_GetReg (state, state->Mode, rn);
 616       break;
 617
 618     case SIM_ARM_FP0_REGNUM:
 619     case SIM_ARM_FP1_REGNUM:
 620     case SIM_ARM_FP2_REGNUM:
 621     case SIM_ARM_FP3_REGNUM:
 622     case SIM_ARM_FP4_REGNUM:
 623     case SIM_ARM_FP5_REGNUM:
 624     case SIM_ARM_FP6_REGNUM:
 625     case SIM_ARM_FP7_REGNUM:
 626     case SIM_ARM_FPS_REGNUM:
 627       memset (memory, 0, length);
 628       return 0;
 629
 630     case SIM_ARM_PS_REGNUM:
 631       regval = ARMul_GetCPSR (state);
 632       break;
 633
 634     case SIM_ARM_MAVERIC_COP0R0_REGNUM:
 635     case SIM_ARM_MAVERIC_COP0R1_REGNUM:
 636     case SIM_ARM_MAVERIC_COP0R2_REGNUM:
 637     case SIM_ARM_MAVERIC_COP0R3_REGNUM:
 638     case SIM_ARM_MAVERIC_COP0R4_REGNUM:
 639     case SIM_ARM_MAVERIC_COP0R5_REGNUM:
 640     case SIM_ARM_MAVERIC_COP0R6_REGNUM:
 641     case SIM_ARM_MAVERIC_COP0R7_REGNUM:
 642     case SIM_ARM_MAVERIC_COP0R8_REGNUM:
 643     case SIM_ARM_MAVERIC_COP0R9_REGNUM:
 644     case SIM_ARM_MAVERIC_COP0R10_REGNUM:
 645     case SIM_ARM_MAVERIC_COP0R11_REGNUM:
 646     case SIM_ARM_MAVERIC_COP0R12_REGNUM:
 647     case SIM_ARM_MAVERIC_COP0R13_REGNUM:
 648     case SIM_ARM_MAVERIC_COP0R14_REGNUM:
 649     case SIM_ARM_MAVERIC_COP0R15_REGNUM:
 650       memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
 651               sizeof (struct maverick_regs));
 652       return sizeof (struct maverick_regs);
 653
 654     case SIM_ARM_MAVERIC_DSPSC_REGNUM:
 655       memcpy (memory, & DSPsc, sizeof DSPsc);
 656       return sizeof DSPsc;
 657
 658     case SIM_ARM_IWMMXT_COP0R0_REGNUM:
 659     case SIM_ARM_IWMMXT_COP0R1_REGNUM:
 660     case SIM_ARM_IWMMXT_COP0R2_REGNUM:
 661     case SIM_ARM_IWMMXT_COP0R3_REGNUM:
 662     case SIM_ARM_IWMMXT_COP0R4_REGNUM:
 663     case SIM_ARM_IWMMXT_COP0R5_REGNUM:
 664     case SIM_ARM_IWMMXT_COP0R6_REGNUM:
 665     case SIM_ARM_IWMMXT_COP0R7_REGNUM:
 666     case SIM_ARM_IWMMXT_COP0R8_REGNUM:
 667     case SIM_ARM_IWMMXT_COP0R9_REGNUM:
 668     case SIM_ARM_IWMMXT_COP0R10_REGNUM:
 669     case SIM_ARM_IWMMXT_COP0R11_REGNUM:
 670     case SIM_ARM_IWMMXT_COP0R12_REGNUM:
 671     case SIM_ARM_IWMMXT_COP0R13_REGNUM:
 672     case SIM_ARM_IWMMXT_COP0R14_REGNUM:
 673     case SIM_ARM_IWMMXT_COP0R15_REGNUM:
 674     case SIM_ARM_IWMMXT_COP1R0_REGNUM:
 675     case SIM_ARM_IWMMXT_COP1R1_REGNUM:
 676     case SIM_ARM_IWMMXT_COP1R2_REGNUM:
 677     case SIM_ARM_IWMMXT_COP1R3_REGNUM:
 678     case SIM_ARM_IWMMXT_COP1R4_REGNUM:
 679     case SIM_ARM_IWMMXT_COP1R5_REGNUM:
 680     case SIM_ARM_IWMMXT_COP1R6_REGNUM:
 681     case SIM_ARM_IWMMXT_COP1R7_REGNUM:
 682     case SIM_ARM_IWMMXT_COP1R8_REGNUM:
 683     case SIM_ARM_IWMMXT_COP1R9_REGNUM:
 684     case SIM_ARM_IWMMXT_COP1R10_REGNUM:
 685     case SIM_ARM_IWMMXT_COP1R11_REGNUM:
 686     case SIM_ARM_IWMMXT_COP1R12_REGNUM:
 687     case SIM_ARM_IWMMXT_COP1R13_REGNUM:
 688     case SIM_ARM_IWMMXT_COP1R14_REGNUM:
 689     case SIM_ARM_IWMMXT_COP1R15_REGNUM:
 690       return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
 691
 692     default:
 693       return 0;
 694     }
 695
 696   while (len)
 697     {
 698       tomem (state, memory, regval);
 699
 700       len -= 4;
 701       memory += 4;
 702       regval = 0;
 703     }
 704
 705   return length;
 706 }
 707
 708 typedef struct
 709 {
 710   char *        swi_option;
 711   unsigned int  swi_mask;
 712 } swi_options;
 713
 714 #define SWI_SWITCH      "--swi-support"
 715
 716 static swi_options options[] =
 717   {
 718     { "none",    0 },
 719     { "demon",   SWI_MASK_DEMON },
 720     { "angel",   SWI_MASK_ANGEL },
 721     { "redboot", SWI_MASK_REDBOOT },
 722     { "all",     -1 },
 723     { "NONE",    0 },
 724     { "DEMON",   SWI_MASK_DEMON },
 725     { "ANGEL",   SWI_MASK_ANGEL },
 726     { "REDBOOT", SWI_MASK_REDBOOT },
 727     { "ALL",     -1 }
 728   };
 729
 730
 731 int
 732 sim_target_parse_command_line (int argc, char ** argv)
 733 {
 734   int i;
 735
 736   for (i = 1; i < argc; i++)
 737     {
 738       char * ptr = argv[i];
 739       int arg;
 740
 741       if ((ptr == NULL) || (* ptr != '-'))
 742         break;
 743
 744       if (strcmp (ptr, "-t") == 0)
 745         {
 746           trace = 1;
 747           continue;
 748         }
 749
 750       if (strcmp (ptr, "-z") == 0)
 751         {
 752           /* Remove this option from the argv array.  */
 753           for (arg = i; arg < argc; arg ++)
 754             argv[arg] = argv[arg + 1];
 755           argc --;
 756           i --;
 757           trace_funcs = 1;
 758           continue;
 759         }
 760
 761       if (strcmp (ptr, "-d") == 0)
 762         {
 763           /* Remove this option from the argv array.  */
 764           for (arg = i; arg < argc; arg ++)
 765             argv[arg] = argv[arg + 1];
 766           argc --;
 767           i --;
 768           disas = 1;
 769           continue;
 770         }
 771
 772       if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0)
 773         continue;
 774
 775       if (ptr[sizeof SWI_SWITCH - 1] == 0)
 776         {
 777           /* Remove this option from the argv array.  */
 778           for (arg = i; arg < argc; arg ++)
 779             argv[arg] = argv[arg + 1];
 780           argc --;
 781
 782           ptr = argv[i];
 783         }
 784       else
 785         ptr += sizeof SWI_SWITCH;
 786
 787       swi_mask = 0;
 788
 789       while (* ptr)
 790         {
 791           int i;
 792
 793           for (i = sizeof options / sizeof options[0]; i--;)
 794             if (strncmp (ptr, options[i].swi_option,
 795                          strlen (options[i].swi_option)) == 0)
 796               {
 797                 swi_mask |= options[i].swi_mask;
 798                 ptr += strlen (options[i].swi_option);
 799
 800                 if (* ptr == ',')
 801                   ++ ptr;
 802
 803                 break;
 804               }
 805
 806           if (i < 0)
 807             break;
 808         }
 809
 810       if (* ptr != 0)
 811         fprintf (stderr, "Ignoring swi options: %s\n", ptr);
 812
 813       /* Remove this option from the argv array.  */
 814       for (arg = i; arg < argc; arg ++)
 815         argv[arg] = argv[arg + 1];
 816       argc --;
 817       i --;
 818     }
 819   return argc;
 820 }
 821
 822 static void
 823 sim_target_parse_arg_array (char ** argv)
 824 {
 825   int i;
 826
 827   for (i = 0; argv[i]; i++)
 828     ;
 829
 830   sim_target_parse_command_line (i, argv);
 831 }
 832
 833 void
 834 sim_target_display_usage (int help)
 835 {
 836   FILE *stream = help ? stdout : stderr;
 837
 838   fprintf (stream, "%s=<list>  Comma seperated list of SWI protocols to supoport.\n\
 839                 This list can contain: NONE, DEMON, ANGEL, REDBOOT and/or ALL.\n",
 840            SWI_SWITCH);
 841   fprintf (stream, "-d\t\tEnable disassembly of instructions during tracing.\n");
 842   fprintf (stream, "-z\t\tTrace entering and leaving functions.\n\n");
 843 }
 844
 845 SIM_DESC
 846 sim_open (SIM_OPEN_KIND   kind,
 847           host_callback * ptr,
 848           struct bfd *    abfd,
 849           char **         argv)
 850 {
 851   sim_kind = kind;
 852
 853   if (myname)
 854     free (myname);
 855   myname = (char *) xstrdup (argv[0]);
 856
 857   sim_callback = ptr;
 858
 859 #ifdef SIM_TARGET_SWITCHES
 860   sim_target_parse_arg_array (argv);
 861 #endif
 862
 863   /* Decide upon the endian-ness of the processor.
 864      If we can, get the information from the bfd itself.
 865      Otherwise look to see if we have been given a command
 866      line switch that tells us.  Otherwise default to little endian.  */
 867   if (abfd != NULL)
 868     big_endian = bfd_big_endian (abfd);
 869   else if (argv[1] != NULL)
 870     {
 871       int i;
 872
 873       /* Scan for endian-ness and memory-size switches.  */
 874       for (i = 0; (argv[i] != NULL) && (argv[i][0] != 0); i++)
 875         if (argv[i][0] == '-' && argv[i][1] == 'E')
 876           {
 877             char c;
 878
 879             if ((c = argv[i][2]) == 0)
 880               {
 881                 ++i;
 882                 c = argv[i][0];
 883               }
 884
 885             switch (c)
 886               {
 887               case 0:
 888                 sim_callback->printf_filtered
 889                   (sim_callback, "No argument to -E option provided\n");
 890                 break;
 891
 892               case 'b':
 893               case 'B':
 894                 big_endian = 1;
 895                 break;
 896
 897               case 'l':
 898               case 'L':
 899                 big_endian = 0;
 900                 break;
 901
 902               default:
 903                 sim_callback->printf_filtered
 904                   (sim_callback, "Unrecognised argument to -E option\n");
 905                 break;
 906               }
 907           }
 908         else if (argv[i][0] == '-' && argv[i][1] == 'm')
 909           {
 910             if (argv[i][2] != '\0')
 911               sim_size (atoi (&argv[i][2]));
 912             else if (argv[i + 1] != NULL)
 913               {
 914                 sim_size (atoi (argv[i + 1]));
 915                 i++;
 916               }
 917             else
 918               {
 919                 sim_callback->printf_filtered (sim_callback,
 920                                                "Missing argument to -m option\n");
 921                 return NULL;
 922               }
 923
 924           }
 925     }
 926
 927   return (SIM_DESC) 1;
 928 }
 929
 930 void
 931 sim_close (SIM_DESC sd ATTRIBUTE_UNUSED,
 932            int quitting ATTRIBUTE_UNUSED)
 933 {
 934   if (myname)
 935     free (myname);
 936   myname = NULL;
 937 }
 938
 939 SIM_RC
 940 sim_load (SIM_DESC sd,
 941           const char *prog,
 942           bfd *abfd,
 943           int from_tty ATTRIBUTE_UNUSED)
 944 {
 945   bfd *prog_bfd;
 946
 947   prog_bfd = sim_load_file (sd, myname, sim_callback, prog, abfd,
 948                             sim_kind == SIM_OPEN_DEBUG, 0, sim_write);
 949   if (prog_bfd == NULL)
 950     return SIM_RC_FAIL;
 951   ARMul_SetPC (state, bfd_get_start_address (prog_bfd));
 952   if (abfd == NULL)
 953     bfd_close (prog_bfd);
 954   return SIM_RC_OK;
 955 }
 956
 957 void
 958 sim_stop_reason (SIM_DESC sd ATTRIBUTE_UNUSED,
 959                  enum sim_stop *reason,
 960                  int *sigrc)
 961 {
 962   if (stop_simulator)
 963     {
 964       *reason = sim_stopped;
 965       *sigrc = GDB_SIGNAL_INT;
 966     }
 967   else if (state->EndCondition == 0)
 968     {
 969       *reason = sim_exited;
 970       *sigrc = state->Reg[0] & 255;
 971     }
 972   else
 973     {
 974       *reason = sim_stopped;
 975       if (state->EndCondition == RDIError_BreakpointReached)
 976         *sigrc = GDB_SIGNAL_TRAP;
 977       else if (   state->EndCondition == RDIError_DataAbort
 978                || state->EndCondition == RDIError_AddressException)
 979         *sigrc = GDB_SIGNAL_BUS;
 980       else
 981         *sigrc = 0;
 982     }
 983 }
 984
 985 void
 986 sim_do_command (SIM_DESC sd ATTRIBUTE_UNUSED,
 987                 const char *cmd ATTRIBUTE_UNUSED)
 988 {
 989   (*sim_callback->printf_filtered)
 990     (sim_callback,
 991      "This simulator does not accept any commands.\n");
 992 }
 993
 994 void
 995 sim_set_callbacks (host_callback *ptr)
 996 {
 997   sim_callback = ptr;
 998 }
 999
1000 char **
1001 sim_complete_command (SIM_DESC sd, const char *text, const char *word)
1002 {
1003   return NULL;
1004 }