1 /* Simulator for Atmel's AVR core.
2 Copyright (C) 2009-2014 Free Software Foundation, Inc.
3 Written by Tristan Gingold, AdaCore.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb/callback.h"
27 #include "gdb/signals.h"
28 #include "libiberty.h"
29 #include "gdb/remote-sim.h"
31 #include "sim-utils.h"
33 /* As AVR is a 8/16 bits processor, define handy types. */
34 typedef unsigned short int word
;
35 typedef signed short int sword
;
36 typedef unsigned char byte
;
37 typedef signed char sbyte
;
39 /* Debug flag to display instructions and registers. */
40 static int tracing
= 0;
41 static int lock_step
= 0;
44 /* The only real register. */
45 static unsigned int pc
;
47 /* We update a cycle counter. */
48 static unsigned int cycles
= 0;
50 /* If true, the pc needs more than 2 bytes. */
53 static struct bfd
*cur_bfd
;
55 static enum sim_stop cpu_exception
;
56 static int cpu_signal
;
58 static SIM_OPEN_KIND sim_kind
;
60 static host_callback
*callback
;
62 /* Max size of I space (which is always flash on avr). */
63 #define MAX_AVR_FLASH (128 * 1024)
64 #define PC_MASK (MAX_AVR_FLASH - 1)
66 /* Mac size of D space. */
67 #define MAX_AVR_SRAM (64 * 1024)
68 #define SRAM_MASK (MAX_AVR_SRAM - 1)
70 /* D space offset in ELF file. */
71 #define SRAM_VADDR 0x800000
73 /* Simulator specific ports. */
74 #define STDIO_PORT 0x52
75 #define EXIT_PORT 0x4F
76 #define ABORT_PORT 0x49
78 /* GDB defined register numbers. */
79 #define AVR_SREG_REGNUM 32
80 #define AVR_SP_REGNUM 33
81 #define AVR_PC_REGNUM 34
83 /* Memory mapped registers. */
95 /* Sreg (status) bits. */
105 /* In order to speed up emulation we use a simple approach:
106 a code is associated with each instruction. The pre-decoding occurs
107 usually once when the instruction is first seen.
108 This works well because I&D spaces are separated.
110 Missing opcodes: sleep, spm, wdr (as they are mmcu dependent).
114 /* Opcode not yet decoded. */
220 /* 2 words opcodes. */
221 #define OP_2words OP_jmp
230 /* The insn (16 bits). */
233 /* Pre-decoding code. */
234 enum avr_opcode code
: 8;
235 /* One byte of additional information. */
240 static struct avr_insn_cell flash
[MAX_AVR_FLASH
];
241 static byte sram
[MAX_AVR_SRAM
];
248 /* Sign extend a value. */
249 static int sign_ext (word val
, int nb_bits
)
251 if (val
& (1 << (nb_bits
- 1)))
252 return val
| (-1 << nb_bits
);
256 /* Insn field extractors. */
258 /* Extract xxxx_xxxRx_xxxx_RRRR. */
259 static inline byte
get_r (word op
)
261 return (op
& 0xf) | ((op
>> 5) & 0x10);
264 /* Extract xxxx_xxxxx_xxxx_RRRR. */
265 static inline byte
get_r16 (word op
)
267 return 16 + (op
& 0xf);
270 /* Extract xxxx_xxxxx_xxxx_xRRR. */
271 static inline byte
get_r16_23 (word op
)
273 return 16 + (op
& 0x7);
276 /* Extract xxxx_xxxD_DDDD_xxxx. */
277 static inline byte
get_d (word op
)
279 return (op
>> 4) & 0x1f;
282 /* Extract xxxx_xxxx_DDDD_xxxx. */
283 static inline byte
get_d16 (word op
)
285 return 16 + ((op
>> 4) & 0x0f);
288 /* Extract xxxx_xxxx_xDDD_xxxx. */
289 static inline byte
get_d16_23 (word op
)
291 return 16 + ((op
>> 4) & 0x07);
294 /* Extract xxxx_xAAx_xxxx_AAAA. */
295 static inline byte
get_A (word op
)
297 return (op
& 0x0f) | ((op
& 0x600) >> 5);
300 /* Extract xxxx_xxxx_AAAA_Axxx. */
301 static inline byte
get_biA (word op
)
303 return (op
>> 3) & 0x1f;
306 /* Extract xxxx_KKKK_xxxx_KKKK. */
307 static inline byte
get_K (word op
)
309 return (op
& 0xf) | ((op
& 0xf00) >> 4);
312 /* Extract xxxx_xxKK_KKKK_Kxxx. */
313 static inline int get_k (word op
)
315 return sign_ext ((op
& 0x3f8) >> 3, 7);
318 /* Extract xxxx_xxxx_xxDD_xxxx. */
319 static inline byte
get_d24 (word op
)
321 return 24 + ((op
>> 3) & 6);
324 /* Extract xxxx_xxxx_KKxx_KKKK. */
325 static inline byte
get_k6 (word op
)
327 return (op
& 0xf) | ((op
>> 2) & 0x30);
330 /* Extract xxQx_QQxx_xxxx_xQQQ. */
331 static inline byte
get_q (word op
)
333 return (op
& 7) | ((op
>> 7) & 0x18)| ((op
>> 8) & 0x20);
336 /* Extract xxxx_xxxx_xxxx_xBBB. */
337 static inline byte
get_b (word op
)
342 /* AVR is little endian. */
344 read_word (unsigned int addr
)
346 return sram
[addr
] | (sram
[addr
+ 1] << 8);
350 write_word (unsigned int addr
, word w
)
353 sram
[addr
+ 1] = w
>> 8;
357 read_word_post_inc (unsigned int addr
)
359 word v
= read_word (addr
);
360 write_word (addr
, v
+ 1);
365 read_word_pre_dec (unsigned int addr
)
367 word v
= read_word (addr
) - 1;
368 write_word (addr
, v
);
373 update_flags_logic (byte res
)
375 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
);
377 sram
[SREG
] |= SREG_Z
;
379 sram
[SREG
] |= SREG_N
| SREG_S
;
383 update_flags_add (byte r
, byte a
, byte b
)
387 sram
[SREG
] &= ~(SREG_H
| SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
389 sram
[SREG
] |= SREG_N
;
390 carry
= (a
& b
) | (a
& ~r
) | (b
& ~r
);
392 sram
[SREG
] |= SREG_H
;
394 sram
[SREG
] |= SREG_C
;
395 if (((a
& b
& ~r
) | (~a
& ~b
& r
)) & 0x80)
396 sram
[SREG
] |= SREG_V
;
397 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_V
))
398 sram
[SREG
] |= SREG_S
;
400 sram
[SREG
] |= SREG_Z
;
403 static void update_flags_sub (byte r
, byte a
, byte b
)
407 sram
[SREG
] &= ~(SREG_H
| SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
409 sram
[SREG
] |= SREG_N
;
410 carry
= (~a
& b
) | (b
& r
) | (r
& ~a
);
412 sram
[SREG
] |= SREG_H
;
414 sram
[SREG
] |= SREG_C
;
415 if (((a
& ~b
& ~r
) | (~a
& b
& r
)) & 0x80)
416 sram
[SREG
] |= SREG_V
;
417 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_V
))
418 sram
[SREG
] |= SREG_S
;
419 /* Note: Z is not set. */
422 static enum avr_opcode
423 decode (unsigned int pc
)
425 word op1
= flash
[pc
].op
;
427 switch ((op1
>> 12) & 0x0f)
430 switch ((op1
>> 10) & 0x3)
433 switch ((op1
>> 8) & 0x3)
463 flash
[pc
].r
= SREG_C
;
471 switch ((op1
>> 10) & 0x3)
481 flash
[pc
].r
= SREG_C
;
486 switch ((op1
>> 10) & 0x3)
514 flash
[pc
].r
= get_q (op1
);
519 flash
[pc
].r
= get_q (op1
);
527 flash
[pc
].r
= get_q (op1
);
532 flash
[pc
].r
= get_q (op1
);
538 switch ((op1
>> 8) & 0xf)
542 switch ((op1
>> 0) & 0xf)
557 return OP_elpm_inc_Z
;
574 switch ((op1
>> 0) & 0xf)
616 case 0x8: /* 9[45]x8 */
617 switch ((op1
>> 4) & 0x1f)
651 case 0x9: /* 9[45]x9 */
652 switch ((op1
>> 4) & 0x1f)
670 flash
[pc
].r
= ((op1
& 0x1f0) >> 3) | (op1
& 1);
674 flash
[pc
].r
= ((op1
& 0x1f0) >> 3) | (op1
& 1);
698 flash
[pc
].r
= get_A (op1
);
699 if (((op1
>> 11) & 1) == 0)
710 switch ((op1
>> 9) & 7)
714 flash
[pc
].r
= 1 << (op1
& 7);
718 flash
[pc
].r
= 1 << (op1
& 7);
723 flash
[pc
].r
= 1 << (op1
& 7);
730 flash
[pc
].r
= 1 << (op1
& 7);
737 flash
[pc
].r
= 1 << (op1
& 7);
744 flash
[pc
].r
= 1 << (op1
& 7);
750 sim_cb_eprintf (callback
,
751 "Unhandled instruction at pc=0x%x, op=%04x\n", pc
* 2, op1
);
755 /* Disassemble an instruction. */
758 disasm_read_memory (bfd_vma memaddr
, bfd_byte
*myaddr
, unsigned int length
,
759 struct disassemble_info
*info
)
763 res
= sim_read (NULL
, memaddr
, myaddr
, length
);
769 /* Memory error support for an opcodes disassembler. */
772 disasm_perror_memory (int status
, bfd_vma memaddr
,
773 struct disassemble_info
*info
)
777 info
->fprintf_func (info
->stream
, "Unknown error %d.", status
);
779 /* Actually, address between memaddr and memaddr + len was
781 info
->fprintf_func (info
->stream
,
782 "Address 0x%x is out of bounds.",
787 disassemble_insn (SIM_DESC sd
, SIM_ADDR pc
)
789 struct disassemble_info disasm_info
;
793 INIT_DISASSEMBLE_INFO (disasm_info
, callback
, sim_cb_eprintf
);
795 disasm_info
.arch
= bfd_get_arch (cur_bfd
);
796 disasm_info
.mach
= bfd_get_mach (cur_bfd
);
797 disasm_info
.endian
= BFD_ENDIAN_LITTLE
;
798 disasm_info
.read_memory_func
= disasm_read_memory
;
799 disasm_info
.memory_error_func
= disasm_perror_memory
;
801 len
= print_insn_avr (pc
<< 1, &disasm_info
);
803 for (i
= 0; i
< len
; i
++)
804 sim_cb_eprintf (callback
, " %04x", flash
[pc
+ i
].op
);
808 do_call (unsigned int npc
)
810 unsigned int sp
= read_word (REG_SP
);
814 sram
[sp
--] = pc
>> 8;
817 sram
[sp
--] = pc
>> 16;
820 write_word (REG_SP
, sp
);
826 get_insn_length (unsigned int p
)
828 if (flash
[p
].code
== OP_unknown
)
829 flash
[p
].code
= decode(p
);
830 if (flash
[p
].code
>= OP_2words
)
839 return (sram
[RAMPZ
] << 16) | (sram
[REGZ_HI
] << 8) | sram
[REGZ_LO
];
843 get_lpm (unsigned int addr
)
847 w
= flash
[(addr
>> 1) & PC_MASK
].op
;
854 gen_mul (unsigned int res
)
857 sram
[SREG
] &= ~(SREG_Z
| SREG_C
);
859 sram
[SREG
] |= SREG_Z
;
861 sram
[SREG
] |= SREG_C
;
866 sim_resume (SIM_DESC sd
, int step
, int signal
)
872 cpu_exception
= sim_stopped
;
873 cpu_signal
= GDB_SIGNAL_TRAP
;
876 cpu_exception
= sim_running
;
886 code
= flash
[pc
].code
;
890 if ((tracing
|| lock_step
) && code
!= OP_unknown
)
896 sim_cb_eprintf (callback
, "R00-07:");
897 for (i
= 0; i
< 8; i
++)
898 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
899 sim_cb_eprintf (callback
, " -");
900 for (i
= 8; i
< 16; i
++)
901 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
902 sim_cb_eprintf (callback
, " SP: %02x %02x",
903 sram
[REG_SP
+ 1], sram
[REG_SP
]);
904 sim_cb_eprintf (callback
, "\n");
905 sim_cb_eprintf (callback
, "R16-31:");
906 for (i
= 16; i
< 24; i
++)
907 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
908 sim_cb_eprintf (callback
, " -");
909 for (i
= 24; i
< 32; i
++)
910 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
911 sim_cb_eprintf (callback
, " ");
913 for (i
= 0; i
< 8; i
++)
914 sim_cb_eprintf (callback
, "%c",
915 flags
& (0x80 >> i
) ? "ITHSVNZC"[i
] : '-');
916 sim_cb_eprintf (callback
, "\n");
919 if (lock_step
&& !tracing
)
920 sim_cb_eprintf (callback
, "%06x: %04x\n", 2 * pc
, flash
[pc
].op
);
923 sim_cb_eprintf (callback
, "pc=0x%06x insn=0x%04x code=%d r=%d\n",
924 2 * pc
, flash
[pc
].op
, code
, flash
[pc
].r
);
925 disassemble_insn (sd
, pc
);
926 sim_cb_eprintf (callback
, "\n");
931 pc
= (pc
+ 1) & PC_MASK
;
937 flash
[ipc
].code
= decode(ipc
);
947 /* 2 words instruction, but we don't care about the pc. */
948 pc
= ((flash
[ipc
].r
<< 16) | flash
[ipc
+ 1].op
) & PC_MASK
;
953 pc
= ((sram
[EIND
] << 16) | read_word (REGZ
)) & PC_MASK
;
958 pc
= read_word (REGZ
) & PC_MASK
;
963 /* 2 words instruction. */
965 do_call ((flash
[ipc
].r
<< 16) | flash
[ipc
+ 1].op
);
969 do_call ((sram
[EIND
] << 16) | read_word (REGZ
));
973 do_call (read_word (REGZ
));
977 do_call (pc
+ sign_ext (op
& 0xfff, 12));
981 sram
[SREG
] |= SREG_I
;
985 unsigned int sp
= read_word (REG_SP
);
988 pc
= sram
[++sp
] << 16;
993 pc
|= sram
[++sp
] << 8;
995 write_word (REG_SP
, sp
);
1001 /* Stop on this address. */
1002 cpu_exception
= sim_stopped
;
1003 cpu_signal
= GDB_SIGNAL_TRAP
;
1010 if (sram
[SREG
] & SREG_T
)
1017 if (sram
[get_d (op
)] & flash
[ipc
].r
)
1018 sram
[SREG
] |= SREG_T
;
1020 sram
[SREG
] &= ~SREG_T
;
1025 if (((sram
[get_d (op
)] & flash
[ipc
].r
) == 0) ^ ((op
& 0x0200) != 0))
1027 int l
= get_insn_length(pc
);
1035 unsigned int sp
= read_word (REG_SP
);
1036 sram
[sp
--] = sram
[get_d (op
)];
1037 write_word (REG_SP
, sp
);
1044 unsigned int sp
= read_word (REG_SP
);
1045 sram
[get_d (op
)] = sram
[++sp
];
1046 write_word (REG_SP
, sp
);
1052 sram
[SREG
] &= ~(1 << ((op
>> 4) & 0x7));
1056 sram
[SREG
] |= 1 << ((op
>> 4) & 0x7);
1060 pc
= (pc
+ sign_ext (op
& 0xfff, 12)) & PC_MASK
;
1066 res
= sram
[d
] ^ sram
[get_r (op
)];
1068 update_flags_logic (res
);
1073 res
= sram
[d
] & sram
[get_r (op
)];
1075 update_flags_logic (res
);
1080 res
= sram
[d
] & get_K (op
);
1082 update_flags_logic (res
);
1087 res
= sram
[d
] | sram
[get_r (op
)];
1089 update_flags_logic (res
);
1094 res
= sram
[d
] | get_K (op
);
1096 update_flags_logic (res
);
1103 update_flags_logic (res
);
1104 sram
[SREG
] |= SREG_C
;
1110 sram
[d
] = (vd
>> 4) | (vd
<< 4);
1118 sram
[SREG
] &= ~(SREG_H
| SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1120 sram
[SREG
] |= SREG_Z
;
1122 sram
[SREG
] |= SREG_C
;
1124 sram
[SREG
] |= SREG_V
| SREG_N
;
1125 else if (res
& 0x80)
1126 sram
[SREG
] |= SREG_N
| SREG_S
;
1127 if ((res
| vd
) & 0x08)
1128 sram
[SREG
] |= SREG_H
;
1135 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
);
1137 sram
[SREG
] |= SREG_V
| SREG_N
;
1138 else if (res
& 0x80)
1139 sram
[SREG
] |= SREG_N
| SREG_S
;
1141 sram
[SREG
] |= SREG_Z
;
1148 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
);
1150 sram
[SREG
] |= SREG_V
| SREG_S
;
1151 else if (res
& 0x80)
1152 sram
[SREG
] |= SREG_N
| SREG_S
;
1154 sram
[SREG
] |= SREG_Z
;
1161 res
= (vd
>> 1) | (vd
& flash
[ipc
].r
);
1163 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1165 sram
[SREG
] |= SREG_C
| SREG_S
;
1167 sram
[SREG
] |= SREG_N
;
1168 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_C
))
1169 sram
[SREG
] |= SREG_V
;
1171 sram
[SREG
] |= SREG_Z
;
1177 res
= vd
>> 1 | (sram
[SREG
] << 7);
1179 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1181 sram
[SREG
] |= SREG_C
| SREG_S
;
1183 sram
[SREG
] |= SREG_N
;
1184 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_C
))
1185 sram
[SREG
] |= SREG_V
;
1187 sram
[SREG
] |= SREG_Z
;
1191 gen_mul ((word
)sram
[get_r (op
)] * (word
)sram
[get_d (op
)]);
1195 gen_mul((sword
)(sbyte
)sram
[get_r16 (op
)]
1196 * (sword
)(sbyte
)sram
[get_d16 (op
)]);
1200 gen_mul ((sword
)(word
)sram
[get_r16_23 (op
)]
1201 * (sword
)(sbyte
)sram
[get_d16_23 (op
)]);
1205 gen_mul(((word
)sram
[get_r16_23 (op
)]
1206 * (word
)sram
[get_d16_23 (op
)]) << 1);
1210 gen_mul(((sword
)(sbyte
)sram
[get_r16_23 (op
)]
1211 * (sword
)(sbyte
)sram
[get_d16_23 (op
)]) << 1);
1215 gen_mul(((sword
)(word
)sram
[get_r16_23 (op
)]
1216 * (sword
)(sbyte
)sram
[get_d16_23 (op
)]) << 1);
1221 r
= sram
[get_r (op
)];
1224 res
= r
+ vd
+ (sram
[SREG
] & flash
[ipc
].r
);
1226 update_flags_add (res
, vd
, r
);
1232 r
= sram
[get_r (op
)];
1235 update_flags_sub (res
, vd
, r
);
1237 sram
[SREG
] |= SREG_Z
;
1242 byte old
= sram
[SREG
];
1245 r
= sram
[get_r (op
)];
1246 res
= vd
- r
- (old
& SREG_C
);
1248 update_flags_sub (res
, vd
, r
);
1249 if (res
== 0 && (old
& SREG_Z
))
1250 sram
[SREG
] |= SREG_Z
;
1260 update_flags_sub (res
, vd
, r
);
1262 sram
[SREG
] |= SREG_Z
;
1267 byte old
= sram
[SREG
];
1272 res
= vd
- r
- (old
& SREG_C
);
1274 update_flags_sub (res
, vd
, r
);
1275 if (res
== 0 && (old
& SREG_Z
))
1276 sram
[SREG
] |= SREG_Z
;
1281 sram
[get_d (op
)] = sram
[get_r (op
)];
1285 d
= (op
& 0xf0) >> 3;
1286 r
= (op
& 0x0f) << 1;
1288 sram
[d
+ 1] = sram
[r
+ 1];
1292 d
= get_A (op
) + 0x20;
1293 res
= sram
[get_d (op
)];
1295 if (d
== STDIO_PORT
)
1297 else if (d
== EXIT_PORT
)
1299 cpu_exception
= sim_exited
;
1303 else if (d
== ABORT_PORT
)
1305 cpu_exception
= sim_exited
;
1312 d
= get_A (op
) + 0x20;
1313 sram
[get_d (op
)] = sram
[d
];
1317 d
= get_biA (op
) + 0x20;
1318 sram
[d
] &= ~(1 << get_b(op
));
1322 d
= get_biA (op
) + 0x20;
1323 sram
[d
] |= 1 << get_b(op
);
1327 if (!(sram
[get_biA (op
) + 0x20] & 1 << get_b(op
)))
1329 int l
= get_insn_length(pc
);
1336 if (sram
[get_biA (op
) + 0x20] & 1 << get_b(op
))
1338 int l
= get_insn_length(pc
);
1351 sram
[get_d (op
)] = sram
[flash
[pc
].op
];
1357 sram
[flash
[pc
].op
] = sram
[get_d (op
)];
1363 if (sram
[get_r (op
)] == sram
[get_d (op
)])
1365 int l
= get_insn_length(pc
);
1372 r
= sram
[get_r (op
)];
1373 d
= sram
[get_d (op
)];
1375 update_flags_sub (res
, d
, r
);
1377 sram
[SREG
] |= SREG_Z
;
1382 d
= sram
[get_d16 (op
)];
1384 update_flags_sub (res
, d
, r
);
1386 sram
[SREG
] |= SREG_Z
;
1391 byte old
= sram
[SREG
];
1392 d
= sram
[get_d (op
)];
1393 r
= sram
[get_r (op
)];
1394 res
= d
- r
- (old
& SREG_C
);
1395 update_flags_sub (res
, d
, r
);
1396 if (res
== 0 && (old
& SREG_Z
))
1397 sram
[SREG
] |= SREG_Z
;
1402 if (!(sram
[SREG
] & flash
[ipc
].r
))
1404 pc
= (pc
+ get_k (op
)) & PC_MASK
;
1410 if (sram
[SREG
] & flash
[ipc
].r
)
1412 pc
= (pc
+ get_k (op
)) & PC_MASK
;
1418 sram
[0] = get_lpm (read_word (REGZ
));
1423 sram
[get_d (op
)] = get_lpm (read_word (REGZ
));
1428 sram
[get_d (op
)] = get_lpm (read_word_post_inc (REGZ
));
1433 sram
[0] = get_lpm (get_z ());
1438 sram
[get_d (op
)] = get_lpm (get_z ());
1444 unsigned int z
= get_z ();
1446 sram
[get_d (op
)] = get_lpm (z
);
1449 sram
[REGZ_HI
] = z
>> 8;
1450 sram
[RAMPZ
] = z
>> 16;
1456 sram
[get_d (op
)] = sram
[read_word_post_inc (REGZ
) & SRAM_MASK
];
1461 sram
[get_d (op
)] = sram
[read_word_pre_dec (REGZ
) & SRAM_MASK
];
1466 sram
[get_d (op
)] = sram
[read_word_post_inc (REGX
) & SRAM_MASK
];
1471 sram
[get_d (op
)] = sram
[read_word_pre_dec (REGX
) & SRAM_MASK
];
1476 sram
[get_d (op
)] = sram
[read_word_post_inc (REGY
) & SRAM_MASK
];
1481 sram
[get_d (op
)] = sram
[read_word_pre_dec (REGY
) & SRAM_MASK
];
1486 sram
[read_word (REGX
) & SRAM_MASK
] = sram
[get_d (op
)];
1491 sram
[read_word_post_inc (REGX
) & SRAM_MASK
] = sram
[get_d (op
)];
1496 sram
[read_word_pre_dec (REGX
) & SRAM_MASK
] = sram
[get_d (op
)];
1501 sram
[read_word_post_inc (REGZ
) & SRAM_MASK
] = sram
[get_d (op
)];
1506 sram
[read_word_pre_dec (REGZ
) & SRAM_MASK
] = sram
[get_d (op
)];
1511 sram
[read_word_post_inc (REGY
) & SRAM_MASK
] = sram
[get_d (op
)];
1516 sram
[read_word_pre_dec (REGY
) & SRAM_MASK
] = sram
[get_d (op
)];
1521 sram
[read_word (REGY
) + flash
[ipc
].r
] = sram
[get_d (op
)];
1526 sram
[read_word (REGZ
) + flash
[ipc
].r
] = sram
[get_d (op
)];
1531 sram
[get_d (op
)] = sram
[read_word (REGZ
) + flash
[ipc
].r
];
1536 sram
[get_d (op
)] = sram
[read_word (REGY
) + flash
[ipc
].r
];
1541 sram
[get_d (op
)] = sram
[read_word (REGX
) & SRAM_MASK
];
1547 word wk
= get_k6 (op
);
1555 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1557 sram
[SREG
] |= SREG_Z
;
1559 sram
[SREG
] |= SREG_N
;
1560 if (wres
& ~wr
& 0x8000)
1561 sram
[SREG
] |= SREG_C
;
1562 if (~wres
& wr
& 0x8000)
1563 sram
[SREG
] |= SREG_V
;
1564 if (((~wres
& wr
) ^ wres
) & 0x8000)
1565 sram
[SREG
] |= SREG_S
;
1566 write_word (d
, wres
);
1573 word wk
= get_k6 (op
);
1581 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1583 sram
[SREG
] |= SREG_Z
;
1585 sram
[SREG
] |= SREG_N
;
1586 if (~wres
& wr
& 0x8000)
1587 sram
[SREG
] |= SREG_C
;
1588 if (wres
& ~wr
& 0x8000)
1589 sram
[SREG
] |= SREG_V
;
1590 if (((wres
& ~wr
) ^ wres
) & 0x8000)
1591 sram
[SREG
] |= SREG_S
;
1592 write_word (d
, wres
);
1598 sim_cb_eprintf (callback
, "Bad instruction at pc=0x%x\n", ipc
* 2);
1602 sim_cb_eprintf (callback
,
1603 "Unhandled instruction at pc=0x%x, code=%d\n",
1608 while (cpu_exception
== sim_running
);
1613 sim_trace (SIM_DESC sd
)
1617 sim_resume (sd
, 0, 0);
1625 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
1629 if (addr
>= 0 && addr
< SRAM_VADDR
)
1631 while (size
> 0 && addr
< (MAX_AVR_FLASH
<< 1))
1633 word val
= flash
[addr
>> 1].op
;
1636 val
= (val
& 0xff) | (buffer
[0] << 8);
1638 val
= (val
& 0xff00) | buffer
[0];
1640 flash
[addr
>> 1].op
= val
;
1641 flash
[addr
>> 1].code
= OP_unknown
;
1646 return osize
- size
;
1648 else if (addr
>= SRAM_VADDR
&& addr
< SRAM_VADDR
+ MAX_AVR_SRAM
)
1651 if (addr
+ size
> MAX_AVR_SRAM
)
1652 size
= MAX_AVR_SRAM
- addr
;
1653 memcpy (sram
+ addr
, buffer
, size
);
1661 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
1665 if (addr
>= 0 && addr
< SRAM_VADDR
)
1667 while (size
> 0 && addr
< (MAX_AVR_FLASH
<< 1))
1669 word val
= flash
[addr
>> 1].op
;
1678 return osize
- size
;
1680 else if (addr
>= SRAM_VADDR
&& addr
< SRAM_VADDR
+ MAX_AVR_SRAM
)
1683 if (addr
+ size
> MAX_AVR_SRAM
)
1684 size
= MAX_AVR_SRAM
- addr
;
1685 memcpy (buffer
, sram
+ addr
, size
);
1691 memset (buffer
, 0, size
);
1697 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
1699 if (rn
< 32 && length
== 1)
1704 if (rn
== AVR_SREG_REGNUM
&& length
== 1)
1706 sram
[SREG
] = *memory
;
1709 if (rn
== AVR_SP_REGNUM
&& length
== 2)
1711 sram
[REG_SP
] = memory
[0];
1712 sram
[REG_SP
+ 1] = memory
[1];
1715 if (rn
== AVR_PC_REGNUM
&& length
== 4)
1717 pc
= (memory
[0] >> 1) | (memory
[1] << 7)
1718 | (memory
[2] << 15) | (memory
[3] << 23);
1726 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
1728 if (rn
< 32 && length
== 1)
1733 if (rn
== AVR_SREG_REGNUM
&& length
== 1)
1735 *memory
= sram
[SREG
];
1738 if (rn
== AVR_SP_REGNUM
&& length
== 2)
1740 memory
[0] = sram
[REG_SP
];
1741 memory
[1] = sram
[REG_SP
+ 1];
1744 if (rn
== AVR_PC_REGNUM
&& length
== 4)
1746 memory
[0] = pc
<< 1;
1747 memory
[1] = pc
>> 7;
1748 memory
[2] = pc
>> 15;
1749 memory
[3] = pc
>> 23;
1756 sim_stop_reason (SIM_DESC sd
, enum sim_stop
* reason
, int *sigrc
)
1758 *reason
= cpu_exception
;
1759 *sigrc
= cpu_signal
;
1763 sim_stop (SIM_DESC sd
)
1765 cpu_exception
= sim_stopped
;
1766 cpu_signal
= GDB_SIGNAL_INT
;
1771 sim_info (SIM_DESC sd
, int verbose
)
1773 callback
->printf_filtered
1774 (callback
, "\n\n# cycles %10u\n", cycles
);
1778 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
, struct bfd
*abfd
, char **argv
)
1785 /* Fudge our descriptor for now. */
1786 return (SIM_DESC
) 1;
1790 sim_close (SIM_DESC sd
, int quitting
)
1796 sim_load (SIM_DESC sd
, const char *prog
, bfd
*abfd
, int from_tty
)
1800 /* Clear all the memory. */
1801 memset (sram
, 0, sizeof (sram
));
1802 memset (flash
, 0, sizeof (flash
));
1804 prog_bfd
= sim_load_file (sd
, myname
, callback
, prog
, abfd
,
1805 sim_kind
== SIM_OPEN_DEBUG
,
1807 if (prog_bfd
== NULL
)
1810 avr_pc22
= (bfd_get_mach (prog_bfd
) >= bfd_mach_avr6
);
1819 sim_create_inferior (SIM_DESC sd
, struct bfd
*prog_bfd
, char **argv
, char **env
)
1821 /* Set the initial register set. */
1828 sim_kill (SIM_DESC sd
)
1834 sim_do_command (SIM_DESC sd
, char *cmd
)
1836 /* Nothing there yet; it's all an error. */
1841 if (strcmp (cmd
, "verbose") == 0)
1843 else if (strcmp (cmd
, "trace") == 0)
1846 sim_cb_eprintf (callback
,
1847 "Error: \"%s\" is not a valid avr simulator command.\n",
1852 sim_set_callbacks (host_callback
*ptr
)
1858 sim_complete_command (SIM_DESC sd
, const char *text
, const char *word
)