1 /* Simulator for Atmel's AVR core.
2 Copyright (C) 2009-2016 Free Software Foundation, Inc.
3 Written by Tristan Gingold, AdaCore.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "libiberty.h"
27 #include "gdb/remote-sim.h"
31 #include "sim-options.h"
33 /* As AVR is a 8/16 bits processor, define handy types. */
34 typedef unsigned short int word
;
35 typedef signed short int sword
;
36 typedef unsigned char byte
;
37 typedef signed char sbyte
;
39 /* Max size of I space (which is always flash on avr). */
40 #define MAX_AVR_FLASH (128 * 1024)
41 #define PC_MASK (MAX_AVR_FLASH - 1)
43 /* Mac size of D space. */
44 #define MAX_AVR_SRAM (64 * 1024)
45 #define SRAM_MASK (MAX_AVR_SRAM - 1)
47 /* D space offset in ELF file. */
48 #define SRAM_VADDR 0x800000
50 /* Simulator specific ports. */
51 #define STDIO_PORT 0x52
52 #define EXIT_PORT 0x4F
53 #define ABORT_PORT 0x49
55 /* GDB defined register numbers. */
56 #define AVR_SREG_REGNUM 32
57 #define AVR_SP_REGNUM 33
58 #define AVR_PC_REGNUM 34
60 /* Memory mapped registers. */
72 /* Sreg (status) bits. */
82 /* In order to speed up emulation we use a simple approach:
83 a code is associated with each instruction. The pre-decoding occurs
84 usually once when the instruction is first seen.
85 This works well because I&D spaces are separated.
87 Missing opcodes: sleep, spm, wdr (as they are mmcu dependent).
91 /* Opcode not yet decoded. */
197 /* 2 words opcodes. */
198 #define OP_2words OP_jmp
207 /* The insn (16 bits). */
210 /* Pre-decoding code. */
211 enum avr_opcode code
: 8;
212 /* One byte of additional information. */
217 /* TODO: Should be moved to SIM_CPU. */
218 static struct avr_insn_cell flash
[MAX_AVR_FLASH
];
219 static byte sram
[MAX_AVR_SRAM
];
221 /* Sign extend a value. */
222 static int sign_ext (word val
, int nb_bits
)
224 if (val
& (1 << (nb_bits
- 1)))
225 return val
| -(1 << nb_bits
);
229 /* Insn field extractors. */
231 /* Extract xxxx_xxxRx_xxxx_RRRR. */
232 static inline byte
get_r (word op
)
234 return (op
& 0xf) | ((op
>> 5) & 0x10);
237 /* Extract xxxx_xxxxx_xxxx_RRRR. */
238 static inline byte
get_r16 (word op
)
240 return 16 + (op
& 0xf);
243 /* Extract xxxx_xxxxx_xxxx_xRRR. */
244 static inline byte
get_r16_23 (word op
)
246 return 16 + (op
& 0x7);
249 /* Extract xxxx_xxxD_DDDD_xxxx. */
250 static inline byte
get_d (word op
)
252 return (op
>> 4) & 0x1f;
255 /* Extract xxxx_xxxx_DDDD_xxxx. */
256 static inline byte
get_d16 (word op
)
258 return 16 + ((op
>> 4) & 0x0f);
261 /* Extract xxxx_xxxx_xDDD_xxxx. */
262 static inline byte
get_d16_23 (word op
)
264 return 16 + ((op
>> 4) & 0x07);
267 /* Extract xxxx_xAAx_xxxx_AAAA. */
268 static inline byte
get_A (word op
)
270 return (op
& 0x0f) | ((op
& 0x600) >> 5);
273 /* Extract xxxx_xxxx_AAAA_Axxx. */
274 static inline byte
get_biA (word op
)
276 return (op
>> 3) & 0x1f;
279 /* Extract xxxx_KKKK_xxxx_KKKK. */
280 static inline byte
get_K (word op
)
282 return (op
& 0xf) | ((op
& 0xf00) >> 4);
285 /* Extract xxxx_xxKK_KKKK_Kxxx. */
286 static inline int get_k (word op
)
288 return sign_ext ((op
& 0x3f8) >> 3, 7);
291 /* Extract xxxx_xxxx_xxDD_xxxx. */
292 static inline byte
get_d24 (word op
)
294 return 24 + ((op
>> 3) & 6);
297 /* Extract xxxx_xxxx_KKxx_KKKK. */
298 static inline byte
get_k6 (word op
)
300 return (op
& 0xf) | ((op
>> 2) & 0x30);
303 /* Extract xxQx_QQxx_xxxx_xQQQ. */
304 static inline byte
get_q (word op
)
306 return (op
& 7) | ((op
>> 7) & 0x18)| ((op
>> 8) & 0x20);
309 /* Extract xxxx_xxxx_xxxx_xBBB. */
310 static inline byte
get_b (word op
)
315 /* AVR is little endian. */
317 read_word (unsigned int addr
)
319 return sram
[addr
] | (sram
[addr
+ 1] << 8);
323 write_word (unsigned int addr
, word w
)
326 sram
[addr
+ 1] = w
>> 8;
330 read_word_post_inc (unsigned int addr
)
332 word v
= read_word (addr
);
333 write_word (addr
, v
+ 1);
338 read_word_pre_dec (unsigned int addr
)
340 word v
= read_word (addr
) - 1;
341 write_word (addr
, v
);
346 update_flags_logic (byte res
)
348 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
);
350 sram
[SREG
] |= SREG_Z
;
352 sram
[SREG
] |= SREG_N
| SREG_S
;
356 update_flags_add (byte r
, byte a
, byte b
)
360 sram
[SREG
] &= ~(SREG_H
| SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
362 sram
[SREG
] |= SREG_N
;
363 carry
= (a
& b
) | (a
& ~r
) | (b
& ~r
);
365 sram
[SREG
] |= SREG_H
;
367 sram
[SREG
] |= SREG_C
;
368 if (((a
& b
& ~r
) | (~a
& ~b
& r
)) & 0x80)
369 sram
[SREG
] |= SREG_V
;
370 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_V
))
371 sram
[SREG
] |= SREG_S
;
373 sram
[SREG
] |= SREG_Z
;
376 static void update_flags_sub (byte r
, byte a
, byte b
)
380 sram
[SREG
] &= ~(SREG_H
| SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
382 sram
[SREG
] |= SREG_N
;
383 carry
= (~a
& b
) | (b
& r
) | (r
& ~a
);
385 sram
[SREG
] |= SREG_H
;
387 sram
[SREG
] |= SREG_C
;
388 if (((a
& ~b
& ~r
) | (~a
& b
& r
)) & 0x80)
389 sram
[SREG
] |= SREG_V
;
390 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_V
))
391 sram
[SREG
] |= SREG_S
;
392 /* Note: Z is not set. */
395 static enum avr_opcode
396 decode (unsigned int pc
)
398 word op1
= flash
[pc
].op
;
400 switch ((op1
>> 12) & 0x0f)
403 switch ((op1
>> 10) & 0x3)
406 switch ((op1
>> 8) & 0x3)
436 flash
[pc
].r
= SREG_C
;
444 switch ((op1
>> 10) & 0x3)
454 flash
[pc
].r
= SREG_C
;
459 switch ((op1
>> 10) & 0x3)
487 flash
[pc
].r
= get_q (op1
);
492 flash
[pc
].r
= get_q (op1
);
500 flash
[pc
].r
= get_q (op1
);
505 flash
[pc
].r
= get_q (op1
);
511 switch ((op1
>> 8) & 0xf)
515 switch ((op1
>> 0) & 0xf)
530 return OP_elpm_inc_Z
;
547 switch ((op1
>> 0) & 0xf)
589 case 0x8: /* 9[45]x8 */
590 switch ((op1
>> 4) & 0x1f)
624 case 0x9: /* 9[45]x9 */
625 switch ((op1
>> 4) & 0x1f)
643 flash
[pc
].r
= ((op1
& 0x1f0) >> 3) | (op1
& 1);
647 flash
[pc
].r
= ((op1
& 0x1f0) >> 3) | (op1
& 1);
671 flash
[pc
].r
= get_A (op1
);
672 if (((op1
>> 11) & 1) == 0)
683 switch ((op1
>> 9) & 7)
687 flash
[pc
].r
= 1 << (op1
& 7);
691 flash
[pc
].r
= 1 << (op1
& 7);
696 flash
[pc
].r
= 1 << (op1
& 7);
703 flash
[pc
].r
= 1 << (op1
& 7);
710 flash
[pc
].r
= 1 << (op1
& 7);
717 flash
[pc
].r
= 1 << (op1
& 7);
728 do_call (SIM_CPU
*cpu
, unsigned int npc
)
730 SIM_DESC sd
= CPU_STATE (cpu
);
731 unsigned int sp
= read_word (REG_SP
);
734 sram
[sp
--] = cpu
->pc
;
735 sram
[sp
--] = cpu
->pc
>> 8;
738 sram
[sp
--] = cpu
->pc
>> 16;
741 write_word (REG_SP
, sp
);
742 cpu
->pc
= npc
& PC_MASK
;
747 get_insn_length (unsigned int p
)
749 if (flash
[p
].code
== OP_unknown
)
750 flash
[p
].code
= decode(p
);
751 if (flash
[p
].code
>= OP_2words
)
760 return (sram
[RAMPZ
] << 16) | (sram
[REGZ_HI
] << 8) | sram
[REGZ_LO
];
764 get_lpm (unsigned int addr
)
768 w
= flash
[(addr
>> 1) & PC_MASK
].op
;
775 gen_mul (SIM_CPU
*cpu
, unsigned int res
)
778 sram
[SREG
] &= ~(SREG_Z
| SREG_C
);
780 sram
[SREG
] |= SREG_Z
;
782 sram
[SREG
] |= SREG_C
;
787 step_once (SIM_CPU
*cpu
)
797 code
= flash
[cpu
->pc
].code
;
798 op
= flash
[cpu
->pc
].op
;
801 if (tracing
&& code
!= OP_unknown
)
807 sim_cb_eprintf (callback
, "R00-07:");
808 for (i
= 0; i
< 8; i
++)
809 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
810 sim_cb_eprintf (callback
, " -");
811 for (i
= 8; i
< 16; i
++)
812 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
813 sim_cb_eprintf (callback
, " SP: %02x %02x",
814 sram
[REG_SP
+ 1], sram
[REG_SP
]);
815 sim_cb_eprintf (callback
, "\n");
816 sim_cb_eprintf (callback
, "R16-31:");
817 for (i
= 16; i
< 24; i
++)
818 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
819 sim_cb_eprintf (callback
, " -");
820 for (i
= 24; i
< 32; i
++)
821 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
822 sim_cb_eprintf (callback
, " ");
824 for (i
= 0; i
< 8; i
++)
825 sim_cb_eprintf (callback
, "%c",
826 flags
& (0x80 >> i
) ? "ITHSVNZC"[i
] : '-');
827 sim_cb_eprintf (callback
, "\n");
831 sim_cb_eprintf (callback
, "%06x: %04x\n", 2 * cpu
->pc
, flash
[cpu
->pc
].op
);
834 sim_cb_eprintf (callback
, "pc=0x%06x insn=0x%04x code=%d r=%d\n",
835 2 * cpu
->pc
, flash
[cpu
->pc
].op
, code
, flash
[cpu
->pc
].r
);
836 disassemble_insn (CPU_STATE (cpu
), cpu
->pc
);
837 sim_cb_eprintf (callback
, "\n");
843 cpu
->pc
= (cpu
->pc
+ 1) & PC_MASK
;
849 flash
[ipc
].code
= decode(ipc
);
858 /* 2 words instruction, but we don't care about the pc. */
859 cpu
->pc
= ((flash
[ipc
].r
<< 16) | flash
[ipc
+ 1].op
) & PC_MASK
;
864 cpu
->pc
= ((sram
[EIND
] << 16) | read_word (REGZ
)) & PC_MASK
;
869 cpu
->pc
= read_word (REGZ
) & PC_MASK
;
874 /* 2 words instruction. */
876 do_call (cpu
, (flash
[ipc
].r
<< 16) | flash
[ipc
+ 1].op
);
880 do_call (cpu
, (sram
[EIND
] << 16) | read_word (REGZ
));
884 do_call (cpu
, read_word (REGZ
));
888 do_call (cpu
, cpu
->pc
+ sign_ext (op
& 0xfff, 12));
892 sram
[SREG
] |= SREG_I
;
896 SIM_DESC sd
= CPU_STATE (cpu
);
897 unsigned int sp
= read_word (REG_SP
);
900 cpu
->pc
= sram
[++sp
] << 16;
905 cpu
->pc
|= sram
[++sp
] << 8;
906 cpu
->pc
|= sram
[++sp
];
907 write_word (REG_SP
, sp
);
913 /* Stop on this address. */
914 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
, cpu
->pc
, sim_stopped
, SIM_SIGTRAP
);
921 if (sram
[SREG
] & SREG_T
)
928 if (sram
[get_d (op
)] & flash
[ipc
].r
)
929 sram
[SREG
] |= SREG_T
;
931 sram
[SREG
] &= ~SREG_T
;
936 if (((sram
[get_d (op
)] & flash
[ipc
].r
) == 0) ^ ((op
& 0x0200) != 0))
938 int l
= get_insn_length (cpu
->pc
);
946 unsigned int sp
= read_word (REG_SP
);
947 sram
[sp
--] = sram
[get_d (op
)];
948 write_word (REG_SP
, sp
);
955 unsigned int sp
= read_word (REG_SP
);
956 sram
[get_d (op
)] = sram
[++sp
];
957 write_word (REG_SP
, sp
);
963 sram
[SREG
] &= ~(1 << ((op
>> 4) & 0x7));
967 sram
[SREG
] |= 1 << ((op
>> 4) & 0x7);
971 cpu
->pc
= (cpu
->pc
+ sign_ext (op
& 0xfff, 12)) & PC_MASK
;
977 res
= sram
[d
] ^ sram
[get_r (op
)];
979 update_flags_logic (res
);
984 res
= sram
[d
] & sram
[get_r (op
)];
986 update_flags_logic (res
);
991 res
= sram
[d
] & get_K (op
);
993 update_flags_logic (res
);
998 res
= sram
[d
] | sram
[get_r (op
)];
1000 update_flags_logic (res
);
1005 res
= sram
[d
] | get_K (op
);
1007 update_flags_logic (res
);
1014 update_flags_logic (res
);
1015 sram
[SREG
] |= SREG_C
;
1021 sram
[d
] = (vd
>> 4) | (vd
<< 4);
1029 sram
[SREG
] &= ~(SREG_H
| SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1031 sram
[SREG
] |= SREG_Z
;
1033 sram
[SREG
] |= SREG_C
;
1035 sram
[SREG
] |= SREG_V
| SREG_N
;
1036 else if (res
& 0x80)
1037 sram
[SREG
] |= SREG_N
| SREG_S
;
1038 if ((res
| vd
) & 0x08)
1039 sram
[SREG
] |= SREG_H
;
1046 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
);
1048 sram
[SREG
] |= SREG_V
| SREG_N
;
1049 else if (res
& 0x80)
1050 sram
[SREG
] |= SREG_N
| SREG_S
;
1052 sram
[SREG
] |= SREG_Z
;
1059 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
);
1061 sram
[SREG
] |= SREG_V
| SREG_S
;
1062 else if (res
& 0x80)
1063 sram
[SREG
] |= SREG_N
| SREG_S
;
1065 sram
[SREG
] |= SREG_Z
;
1072 res
= (vd
>> 1) | (vd
& flash
[ipc
].r
);
1074 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1076 sram
[SREG
] |= SREG_C
| SREG_S
;
1078 sram
[SREG
] |= SREG_N
;
1079 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_C
))
1080 sram
[SREG
] |= SREG_V
;
1082 sram
[SREG
] |= SREG_Z
;
1088 res
= vd
>> 1 | (sram
[SREG
] << 7);
1090 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1092 sram
[SREG
] |= SREG_C
| SREG_S
;
1094 sram
[SREG
] |= SREG_N
;
1095 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_C
))
1096 sram
[SREG
] |= SREG_V
;
1098 sram
[SREG
] |= SREG_Z
;
1102 gen_mul (cpu
, (word
)sram
[get_r (op
)] * (word
)sram
[get_d (op
)]);
1106 gen_mul (cpu
, (sword
)(sbyte
)sram
[get_r16 (op
)]
1107 * (sword
)(sbyte
)sram
[get_d16 (op
)]);
1111 gen_mul (cpu
, (sword
)(word
)sram
[get_r16_23 (op
)]
1112 * (sword
)(sbyte
)sram
[get_d16_23 (op
)]);
1116 gen_mul (cpu
, ((word
)sram
[get_r16_23 (op
)]
1117 * (word
)sram
[get_d16_23 (op
)]) << 1);
1121 gen_mul (cpu
, ((sword
)(sbyte
)sram
[get_r16_23 (op
)]
1122 * (sword
)(sbyte
)sram
[get_d16_23 (op
)]) << 1);
1126 gen_mul (cpu
, ((sword
)(word
)sram
[get_r16_23 (op
)]
1127 * (sword
)(sbyte
)sram
[get_d16_23 (op
)]) << 1);
1132 r
= sram
[get_r (op
)];
1135 res
= r
+ vd
+ (sram
[SREG
] & flash
[ipc
].r
);
1137 update_flags_add (res
, vd
, r
);
1143 r
= sram
[get_r (op
)];
1146 update_flags_sub (res
, vd
, r
);
1148 sram
[SREG
] |= SREG_Z
;
1153 byte old
= sram
[SREG
];
1156 r
= sram
[get_r (op
)];
1157 res
= vd
- r
- (old
& SREG_C
);
1159 update_flags_sub (res
, vd
, r
);
1160 if (res
== 0 && (old
& SREG_Z
))
1161 sram
[SREG
] |= SREG_Z
;
1171 update_flags_sub (res
, vd
, r
);
1173 sram
[SREG
] |= SREG_Z
;
1178 byte old
= sram
[SREG
];
1183 res
= vd
- r
- (old
& SREG_C
);
1185 update_flags_sub (res
, vd
, r
);
1186 if (res
== 0 && (old
& SREG_Z
))
1187 sram
[SREG
] |= SREG_Z
;
1192 sram
[get_d (op
)] = sram
[get_r (op
)];
1196 d
= (op
& 0xf0) >> 3;
1197 r
= (op
& 0x0f) << 1;
1199 sram
[d
+ 1] = sram
[r
+ 1];
1203 d
= get_A (op
) + 0x20;
1204 res
= sram
[get_d (op
)];
1206 if (d
== STDIO_PORT
)
1208 else if (d
== EXIT_PORT
)
1209 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
, cpu
->pc
, sim_exited
, 0);
1210 else if (d
== ABORT_PORT
)
1211 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
, cpu
->pc
, sim_exited
, 1);
1215 d
= get_A (op
) + 0x20;
1216 sram
[get_d (op
)] = sram
[d
];
1220 d
= get_biA (op
) + 0x20;
1221 sram
[d
] &= ~(1 << get_b(op
));
1225 d
= get_biA (op
) + 0x20;
1226 sram
[d
] |= 1 << get_b(op
);
1230 if (!(sram
[get_biA (op
) + 0x20] & 1 << get_b(op
)))
1232 int l
= get_insn_length (cpu
->pc
);
1239 if (sram
[get_biA (op
) + 0x20] & 1 << get_b(op
))
1241 int l
= get_insn_length (cpu
->pc
);
1254 sram
[get_d (op
)] = sram
[flash
[cpu
->pc
].op
];
1260 sram
[flash
[cpu
->pc
].op
] = sram
[get_d (op
)];
1266 if (sram
[get_r (op
)] == sram
[get_d (op
)])
1268 int l
= get_insn_length (cpu
->pc
);
1275 r
= sram
[get_r (op
)];
1276 d
= sram
[get_d (op
)];
1278 update_flags_sub (res
, d
, r
);
1280 sram
[SREG
] |= SREG_Z
;
1285 d
= sram
[get_d16 (op
)];
1287 update_flags_sub (res
, d
, r
);
1289 sram
[SREG
] |= SREG_Z
;
1294 byte old
= sram
[SREG
];
1295 d
= sram
[get_d (op
)];
1296 r
= sram
[get_r (op
)];
1297 res
= d
- r
- (old
& SREG_C
);
1298 update_flags_sub (res
, d
, r
);
1299 if (res
== 0 && (old
& SREG_Z
))
1300 sram
[SREG
] |= SREG_Z
;
1305 if (!(sram
[SREG
] & flash
[ipc
].r
))
1307 cpu
->pc
= (cpu
->pc
+ get_k (op
)) & PC_MASK
;
1313 if (sram
[SREG
] & flash
[ipc
].r
)
1315 cpu
->pc
= (cpu
->pc
+ get_k (op
)) & PC_MASK
;
1321 sram
[0] = get_lpm (read_word (REGZ
));
1326 sram
[get_d (op
)] = get_lpm (read_word (REGZ
));
1331 sram
[get_d (op
)] = get_lpm (read_word_post_inc (REGZ
));
1336 sram
[0] = get_lpm (get_z ());
1341 sram
[get_d (op
)] = get_lpm (get_z ());
1347 unsigned int z
= get_z ();
1349 sram
[get_d (op
)] = get_lpm (z
);
1352 sram
[REGZ_HI
] = z
>> 8;
1353 sram
[RAMPZ
] = z
>> 16;
1359 sram
[get_d (op
)] = sram
[read_word_post_inc (REGZ
) & SRAM_MASK
];
1364 sram
[get_d (op
)] = sram
[read_word_pre_dec (REGZ
) & SRAM_MASK
];
1369 sram
[get_d (op
)] = sram
[read_word_post_inc (REGX
) & SRAM_MASK
];
1374 sram
[get_d (op
)] = sram
[read_word_pre_dec (REGX
) & SRAM_MASK
];
1379 sram
[get_d (op
)] = sram
[read_word_post_inc (REGY
) & SRAM_MASK
];
1384 sram
[get_d (op
)] = sram
[read_word_pre_dec (REGY
) & SRAM_MASK
];
1389 sram
[read_word (REGX
) & SRAM_MASK
] = sram
[get_d (op
)];
1394 sram
[read_word_post_inc (REGX
) & SRAM_MASK
] = sram
[get_d (op
)];
1399 sram
[read_word_pre_dec (REGX
) & SRAM_MASK
] = sram
[get_d (op
)];
1404 sram
[read_word_post_inc (REGZ
) & SRAM_MASK
] = sram
[get_d (op
)];
1409 sram
[read_word_pre_dec (REGZ
) & SRAM_MASK
] = sram
[get_d (op
)];
1414 sram
[read_word_post_inc (REGY
) & SRAM_MASK
] = sram
[get_d (op
)];
1419 sram
[read_word_pre_dec (REGY
) & SRAM_MASK
] = sram
[get_d (op
)];
1424 sram
[read_word (REGY
) + flash
[ipc
].r
] = sram
[get_d (op
)];
1429 sram
[read_word (REGZ
) + flash
[ipc
].r
] = sram
[get_d (op
)];
1434 sram
[get_d (op
)] = sram
[read_word (REGZ
) + flash
[ipc
].r
];
1439 sram
[get_d (op
)] = sram
[read_word (REGY
) + flash
[ipc
].r
];
1444 sram
[get_d (op
)] = sram
[read_word (REGX
) & SRAM_MASK
];
1450 word wk
= get_k6 (op
);
1458 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1460 sram
[SREG
] |= SREG_Z
;
1462 sram
[SREG
] |= SREG_N
;
1463 if (wres
& ~wr
& 0x8000)
1464 sram
[SREG
] |= SREG_C
;
1465 if (~wres
& wr
& 0x8000)
1466 sram
[SREG
] |= SREG_V
;
1467 if (((~wres
& wr
) ^ wres
) & 0x8000)
1468 sram
[SREG
] |= SREG_S
;
1469 write_word (d
, wres
);
1476 word wk
= get_k6 (op
);
1484 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1486 sram
[SREG
] |= SREG_Z
;
1488 sram
[SREG
] |= SREG_N
;
1489 if (~wres
& wr
& 0x8000)
1490 sram
[SREG
] |= SREG_C
;
1491 if (wres
& ~wr
& 0x8000)
1492 sram
[SREG
] |= SREG_V
;
1493 if (((wres
& ~wr
) ^ wres
) & 0x8000)
1494 sram
[SREG
] |= SREG_S
;
1495 write_word (d
, wres
);
1501 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
, cpu
->pc
, sim_signalled
, SIM_SIGILL
);
1504 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
, cpu
->pc
, sim_signalled
, SIM_SIGILL
);
1509 sim_engine_run (SIM_DESC sd
,
1510 int next_cpu_nr
, /* ignore */
1511 int nr_cpus
, /* ignore */
1512 int siggnal
) /* ignore */
1516 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1518 cpu
= STATE_CPU (sd
, 0);
1523 if (sim_events_tick (sd
))
1524 sim_events_process (sd
);
1529 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
1533 if (addr
>= 0 && addr
< SRAM_VADDR
)
1535 while (size
> 0 && addr
< (MAX_AVR_FLASH
<< 1))
1537 word val
= flash
[addr
>> 1].op
;
1540 val
= (val
& 0xff) | (buffer
[0] << 8);
1542 val
= (val
& 0xff00) | buffer
[0];
1544 flash
[addr
>> 1].op
= val
;
1545 flash
[addr
>> 1].code
= OP_unknown
;
1550 return osize
- size
;
1552 else if (addr
>= SRAM_VADDR
&& addr
< SRAM_VADDR
+ MAX_AVR_SRAM
)
1555 if (addr
+ size
> MAX_AVR_SRAM
)
1556 size
= MAX_AVR_SRAM
- addr
;
1557 memcpy (sram
+ addr
, buffer
, size
);
1565 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
1569 if (addr
>= 0 && addr
< SRAM_VADDR
)
1571 while (size
> 0 && addr
< (MAX_AVR_FLASH
<< 1))
1573 word val
= flash
[addr
>> 1].op
;
1582 return osize
- size
;
1584 else if (addr
>= SRAM_VADDR
&& addr
< SRAM_VADDR
+ MAX_AVR_SRAM
)
1587 if (addr
+ size
> MAX_AVR_SRAM
)
1588 size
= MAX_AVR_SRAM
- addr
;
1589 memcpy (buffer
, sram
+ addr
, size
);
1595 memset (buffer
, 0, size
);
1601 avr_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1603 if (rn
< 32 && length
== 1)
1608 if (rn
== AVR_SREG_REGNUM
&& length
== 1)
1610 sram
[SREG
] = *memory
;
1613 if (rn
== AVR_SP_REGNUM
&& length
== 2)
1615 sram
[REG_SP
] = memory
[0];
1616 sram
[REG_SP
+ 1] = memory
[1];
1619 if (rn
== AVR_PC_REGNUM
&& length
== 4)
1621 cpu
->pc
= (memory
[0] >> 1) | (memory
[1] << 7)
1622 | (memory
[2] << 15) | (memory
[3] << 23);
1630 avr_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1632 if (rn
< 32 && length
== 1)
1637 if (rn
== AVR_SREG_REGNUM
&& length
== 1)
1639 *memory
= sram
[SREG
];
1642 if (rn
== AVR_SP_REGNUM
&& length
== 2)
1644 memory
[0] = sram
[REG_SP
];
1645 memory
[1] = sram
[REG_SP
+ 1];
1648 if (rn
== AVR_PC_REGNUM
&& length
== 4)
1650 memory
[0] = cpu
->pc
<< 1;
1651 memory
[1] = cpu
->pc
>> 7;
1652 memory
[2] = cpu
->pc
>> 15;
1653 memory
[3] = cpu
->pc
>> 23;
1660 avr_pc_get (sim_cpu
*cpu
)
1666 avr_pc_set (sim_cpu
*cpu
, sim_cia pc
)
1672 free_state (SIM_DESC sd
)
1674 if (STATE_MODULES (sd
) != NULL
)
1675 sim_module_uninstall (sd
);
1676 sim_cpu_free_all (sd
);
1677 sim_state_free (sd
);
1681 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
,
1682 struct bfd
*abfd
, char * const *argv
)
1685 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
1686 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1688 /* The cpu data is kept in a separately allocated chunk of memory. */
1689 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
1696 /* XXX: Only first core gets profiled ? */
1697 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1698 STATE_WATCHPOINTS (sd
)->pc
= &cpu
->pc
;
1699 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (cpu
->pc
);
1702 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
1708 /* The parser will print an error message for us, so we silently return. */
1709 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
1715 /* Check for/establish the a reference program image. */
1716 if (sim_analyze_program (sd
,
1717 (STATE_PROG_ARGV (sd
) != NULL
1718 ? *STATE_PROG_ARGV (sd
)
1719 : NULL
), abfd
) != SIM_RC_OK
)
1725 /* Configure/verify the target byte order and other runtime
1726 configuration options. */
1727 if (sim_config (sd
) != SIM_RC_OK
)
1729 sim_module_uninstall (sd
);
1733 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
1735 /* Uninstall the modules to avoid memory leaks,
1736 file descriptor leaks, etc. */
1737 sim_module_uninstall (sd
);
1741 /* CPU specific initialization. */
1742 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
1744 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
1746 CPU_REG_FETCH (cpu
) = avr_reg_fetch
;
1747 CPU_REG_STORE (cpu
) = avr_reg_store
;
1748 CPU_PC_FETCH (cpu
) = avr_pc_get
;
1749 CPU_PC_STORE (cpu
) = avr_pc_set
;
1752 /* Clear all the memory. */
1753 memset (sram
, 0, sizeof (sram
));
1754 memset (flash
, 0, sizeof (flash
));
1760 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
1761 char * const *argv
, char * const *env
)
1763 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1768 addr
= bfd_get_start_address (abfd
);
1771 sim_pc_set (cpu
, addr
);
1774 sd
->avr_pc22
= (bfd_get_mach (abfd
) >= bfd_mach_avr6
);
This page took 0.08943 seconds and 4 git commands to generate.