1 /* Simulator for Atmel's AVR core.
2 Copyright (C) 2009-2019 Free Software Foundation, Inc.
3 Written by Tristan Gingold, AdaCore.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "libiberty.h"
27 #include "gdb/remote-sim.h"
31 #include "sim-options.h"
33 /* As AVR is a 8/16 bits processor, define handy types. */
34 typedef unsigned short int word
;
35 typedef signed short int sword
;
36 typedef unsigned char byte
;
37 typedef signed char sbyte
;
39 /* Max size of I space (which is always flash on avr). */
40 #define MAX_AVR_FLASH (128 * 1024)
41 #define PC_MASK (MAX_AVR_FLASH - 1)
43 /* Mac size of D space. */
44 #define MAX_AVR_SRAM (64 * 1024)
45 #define SRAM_MASK (MAX_AVR_SRAM - 1)
47 /* D space offset in ELF file. */
48 #define SRAM_VADDR 0x800000
50 /* Simulator specific ports. */
51 #define STDIO_PORT 0x52
52 #define EXIT_PORT 0x4F
53 #define ABORT_PORT 0x49
55 /* GDB defined register numbers. */
56 #define AVR_SREG_REGNUM 32
57 #define AVR_SP_REGNUM 33
58 #define AVR_PC_REGNUM 34
60 /* Memory mapped registers. */
72 /* Sreg (status) bits. */
82 /* In order to speed up emulation we use a simple approach:
83 a code is associated with each instruction. The pre-decoding occurs
84 usually once when the instruction is first seen.
85 This works well because I&D spaces are separated.
87 Missing opcodes: sleep, spm, wdr (as they are mmcu dependent).
91 /* Opcode not yet decoded. */
197 /* 2 words opcodes. */
198 #define OP_2words OP_jmp
207 /* The insn (16 bits). */
210 /* Pre-decoding code. */
211 enum avr_opcode code
: 8;
212 /* One byte of additional information. */
217 /* TODO: Should be moved to SIM_CPU. */
218 static struct avr_insn_cell flash
[MAX_AVR_FLASH
];
219 static byte sram
[MAX_AVR_SRAM
];
221 /* Sign extend a value. */
222 static int sign_ext (word val
, int nb_bits
)
224 if (val
& (1 << (nb_bits
- 1)))
225 return val
| -(1 << nb_bits
);
229 /* Insn field extractors. */
231 /* Extract xxxx_xxxRx_xxxx_RRRR. */
232 static inline byte
get_r (word op
)
234 return (op
& 0xf) | ((op
>> 5) & 0x10);
237 /* Extract xxxx_xxxxx_xxxx_RRRR. */
238 static inline byte
get_r16 (word op
)
240 return 16 + (op
& 0xf);
243 /* Extract xxxx_xxxxx_xxxx_xRRR. */
244 static inline byte
get_r16_23 (word op
)
246 return 16 + (op
& 0x7);
249 /* Extract xxxx_xxxD_DDDD_xxxx. */
250 static inline byte
get_d (word op
)
252 return (op
>> 4) & 0x1f;
255 /* Extract xxxx_xxxx_DDDD_xxxx. */
256 static inline byte
get_d16 (word op
)
258 return 16 + ((op
>> 4) & 0x0f);
261 /* Extract xxxx_xxxx_xDDD_xxxx. */
262 static inline byte
get_d16_23 (word op
)
264 return 16 + ((op
>> 4) & 0x07);
267 /* Extract xxxx_xAAx_xxxx_AAAA. */
268 static inline byte
get_A (word op
)
270 return (op
& 0x0f) | ((op
& 0x600) >> 5);
273 /* Extract xxxx_xxxx_AAAA_Axxx. */
274 static inline byte
get_biA (word op
)
276 return (op
>> 3) & 0x1f;
279 /* Extract xxxx_KKKK_xxxx_KKKK. */
280 static inline byte
get_K (word op
)
282 return (op
& 0xf) | ((op
& 0xf00) >> 4);
285 /* Extract xxxx_xxKK_KKKK_Kxxx. */
286 static inline int get_k (word op
)
288 return sign_ext ((op
& 0x3f8) >> 3, 7);
291 /* Extract xxxx_xxxx_xxDD_xxxx. */
292 static inline byte
get_d24 (word op
)
294 return 24 + ((op
>> 3) & 6);
297 /* Extract xxxx_xxxx_KKxx_KKKK. */
298 static inline byte
get_k6 (word op
)
300 return (op
& 0xf) | ((op
>> 2) & 0x30);
303 /* Extract xxQx_QQxx_xxxx_xQQQ. */
304 static inline byte
get_q (word op
)
306 return (op
& 7) | ((op
>> 7) & 0x18)| ((op
>> 8) & 0x20);
309 /* Extract xxxx_xxxx_xxxx_xBBB. */
310 static inline byte
get_b (word op
)
315 /* AVR is little endian. */
317 read_word (unsigned int addr
)
319 return sram
[addr
] | (sram
[addr
+ 1] << 8);
323 write_word (unsigned int addr
, word w
)
326 sram
[addr
+ 1] = w
>> 8;
330 read_word_post_inc (unsigned int addr
)
332 word v
= read_word (addr
);
333 write_word (addr
, v
+ 1);
338 read_word_pre_dec (unsigned int addr
)
340 word v
= read_word (addr
) - 1;
341 write_word (addr
, v
);
346 update_flags_logic (byte res
)
348 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
);
350 sram
[SREG
] |= SREG_Z
;
352 sram
[SREG
] |= SREG_N
| SREG_S
;
356 update_flags_add (byte r
, byte a
, byte b
)
360 sram
[SREG
] &= ~(SREG_H
| SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
362 sram
[SREG
] |= SREG_N
;
363 carry
= (a
& b
) | (a
& ~r
) | (b
& ~r
);
365 sram
[SREG
] |= SREG_H
;
367 sram
[SREG
] |= SREG_C
;
368 if (((a
& b
& ~r
) | (~a
& ~b
& r
)) & 0x80)
369 sram
[SREG
] |= SREG_V
;
370 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_V
))
371 sram
[SREG
] |= SREG_S
;
373 sram
[SREG
] |= SREG_Z
;
376 static void update_flags_sub (byte r
, byte a
, byte b
)
380 sram
[SREG
] &= ~(SREG_H
| SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
382 sram
[SREG
] |= SREG_N
;
383 carry
= (~a
& b
) | (b
& r
) | (r
& ~a
);
385 sram
[SREG
] |= SREG_H
;
387 sram
[SREG
] |= SREG_C
;
388 if (((a
& ~b
& ~r
) | (~a
& b
& r
)) & 0x80)
389 sram
[SREG
] |= SREG_V
;
390 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_V
))
391 sram
[SREG
] |= SREG_S
;
392 /* Note: Z is not set. */
395 static enum avr_opcode
396 decode (unsigned int pc
)
398 word op1
= flash
[pc
].op
;
400 switch ((op1
>> 12) & 0x0f)
403 switch ((op1
>> 10) & 0x3)
406 switch ((op1
>> 8) & 0x3)
436 flash
[pc
].r
= SREG_C
;
444 switch ((op1
>> 10) & 0x3)
454 flash
[pc
].r
= SREG_C
;
459 switch ((op1
>> 10) & 0x3)
487 flash
[pc
].r
= get_q (op1
);
492 flash
[pc
].r
= get_q (op1
);
500 flash
[pc
].r
= get_q (op1
);
505 flash
[pc
].r
= get_q (op1
);
511 switch ((op1
>> 8) & 0xf)
515 switch ((op1
>> 0) & 0xf)
530 return OP_elpm_inc_Z
;
547 switch ((op1
>> 0) & 0xf)
589 case 0x8: /* 9[45]x8 */
590 switch ((op1
>> 4) & 0x1f)
624 case 0x9: /* 9[45]x9 */
625 switch ((op1
>> 4) & 0x1f)
643 flash
[pc
].r
= ((op1
& 0x1f0) >> 3) | (op1
& 1);
647 flash
[pc
].r
= ((op1
& 0x1f0) >> 3) | (op1
& 1);
671 flash
[pc
].r
= get_A (op1
);
672 if (((op1
>> 11) & 1) == 0)
683 switch ((op1
>> 9) & 7)
687 flash
[pc
].r
= 1 << (op1
& 7);
691 flash
[pc
].r
= 1 << (op1
& 7);
696 flash
[pc
].r
= 1 << (op1
& 7);
703 flash
[pc
].r
= 1 << (op1
& 7);
710 flash
[pc
].r
= 1 << (op1
& 7);
717 flash
[pc
].r
= 1 << (op1
& 7);
728 do_call (SIM_CPU
*cpu
, unsigned int npc
)
730 SIM_DESC sd
= CPU_STATE (cpu
);
731 unsigned int sp
= read_word (REG_SP
);
734 sram
[sp
--] = cpu
->pc
;
735 sram
[sp
--] = cpu
->pc
>> 8;
738 sram
[sp
--] = cpu
->pc
>> 16;
741 write_word (REG_SP
, sp
);
742 cpu
->pc
= npc
& PC_MASK
;
747 get_insn_length (unsigned int p
)
749 if (flash
[p
].code
== OP_unknown
)
750 flash
[p
].code
= decode(p
);
751 if (flash
[p
].code
>= OP_2words
)
760 return (sram
[RAMPZ
] << 16) | (sram
[REGZ_HI
] << 8) | sram
[REGZ_LO
];
764 get_lpm (unsigned int addr
)
768 w
= flash
[(addr
>> 1) & PC_MASK
].op
;
775 gen_mul (SIM_CPU
*cpu
, unsigned int res
)
778 sram
[SREG
] &= ~(SREG_Z
| SREG_C
);
780 sram
[SREG
] |= SREG_Z
;
782 sram
[SREG
] |= SREG_C
;
787 step_once (SIM_CPU
*cpu
)
797 code
= flash
[cpu
->pc
].code
;
798 op
= flash
[cpu
->pc
].op
;
801 if (tracing
&& code
!= OP_unknown
)
807 sim_cb_eprintf (callback
, "R00-07:");
808 for (i
= 0; i
< 8; i
++)
809 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
810 sim_cb_eprintf (callback
, " -");
811 for (i
= 8; i
< 16; i
++)
812 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
813 sim_cb_eprintf (callback
, " SP: %02x %02x",
814 sram
[REG_SP
+ 1], sram
[REG_SP
]);
815 sim_cb_eprintf (callback
, "\n");
816 sim_cb_eprintf (callback
, "R16-31:");
817 for (i
= 16; i
< 24; i
++)
818 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
819 sim_cb_eprintf (callback
, " -");
820 for (i
= 24; i
< 32; i
++)
821 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
822 sim_cb_eprintf (callback
, " ");
824 for (i
= 0; i
< 8; i
++)
825 sim_cb_eprintf (callback
, "%c",
826 flags
& (0x80 >> i
) ? "ITHSVNZC"[i
] : '-');
827 sim_cb_eprintf (callback
, "\n");
831 sim_cb_eprintf (callback
, "%06x: %04x\n", 2 * cpu
->pc
, flash
[cpu
->pc
].op
);
834 sim_cb_eprintf (callback
, "pc=0x%06x insn=0x%04x code=%d r=%d\n",
835 2 * cpu
->pc
, flash
[cpu
->pc
].op
, code
, flash
[cpu
->pc
].r
);
836 disassemble_insn (CPU_STATE (cpu
), cpu
->pc
);
837 sim_cb_eprintf (callback
, "\n");
843 cpu
->pc
= (cpu
->pc
+ 1) & PC_MASK
;
849 flash
[ipc
].code
= decode(ipc
);
858 /* 2 words instruction, but we don't care about the pc. */
859 cpu
->pc
= ((flash
[ipc
].r
<< 16) | flash
[ipc
+ 1].op
) & PC_MASK
;
864 cpu
->pc
= ((sram
[EIND
] << 16) | read_word (REGZ
)) & PC_MASK
;
869 cpu
->pc
= read_word (REGZ
) & PC_MASK
;
874 /* 2 words instruction. */
876 do_call (cpu
, (flash
[ipc
].r
<< 16) | flash
[ipc
+ 1].op
);
880 do_call (cpu
, (sram
[EIND
] << 16) | read_word (REGZ
));
884 do_call (cpu
, read_word (REGZ
));
888 do_call (cpu
, cpu
->pc
+ sign_ext (op
& 0xfff, 12));
892 sram
[SREG
] |= SREG_I
;
896 SIM_DESC sd
= CPU_STATE (cpu
);
897 unsigned int sp
= read_word (REG_SP
);
900 cpu
->pc
= sram
[++sp
] << 16;
905 cpu
->pc
|= sram
[++sp
] << 8;
906 cpu
->pc
|= sram
[++sp
];
907 write_word (REG_SP
, sp
);
913 /* Stop on this address. */
914 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
, ipc
, sim_stopped
, SIM_SIGTRAP
);
920 if (sram
[SREG
] & SREG_T
)
927 if (sram
[get_d (op
)] & flash
[ipc
].r
)
928 sram
[SREG
] |= SREG_T
;
930 sram
[SREG
] &= ~SREG_T
;
935 if (((sram
[get_d (op
)] & flash
[ipc
].r
) == 0) ^ ((op
& 0x0200) != 0))
937 int l
= get_insn_length (cpu
->pc
);
945 unsigned int sp
= read_word (REG_SP
);
946 sram
[sp
--] = sram
[get_d (op
)];
947 write_word (REG_SP
, sp
);
954 unsigned int sp
= read_word (REG_SP
);
955 sram
[get_d (op
)] = sram
[++sp
];
956 write_word (REG_SP
, sp
);
962 sram
[SREG
] &= ~(1 << ((op
>> 4) & 0x7));
966 sram
[SREG
] |= 1 << ((op
>> 4) & 0x7);
970 cpu
->pc
= (cpu
->pc
+ sign_ext (op
& 0xfff, 12)) & PC_MASK
;
976 res
= sram
[d
] ^ sram
[get_r (op
)];
978 update_flags_logic (res
);
983 res
= sram
[d
] & sram
[get_r (op
)];
985 update_flags_logic (res
);
990 res
= sram
[d
] & get_K (op
);
992 update_flags_logic (res
);
997 res
= sram
[d
] | sram
[get_r (op
)];
999 update_flags_logic (res
);
1004 res
= sram
[d
] | get_K (op
);
1006 update_flags_logic (res
);
1013 update_flags_logic (res
);
1014 sram
[SREG
] |= SREG_C
;
1020 sram
[d
] = (vd
>> 4) | (vd
<< 4);
1028 sram
[SREG
] &= ~(SREG_H
| SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1030 sram
[SREG
] |= SREG_Z
;
1032 sram
[SREG
] |= SREG_C
;
1034 sram
[SREG
] |= SREG_V
| SREG_N
;
1035 else if (res
& 0x80)
1036 sram
[SREG
] |= SREG_N
| SREG_S
;
1037 if ((res
| vd
) & 0x08)
1038 sram
[SREG
] |= SREG_H
;
1045 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
);
1047 sram
[SREG
] |= SREG_V
| SREG_N
;
1048 else if (res
& 0x80)
1049 sram
[SREG
] |= SREG_N
| SREG_S
;
1051 sram
[SREG
] |= SREG_Z
;
1058 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
);
1060 sram
[SREG
] |= SREG_V
| SREG_S
;
1061 else if (res
& 0x80)
1062 sram
[SREG
] |= SREG_N
| SREG_S
;
1064 sram
[SREG
] |= SREG_Z
;
1071 res
= (vd
>> 1) | (vd
& flash
[ipc
].r
);
1073 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1075 sram
[SREG
] |= SREG_C
| SREG_S
;
1077 sram
[SREG
] |= SREG_N
;
1078 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_C
))
1079 sram
[SREG
] |= SREG_V
;
1081 sram
[SREG
] |= SREG_Z
;
1087 res
= vd
>> 1 | (sram
[SREG
] << 7);
1089 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1091 sram
[SREG
] |= SREG_C
| SREG_S
;
1093 sram
[SREG
] |= SREG_N
;
1094 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_C
))
1095 sram
[SREG
] |= SREG_V
;
1097 sram
[SREG
] |= SREG_Z
;
1101 gen_mul (cpu
, (word
)sram
[get_r (op
)] * (word
)sram
[get_d (op
)]);
1105 gen_mul (cpu
, (sword
)(sbyte
)sram
[get_r16 (op
)]
1106 * (sword
)(sbyte
)sram
[get_d16 (op
)]);
1110 gen_mul (cpu
, (sword
)(word
)sram
[get_r16_23 (op
)]
1111 * (sword
)(sbyte
)sram
[get_d16_23 (op
)]);
1115 gen_mul (cpu
, ((word
)sram
[get_r16_23 (op
)]
1116 * (word
)sram
[get_d16_23 (op
)]) << 1);
1120 gen_mul (cpu
, ((sword
)(sbyte
)sram
[get_r16_23 (op
)]
1121 * (sword
)(sbyte
)sram
[get_d16_23 (op
)]) << 1);
1125 gen_mul (cpu
, ((sword
)(word
)sram
[get_r16_23 (op
)]
1126 * (sword
)(sbyte
)sram
[get_d16_23 (op
)]) << 1);
1131 r
= sram
[get_r (op
)];
1134 res
= r
+ vd
+ (sram
[SREG
] & flash
[ipc
].r
);
1136 update_flags_add (res
, vd
, r
);
1142 r
= sram
[get_r (op
)];
1145 update_flags_sub (res
, vd
, r
);
1147 sram
[SREG
] |= SREG_Z
;
1152 byte old
= sram
[SREG
];
1155 r
= sram
[get_r (op
)];
1156 res
= vd
- r
- (old
& SREG_C
);
1158 update_flags_sub (res
, vd
, r
);
1159 if (res
== 0 && (old
& SREG_Z
))
1160 sram
[SREG
] |= SREG_Z
;
1170 update_flags_sub (res
, vd
, r
);
1172 sram
[SREG
] |= SREG_Z
;
1177 byte old
= sram
[SREG
];
1182 res
= vd
- r
- (old
& SREG_C
);
1184 update_flags_sub (res
, vd
, r
);
1185 if (res
== 0 && (old
& SREG_Z
))
1186 sram
[SREG
] |= SREG_Z
;
1191 sram
[get_d (op
)] = sram
[get_r (op
)];
1195 d
= (op
& 0xf0) >> 3;
1196 r
= (op
& 0x0f) << 1;
1198 sram
[d
+ 1] = sram
[r
+ 1];
1202 d
= get_A (op
) + 0x20;
1203 res
= sram
[get_d (op
)];
1205 if (d
== STDIO_PORT
)
1207 else if (d
== EXIT_PORT
)
1208 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
, cpu
->pc
, sim_exited
, 0);
1209 else if (d
== ABORT_PORT
)
1210 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
, cpu
->pc
, sim_exited
, 1);
1214 d
= get_A (op
) + 0x20;
1215 sram
[get_d (op
)] = sram
[d
];
1219 d
= get_biA (op
) + 0x20;
1220 sram
[d
] &= ~(1 << get_b(op
));
1224 d
= get_biA (op
) + 0x20;
1225 sram
[d
] |= 1 << get_b(op
);
1229 if (!(sram
[get_biA (op
) + 0x20] & 1 << get_b(op
)))
1231 int l
= get_insn_length (cpu
->pc
);
1238 if (sram
[get_biA (op
) + 0x20] & 1 << get_b(op
))
1240 int l
= get_insn_length (cpu
->pc
);
1253 sram
[get_d (op
)] = sram
[flash
[cpu
->pc
].op
];
1259 sram
[flash
[cpu
->pc
].op
] = sram
[get_d (op
)];
1265 if (sram
[get_r (op
)] == sram
[get_d (op
)])
1267 int l
= get_insn_length (cpu
->pc
);
1274 r
= sram
[get_r (op
)];
1275 d
= sram
[get_d (op
)];
1277 update_flags_sub (res
, d
, r
);
1279 sram
[SREG
] |= SREG_Z
;
1284 d
= sram
[get_d16 (op
)];
1286 update_flags_sub (res
, d
, r
);
1288 sram
[SREG
] |= SREG_Z
;
1293 byte old
= sram
[SREG
];
1294 d
= sram
[get_d (op
)];
1295 r
= sram
[get_r (op
)];
1296 res
= d
- r
- (old
& SREG_C
);
1297 update_flags_sub (res
, d
, r
);
1298 if (res
== 0 && (old
& SREG_Z
))
1299 sram
[SREG
] |= SREG_Z
;
1304 if (!(sram
[SREG
] & flash
[ipc
].r
))
1306 cpu
->pc
= (cpu
->pc
+ get_k (op
)) & PC_MASK
;
1312 if (sram
[SREG
] & flash
[ipc
].r
)
1314 cpu
->pc
= (cpu
->pc
+ get_k (op
)) & PC_MASK
;
1320 sram
[0] = get_lpm (read_word (REGZ
));
1325 sram
[get_d (op
)] = get_lpm (read_word (REGZ
));
1330 sram
[get_d (op
)] = get_lpm (read_word_post_inc (REGZ
));
1335 sram
[0] = get_lpm (get_z ());
1340 sram
[get_d (op
)] = get_lpm (get_z ());
1346 unsigned int z
= get_z ();
1348 sram
[get_d (op
)] = get_lpm (z
);
1351 sram
[REGZ_HI
] = z
>> 8;
1352 sram
[RAMPZ
] = z
>> 16;
1358 sram
[get_d (op
)] = sram
[read_word_post_inc (REGZ
) & SRAM_MASK
];
1363 sram
[get_d (op
)] = sram
[read_word_pre_dec (REGZ
) & SRAM_MASK
];
1368 sram
[get_d (op
)] = sram
[read_word_post_inc (REGX
) & SRAM_MASK
];
1373 sram
[get_d (op
)] = sram
[read_word_pre_dec (REGX
) & SRAM_MASK
];
1378 sram
[get_d (op
)] = sram
[read_word_post_inc (REGY
) & SRAM_MASK
];
1383 sram
[get_d (op
)] = sram
[read_word_pre_dec (REGY
) & SRAM_MASK
];
1388 sram
[read_word (REGX
) & SRAM_MASK
] = sram
[get_d (op
)];
1393 sram
[read_word_post_inc (REGX
) & SRAM_MASK
] = sram
[get_d (op
)];
1398 sram
[read_word_pre_dec (REGX
) & SRAM_MASK
] = sram
[get_d (op
)];
1403 sram
[read_word_post_inc (REGZ
) & SRAM_MASK
] = sram
[get_d (op
)];
1408 sram
[read_word_pre_dec (REGZ
) & SRAM_MASK
] = sram
[get_d (op
)];
1413 sram
[read_word_post_inc (REGY
) & SRAM_MASK
] = sram
[get_d (op
)];
1418 sram
[read_word_pre_dec (REGY
) & SRAM_MASK
] = sram
[get_d (op
)];
1423 sram
[read_word (REGY
) + flash
[ipc
].r
] = sram
[get_d (op
)];
1428 sram
[read_word (REGZ
) + flash
[ipc
].r
] = sram
[get_d (op
)];
1433 sram
[get_d (op
)] = sram
[read_word (REGZ
) + flash
[ipc
].r
];
1438 sram
[get_d (op
)] = sram
[read_word (REGY
) + flash
[ipc
].r
];
1443 sram
[get_d (op
)] = sram
[read_word (REGX
) & SRAM_MASK
];
1449 word wk
= get_k6 (op
);
1457 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1459 sram
[SREG
] |= SREG_Z
;
1461 sram
[SREG
] |= SREG_N
;
1462 if (wres
& ~wr
& 0x8000)
1463 sram
[SREG
] |= SREG_C
;
1464 if (~wres
& wr
& 0x8000)
1465 sram
[SREG
] |= SREG_V
;
1466 if (((~wres
& wr
) ^ wres
) & 0x8000)
1467 sram
[SREG
] |= SREG_S
;
1468 write_word (d
, wres
);
1475 word wk
= get_k6 (op
);
1483 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1485 sram
[SREG
] |= SREG_Z
;
1487 sram
[SREG
] |= SREG_N
;
1488 if (~wres
& wr
& 0x8000)
1489 sram
[SREG
] |= SREG_C
;
1490 if (wres
& ~wr
& 0x8000)
1491 sram
[SREG
] |= SREG_V
;
1492 if (((wres
& ~wr
) ^ wres
) & 0x8000)
1493 sram
[SREG
] |= SREG_S
;
1494 write_word (d
, wres
);
1500 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
, cpu
->pc
, sim_signalled
, SIM_SIGILL
);
1503 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
, cpu
->pc
, sim_signalled
, SIM_SIGILL
);
1508 sim_engine_run (SIM_DESC sd
,
1509 int next_cpu_nr
, /* ignore */
1510 int nr_cpus
, /* ignore */
1511 int siggnal
) /* ignore */
1515 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1517 cpu
= STATE_CPU (sd
, 0);
1522 if (sim_events_tick (sd
))
1523 sim_events_process (sd
);
1528 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
1532 if (addr
>= 0 && addr
< SRAM_VADDR
)
1534 while (size
> 0 && addr
< (MAX_AVR_FLASH
<< 1))
1536 word val
= flash
[addr
>> 1].op
;
1539 val
= (val
& 0xff) | (buffer
[0] << 8);
1541 val
= (val
& 0xff00) | buffer
[0];
1543 flash
[addr
>> 1].op
= val
;
1544 flash
[addr
>> 1].code
= OP_unknown
;
1549 return osize
- size
;
1551 else if (addr
>= SRAM_VADDR
&& addr
< SRAM_VADDR
+ MAX_AVR_SRAM
)
1554 if (addr
+ size
> MAX_AVR_SRAM
)
1555 size
= MAX_AVR_SRAM
- addr
;
1556 memcpy (sram
+ addr
, buffer
, size
);
1564 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
1568 if (addr
>= 0 && addr
< SRAM_VADDR
)
1570 while (size
> 0 && addr
< (MAX_AVR_FLASH
<< 1))
1572 word val
= flash
[addr
>> 1].op
;
1581 return osize
- size
;
1583 else if (addr
>= SRAM_VADDR
&& addr
< SRAM_VADDR
+ MAX_AVR_SRAM
)
1586 if (addr
+ size
> MAX_AVR_SRAM
)
1587 size
= MAX_AVR_SRAM
- addr
;
1588 memcpy (buffer
, sram
+ addr
, size
);
1594 memset (buffer
, 0, size
);
1600 avr_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1602 if (rn
< 32 && length
== 1)
1607 if (rn
== AVR_SREG_REGNUM
&& length
== 1)
1609 sram
[SREG
] = *memory
;
1612 if (rn
== AVR_SP_REGNUM
&& length
== 2)
1614 sram
[REG_SP
] = memory
[0];
1615 sram
[REG_SP
+ 1] = memory
[1];
1618 if (rn
== AVR_PC_REGNUM
&& length
== 4)
1620 cpu
->pc
= (memory
[0] >> 1) | (memory
[1] << 7)
1621 | (memory
[2] << 15) | (memory
[3] << 23);
1629 avr_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1631 if (rn
< 32 && length
== 1)
1636 if (rn
== AVR_SREG_REGNUM
&& length
== 1)
1638 *memory
= sram
[SREG
];
1641 if (rn
== AVR_SP_REGNUM
&& length
== 2)
1643 memory
[0] = sram
[REG_SP
];
1644 memory
[1] = sram
[REG_SP
+ 1];
1647 if (rn
== AVR_PC_REGNUM
&& length
== 4)
1649 memory
[0] = cpu
->pc
<< 1;
1650 memory
[1] = cpu
->pc
>> 7;
1651 memory
[2] = cpu
->pc
>> 15;
1652 memory
[3] = cpu
->pc
>> 23;
1659 avr_pc_get (sim_cpu
*cpu
)
1665 avr_pc_set (sim_cpu
*cpu
, sim_cia pc
)
1671 free_state (SIM_DESC sd
)
1673 if (STATE_MODULES (sd
) != NULL
)
1674 sim_module_uninstall (sd
);
1675 sim_cpu_free_all (sd
);
1676 sim_state_free (sd
);
1680 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
,
1681 struct bfd
*abfd
, char * const *argv
)
1684 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
1685 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1687 /* The cpu data is kept in a separately allocated chunk of memory. */
1688 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
1695 /* XXX: Only first core gets profiled ? */
1696 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1697 STATE_WATCHPOINTS (sd
)->pc
= &cpu
->pc
;
1698 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (cpu
->pc
);
1701 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
1707 /* The parser will print an error message for us, so we silently return. */
1708 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
1714 /* Check for/establish the a reference program image. */
1715 if (sim_analyze_program (sd
,
1716 (STATE_PROG_ARGV (sd
) != NULL
1717 ? *STATE_PROG_ARGV (sd
)
1718 : NULL
), abfd
) != SIM_RC_OK
)
1724 /* Configure/verify the target byte order and other runtime
1725 configuration options. */
1726 if (sim_config (sd
) != SIM_RC_OK
)
1728 sim_module_uninstall (sd
);
1732 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
1734 /* Uninstall the modules to avoid memory leaks,
1735 file descriptor leaks, etc. */
1736 sim_module_uninstall (sd
);
1740 /* CPU specific initialization. */
1741 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
1743 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
1745 CPU_REG_FETCH (cpu
) = avr_reg_fetch
;
1746 CPU_REG_STORE (cpu
) = avr_reg_store
;
1747 CPU_PC_FETCH (cpu
) = avr_pc_get
;
1748 CPU_PC_STORE (cpu
) = avr_pc_set
;
1751 /* Clear all the memory. */
1752 memset (sram
, 0, sizeof (sram
));
1753 memset (flash
, 0, sizeof (flash
));
1759 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
1760 char * const *argv
, char * const *env
)
1762 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1767 addr
= bfd_get_start_address (abfd
);
1770 sim_pc_set (cpu
, addr
);
1773 sd
->avr_pc22
= (bfd_get_mach (abfd
) >= bfd_mach_avr6
);
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