1 /* Simulator for Atmel's AVR core.
2 Copyright (C) 2009-2021 Free Software Foundation, Inc.
3 Written by Tristan Gingold, AdaCore.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "libiberty.h"
26 #include "gdb/remote-sim.h"
30 #include "sim-options.h"
32 /* As AVR is a 8/16 bits processor, define handy types. */
33 typedef unsigned short int word
;
34 typedef signed short int sword
;
35 typedef unsigned char byte
;
36 typedef signed char sbyte
;
38 /* Max size of I space (which is always flash on avr). */
39 #define MAX_AVR_FLASH (128 * 1024)
40 #define PC_MASK (MAX_AVR_FLASH - 1)
42 /* Mac size of D space. */
43 #define MAX_AVR_SRAM (64 * 1024)
44 #define SRAM_MASK (MAX_AVR_SRAM - 1)
46 /* D space offset in ELF file. */
47 #define SRAM_VADDR 0x800000
49 /* Simulator specific ports. */
50 #define STDIO_PORT 0x52
51 #define EXIT_PORT 0x4F
52 #define ABORT_PORT 0x49
54 /* GDB defined register numbers. */
55 #define AVR_SREG_REGNUM 32
56 #define AVR_SP_REGNUM 33
57 #define AVR_PC_REGNUM 34
59 /* Memory mapped registers. */
71 /* Sreg (status) bits. */
81 /* In order to speed up emulation we use a simple approach:
82 a code is associated with each instruction. The pre-decoding occurs
83 usually once when the instruction is first seen.
84 This works well because I&D spaces are separated.
86 Missing opcodes: sleep, spm, wdr (as they are mmcu dependent).
90 /* Opcode not yet decoded. */
196 /* 2 words opcodes. */
197 #define OP_2words OP_jmp
206 /* The insn (16 bits). */
209 /* Pre-decoding code. */
210 enum avr_opcode code
: 8;
211 /* One byte of additional information. */
216 /* TODO: Should be moved to SIM_CPU. */
217 static struct avr_insn_cell flash
[MAX_AVR_FLASH
];
218 static byte sram
[MAX_AVR_SRAM
];
220 /* Sign extend a value. */
221 static int sign_ext (word val
, int nb_bits
)
223 if (val
& (1 << (nb_bits
- 1)))
224 return val
| -(1 << nb_bits
);
228 /* Insn field extractors. */
230 /* Extract xxxx_xxxRx_xxxx_RRRR. */
231 static inline byte
get_r (word op
)
233 return (op
& 0xf) | ((op
>> 5) & 0x10);
236 /* Extract xxxx_xxxxx_xxxx_RRRR. */
237 static inline byte
get_r16 (word op
)
239 return 16 + (op
& 0xf);
242 /* Extract xxxx_xxxxx_xxxx_xRRR. */
243 static inline byte
get_r16_23 (word op
)
245 return 16 + (op
& 0x7);
248 /* Extract xxxx_xxxD_DDDD_xxxx. */
249 static inline byte
get_d (word op
)
251 return (op
>> 4) & 0x1f;
254 /* Extract xxxx_xxxx_DDDD_xxxx. */
255 static inline byte
get_d16 (word op
)
257 return 16 + ((op
>> 4) & 0x0f);
260 /* Extract xxxx_xxxx_xDDD_xxxx. */
261 static inline byte
get_d16_23 (word op
)
263 return 16 + ((op
>> 4) & 0x07);
266 /* Extract xxxx_xAAx_xxxx_AAAA. */
267 static inline byte
get_A (word op
)
269 return (op
& 0x0f) | ((op
& 0x600) >> 5);
272 /* Extract xxxx_xxxx_AAAA_Axxx. */
273 static inline byte
get_biA (word op
)
275 return (op
>> 3) & 0x1f;
278 /* Extract xxxx_KKKK_xxxx_KKKK. */
279 static inline byte
get_K (word op
)
281 return (op
& 0xf) | ((op
& 0xf00) >> 4);
284 /* Extract xxxx_xxKK_KKKK_Kxxx. */
285 static inline int get_k (word op
)
287 return sign_ext ((op
& 0x3f8) >> 3, 7);
290 /* Extract xxxx_xxxx_xxDD_xxxx. */
291 static inline byte
get_d24 (word op
)
293 return 24 + ((op
>> 3) & 6);
296 /* Extract xxxx_xxxx_KKxx_KKKK. */
297 static inline byte
get_k6 (word op
)
299 return (op
& 0xf) | ((op
>> 2) & 0x30);
302 /* Extract xxQx_QQxx_xxxx_xQQQ. */
303 static inline byte
get_q (word op
)
305 return (op
& 7) | ((op
>> 7) & 0x18)| ((op
>> 8) & 0x20);
308 /* Extract xxxx_xxxx_xxxx_xBBB. */
309 static inline byte
get_b (word op
)
314 /* AVR is little endian. */
316 read_word (unsigned int addr
)
318 return sram
[addr
] | (sram
[addr
+ 1] << 8);
322 write_word (unsigned int addr
, word w
)
325 sram
[addr
+ 1] = w
>> 8;
329 read_word_post_inc (unsigned int addr
)
331 word v
= read_word (addr
);
332 write_word (addr
, v
+ 1);
337 read_word_pre_dec (unsigned int addr
)
339 word v
= read_word (addr
) - 1;
340 write_word (addr
, v
);
345 update_flags_logic (byte res
)
347 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
);
349 sram
[SREG
] |= SREG_Z
;
351 sram
[SREG
] |= SREG_N
| SREG_S
;
355 update_flags_add (byte r
, byte a
, byte b
)
359 sram
[SREG
] &= ~(SREG_H
| SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
361 sram
[SREG
] |= SREG_N
;
362 carry
= (a
& b
) | (a
& ~r
) | (b
& ~r
);
364 sram
[SREG
] |= SREG_H
;
366 sram
[SREG
] |= SREG_C
;
367 if (((a
& b
& ~r
) | (~a
& ~b
& r
)) & 0x80)
368 sram
[SREG
] |= SREG_V
;
369 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_V
))
370 sram
[SREG
] |= SREG_S
;
372 sram
[SREG
] |= SREG_Z
;
375 static void update_flags_sub (byte r
, byte a
, byte b
)
379 sram
[SREG
] &= ~(SREG_H
| SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
381 sram
[SREG
] |= SREG_N
;
382 carry
= (~a
& b
) | (b
& r
) | (r
& ~a
);
384 sram
[SREG
] |= SREG_H
;
386 sram
[SREG
] |= SREG_C
;
387 if (((a
& ~b
& ~r
) | (~a
& b
& r
)) & 0x80)
388 sram
[SREG
] |= SREG_V
;
389 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_V
))
390 sram
[SREG
] |= SREG_S
;
391 /* Note: Z is not set. */
394 static enum avr_opcode
395 decode (unsigned int pc
)
397 word op1
= flash
[pc
].op
;
399 switch ((op1
>> 12) & 0x0f)
402 switch ((op1
>> 10) & 0x3)
405 switch ((op1
>> 8) & 0x3)
435 flash
[pc
].r
= SREG_C
;
443 switch ((op1
>> 10) & 0x3)
453 flash
[pc
].r
= SREG_C
;
458 switch ((op1
>> 10) & 0x3)
486 flash
[pc
].r
= get_q (op1
);
491 flash
[pc
].r
= get_q (op1
);
499 flash
[pc
].r
= get_q (op1
);
504 flash
[pc
].r
= get_q (op1
);
510 switch ((op1
>> 8) & 0xf)
514 switch ((op1
>> 0) & 0xf)
529 return OP_elpm_inc_Z
;
546 switch ((op1
>> 0) & 0xf)
588 case 0x8: /* 9[45]x8 */
589 switch ((op1
>> 4) & 0x1f)
623 case 0x9: /* 9[45]x9 */
624 switch ((op1
>> 4) & 0x1f)
642 flash
[pc
].r
= ((op1
& 0x1f0) >> 3) | (op1
& 1);
646 flash
[pc
].r
= ((op1
& 0x1f0) >> 3) | (op1
& 1);
670 flash
[pc
].r
= get_A (op1
);
671 if (((op1
>> 11) & 1) == 0)
682 switch ((op1
>> 9) & 7)
686 flash
[pc
].r
= 1 << (op1
& 7);
690 flash
[pc
].r
= 1 << (op1
& 7);
695 flash
[pc
].r
= 1 << (op1
& 7);
702 flash
[pc
].r
= 1 << (op1
& 7);
709 flash
[pc
].r
= 1 << (op1
& 7);
716 flash
[pc
].r
= 1 << (op1
& 7);
727 do_call (SIM_CPU
*cpu
, unsigned int npc
)
729 SIM_DESC sd
= CPU_STATE (cpu
);
730 unsigned int sp
= read_word (REG_SP
);
733 sram
[sp
--] = cpu
->pc
;
734 sram
[sp
--] = cpu
->pc
>> 8;
737 sram
[sp
--] = cpu
->pc
>> 16;
740 write_word (REG_SP
, sp
);
741 cpu
->pc
= npc
& PC_MASK
;
746 get_insn_length (unsigned int p
)
748 if (flash
[p
].code
== OP_unknown
)
749 flash
[p
].code
= decode(p
);
750 if (flash
[p
].code
>= OP_2words
)
759 return (sram
[RAMPZ
] << 16) | (sram
[REGZ_HI
] << 8) | sram
[REGZ_LO
];
763 get_lpm (unsigned int addr
)
767 w
= flash
[(addr
>> 1) & PC_MASK
].op
;
774 gen_mul (SIM_CPU
*cpu
, unsigned int res
)
777 sram
[SREG
] &= ~(SREG_Z
| SREG_C
);
779 sram
[SREG
] |= SREG_Z
;
781 sram
[SREG
] |= SREG_C
;
786 step_once (SIM_CPU
*cpu
)
796 code
= flash
[cpu
->pc
].code
;
797 op
= flash
[cpu
->pc
].op
;
800 if (tracing
&& code
!= OP_unknown
)
806 sim_cb_eprintf (callback
, "R00-07:");
807 for (i
= 0; i
< 8; i
++)
808 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
809 sim_cb_eprintf (callback
, " -");
810 for (i
= 8; i
< 16; i
++)
811 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
812 sim_cb_eprintf (callback
, " SP: %02x %02x",
813 sram
[REG_SP
+ 1], sram
[REG_SP
]);
814 sim_cb_eprintf (callback
, "\n");
815 sim_cb_eprintf (callback
, "R16-31:");
816 for (i
= 16; i
< 24; i
++)
817 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
818 sim_cb_eprintf (callback
, " -");
819 for (i
= 24; i
< 32; i
++)
820 sim_cb_eprintf (callback
, " %02x", sram
[i
]);
821 sim_cb_eprintf (callback
, " ");
823 for (i
= 0; i
< 8; i
++)
824 sim_cb_eprintf (callback
, "%c",
825 flags
& (0x80 >> i
) ? "ITHSVNZC"[i
] : '-');
826 sim_cb_eprintf (callback
, "\n");
830 sim_cb_eprintf (callback
, "%06x: %04x\n", 2 * cpu
->pc
, flash
[cpu
->pc
].op
);
833 sim_cb_eprintf (callback
, "pc=0x%06x insn=0x%04x code=%d r=%d\n",
834 2 * cpu
->pc
, flash
[cpu
->pc
].op
, code
, flash
[cpu
->pc
].r
);
835 disassemble_insn (CPU_STATE (cpu
), cpu
->pc
);
836 sim_cb_eprintf (callback
, "\n");
842 cpu
->pc
= (cpu
->pc
+ 1) & PC_MASK
;
848 flash
[ipc
].code
= decode(ipc
);
857 /* 2 words instruction, but we don't care about the pc. */
858 cpu
->pc
= ((flash
[ipc
].r
<< 16) | flash
[ipc
+ 1].op
) & PC_MASK
;
863 cpu
->pc
= ((sram
[EIND
] << 16) | read_word (REGZ
)) & PC_MASK
;
868 cpu
->pc
= read_word (REGZ
) & PC_MASK
;
873 /* 2 words instruction. */
875 do_call (cpu
, (flash
[ipc
].r
<< 16) | flash
[ipc
+ 1].op
);
879 do_call (cpu
, (sram
[EIND
] << 16) | read_word (REGZ
));
883 do_call (cpu
, read_word (REGZ
));
887 do_call (cpu
, cpu
->pc
+ sign_ext (op
& 0xfff, 12));
891 sram
[SREG
] |= SREG_I
;
895 SIM_DESC sd
= CPU_STATE (cpu
);
896 unsigned int sp
= read_word (REG_SP
);
899 cpu
->pc
= sram
[++sp
] << 16;
904 cpu
->pc
|= sram
[++sp
] << 8;
905 cpu
->pc
|= sram
[++sp
];
906 write_word (REG_SP
, sp
);
912 /* Stop on this address. */
913 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
, ipc
, sim_stopped
, SIM_SIGTRAP
);
919 if (sram
[SREG
] & SREG_T
)
926 if (sram
[get_d (op
)] & flash
[ipc
].r
)
927 sram
[SREG
] |= SREG_T
;
929 sram
[SREG
] &= ~SREG_T
;
934 if (((sram
[get_d (op
)] & flash
[ipc
].r
) == 0) ^ ((op
& 0x0200) != 0))
936 int l
= get_insn_length (cpu
->pc
);
944 unsigned int sp
= read_word (REG_SP
);
945 sram
[sp
--] = sram
[get_d (op
)];
946 write_word (REG_SP
, sp
);
953 unsigned int sp
= read_word (REG_SP
);
954 sram
[get_d (op
)] = sram
[++sp
];
955 write_word (REG_SP
, sp
);
961 sram
[SREG
] &= ~(1 << ((op
>> 4) & 0x7));
965 sram
[SREG
] |= 1 << ((op
>> 4) & 0x7);
969 cpu
->pc
= (cpu
->pc
+ sign_ext (op
& 0xfff, 12)) & PC_MASK
;
975 res
= sram
[d
] ^ sram
[get_r (op
)];
977 update_flags_logic (res
);
982 res
= sram
[d
] & sram
[get_r (op
)];
984 update_flags_logic (res
);
989 res
= sram
[d
] & get_K (op
);
991 update_flags_logic (res
);
996 res
= sram
[d
] | sram
[get_r (op
)];
998 update_flags_logic (res
);
1003 res
= sram
[d
] | get_K (op
);
1005 update_flags_logic (res
);
1012 update_flags_logic (res
);
1013 sram
[SREG
] |= SREG_C
;
1019 sram
[d
] = (vd
>> 4) | (vd
<< 4);
1027 sram
[SREG
] &= ~(SREG_H
| SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1029 sram
[SREG
] |= SREG_Z
;
1031 sram
[SREG
] |= SREG_C
;
1033 sram
[SREG
] |= SREG_V
| SREG_N
;
1034 else if (res
& 0x80)
1035 sram
[SREG
] |= SREG_N
| SREG_S
;
1036 if ((res
| vd
) & 0x08)
1037 sram
[SREG
] |= SREG_H
;
1044 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
);
1046 sram
[SREG
] |= SREG_V
| SREG_N
;
1047 else if (res
& 0x80)
1048 sram
[SREG
] |= SREG_N
| SREG_S
;
1050 sram
[SREG
] |= SREG_Z
;
1057 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
);
1059 sram
[SREG
] |= SREG_V
| SREG_S
;
1060 else if (res
& 0x80)
1061 sram
[SREG
] |= SREG_N
| SREG_S
;
1063 sram
[SREG
] |= SREG_Z
;
1070 res
= (vd
>> 1) | (vd
& flash
[ipc
].r
);
1072 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1074 sram
[SREG
] |= SREG_C
| SREG_S
;
1076 sram
[SREG
] |= SREG_N
;
1077 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_C
))
1078 sram
[SREG
] |= SREG_V
;
1080 sram
[SREG
] |= SREG_Z
;
1086 res
= vd
>> 1 | (sram
[SREG
] << 7);
1088 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1090 sram
[SREG
] |= SREG_C
| SREG_S
;
1092 sram
[SREG
] |= SREG_N
;
1093 if (!(sram
[SREG
] & SREG_N
) ^ !(sram
[SREG
] & SREG_C
))
1094 sram
[SREG
] |= SREG_V
;
1096 sram
[SREG
] |= SREG_Z
;
1100 gen_mul (cpu
, (word
)sram
[get_r (op
)] * (word
)sram
[get_d (op
)]);
1104 gen_mul (cpu
, (sword
)(sbyte
)sram
[get_r16 (op
)]
1105 * (sword
)(sbyte
)sram
[get_d16 (op
)]);
1109 gen_mul (cpu
, (sword
)(word
)sram
[get_r16_23 (op
)]
1110 * (sword
)(sbyte
)sram
[get_d16_23 (op
)]);
1114 gen_mul (cpu
, ((word
)sram
[get_r16_23 (op
)]
1115 * (word
)sram
[get_d16_23 (op
)]) << 1);
1119 gen_mul (cpu
, ((sword
)(sbyte
)sram
[get_r16_23 (op
)]
1120 * (sword
)(sbyte
)sram
[get_d16_23 (op
)]) << 1);
1124 gen_mul (cpu
, ((sword
)(word
)sram
[get_r16_23 (op
)]
1125 * (sword
)(sbyte
)sram
[get_d16_23 (op
)]) << 1);
1130 r
= sram
[get_r (op
)];
1133 res
= r
+ vd
+ (sram
[SREG
] & flash
[ipc
].r
);
1135 update_flags_add (res
, vd
, r
);
1141 r
= sram
[get_r (op
)];
1144 update_flags_sub (res
, vd
, r
);
1146 sram
[SREG
] |= SREG_Z
;
1151 byte old
= sram
[SREG
];
1154 r
= sram
[get_r (op
)];
1155 res
= vd
- r
- (old
& SREG_C
);
1157 update_flags_sub (res
, vd
, r
);
1158 if (res
== 0 && (old
& SREG_Z
))
1159 sram
[SREG
] |= SREG_Z
;
1169 update_flags_sub (res
, vd
, r
);
1171 sram
[SREG
] |= SREG_Z
;
1176 byte old
= sram
[SREG
];
1181 res
= vd
- r
- (old
& SREG_C
);
1183 update_flags_sub (res
, vd
, r
);
1184 if (res
== 0 && (old
& SREG_Z
))
1185 sram
[SREG
] |= SREG_Z
;
1190 sram
[get_d (op
)] = sram
[get_r (op
)];
1194 d
= (op
& 0xf0) >> 3;
1195 r
= (op
& 0x0f) << 1;
1197 sram
[d
+ 1] = sram
[r
+ 1];
1201 d
= get_A (op
) + 0x20;
1202 res
= sram
[get_d (op
)];
1204 if (d
== STDIO_PORT
)
1206 else if (d
== EXIT_PORT
)
1207 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
, cpu
->pc
, sim_exited
, 0);
1208 else if (d
== ABORT_PORT
)
1209 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
, cpu
->pc
, sim_exited
, 1);
1213 d
= get_A (op
) + 0x20;
1214 sram
[get_d (op
)] = sram
[d
];
1218 d
= get_biA (op
) + 0x20;
1219 sram
[d
] &= ~(1 << get_b(op
));
1223 d
= get_biA (op
) + 0x20;
1224 sram
[d
] |= 1 << get_b(op
);
1228 if (!(sram
[get_biA (op
) + 0x20] & 1 << get_b(op
)))
1230 int l
= get_insn_length (cpu
->pc
);
1237 if (sram
[get_biA (op
) + 0x20] & 1 << get_b(op
))
1239 int l
= get_insn_length (cpu
->pc
);
1252 sram
[get_d (op
)] = sram
[flash
[cpu
->pc
].op
];
1258 sram
[flash
[cpu
->pc
].op
] = sram
[get_d (op
)];
1264 if (sram
[get_r (op
)] == sram
[get_d (op
)])
1266 int l
= get_insn_length (cpu
->pc
);
1273 r
= sram
[get_r (op
)];
1274 d
= sram
[get_d (op
)];
1276 update_flags_sub (res
, d
, r
);
1278 sram
[SREG
] |= SREG_Z
;
1283 d
= sram
[get_d16 (op
)];
1285 update_flags_sub (res
, d
, r
);
1287 sram
[SREG
] |= SREG_Z
;
1292 byte old
= sram
[SREG
];
1293 d
= sram
[get_d (op
)];
1294 r
= sram
[get_r (op
)];
1295 res
= d
- r
- (old
& SREG_C
);
1296 update_flags_sub (res
, d
, r
);
1297 if (res
== 0 && (old
& SREG_Z
))
1298 sram
[SREG
] |= SREG_Z
;
1303 if (!(sram
[SREG
] & flash
[ipc
].r
))
1305 cpu
->pc
= (cpu
->pc
+ get_k (op
)) & PC_MASK
;
1311 if (sram
[SREG
] & flash
[ipc
].r
)
1313 cpu
->pc
= (cpu
->pc
+ get_k (op
)) & PC_MASK
;
1319 sram
[0] = get_lpm (read_word (REGZ
));
1324 sram
[get_d (op
)] = get_lpm (read_word (REGZ
));
1329 sram
[get_d (op
)] = get_lpm (read_word_post_inc (REGZ
));
1334 sram
[0] = get_lpm (get_z ());
1339 sram
[get_d (op
)] = get_lpm (get_z ());
1345 unsigned int z
= get_z ();
1347 sram
[get_d (op
)] = get_lpm (z
);
1350 sram
[REGZ_HI
] = z
>> 8;
1351 sram
[RAMPZ
] = z
>> 16;
1357 sram
[get_d (op
)] = sram
[read_word_post_inc (REGZ
) & SRAM_MASK
];
1362 sram
[get_d (op
)] = sram
[read_word_pre_dec (REGZ
) & SRAM_MASK
];
1367 sram
[get_d (op
)] = sram
[read_word_post_inc (REGX
) & SRAM_MASK
];
1372 sram
[get_d (op
)] = sram
[read_word_pre_dec (REGX
) & SRAM_MASK
];
1377 sram
[get_d (op
)] = sram
[read_word_post_inc (REGY
) & SRAM_MASK
];
1382 sram
[get_d (op
)] = sram
[read_word_pre_dec (REGY
) & SRAM_MASK
];
1387 sram
[read_word (REGX
) & SRAM_MASK
] = sram
[get_d (op
)];
1392 sram
[read_word_post_inc (REGX
) & SRAM_MASK
] = sram
[get_d (op
)];
1397 sram
[read_word_pre_dec (REGX
) & SRAM_MASK
] = sram
[get_d (op
)];
1402 sram
[read_word_post_inc (REGZ
) & SRAM_MASK
] = sram
[get_d (op
)];
1407 sram
[read_word_pre_dec (REGZ
) & SRAM_MASK
] = sram
[get_d (op
)];
1412 sram
[read_word_post_inc (REGY
) & SRAM_MASK
] = sram
[get_d (op
)];
1417 sram
[read_word_pre_dec (REGY
) & SRAM_MASK
] = sram
[get_d (op
)];
1422 sram
[read_word (REGY
) + flash
[ipc
].r
] = sram
[get_d (op
)];
1427 sram
[read_word (REGZ
) + flash
[ipc
].r
] = sram
[get_d (op
)];
1432 sram
[get_d (op
)] = sram
[read_word (REGZ
) + flash
[ipc
].r
];
1437 sram
[get_d (op
)] = sram
[read_word (REGY
) + flash
[ipc
].r
];
1442 sram
[get_d (op
)] = sram
[read_word (REGX
) & SRAM_MASK
];
1448 word wk
= get_k6 (op
);
1456 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1458 sram
[SREG
] |= SREG_Z
;
1460 sram
[SREG
] |= SREG_N
;
1461 if (wres
& ~wr
& 0x8000)
1462 sram
[SREG
] |= SREG_C
;
1463 if (~wres
& wr
& 0x8000)
1464 sram
[SREG
] |= SREG_V
;
1465 if (((~wres
& wr
) ^ wres
) & 0x8000)
1466 sram
[SREG
] |= SREG_S
;
1467 write_word (d
, wres
);
1474 word wk
= get_k6 (op
);
1482 sram
[SREG
] &= ~(SREG_S
| SREG_V
| SREG_N
| SREG_Z
| SREG_C
);
1484 sram
[SREG
] |= SREG_Z
;
1486 sram
[SREG
] |= SREG_N
;
1487 if (~wres
& wr
& 0x8000)
1488 sram
[SREG
] |= SREG_C
;
1489 if (wres
& ~wr
& 0x8000)
1490 sram
[SREG
] |= SREG_V
;
1491 if (((wres
& ~wr
) ^ wres
) & 0x8000)
1492 sram
[SREG
] |= SREG_S
;
1493 write_word (d
, wres
);
1499 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
, cpu
->pc
, sim_signalled
, SIM_SIGILL
);
1502 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
, cpu
->pc
, sim_signalled
, SIM_SIGILL
);
1507 sim_engine_run (SIM_DESC sd
,
1508 int next_cpu_nr
, /* ignore */
1509 int nr_cpus
, /* ignore */
1510 int siggnal
) /* ignore */
1514 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1516 cpu
= STATE_CPU (sd
, 0);
1521 if (sim_events_tick (sd
))
1522 sim_events_process (sd
);
1527 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
1531 if (addr
>= 0 && addr
< SRAM_VADDR
)
1533 while (size
> 0 && addr
< (MAX_AVR_FLASH
<< 1))
1535 word val
= flash
[addr
>> 1].op
;
1538 val
= (val
& 0xff) | (buffer
[0] << 8);
1540 val
= (val
& 0xff00) | buffer
[0];
1542 flash
[addr
>> 1].op
= val
;
1543 flash
[addr
>> 1].code
= OP_unknown
;
1548 return osize
- size
;
1550 else if (addr
>= SRAM_VADDR
&& addr
< SRAM_VADDR
+ MAX_AVR_SRAM
)
1553 if (addr
+ size
> MAX_AVR_SRAM
)
1554 size
= MAX_AVR_SRAM
- addr
;
1555 memcpy (sram
+ addr
, buffer
, size
);
1563 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
1567 if (addr
>= 0 && addr
< SRAM_VADDR
)
1569 while (size
> 0 && addr
< (MAX_AVR_FLASH
<< 1))
1571 word val
= flash
[addr
>> 1].op
;
1580 return osize
- size
;
1582 else if (addr
>= SRAM_VADDR
&& addr
< SRAM_VADDR
+ MAX_AVR_SRAM
)
1585 if (addr
+ size
> MAX_AVR_SRAM
)
1586 size
= MAX_AVR_SRAM
- addr
;
1587 memcpy (buffer
, sram
+ addr
, size
);
1593 memset (buffer
, 0, size
);
1599 avr_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1601 if (rn
< 32 && length
== 1)
1606 if (rn
== AVR_SREG_REGNUM
&& length
== 1)
1608 sram
[SREG
] = *memory
;
1611 if (rn
== AVR_SP_REGNUM
&& length
== 2)
1613 sram
[REG_SP
] = memory
[0];
1614 sram
[REG_SP
+ 1] = memory
[1];
1617 if (rn
== AVR_PC_REGNUM
&& length
== 4)
1619 cpu
->pc
= (memory
[0] >> 1) | (memory
[1] << 7)
1620 | (memory
[2] << 15) | (memory
[3] << 23);
1628 avr_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1630 if (rn
< 32 && length
== 1)
1635 if (rn
== AVR_SREG_REGNUM
&& length
== 1)
1637 *memory
= sram
[SREG
];
1640 if (rn
== AVR_SP_REGNUM
&& length
== 2)
1642 memory
[0] = sram
[REG_SP
];
1643 memory
[1] = sram
[REG_SP
+ 1];
1646 if (rn
== AVR_PC_REGNUM
&& length
== 4)
1648 memory
[0] = cpu
->pc
<< 1;
1649 memory
[1] = cpu
->pc
>> 7;
1650 memory
[2] = cpu
->pc
>> 15;
1651 memory
[3] = cpu
->pc
>> 23;
1658 avr_pc_get (sim_cpu
*cpu
)
1664 avr_pc_set (sim_cpu
*cpu
, sim_cia pc
)
1670 free_state (SIM_DESC sd
)
1672 if (STATE_MODULES (sd
) != NULL
)
1673 sim_module_uninstall (sd
);
1674 sim_cpu_free_all (sd
);
1675 sim_state_free (sd
);
1679 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
,
1680 struct bfd
*abfd
, char * const *argv
)
1683 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
1684 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1686 /* The cpu data is kept in a separately allocated chunk of memory. */
1687 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
1693 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
1699 /* The parser will print an error message for us, so we silently return. */
1700 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
1706 /* Check for/establish the a reference program image. */
1707 if (sim_analyze_program (sd
,
1708 (STATE_PROG_ARGV (sd
) != NULL
1709 ? *STATE_PROG_ARGV (sd
)
1710 : NULL
), abfd
) != SIM_RC_OK
)
1716 /* Configure/verify the target byte order and other runtime
1717 configuration options. */
1718 if (sim_config (sd
) != SIM_RC_OK
)
1720 sim_module_uninstall (sd
);
1724 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
1726 /* Uninstall the modules to avoid memory leaks,
1727 file descriptor leaks, etc. */
1728 sim_module_uninstall (sd
);
1732 /* CPU specific initialization. */
1733 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
1735 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
1737 CPU_REG_FETCH (cpu
) = avr_reg_fetch
;
1738 CPU_REG_STORE (cpu
) = avr_reg_store
;
1739 CPU_PC_FETCH (cpu
) = avr_pc_get
;
1740 CPU_PC_STORE (cpu
) = avr_pc_set
;
1743 /* Clear all the memory. */
1744 memset (sram
, 0, sizeof (sram
));
1745 memset (flash
, 0, sizeof (flash
));
1751 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
1752 char * const *argv
, char * const *env
)
1754 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1759 addr
= bfd_get_start_address (abfd
);
1762 sim_pc_set (cpu
, addr
);
1765 sd
->avr_pc22
= (bfd_get_mach (abfd
) >= bfd_mach_avr6
);
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