1 /* Blackfin General Purpose Ports (GPIO) model
3 Copyright (C) 2010-2011 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "dv-bfin_gpio.h"
31 /* Order after here is important -- matches hardware MMR layout. */
32 bu16
BFIN_MMR_16(data
);
33 bu16
BFIN_MMR_16(clear
);
34 bu16
BFIN_MMR_16(set
);
35 bu16
BFIN_MMR_16(toggle
);
36 bu16
BFIN_MMR_16(maska
);
37 bu16
BFIN_MMR_16(maska_clear
);
38 bu16
BFIN_MMR_16(maska_set
);
39 bu16
BFIN_MMR_16(maska_toggle
);
40 bu16
BFIN_MMR_16(maskb
);
41 bu16
BFIN_MMR_16(maskb_clear
);
42 bu16
BFIN_MMR_16(maskb_set
);
43 bu16
BFIN_MMR_16(maskb_toggle
);
44 bu16
BFIN_MMR_16(dir
);
45 bu16
BFIN_MMR_16(polar
);
46 bu16
BFIN_MMR_16(edge
);
47 bu16
BFIN_MMR_16(both
);
48 bu16
BFIN_MMR_16(inen
);
50 #define mmr_base() offsetof(struct bfin_gpio, data)
51 #define mmr_offset(mmr) (offsetof(struct bfin_gpio, mmr) - mmr_base())
53 static const char * const mmr_names
[] =
55 "PORTIO", "PORTIO_CLEAR", "PORTIO_SET", "PORTIO_TOGGLE", "PORTIO_MASKA",
56 "PORTIO_MASKA_CLEAR", "PORTIO_MASKA_SET", "PORTIO_MASKA_TOGGLE",
57 "PORTIO_MASKB", "PORTIO_MASKB_CLEAR", "PORTIO_MASKB_SET",
58 "PORTIO_MASKB_TOGGLE", "PORTIO_DIR", "PORTIO_POLAR", "PORTIO_EDGE",
59 "PORTIO_BOTH", "PORTIO_INEN",
61 #define mmr_name(off) mmr_names[(off) / 4]
64 bfin_gpio_io_write_buffer (struct hw
*me
, const void *source
, int space
,
65 address_word addr
, unsigned nr_bytes
)
67 struct bfin_gpio
*port
= hw_data (me
);
72 value
= dv_load_2 (source
);
73 mmr_off
= addr
- port
->base
;
74 valuep
= (void *)((unsigned long)port
+ mmr_base() + mmr_off
);
78 dv_bfin_mmr_require_16 (me
, addr
, nr_bytes
, true);
82 case mmr_offset(data
):
83 case mmr_offset(maska
):
84 case mmr_offset(maskb
):
86 case mmr_offset(polar
):
87 case mmr_offset(edge
):
88 case mmr_offset(both
):
89 case mmr_offset(inen
):
92 case mmr_offset(clear
):
93 case mmr_offset(maska_clear
):
94 case mmr_offset(maskb_clear
):
95 /* We want to clear the related data MMR. */
97 dv_w1c_2 (valuep
, value
, -1);
100 case mmr_offset(maska_set
):
101 case mmr_offset(maskb_set
):
102 /* We want to set the related data MMR. */
106 case mmr_offset(toggle
):
107 case mmr_offset(maska_toggle
):
108 case mmr_offset(maskb_toggle
):
109 /* We want to toggle the related data MMR. */
114 dv_bfin_mmr_invalid (me
, addr
, nr_bytes
, true);
122 bfin_gpio_io_read_buffer (struct hw
*me
, void *dest
, int space
,
123 address_word addr
, unsigned nr_bytes
)
125 struct bfin_gpio
*port
= hw_data (me
);
129 mmr_off
= addr
- port
->base
;
130 valuep
= (void *)((unsigned long)port
+ mmr_base() + mmr_off
);
134 dv_bfin_mmr_require_16 (me
, addr
, nr_bytes
, false);
138 case mmr_offset(data
):
139 case mmr_offset(clear
):
140 case mmr_offset(set
):
141 case mmr_offset(toggle
):
142 dv_store_2 (dest
, port
->data
);
144 case mmr_offset(maska
):
145 case mmr_offset(maska_clear
):
146 case mmr_offset(maska_set
):
147 case mmr_offset(maska_toggle
):
148 dv_store_2 (dest
, port
->maska
);
150 case mmr_offset(maskb
):
151 case mmr_offset(maskb_clear
):
152 case mmr_offset(maskb_set
):
153 case mmr_offset(maskb_toggle
):
154 dv_store_2 (dest
, port
->maskb
);
156 case mmr_offset(dir
):
157 case mmr_offset(polar
):
158 case mmr_offset(edge
):
159 case mmr_offset(both
):
160 case mmr_offset(inen
):
161 dv_store_2 (dest
, *valuep
);
164 dv_bfin_mmr_invalid (me
, addr
, nr_bytes
, false);
171 static const struct hw_port_descriptor bfin_gpio_ports
[] =
173 { "mask_a", 0, 0, output_port
, },
174 { "mask_b", 1, 0, output_port
, },
175 { "p0", 0, 0, input_port
, },
176 { "p1", 1, 0, input_port
, },
177 { "p2", 2, 0, input_port
, },
178 { "p3", 3, 0, input_port
, },
179 { "p4", 4, 0, input_port
, },
180 { "p5", 5, 0, input_port
, },
181 { "p6", 6, 0, input_port
, },
182 { "p7", 7, 0, input_port
, },
183 { "p8", 8, 0, input_port
, },
184 { "p9", 9, 0, input_port
, },
185 { "p10", 10, 0, input_port
, },
186 { "p11", 11, 0, input_port
, },
187 { "p12", 12, 0, input_port
, },
188 { "p13", 13, 0, input_port
, },
189 { "p14", 14, 0, input_port
, },
194 bfin_gpio_port_event (struct hw
*me
, int my_port
, struct hw
*source
,
195 int source_port
, int level
)
197 struct bfin_gpio
*port
= hw_data (me
);
199 bu32 bit
= (1 << my_port
);
201 /* Normalize the level value. A simulated device can send any value
202 it likes to us, but in reality we only care about 0 and 1. This
203 lets us assume only those two values below. */
206 HW_TRACE ((me
, "pin %i set to %i", my_port
, level
));
208 /* Only screw with state if this pin is set as an input, and the
209 input is actually enabled. */
210 if ((port
->dir
& bit
) || !(port
->inen
& bit
))
212 HW_TRACE ((me
, "ignoring level/int due to DIR=%i INEN=%i",
213 !!(port
->dir
& bit
), !!(port
->inen
& bit
)));
217 /* Get the old pin state for calculating an interrupt. */
218 olvl
= !!(port
->data
& bit
);
220 /* Update the new pin state. */
221 port
->data
= (port
->data
& ~bit
) | (level
<< my_port
);
223 /* See if this state transition will generate an interrupt. */
224 nlvl
= !!(port
->data
& bit
);
226 if (port
->edge
& bit
)
228 /* Pin is edge triggered. */
229 if (port
->both
& bit
)
234 HW_TRACE ((me
, "ignoring int due to EDGE=%i BOTH=%i lvl=%i->%i",
235 !!(port
->edge
& bit
), !!(port
->both
& bit
),
243 if (!(((port
->polar
& bit
) && olvl
> nlvl
)
244 || (!(port
->polar
& bit
) && olvl
< nlvl
)))
246 HW_TRACE ((me
, "ignoring int due to EDGE=%i POLAR=%i lvl=%i->%i",
247 !!(port
->edge
& bit
), !!(port
->polar
& bit
),
255 /* Pin is level triggered. */
256 if (nlvl
== !!(port
->polar
& bit
))
258 HW_TRACE ((me
, "ignoring int due to EDGE=%i POLAR=%i lvl=%i",
259 !!(port
->edge
& bit
), !!(port
->polar
& bit
), nlvl
));
264 /* If the masks allow it, push the interrupt even higher. */
265 if (port
->maska
& bit
)
267 HW_TRACE ((me
, "pin %i triggered an int via mask a", my_port
));
268 hw_port_event (me
, 0, 1);
270 if (port
->maskb
& bit
)
272 HW_TRACE ((me
, "pin %i triggered an int via mask b", my_port
));
273 hw_port_event (me
, 1, 1);
278 attach_bfin_gpio_regs (struct hw
*me
, struct bfin_gpio
*port
)
280 address_word attach_address
;
282 unsigned attach_size
;
283 reg_property_spec reg
;
285 if (hw_find_property (me
, "reg") == NULL
)
286 hw_abort (me
, "Missing \"reg\" property");
288 if (!hw_find_reg_array_property (me
, "reg", 0, ®
))
289 hw_abort (me
, "\"reg\" property must contain three addr/size entries");
291 hw_unit_address_to_attach_address (hw_parent (me
),
293 &attach_space
, &attach_address
, me
);
294 hw_unit_size_to_attach_size (hw_parent (me
), ®
.size
, &attach_size
, me
);
296 if (attach_size
!= BFIN_MMR_GPIO_SIZE
)
297 hw_abort (me
, "\"reg\" size must be %#x", BFIN_MMR_GPIO_SIZE
);
299 hw_attach_address (hw_parent (me
),
300 0, attach_space
, attach_address
, attach_size
, me
);
302 port
->base
= attach_address
;
306 bfin_gpio_finish (struct hw
*me
)
308 struct bfin_gpio
*port
;
310 port
= HW_ZALLOC (me
, struct bfin_gpio
);
312 set_hw_data (me
, port
);
313 set_hw_io_read_buffer (me
, bfin_gpio_io_read_buffer
);
314 set_hw_io_write_buffer (me
, bfin_gpio_io_write_buffer
);
315 set_hw_ports (me
, bfin_gpio_ports
);
316 set_hw_port_event (me
, bfin_gpio_port_event
);
318 attach_bfin_gpio_regs (me
, port
);
321 const struct hw_descriptor dv_bfin_gpio_descriptor
[] =
323 {"bfin_gpio", bfin_gpio_finish
,},